A load circuit and a load current regulating method thereof

Abstract

This application provides a load circuit and its load current regulation method. The load circuit includes an adjustable linear regulator, a load resistor, a voltage regulation network, a digital-to-analog converter (DAC), and a controller. The input terminal of the adjustable linear regulator is connected to the source under test. The load resistor is connected between the output terminal and a reference ground. The voltage regulation network is connected to the feedback terminal, the output terminal, and the reference ground, and regulates the output voltage and load current in response to the control voltage provided by the DAC. The controller continuously regulates the load current by setting the control voltage. This application utilizes the negative feedback characteristic of the internal error amplifier of the adjustable linear regulator to achieve a stable constant current output. The load current can be changed by continuously adjusting the control voltage through the DAC without switching circuit paths, simplifying the circuit structure and reducing current ripple. This meets the requirements for high-precision constant current loads in the testing of charge-discharge integrated circuit products, while reducing testing costs.

Description

Technical Field

[0001] This application relates to the field of finished product testing, and in particular to a load circuit and a method for regulating the load current thereon. Background Technology

[0002] For charge-discharge integrated circuits, the accuracy of their charge-discharge parameters often needs to be converged through on-chip testing and adjustment of the internal programmable region. During parameter calibration, voltage parameter calibration is relatively simple, requiring only a precise and stable voltage source and a high-precision analog-to-digital converter. However, current parameter calibration requires a load circuit to simulate the actual charge-discharge process, applying an accurate constant current load to the output of the chip under test to complete the calibration. The current ripple, accuracy, and response speed of the load circuit directly affect the accuracy of the calibration results.

[0003] As products upgrade and customers demand higher chip performance, the requirements for load circuit accuracy in the testing process also increase. Existing load solutions struggle to achieve a good balance between accuracy and cost. Traditional electronic loads typically use power MOSFETs in conjunction with operational amplifiers to form a constant current loop. This type of solution requires carefully designed compensation networks to achieve low ripple and fast response, resulting in high circuit complexity. Furthermore, when continuous current adjustment or current switching according to protocol timing is required, different load paths often need to be switched, which can easily introduce current overshoot and undershoot, affecting calibration accuracy. Summary of the Invention

[0004] This application aims to solve the technical problems of existing load circuits in the testing of charge and discharge integrated circuit products, which are difficult to balance accuracy and cost, have complex circuit structures, and do not support continuous adjustment.

[0005] In a first aspect, this application provides a load circuit, comprising: an adjustable linear regulator, the input terminal of which is connected to a source under test; a load resistor connected between the output terminal of the adjustable linear regulator and a reference ground, for converting the output voltage of the adjustable linear regulator into a load current; a voltage regulation network connected to the feedback terminal, the output terminal, and the reference ground of the adjustable linear regulator, and configured to regulate the output voltage and the load current in response to a control voltage; a digital-to-analog converter (DAC), the output terminal of which is connected to the input terminal of the voltage regulation network, for providing the control voltage to the voltage regulation network; and a controller, the output terminal of which is connected to the input terminal of the DAC, for setting the control voltage of the DAC to achieve continuous regulation of the load current.

[0006] Optionally, the load circuit further includes: a first sampling unit connected between the output terminal of the adjustable linear regulator and the load resistor, for acquiring the load current and obtaining a sampled current signal; and an analog-to-digital converter, the input terminal of which is connected to the output terminal of the first sampling unit, and the output terminal of which is connected to the controller, for converting the sampled current signal into a digital signal and feeding it back to the controller.

[0007] Optionally, the controller is further configured to adjust the control voltage according to the error value between the digital signal and the target current value, so that the load current converges to the target current value.

[0008] Optionally, the load circuit further includes: a non-volatile memory connected to the controller via a communication interface, used to store correction data output by the controller; the correction data includes a mapping relationship between the control voltage and the corresponding sampled current signal; after power-on, the controller loads the correction data from the non-volatile memory and determines the control voltage output by the digital-to-analog converter based on the correction data.

[0009] Optionally, the voltage regulation network includes a third resistor, a fourth resistor, and a fifth resistor; the third resistor is connected between the output terminal and the feedback terminal of the adjustable linear regulator, the fourth resistor is connected between the feedback terminal of the adjustable linear regulator and the reference ground, and the fifth resistor is connected between the feedback terminal of the adjustable linear regulator and the output terminal of the digital-to-analog converter.

[0010] Optionally, the output voltage and the control voltage satisfy the following relationship: VOUT = (R3 / R4 + 1 + R3 / R5) × VFB (R3 / R5) × VDAC, where VOUT is the output voltage, VFB is the feedback voltage at the feedback terminal, VDAC is the control voltage, R3 is the resistance value of the third resistor, R4 is the resistance value of the fourth resistor, and R5 is the resistance value of the fifth resistor.

[0011] Secondly, this application also provides a load current regulation method applied to the load circuit described in the first aspect, comprising: determining a target control voltage of the digital-to-analog converter based on a target current value; driving the digital-to-analog converter to output the target control voltage to the voltage regulation network, thereby enabling the adjustable linear regulator to generate a target output voltage, and forming the target current value through the load resistor.

[0012] Optionally, determining the target control voltage of the digital-to-analog converter based on the target current value includes: acquiring the target current value; and calculating the target control voltage according to the following formula: VDAC = [(R3 / R4 + 1 + R3 / R5) ×VFB – Iload_target × Rload] / (R3 / R5) where Iload_target is the target current value, Rload is the resistance value of the load resistor, VFB is the feedback voltage, R3 is the resistance value of the third resistor, R4 is the resistance value of the fourth resistor, and R5 is the resistance value of the fifth resistor.

[0013] Optionally, determining the target control voltage of the digital-to-analog converter based on the target current value includes: acquiring the target current value; determining the target control voltage based on the target current value and correction data; the correction data includes the mapping relationship between the control voltage and the corresponding sampled current signal.

[0014] Optionally, after driving the digital-to-analog converter to output the target control voltage to the voltage regulation network, the method further includes: sampling the actual load current through a current sampling circuit; adjusting the control voltage of the digital-to-analog converter according to the error value between the actual load current and the target current value; repeating the above steps until the load current converges to the target current value.

[0015] At least one advantage of the load circuit provided in this application embodiment is that it utilizes the negative feedback characteristics of the internal error amplifier of the adjustable linear regulator to achieve a stable constant current output. The load current can be changed by continuously adjusting the control voltage through the digital-to-analog converter without switching the circuit path, which simplifies the circuit structure and reduces current ripple. It can meet the requirements of high-precision constant current load in the testing of charge and discharge integrated circuit products, while reducing testing costs. Attached Figure Description

[0016] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0017] Figure 1 A schematic diagram of a load circuit provided for an embodiment of the present invention; Figure 2 A circuit schematic diagram of a load circuit provided for an embodiment of the present invention; Figure 3 A simulation circuit diagram of a load circuit provided for an embodiment of the present invention. Figure 4 for Figure 3The simulation waveforms of the simulation circuit diagram shown; Figure 5 A schematic diagram of another load circuit provided for an embodiment of the present invention; Figure 6 A circuit schematic diagram of the first sampling unit provided for an embodiment of the present invention; Figure 7 A schematic diagram of another load circuit provided for an embodiment of the present invention; Figure 8 The measured waveform of the load circuit under constant current state provided for the embodiments of the present invention; Figure 9 The measured waveform of the load circuit under continuous adjustment state provided for the embodiments of the present invention; Figure 10 This is a schematic flowchart of a load current regulation method provided for an embodiment of the present invention. Detailed Implementation

[0018] To facilitate understanding of this application, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "upper," "lower," "inner," "outer," "bottom," etc., used in this specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0019] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0020] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0021] Figure 1 This is a schematic diagram of a load circuit 10 provided in an embodiment of this application. Figure 1As shown, the load circuit 10 includes an adjustable linear regulator 110, a load resistor Rload, a voltage regulation network 120, a digital-to-analog converter (DAC), and a controller 130.

[0022] The adjustable linear regulator 110 has an input terminal, an output terminal, and a feedback terminal. The input terminal of the adjustable linear regulator 110 is connected to the source under test 20, such as a charge-discharge integrated circuit to be tested. The adjustable linear regulator 110 is a low dropout linear regulator (LDO) with a feedback terminal. Its internal error amplifier maintains the voltage at the feedback terminal at a stable feedback voltage VFB through a negative feedback mechanism.

[0023] In this application, the adjustable linear regulator 110 is not used as a conventional regulated power supply to power the subsequent circuit. Instead, it utilizes the negative feedback characteristics of its internal error amplifier as the core regulating device of the load circuit, and sets the current flowing through the load resistor Rload by controlling its output voltage.

[0024] The load resistor Rload is connected between the output terminal of the adjustable linear regulator 110 and the reference ground GND. The output terminal of the adjustable linear regulator 110 generates an output voltage VOUT, which is applied to the load resistor Rload to form a load current Iload, i.e., Iload = VOUT / Rload.

[0025] The voltage regulation network 120 is connected to the feedback terminal, output terminal, and reference ground GND of the adjustable linear regulator 110, respectively. The input terminal of the voltage regulation network 120 receives the control voltage VDAC from the digital-to-analog converter. By changing the current balance at the feedback terminal, the voltage regulation network 120 causes the error amplifier of the adjustable linear regulator 110 to readjust the output voltage to maintain the stability of the feedback terminal voltage, thereby regulating the output voltage VOUT. Since there is a definite proportional relationship between the load current Iload and the output voltage VOUT, adjusting the output voltage VOUT can regulate the load current Iload.

[0026] The output of the digital-to-analog converter (DAC) is connected to the input of the voltage regulation network 120, providing a continuously adjustable control voltage VDAC to the voltage regulation network 120. The output of the controller 130 is connected to the input of the DAC, setting the control voltage VDAC output by the DAC. The controller 130 is, for example, a microcontroller (MCU), a field-programmable gate array (FPGA), or a personal computer (PC). The controller 130 sends digital code values ​​to the DAC via a digital interface, and the DAC converts these digital code values ​​into the corresponding analog voltage VDAC and outputs it to the voltage regulation network 120.

[0027] Figure 2The circuit schematic of the load circuit 10 provided in the embodiments of this application is as follows: Figure 2 As shown, the input (VIN) of the adjustable linear regulator 110 is connected to the source under test 20, and the output (VOUT) is connected to the reference ground GND through the load resistor Rload. The voltage regulation network 120 is connected between the feedback (FB), the output, and the reference ground GND of the adjustable linear regulator 110, and receives the control voltage VDAC from the digital-to-analog converter.

[0028] During operation, the source under test 20 supplies current to the input of the adjustable linear regulator 110. The error amplifier inside the adjustable linear regulator 110 continuously monitors the feedback voltage and maintains it at a stable feedback voltage VFB by adjusting the conduction level of the internal power transistor. When the controller 130 changes the control voltage VDAC via a digital-to-analog converter, the current flowing through each resistor in the voltage regulation network 120 changes, disrupting the current balance at the feedback terminal. To re-establish the current balance at the feedback terminal, the error amplifier adjusts the output voltage VOUT to a new steady-state value. The change in the output voltage VOUT directly causes a corresponding change in the load current Iload flowing through the load resistor Rload.

[0029] Utilizing the linear power supply characteristics of the adjustable linear regulator 110, its input current is approximately equal to its output current, i.e., Ivin ≈ Ivout. Therefore, the load current Iload is also the current drawn by the adjustable linear regulator 110 from the source under test 20. The adjustable linear regulator 110 and the load resistor Rload jointly bear the power dissipation, and for the source under test 20, the load circuit 10 is equivalent to a constant current load.

[0030] In this way, the controller 130 only needs to change the output voltage VDAC of the digital-to-analog converter to continuously adjust the load current Iload. The entire adjustment process is completed within the same circuit path without the need to switch between different load branches or resistor levels.

[0031] Compared to traditional tiered electronic load solutions, the load circuit 10 of this application avoids current overshoot and undershoot during loop switching, resulting in smooth current transition and short settling time. Furthermore, since the adjustable linear regulator 110 integrates a high-gain error amplifier and a sophisticated compensation network, the load circuit 10 inherently possesses excellent voltage regulation and low noise characteristics, with low current ripple. It eliminates the need for complex compensation circuits, requires very few external components, and has a simple circuit structure, thus reducing testing costs.

[0032] like Figure 2As shown, the voltage regulation network 120 includes a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The third resistor R3 is connected between the output terminal and the feedback terminal (FB) of the adjustable linear regulator 110; the fourth resistor R4 is connected between the feedback terminal and the reference ground GND; and the fifth resistor R5 is connected between the feedback terminal and the output terminal of the digital-to-analog converter. The three resistors converge at the feedback terminal, forming a three-way current convergence node.

[0033] As described in the aforementioned embodiments, the error amplifier of the adjustable linear regulator 110 maintains the feedback terminal voltage at a stable feedback voltage VFB through negative feedback. Based on this premise, Kirchhoff's Current Law (KCL) equations can be applied to the feedback terminal node to determine the balance relationship between the three currents.

[0034] Let I1 be the current flowing through the third resistor R3, and let its direction be from the output terminal to the feedback terminal. Then I1 = (VOUT) VFB) / R3. Define the current flowing through the fourth resistor R4 as I2, with the direction from the feedback terminal to the reference ground, then I2 = VFB / R4. Define the current flowing through the fifth resistor R5 as I3, with the direction from the digital-to-analog converter output terminal to the feedback terminal, then I3 = (VDAC) / R3. VFB) / R5.

[0035] According to Kirchhoff's current law, at the feedback node, the sum of the currents flowing into the node equals the sum of the currents flowing out of the node, i.e., I1 + I3 = I2. Substituting these into the above current expressions, we get: (VOUT VFB) / R3 + (VDAC VFB) / R5 = VFB / R4 Simplifying and rearranging the above equation, and extracting VOUT as the dependent variable, we can obtain the relationship between the output voltage VOUT and the control voltage VDAC: VOUT = (R3 / R4 + 1 + R3 / R5) × VFB (R3 / R5) × VDAC Since the load current Iload = VOUT / Rload, substituting the above equation yields: Iload = [(R3 / R4 + 1 + R3 / R5) × VFB [(R3 / R5) × VDAC] / Rload As can be seen from the above formula, once the resistance values ​​of each resistor in the voltage regulation network 120 and the feedback voltage VFB are determined, the output voltage VOUT and the control voltage VDAC have a linear relationship, and the load current Iload also has a linear relationship with VDAC. The controller 130 can adjust the load current Iload according to a determined proportional relationship by changing the value of VDAC through a digital-to-analog converter, thus achieving continuous regulation.

[0036] The above relationship is illustrated below using a set of specific values. Assume that in the voltage regulation network 120, the third resistor R3 = 150kΩ, the fourth resistor R4 = 20kΩ, the fifth resistor R5 = 20kΩ, the feedback voltage VFB of the adjustable linear regulator 110 = 0.8V (taking the linear regulator LT3045 as an example, its internal reference voltage is set via the SET pin), and the load resistance Rload = 2Ω. Substituting these parameters into the formula yields: VOUT = (150k / 20k + 1 + 150k / 20k) × 0.8 (150k / 20k) × VDAC = 16.5 × 0.8 7.5 × VDAC = 13.2 7.5 × VDAC Accordingly, Iload = VOUT / Rload = (13.2) 7.5 × VDAC) / 2 When VDAC = 1.0V, VOUT = 13.2V. 7.5 = 5.7V, Iload = 5.7 / 2 = 2.85A; when VDAC = 1.5V, VOUT = 13.2 11.25 = 1.95V, Iload = 1.95 / 2 = 0.975A. It can be seen that for every 0.5V change in VDAC, the load current changes by approximately 1.875A, demonstrating a clear and continuous adjustment relationship. The controller 130 can achieve fine-step current adjustment based on the resolution of the digital-to-analog converter.

[0037] It should be noted that the above linear relationship holds true only if the feedback voltage of the adjustable linear regulator 110 can be precisely maintained at VFB by the error amplifier. When the control voltage VDAC or the output voltage VOUT is lower than the feedback voltage VFB, the current direction in the corresponding branch will reverse.

[0038] Taking the branch containing the fifth resistor R5 as an example, when VDAC is less than VFB, I3 = (VDAC) A negative value for VFB / R5 indicates that the actual current direction is from the feedback terminal to the output terminal of the digital-to-analog converter. The fifth resistor R5 changes from injecting current into the feedback terminal to drawing current from it. In this case, to maintain a stable feedback terminal voltage, the error amplifier needs to drive the output voltage VOUT to a higher level.

[0039] When VOUT rises to near the input voltage VIN, the adjustable linear regulator 110 may enter the operating region of insufficient voltage difference, the adjustment gain of the error amplifier decreases, and the feedback voltage can no longer be accurately maintained at VFB. The premise of the above linear formula is broken, resulting in a sudden change in the proportional relationship between the control voltage VDAC and the load current Iload.

[0040] In a preferred embodiment, the resistance ratios of the resistors in the voltage regulation network 120 can be reasonably selected so that, within the target current regulation range, both the control voltage VDAC and the output voltage VOUT are in a linear operating region greater than the feedback voltage VFB, thereby fully utilizing the aforementioned linear relationship to achieve precise open-loop regulation. In another embodiment, when the application scenario requires a wide current regulation range that inevitably crosses the critical point corresponding to the feedback voltage VFB, closed-loop feedback control is required to ensure regulation accuracy across the entire range.

[0041] Figure 3 A simulation circuit diagram of a load circuit 10 provided for an embodiment of this application, such as... Figure 3 As shown, the LT3045 is selected as the adjustable linear regulator 110 in the simulation circuit.

[0042] The LT3045 is an adjustable linear regulator with ultra-low noise and ultra-high power supply rejection ratio. It integrates a high-performance error amplifier and a sophisticated compensation network, and features input (IN), output (OUT), feedback setting (SET), and ground (GND) pins. In this simulation circuit, the LT3045's input is supplied with a 7V input voltage via voltage source V1, simulating the power supply to the source under test 20. An input bypass capacitor C2 is connected between the input and ground, and an output bypass capacitor C3 is connected between the output and ground. The SET pin sets the internal reference via resistor R2 and capacitor C1, and the enable pin (EN / UV) is connected to the input via resistor R0 to keep the device enabled.

[0043] The voltage regulation network 120 consists of a third resistor R3, a fourth resistor R4, and a fifth resistor R5, connected in the same manner as described in the previous embodiment: R3 is connected between the output terminal and the feedback terminal, R4 is connected between the feedback terminal and the reference ground, and R5 is connected between the feedback terminal and the control voltage VDAC input terminal. In the simulation, the values ​​of each resistor are R3 = 150kΩ, R4 = 20kΩ, and R5 = 20kΩ. The load resistor Rload = 2Ω is connected between the output terminal and the reference ground.

[0044] The control voltage VDAC is provided by a piecewise linear voltage source V2, whose output voltage increases sequentially from 100mV to 350mV in 50mV increments. Each voltage step is held for a certain time to observe the steady-state response of the load current at each voltage point. The simulation time is set to 500ms.

[0045] Figure 4 for Figure 3 The simulation waveform of the circuit shown is as follows. Figure 4 The simulation results simultaneously display the waveforms of the control voltage V (VDAC) and the load current I (Rload) as a function of time. The following characteristics can be observed from the simulation results: The load current I(Rload) changes in accordance with the control voltage V(VDAC), and there is a clear correspondence between the two, verifying the correctness of the mathematical relationship between VOUT and VDAC derived in the aforementioned embodiment. When the control voltage VDAC remains constant at a certain level, the load current stabilizes at a certain value, demonstrating the constant current effect brought about by the negative feedback voltage regulation characteristic of the adjustable linear regulator 110.

[0046] The load current changes continuously and smoothly with the control voltage. When switching between voltage steps, the current transition process is fast and there is no obvious overshoot or undershoot, which reflects the technical advantage of adjusting the current within the same loop without switching paths.

[0047] In the simulation waveforms, it can be observed that when the control voltage VDAC is at a lower value, the slope of the load current change differs from that when the control voltage VDAC is at a higher value. This phenomenon corresponds to the proportional change problem analyzed in the aforementioned embodiments. Specifically, when the value of VDAC is lower than the feedback voltage VFB of the adjustable linear regulator 110, the direction of the current I3 flowing through the fifth resistor R5 reverses, and the fifth resistor R5 changes from injecting current into the feedback terminal to drawing current from the feedback terminal. In this operating region, the operating state of the error amplifier changes, and the feedback terminal voltage may deviate from the ideal VFB value, causing the actual current change ratio to deviate from the ratio predicted by the linear formula in the aforementioned embodiments.

[0048] Continuing with the analysis using the parameters from the aforementioned implementation, when R3 = 150kΩ, R4 = 20kΩ, and R5 = 20kΩ, according to the formula from the aforementioned implementation, VOUT = 16.5 × VFB. 7.5 × VDAC. Taking the feedback voltage of LT3045 under this simulation configuration as an example, as VDAC increases from 100mV to 350mV, some VDAC values ​​may be lower than VFB. At this time, the linear premise of the formula is not fully satisfied, which is reflected in the simulation waveform as the ratio of current to voltage change in this region is different from that in the linear region.

[0049] The simulation results show that the load circuit 10 based on the adjustable linear regulator 110 can achieve continuous regulation of the load current. Within the linear operating region, the relationship between the load current and the control voltage is in high agreement with the theoretical derivation. Simultaneously, the simulation also verifies the theoretical analysis of the proportional change phenomenon in the aforementioned implementation. For applications requiring high-precision current regulation across the entire operating range, including nonlinear regions, relying solely on open-loop theoretical formulas to calculate the control voltage will be insufficient to guarantee accuracy.

[0050] In the aforementioned embodiment, the load circuit 10 directly sets the output voltage VDAC of the digital-to-analog converter through the controller 130 to regulate the load current. This is an open-loop control method. Open-loop control can achieve good current regulation accuracy in the linear operating region, but it has two limitations: when the control voltage VDAC or the output voltage VOUT is lower than the feedback voltage VFB, the current direction in the voltage regulation network 120 is reversed, the linear relationship between the control voltage and the load current is destroyed, and the control voltage set in the open loop cannot accurately correspond to the target current; even in the linear operating region, there is a tolerance deviation between the actual resistance value and the nominal value of each resistor in the voltage regulation network 120, and the actual feedback voltage VFB of the adjustable linear regulator 110 may deviate from the typical value. These factors will cause deviations between the actual load current and the theoretical calculated value.

[0051] Figure 5 This is a schematic diagram of another load circuit 10 provided in an embodiment of this application, as shown below. Figure 5 As shown, with Figure 1 Compared to the load circuit 10 shown, Figure 5 The load circuit 10 shown also includes a first sampling unit 140 and an analog-to-digital converter (ADC).

[0052] The first sampling unit 140 is connected between the output terminal of the adjustable linear regulator 110 and the load resistor Rload, and is positioned in the path of the load current Iload. The first sampling unit 140 is used to acquire the load current flowing through this path in real time to obtain a sampled current signal.

[0053] The input terminal of the analog-to-digital converter (ADC) is connected to the output terminal of the first sampling unit 140, and is used to convert the sampled current signal output by the first sampling unit 140 into a digital signal. The output terminal of the ADC is connected to the controller 130, and feeds back the converted digital signal to the controller 130. Thus, the controller 130 can obtain the actual measured value of the current load current.

[0054] After the introduction of the first sampling unit 140 and the analog-to-digital converter, the controller 130 no longer relies solely on theoretical formulas or preset parameters to determine the control voltage VDAC. Instead, it dynamically adjusts the control voltage based on the deviation between the actual measured load current and the target current, forming a closed-loop control.

[0055] Specifically, the controller 130 converts the digital signal fed back from the analog-to-digital converter into an actual load current value, compares this actual value with the target current value, and obtains the error value between the two. When the error value is greater than a preset convergence threshold, the controller 130 adjusts the control voltage VDAC output by the digital-to-analog converter according to the direction and magnitude of the error value, so that the load current moves closer to the target current value. The controller 130 continues to execute the above sampling, comparison, and adjustment process until the error value is less than the convergence threshold and the load current converges to the target current value.

[0056] Continuing with the parameters from the aforementioned embodiments, assuming the target load current is 500mA, controller 130 first calculates the initial control voltage VDAC according to the formula in the aforementioned embodiments and sets it to the digital-to-analog converter. At this time, the actual load current sampled by the first sampling unit 140 may be 485mA, with an error of 15mA compared to the target value of 500mA. After detecting this error, controller 130 adjusts the control voltage in the direction of reducing VDAC (as described in the aforementioned embodiments, a decrease in VDAC leads to an increase in VOUT, and the load current increases accordingly), bringing the load current closer to 500mA. After several rounds of iterative adjustments, the actual load current converges to within the range of 500mA ± the allowable error, and the closed-loop control is completed.

[0057] The advantage of closed-loop feedback control is that its adjustment accuracy does not depend on the precise knowledge of the resistor parameters in the voltage regulation network 120 and the feedback voltage VFB, nor on the strict establishment of the linear relationship between the control voltage VDAC and the load current Iload. Regardless of whether the circuit is in the linear operating region or the nonlinear region described in Embodiments 2 and 3, the controller 130 always adjusts based on the measured current of the first sampling unit 140.

[0058] In the nonlinear region, although the adjustment ratio between the control voltage and the load current changes, the closed-loop control does not need to know the precise value of this ratio in advance. It only needs to determine the direction of the deviation based on the results of each sampling and adjust accordingly, eventually converging to the target current value. In the linear region, because the adjustment ratio is constant, the closed-loop convergence speed is relatively fast; in the nonlinear region, the convergence speed may vary, but it does not affect the final adjustment accuracy.

[0059] Through the aforementioned closed-loop feedback control, the current accuracy of the load circuit 10 is improved from relying on the tolerance of circuit components to relying on the sampling accuracy of the first sampling unit 140 and the analog-to-digital converter, achieving high-precision load current regulation across the entire operating range. Simultaneously, since the closed-loop control is completed within the same loop and does not involve switching of the load path, the current adjustment process is smooth and continuous, without introducing additional overshoot or undershoot.

[0060] Figure 6 The circuit schematic of the first sampling unit 140 provided in the embodiments of this application is as follows: Figure 6 As shown, the first sampling unit 140 includes a sampling resistor Rload, a current sampling amplifier U2, an input filter circuit, and an output filter capacitor C5.

[0061] The sampling resistor Rload is connected in series in the path of the load current Iload, and its two ends are marked LOAD+ and LOAD-, respectively. In this embodiment, the load resistor and the sampling resistor share the same resistor Rload, that is, the load resistor through which the load current flows also serves as the sensing resistor for current sampling. When the load current Iload flows through the sampling resistor Rload, a differential voltage Vr = Iload × Rload is generated across its two ends.

[0062] The current sampling amplifier U2 is a differential input, single-ended output current sensing amplifier. The two differential input terminals of the current sampling amplifier U2 are connected to the two ends of the sampling resistor Rload through an input filter circuit. Specifically, the non-inverting input terminal of the current sampling amplifier U2 is connected to the LOAD+ terminal of the sampling resistor Rload through resistor R6, and the inverting input terminal is connected to the LOAD- terminal of the sampling resistor Rload through resistor R7. A filter capacitor C4 is also connected between resistors R6 and R7 to filter out high-frequency noise in the differential input signal and improve sampling stability.

[0063] The power supply terminal of the current sampling amplifier U2 is connected to the power supply voltage VCC. Its output terminal outputs a single-ended voltage signal that is proportionally amplified to the differential input voltage, i.e., the sampled current signal. A filter capacitor C5 is also connected to the output terminal to filter the output signal and further suppress noise.

[0064] The current sampling amplifier U2 amplifies the differential voltage Vr across the sampling resistor Rload by a fixed factor and outputs it as a single-ended voltage signal, which can be directly acquired by the analog-to-digital converter (ADC). Let the amplification factor of the current sampling amplifier U2 be G, then the output sampling current signal voltage Vsample = Vr × G = Iload × Rload × G. After obtaining Vsample through the ADC, the controller 130 can calculate the actual load current Iload = Vsample / (G × Rload).

[0065] Continuing with the explanation using the parameters from the previous embodiments, assuming a load resistance Rload = 2Ω, when the target load current Iload = 500mA, the differential voltage Vr across the sampling resistor = 0.5A × 2Ω = 1V. If a current sampling amplifier with a gain G = 1 is selected, the output sampling current signal voltage Vsample = 1V. This voltage value is within the range of commonly used analog-to-digital converters and can be directly sampled and converted.

[0066] In another implementation, when the load current is small or the sampling resistor value is low, the differential voltage across the sampling resistor may be very weak. For example, if a milliohm-level resistor with a resistance of 20mΩ is used, the differential voltage will be only Vr = 0.5A × 0.02Ω = 10mV when the load current is 500mA. In this case, a current sampling amplifier with a higher amplification factor is needed to obtain an output signal with sufficient amplitude.

[0067] For example, if a current sampling amplifier with a gain of G=100 (such as the INA190 series) is selected, the output sampling current signal voltage Vsample = 10mV × 100 = 1000mV = 1V, which can also be accurately acquired by the analog-to-digital converter. The advantage of using a milliohm-level sampling resistor is that its voltage drop is extremely small, and its impact on the load current path is negligible, so the introduction of the sampling resistor will not cause the load current to fall short of the design requirements. However, the tolerance and gain error of the milliohm-level sampling resistor and the high-gain amplifier itself will affect the final sampling accuracy.

[0068] It should be noted that the relationship between the sampling resistor and the load resistor differs in the two implementation methods described above. When the sampling resistor has a large value (e.g., 2Ω), the sampling resistor itself is the load resistor Rload, and the two are combined, resulting in the simplest circuit. When the sampling resistor has a value in the milliohm range, the sampling resistor is connected in series separately in the load current path, and is set separately from the load resistor Rload. The sampling resistor is only used for current sensing, while the load resistor bears the main voltage drop and power dissipation. Those skilled in the art can flexibly select the value of the sampling resistor and the amplifier gain according to the current range, accuracy requirements, and power dissipation needs in the actual application.

[0069] In practical applications, due to factors such as manufacturing tolerances of the resistors in the voltage regulation network 120, the feedback voltage VFB deviation of the adjustable linear regulator 110, and the gain errors of the sampling resistor and current sampling amplifier described in the aforementioned embodiments, the actual electrical parameters differ between different load circuit boards. If each board is calculated using the same theoretical formula, the actual output current of the same target current value on different boards will have inter-board deviations, which cannot meet the consistency requirements of high-precision testing scenarios.

[0070] Figure 7 A schematic diagram of another load circuit 10 provided in the embodiments of this application is shown below. Figure 7 As shown, with Figure 5 Compared to the load circuit 10 shown, Figure 7 The load circuit 10 shown also includes a non-volatile memory 150. The non-volatile memory 150 is connected to the controller 130 via a communication interface. In this embodiment, the non-volatile memory 150 is, for example, an EEPROM, and the communication interface is, for example, an IIC interface.

[0071] The non-volatile memory 150 is used to store the correction data of the load circuit 10. The correction data includes the mapping relationship between the control voltage VDAC output by the digital-to-analog converter and the corresponding sampled current signal. This mapping relationship reflects the true correspondence between the control voltage VDAC and the actual load current for each load circuit board under actual component parameter conditions, rather than a theoretically calculated value based on nominal parameters.

[0072] The calibration data is acquired through a factory calibration process. Specifically, after each load circuit board is manufactured, it is calibrated board by board using standard instruments. During the calibration process, the controller 130 sequentially sets different control voltages VDAC to be output by the digital-to-analog converter. Under each control voltage, the actual load current value is acquired through the first sampling unit 140 and the analog-to-digital converter, and can be verified using an external standard ammeter. Each set of control voltages and the corresponding measured load current are recorded to form a set of discrete mapping data points. The controller 130 writes these mapping data points to the non-volatile memory 150 for persistent storage via the IIC interface.

[0073] Continuing with the parameters from the previous embodiments, assume that during the calibration process, the following mapping data was collected for a certain load circuit board: the measured load current is 510mA when VDAC = 1.00V, 480mA when VDAC = 1.10V, 452mA when VDAC = 1.20V, and so on, covering several calibration points within the target current adjustment range. This data is stored as calibration data in non-volatile memory 150. For another load circuit board, due to different component tolerances, the same VDAC = 1.00V may correspond to a measured load current of 505mA. Its calibration data differs from the previous board and is stored in its respective non-volatile memory 150.

[0074] During normal operation, after power-on, the controller 130 first loads calibration data from the non-volatile memory 150 via the IIC interface. When a target load current needs to be output, the controller 130 no longer uses the theoretical formula in the aforementioned embodiment for calculation, but instead determines the corresponding control voltage VDAC based on the mapping relationship in the loaded calibration data.

[0075] If the target current value falls exactly at a calibration point, the controller 130 directly uses the VDAC value corresponding to that calibration point; if the target current value is between two adjacent calibration points, the controller 130 calculates the corresponding VDAC value through interpolation. The controller 130 sets the determined VDAC value to the digital-to-analog converter, which allows the load current to quickly reach the vicinity of the target value.

[0076] For example, when the target load current is 490mA, this value lies between the calibration points of 480mA (VDAC = 1.10V) and 510mA (VDAC = 1.00V). Controller 130 calculates VDAC = 1.10V using linear interpolation. (490 480) / (510 480) × (1.10 1.00) = 1.10 0.033 = 1.067V. Set this value to the digital-to-analog converter. Since this value comes from the actual measured data of this board, it corresponds to the target current more accurately than the value calculated by the theoretical formula.

[0077] In the working mode that combines calibration data and closed-loop feedback control, the calibration data is used to determine the initial control voltage close to the target current, shortening the convergence time of the closed-loop feedback; the closed-loop feedback control as described in the aforementioned embodiments is used to eliminate the residual errors caused by discrete calibration and interpolation calculations in the calibration data, and to accurately converge the load current to the target value.

[0078] Through the aforementioned calibration data scheme, each load circuit board uses its own calibrated mapping relationship to determine the control voltage, eliminating inter-board differences caused by component tolerances and achieving batch consistency of the load circuits. Simultaneously, the calibration data is stored in non-volatile memory 150, which is not lost when power is off and can be loaded and used immediately upon power-on, eliminating the need for recalibration each time.

[0079] Figure 8 This is a measured waveform of the load circuit 10 provided in this embodiment under constant current conditions. This waveform corresponds to the load circuit 10 operating at a constant current of 500mA, where the closed-loop feedback control described in the aforementioned embodiment stabilizes the load current at the target value. Figure 8 The measured data can be read. The average load current is 501.06mA, with a deviation of only 1.06mA from the target value of 500mA, and a relative error of approximately 0.2%. The peak-to-peak ripple of the load current is 13mA, accounting for 2.6% of the target current.

[0080] The above experimental results show that, under closed-loop feedback control, the load circuit 10 can accurately stabilize the load current near the target value. The peak-to-peak ripple of 13mA demonstrates the low-noise advantage brought by the negative feedback voltage regulation characteristics of the internal error amplifier of the adjustable linear regulator 110. Compared with the traditional constant current load scheme composed of power MOSFETs and operational amplifiers, the load circuit 10 of this application can achieve good ripple suppression without the need for additional complex compensation networks.

[0081] Figure 9 The measured waveform of the load circuit 10 provided in the embodiment of this application in the continuous adjustment state shows the process of the load current changing continuously when the controller 130 continuously changes the control voltage VDAC through the digital-to-analog converter. Figure 9 The waveforms of the control voltage VDAC and the load current Iload are displayed simultaneously.

[0082] from Figure 9The measured data can be read, with an average load current of 294.9mA and a peak-to-peak value of 696mA. The peak-to-peak value of 696mA reflects the range of load current change from minimum to maximum during the entire continuous adjustment process, that is, the current adjustment range covered by the load circuit 10 during this adjustment process, rather than the current ripple under steady state.

[0083] from Figure 9 As can be observed from the waveform, as the control voltage VDAC gradually changes, the load current Iload smoothly and continuously follows the change, maintaining a clear correspondence between the two. No step jumps or obvious overshoots or undershoots occur during the transition. As described in the aforementioned embodiment, since the current regulation is completed within the same loop, the controller 130 can switch between different currents simply by changing the output voltage of the digital-to-analog converter, without needing to switch between different load branches or resistor levels.

[0084] Figure 9 The measured results also verified the proportional change phenomenon analyzed in the aforementioned implementation method. It can be observed from the waveform that the slope of the load current change with the control voltage varies in different ranges. When the control voltage is at a low value, the current change is slower, and when the control voltage rises to a certain value, the current change accelerates.

[0085] This is consistent with the phenomenon analyzed in the aforementioned embodiments: when the control voltage or output voltage is lower than the feedback voltage VFB, the current direction in the voltage regulation network 120 reverses, and the regulation ratio between the control voltage and the load current changes. Despite the abrupt change in the ratio, the load current can still continuously change with the control voltage. As described in the aforementioned embodiments, precise current regulation can be achieved across the entire operating range, including the nonlinear region, through closed-loop feedback control.

[0086] Combination Figure 8 and Figure 9 Based on the measured results, a comprehensive analysis of the performance of the load circuit 10 is conducted. Regarding constant current accuracy, the deviation between the measured average current and the target value is in the milliampere range, meeting the requirements of high-precision constant current loads for charge / discharge integrated circuit product testing. As for current ripple, the peak-to-peak ripple is controlled within 13mA, thanks to the mature compensation network within the adjustable linear regulator 110, achieving this without the need for additional filtering circuitry.

[0087] In terms of continuous adjustment, the load current can smoothly change with the control voltage within a range of approximately 696mA, supporting the setting of any current point. This feature enables the load circuit 10 to meet the requirements of protocol timing tests. For example, when calibrating the MTK protocol current, the controller 130 can achieve smooth switching between different target currents by setting different VDAC values ​​according to the timing sequence, and can achieve precise timing control through software timing.

[0088] Based on the load circuit provided in the foregoing embodiments, this invention also provides a load current regulation method, the flowchart of which is shown below. Figure 10 As shown, the specific steps include the following: Step S100: Determine the target control voltage of the digital-to-analog converter based on the target current value.

[0089] The controller 130 acquires the target current value Iload_target. This target current value can be sent from an external host computer or determined by the controller 130 itself according to a preset test procedure. Based on the target current value, the controller 130 determines the target control voltage VDAC required for the digital-to-analog converter output.

[0090] In one implementation, the controller 130 directly calculates the target control voltage using theoretical formulas based on the parameters of each resistor in the voltage regulation network 120 and the feedback voltage VFB of the adjustable linear regulator 110. Specifically, based on the relationship between VOUT and VDAC, combined with Iload = VOUT / Rload, the following can be calculated: VDAC = [(R3 / R4 + 1 + R3 / R5) × VFB Iload_target × Rload] / (R3 / R5) Continuing with the explanation using the parameters from the aforementioned implementation, assume R3 = 150kΩ, R4 = 20kΩ, R5 = 20kΩ, VFB = 0.8V, Rload = 2Ω, and the target current Iload_target = 500mA. Substituting these values ​​into the above formula yields: VDAC = [(150k / 20k + 1 + 150k / 20k) × 0.8 [0.5 × 2] / (150k / 20k) = (16.5 × 0.8 1) / 7.5 = (13.2 1) / 7.5 = 1.627V The controller 130 sends the digital code value corresponding to 1.627V to the digital-to-analog converter as the target control voltage.

[0091] In another implementation, as described in the preceding embodiments, the controller 130 does not use theoretical formulas for calculation. Instead, it determines the target control voltage based on calibration data pre-stored in the non-volatile memory 150. The calibration data includes a mapping relationship between the control voltage and the corresponding sampled current signal. After power-on, the controller 130 loads the calibration data from the non-volatile memory 150. When a target current needs to be output, it searches for or interpolates to calculate the corresponding target control voltage VDAC based on the mapping relationship.

[0092] For example, continuing to use the calibration data from the aforementioned implementation, when the target current is 490mA, this value lies between the calibration points of 480mA (VDAC = 1.10V) and 510mA (VDAC = 1.00V). The controller 130 calculates VDAC = 1.067V through linear interpolation. Compared to calculations based on theoretical formulas, the control voltage determined based on the calibration data is closer to the actual characteristics of the board and can approach the target current value more quickly.

[0093] Step S200: Drive the digital-to-analog converter to output the target control voltage to the voltage regulation network, so that the adjustable linear regulator generates the target output voltage and forms the target current value through the load resistor.

[0094] The controller 130 drives the digital-to-analog converter to output the target control voltage VDAC determined in step S100 to the voltage regulation network 120. As described in the previous embodiment, the voltage regulation network 120 responds to the control voltage by changing the current balance relationship at the feedback terminal of the adjustable linear regulator 110, causing the error amplifier to adjust the output voltage VOUT to the corresponding steady-state value. The output voltage VOUT is applied across the load resistor Rload, forming the load current Iload.

[0095] If theoretical formulas are used for calculation or data lookup in step S100, the load current will reach near the target value after step S200. For applications where high accuracy is not required, the above two steps are sufficient, and the process flow ends.

[0096] For applications requiring high precision, a closed-loop feedback adjustment process can be further executed after step S200 to eliminate residual errors from the open-loop setting. As described in the aforementioned embodiments, the closed-loop feedback adjustment includes the following sub-steps: Step S210: Sample the actual load current through the current sampling circuit.

[0097] The first sampling unit 140 collects the current load current, amplifies it through a current sampling amplifier, and outputs a sampled current signal. The analog-to-digital converter converts this signal into a digital signal and feeds it back to the controller 130. The controller 130 calculates the actual load current value Iload_actual based on this digital signal.

[0098] Step S220: Adjust the control voltage of the digital-to-analog converter according to the error value between the actual load current and the target current value.

[0099] Controller 130 compares the actual load current value Iload_actual with the target current value Iload_target, and calculates the error value ΔI = Iload_target between the two. When the absolute value of the error value ΔI is greater than the preset convergence threshold, the controller 130 adjusts the control voltage VDAC output by the digital-to-analog converter according to the direction of the error value. As described in the aforementioned embodiment, VDAC is negatively correlated with the load current in the linear operating region. Therefore, when the actual current is less than the target value (ΔI is positive), the controller 130 decreases VDAC to increase the load current; when the actual current is greater than the target value (ΔI is negative), the controller 130 increases VDAC to decrease the load current.

[0100] Continuing with the previous example, assume that after step S200, the actual load current sampled by the first sampling unit 140 is 485mA, which has an error of 15mA compared to the target value of 500mA. Upon detecting this error, the controller 130 decreases VDAC, thereby increasing the load current.

[0101] Step S230: Repeat steps S210 and S220 until the load current converges to the target current value.

[0102] The controller 130 continuously performs an iterative process of sampling and adjustment. After each adjustment, the actual load current is resampled and the error value is recalculated until the absolute value of the error value is less than the convergence threshold. As analyzed in Example 4, the closed-loop feedback control does not depend on the strict validity of the linear relationship between the control voltage and the load current, and can converge to the target current value throughout the entire operating range, including the nonlinear region.

[0103] Based on the above method flow, when it is necessary to switch different target current values ​​according to a preset protocol timing sequence, the controller 130 sets different target current values ​​sequentially according to the protocol timing sequence, and re-executes steps S100 and S200 for each target current value. As described in the aforementioned embodiments, since the current regulation is completed within the same loop, the switching between different target currents is smooth and continuous, without the need to switch circuit paths, thus avoiding current overshoot and undershoot caused by loop switching. The controller 130 uses software timing to control the holding time and switching time of each target current, achieving precise timing control.

[0104] For example, in an application scenario for calibrating MTK protocol current, controller 130 first sets the target current to 250mA, executes steps S100 and S200 to stabilize the load current at 250mA, and completes comparator calibration under the threshold current. Subsequently, according to the protocol timing, controller 130 switches the target current to the next target value and re-executes steps S100 and S200. The entire process is completed continuously within the same loop.

[0105] The load circuit 10 described in this application is mainly used in the field of final product testing (FT testing) of charge-discharge integrated circuits. During the production process of charge-discharge integrated circuits, the charging and discharging parameters inside the chip need to be adjusted and calibrated through FT testing to achieve convergence of parameter accuracy. As described in the background section, the calibration of current parameters requires applying an accurate constant current load to the output terminal of the chip under test, and the calibration of the corresponding parameters is completed by actually simulating the charging and discharging process. The load circuit 10, as a core component of the testing system, provides a precise and controllable constant current load to the chip under test.

[0106] In a specific application scenario, load circuit 10 is used to calibrate the current parameters related to the MTK protocol in the charge / discharge integrated circuit. The MTK protocol sets a specific threshold for the charging current, and the chip under test has a corresponding comparator to determine whether the current reaches the threshold. During FT testing, this comparator needs to be calibrated so that its judgment threshold is consistent with the value specified in the protocol.

[0107] The calibration process is as follows: First, the controller 130 sets the load current of the load circuit 10 to the threshold current specified in the protocol, such as 250mA, according to the method described in the aforementioned embodiment. The load circuit 10 draws an accurate 250mA constant current from the charging output terminal of the chip under test. The comparator inside the chip under test generates a judgment result under this current condition. The test system reads the output state of the comparator. If the judgment result does not match the expectation, the threshold of the comparator is adjusted by modifying the register value of the programmable area inside the chip under test until the comparator generates the correct judgment result under the 250mA load current, thus completing the calibration of the comparator.

[0108] In the aforementioned calibration process, the accuracy of the load current directly determines the accuracy of the comparator calibration. If the 250mA current provided by the load circuit has a large deviation, the comparator threshold will be calibrated to an incorrect value, causing the chip's charging behavior in actual use to deviate from the protocol specifications. The load circuit 10 of this application, through the closed-loop feedback control and correction data compensation described in the foregoing embodiments, can provide a constant current load with milliampere-level accuracy, as shown in the example. Figure 8 The measured data shows that the deviation at the target current of 500mA is only 1.06mA, which meets the requirements of the protocol current calibration for load accuracy.

[0109] In another specific application scenario, the load circuit 10 needs to simulate protocol timing, switching between different current values ​​according to a specified timing sequence. The protocol timing specifies the current magnitude, hold time, and switching order at each stage. The chip under test needs to complete the switching of charging and discharging states and parameter calibration under this timing sequence. As described in the aforementioned implementation, the controller 130 sets different target current values ​​sequentially according to the protocol timing sequence via software timing. The load circuit 10 completes current switching within the same loop, with a smooth transition process, free from overshoot and undershoot. Figure 9 This has been verified by measured waveforms. Furthermore, the software timing system can precisely control the hold time and switching time of each current phase, meeting the timing accuracy requirements of the protocol.

[0110] In addition to the MTK protocol current calibration scenario mentioned above, the load circuit 10 is also suitable for testing other proprietary protocols and for high-precision calibration of self-developed circuits. Different protocols have different requirements for current parameters. The load circuit 10 achieves continuously adjustable current output through a digital-to-analog converter, which can flexibly adapt to the current values ​​and timing requirements specified by different protocols without the need to design dedicated load hardware for each protocol.

[0111] In mass production testing scenarios, the load circuit 10 achieves inter-board consistency through the calibration data scheme described in the aforementioned embodiments. Each load circuit board is calibrated board-by-board using standard instruments before leaving the factory, and the calibration data is stored in the non-volatile memory 150. On the testing production line, multiple load circuit boards can be used in parallel for testing at different workstations. Each board outputs current according to its own calibration data, ensuring consistency and repeatability of test results between different workstations.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A load circuit, characterized in that, include: An adjustable linear regulator, wherein the input terminal of the adjustable linear regulator is connected to the source under test; A load resistor is connected between the output terminal of the adjustable linear regulator and the reference ground to convert the output voltage of the adjustable linear regulator into a load current. A voltage regulation network, which is connected to the feedback terminal, the output terminal, and the reference ground of the adjustable linear regulator, is configured to regulate the output voltage and the load current in response to a control voltage. A digital-to-analog converter, the output of which is connected to the input of the voltage regulation network, for providing the control voltage to the voltage regulation network; A controller, the output of which is connected to the input of the digital-to-analog converter, is used to set the control voltage of the digital-to-analog converter in order to achieve continuous adjustment of the load current.

2. The circuit according to claim 1, characterized in that, Also includes: The first sampling unit is connected between the output terminal of the adjustable linear regulator and the load resistor, and is used to collect the load current and obtain a sampling current signal. An analog-to-digital converter (ADC) is provided, with its input terminal connected to the output terminal of the first sampling unit and its output terminal connected to the controller. The ADC is used to convert the sampled current signal into a digital signal and feed it back to the controller.

3. The circuit according to claim 2, characterized in that, The controller is also configured to adjust the control voltage based on the error value between the digital signal and the target current value, so that the load current converges to the target current value.

4. The circuit according to claim 3, characterized in that, Also includes: A non-volatile memory, connected to the controller via a communication interface, is used to store the correction data output by the controller; the correction data includes the mapping relationship between the control voltage and the corresponding sampled current signal; After power-on, the controller loads the correction data from the non-volatile memory and determines the control voltage output by the digital-to-analog converter based on the correction data.

5. The circuit according to claim 1, characterized in that, The voltage regulation network includes a third resistor, a fourth resistor, and a fifth resistor; The third resistor is connected between the output terminal and the feedback terminal of the adjustable linear regulator, the fourth resistor is connected between the feedback terminal of the adjustable linear regulator and the reference ground, and the fifth resistor is connected between the feedback terminal of the adjustable linear regulator and the output terminal of the digital-to-analog converter.

6. The circuit according to claim 5, characterized in that, The output voltage and the control voltage satisfy the following relationship: VOUT = (R3 / R4 + 1 + R3 / R5) × VFB (R3 / R5) × VDAC Wherein, VOUT is the output voltage, VFB is the feedback voltage at the feedback terminal, VDAC is the control voltage, R3 is the resistance value of the third resistor, R4 is the resistance value of the fourth resistor, and R5 is the resistance value of the fifth resistor.

7. A method for regulating load current, characterized in that, Applied to the load circuit as described in any one of claims 1-6, comprising: The target control voltage of the digital-to-analog converter is determined based on the target current value; The digital-to-analog converter is driven to output the target control voltage to the voltage regulation network, so that the adjustable linear regulator generates the target output voltage and forms the target current value through the load resistor.

8. The method according to claim 7, characterized in that, Determining the target control voltage of the digital-to-analog converter based on the target current value includes: Obtain the target current value; The target control voltage is calculated using the following formula: VDAC = [(R3 / R4 + 1 + R3 / R5) × VFB – Iload_target × Rload] / (R3 / R5) Wherein, Iload_target is the target current value, Rload is the resistance value of the load resistor, VFB is the feedback voltage, R3 is the resistance value of the third resistor, R4 is the resistance value of the fourth resistor, and R5 is the resistance value of the fifth resistor.

9. The method according to claim 7, characterized in that, Determining the target control voltage of the digital-to-analog converter based on the target current value includes: Obtain the target current value; The target control voltage is determined based on the target current value and the correction data; the correction data includes the mapping relationship between the control voltage and the corresponding sampled current signal.

10. The method according to claim 7, characterized in that, After driving the digital-to-analog converter to output the target control voltage to the voltage regulation network, the method further includes: The actual load current is sampled using a current sampling circuit. The control voltage of the digital-to-analog converter is adjusted based on the error between the actual load current and the target current value. Repeat the above steps until the load current converges to the target current value.

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