A spatiotemporal discretization control circuit and control method

Abstract

This application relates to a spatiotemporal discretization control circuit and control method. The spatiotemporal discretization control method includes a spatial discretization mode, comprising: acquiring a spatial configuration value, which represents the workload required for the control circuit of the power consumption unit array to output; acquiring a spatial grouping value; which is used to divide the workload into 2... N The application involves grouping the workload into sub-workloads; obtaining the channel address value; dividing the channel address value into two parts based on the spatial grouping value; dividing the spatial configuration value into two parts based on the spatial grouping value; and comparing the second part of the bit-reversed channel address value with the first part of the spatial configuration value. This application also relates to a spatiotemporal discretization control method, including a time discretization mode. This application further relates to a spatiotemporal discretization control circuit, including a spatial discretization module. This application also relates to a spatiotemporal discretization control circuit, including a time discretization module.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and particularly to a spatiotemporal discretization control circuit and control method. Background Technology

[0002] In modern high-performance electronic systems, the power consumption unit is the smallest unit that constitutes a power consumption unit array, which is formed according to a specific topology. As the core component that performs power conversion and signal processing, the operation of the power consumption unit is inevitably accompanied by non-functional energy dissipation.

[0003] In the spatial dimension, the energy dissipated by power consumption cells is released in the form of Joule heat. When multiple activated power consumption cells are physically close to each other, the local heat flux density increases sharply, thus forming a "hot spot". This hot spot, which is generated by the heat accumulation effect in the spatial dimension, can not only cause device performance drift (such as increased MOSFET on-resistance and increased logic gate delay), but also, in severe cases, cause thermal breakdown or accelerate electromigration aging, reducing the lifespan of the chip.

[0004] In the time dimension, the energy dissipated by the power consumption unit is released in the form of electromagnetic radiation. Existing pulse width modulation (PWM) control typically employs a single-pulse concentrated conduction strategy, that is, releasing the required energy in a large pulse width at once within one control cycle. This energy accumulation in the time dimension brings significant transient impacts to the power consumption unit array, easily causing synchronous switching noise and voltage sag. During this process, the energy is highly concentrated at low frequencies, causing low-frequency EMI to exceed the limits, resulting in high-amplitude interference spikes in the spectrum that are difficult to filter out by conventional filters, seriously affecting the electromagnetic compatibility of the system.

[0005] The dual concentration of dissipated energy in both time and space severely restricts the stability and reliability of the system. Existing solutions typically address these two issues through separate designs, such as using heat sinks to solve heat accumulation problems and using spread spectrum clocks (SSCG) or phase jitter to address EMI issues. However, limited by current manufacturing processes, independent designs can no longer significantly improve energy efficiency. The greater expectation is to directly map the dissipated energy of the power unit array into control signals in both time and space through a simple mechanism, thereby breaking the thermal concentration of dissipated energy in physical space and / or the synchronization of energy in time phase. Summary of the Invention

[0006] To address the technical problems existing in the prior art, this application proposes a spatiotemporal discretization control method, including a spatial discretization mode, which includes obtaining a spatial configuration value; the spatial configuration value represents the workload that the control circuit of the power consumption unit array needs to output, and the spatial configuration value is an I-bit binary number, where I is a positive integer greater than or equal to 1; obtaining a spatial grouping value; the spatial grouping value is used to divide the workload into 2 N The workload is divided into sub-workload groups, each containing a different number of sub-workloads; the space grouping value is N, where N is a positive integer less than or equal to 1 and greater than or equal to 1; the channel address value is obtained; where the channel address value is 1 bit binary; based on the space grouping value, the channel address value is divided into a first part and a second part; where the first part of the channel address value includes the remaining bits of the channel address value except for the high N bits, representing the channel's sequence number in the channel group; the second part of the channel address value includes the high N bits of the channel address value, representing the sequence number of the channel group to which the channel belongs; based on the space grouping value, the space configuration value is... The space configuration value is divided into a first part and a second part; wherein, the first part of the space configuration value includes the lower N bits of the space configuration value, which is related to the sequence number of the channel group; the second part of the space configuration value includes the remaining bits of the space configuration value other than the lower N bits, which is related to the number of channels selected in the channel group; the second part of the address value of the channel after bit reversal is compared with the first part of the space configuration value; wherein, when the second part of the address value of the channel after bit reversal is less than or equal to the first part of the space configuration value, the channel group is selected, the first channel selection signal is valid and the second part of the space configuration value plus 1 is provided.

[0007] Specifically, in the spatiotemporal discretization control method, the second part of the address value of the channel after bit reversal is compared with the first part of the spatial configuration value; when the second part of the address value of the channel after bit reversal is greater than the first part of the spatial configuration value, the channel group is not selected, the first channel selection signal is in a failed state and the second part of the spatial configuration value is provided.

[0008] Specifically, in the spatiotemporal discretization control method, when the first channel selection signal is valid, the number of channels selected in the channel group is the decimal number corresponding to the value of the second part of the spatial configuration value plus 1; or, when the first channel selection signal is invalid, the number of channels selected in the channel group is the decimal number corresponding to the value of the second part of the spatial configuration value.

[0009] Specifically, the spatiotemporal discretization control method further includes, when the first channel selection signal is valid, obtaining the value of the second part of the spatial configuration value plus 1 and comparing it with the sum of the first part of the channel address value; wherein, when the first part of the channel address value is less than the value of the second part of the spatial configuration value plus 1, the channel is selected and the second channel selection signal is valid; when the first part of the channel address value is greater than or equal to the value of the second part of the spatial configuration value plus 1, the channel is not selected and the second channel selection signal is invalid.

[0010] Specifically, the spatiotemporal discretization control method further includes, when the first channel selection signal fails, obtaining the second part of the spatial configuration value and comparing it with the first part of the channel address value; wherein, when the first part of the channel address value is less than the second part of the spatial configuration value, the channel is selected and the second channel selection signal is valid; when the first part of the channel address value is greater than or equal to the second part of the spatial configuration value, the channel is not selected and the second channel selection signal fails.

[0011] Specifically, the spatiotemporal discretization control method further includes: acquiring a working mode control signal; when the working mode control signal requires selecting the channel in the channel group in a bit-reversed manner, acquiring the first part of the address value of the channel after bit reversal; or, when the working mode control signal requires selecting the channel in the channel group in a sequential manner, acquiring the first part of the address value of the channel.

[0012] Specifically, the spatiotemporal discretization control method further includes, when the working mode control signal requires a channel in the channel group to be selected in bit-reversed order and the first channel selection signal is valid, comparing the value of the second part of the spatial configuration value plus 1 with the first part of the address value of the channel after bit reversal; wherein, when the first part of the address value of the channel after bit reversal is less than the value of the second part of the spatial configuration value plus 1, the channel is selected and the second channel selection signal is valid; when the first part of the address value of the channel after bit reversal is greater than or equal to the value of the second part of the spatial configuration value plus 1, the channel is not selected and the second channel selection signal is invalid.

[0013] Specifically, the spatiotemporal discretization control method further includes, when the working mode control signal requires the selection of a channel in the channel group in a bit-reversed manner and the first channel selection signal fails, comparing the second part of the spatial configuration value with the first part of the address value of the channel after bit reversal; wherein, when the first part of the address value of the channel after bit reversal is less than the second part of the spatial configuration value, the channel is selected and the second channel selection signal is valid; or, when the first part of the address value of the channel after bit reversal is greater than or equal to the second part of the spatial configuration value, the channel is not selected and the second channel selection signal fails.

[0014] Specifically, the spatiotemporal discretization control method further includes: acquiring a coupling enable signal, a data selection signal, and an optional time configuration value; providing the optional time configuration value when the coupling enable signal fails; acquiring the second part of the spatial configuration value or the value of the second part of the spatial configuration value plus 1 when the coupling enable signal is valid; providing the value of the second part of the spatial configuration value plus 1 or the second part of the spatial configuration value if the data selection signal is valid; and providing the optional time configuration value if the data selection signal fails.

[0015] Specifically, the spatiotemporal discretization control method further includes a time discretization mode, which includes: obtaining the optional time configuration value as the time configuration value; or obtaining the value of the second part of the spatial configuration value plus 1, or the second part of the spatial configuration value as the time configuration value; wherein the time configuration value corresponds to the duty cycle of the target PWM signal; the time configuration value is a J-bit binary number, where J is a positive integer greater than or equal to 1; obtaining a time grouping value; the time grouping value is used to determine the number of sub-PWM signals when the target PWM signal is equivalent to a sub-PWM signal, and the duty cycle of the target PWM signal is equal to 2. AThe sum of the duty cycles of the sub-PWM signals; the time grouping value is A; where A is a positive integer less than or equal to J and greater than or equal to 1; obtain the count value; based on the time grouping value, divide the count value into a first part and a second part; wherein the first part of the count value includes the remaining bits of the count value except for the high A bits, representing the sequence number of the count value in the count value group; the second part of the count value includes the high A bits of the count value, representing the sequence number of the count value group in which the count value is located; based on the time grouping value, divide the time configuration value into a first part and a second part; wherein the first part of the time configuration value includes the low A bits of the time configuration value, used to determine the sequence number of the count value group; the second part of the time configuration value includes the remaining bits of the time configuration value except for the low A bits, which are related to the duty cycles of the sub-PWM signals. The process involves: determining the relative position of the count value; acquiring the operating mode control signal; comparing the second part of the bit-reversed count value with the first part of the time configuration value; wherein, when the second part of the bit-reversed count value is less than or equal to the first part of the time configuration value, the count value group is selected, and the count value group selection signal is active; and, when the operating mode control signal requires the count value in the count value group to be selected in bit-reversed order and the count value group selection signal is active, acquiring the first part of the bit-reversed count value and the value of the second part of the time configuration value plus 1, comparing the first part of the bit-reversed count value with the value of the second part of the time configuration value plus 1; wherein, when the first part of the bit-reversed count value is less than the value of the second part of the time configuration value plus 1, the count value is selected, and the count value selection signal is active.

[0016] Specifically, the spatiotemporal discretization control method further includes comparing the second part of the bit-reversed count value with the first part of the time configuration value; and also includes that when the second part of the bit-reversed count value is greater than the first part of the time configuration value, the count value group is not selected, and the count value group selection signal is in a failed state.

[0017] Specifically, in the spatiotemporal discretization control method, when the count value group selection signal is valid, the number of selected count values ​​in the count value group is the decimal number corresponding to the value of the second part of the time configuration value plus 1; or, when the count value group selection signal is invalid, the number of selected count values ​​in the count value group is the decimal number corresponding to the value of the second part of the time configuration value.

[0018] Specifically, the spatiotemporal discretization control method further includes the following: when the working mode control signal requires the selection of the count value in the count value group in a bit-reversed manner and the count value group selection signal is valid, if the first part of the count value after bit reversal is greater than or equal to the value of the second part of the time configuration value plus 1, the count value is not selected and the count value selection signal is invalid.

[0019] Specifically, the spatiotemporal discretization control method further includes, when the working mode control signal requires the selection of a count value in the count value group in a bit-reversed manner and the count value group selection signal is invalid, obtaining a first part of the bit-reversed count value and a second part of the time configuration value; when the first part of the bit-reversed count value is less than the second part of the time configuration value, the count value is selected and the count value selection signal is valid; when the first part of the bit-reversed count value is greater than or equal to the second part of the time configuration value, the count value is not selected and the count value selection signal is invalid.

[0020] This application also relates to a spatiotemporal discretization control method, including a time discretization mode, comprising: acquiring a time configuration value; the time configuration value corresponding to the duty cycle of a target PWM signal; wherein the time configuration value is a J-bit binary number, where J is a positive integer greater than or equal to 1; acquiring a time grouping value; the time grouping value is used to determine the number of sub-PWM signals corresponding to when the target PWM signal is equivalent to a sub-PWM signal, and the duty cycle of the target PWM signal is equal to 2. AThe sum of the duty cycles of the sub-PWM signals; the time grouping value is A; where A is a positive integer less than or equal to J and greater than or equal to 1; obtain the count value; based on the time grouping value, divide the count value into a first part and a second part; wherein the first part of the count value includes the remaining bits of the count value except for the high A bits, representing the sequence number of the count value in the count value group; the second part of the count value includes the high A bits of the count value, representing the sequence number of the count value group in which the count value is located; based on the time grouping value, divide the time configuration value into a first part and a second part; wherein the first part of the time configuration value includes the low A bits of the time configuration value, used to determine the sequence number of the count value group; the second part of the time configuration value includes the remaining bits of the time configuration value except for the low A bits, which, together with the sub-PWM signals, form a time configuration value. The signal's duty cycle is relevant; the second part of the bit-reversed count value is compared with the first part of the time configuration value; wherein, when the second part of the bit-reversed count value is less than or equal to the first part of the time configuration value, the count value group is selected, and the count value group selection signal is valid; and, when the operating mode control signal requires the count value in the count value group to be selected in bit-reversed manner and the count value group selection signal is valid, the first part of the bit-reversed count value and the value of the second part of the time configuration value plus 1 are obtained, and the first part of the bit-reversed count value and the value of the second part of the time configuration value plus 1 are compared; wherein, when the first part of the bit-reversed count value is less than the value of the second part of the time configuration value plus 1, the count value is selected, and the count value selection signal is valid.

[0021] Specifically, the spatiotemporal discretization control method further includes comparing the second part of the bit-reversed count value with the first part of the time configuration value; and also includes that when the second part of the bit-reversed count value is greater than the first part of the time configuration value, the count value group is not selected, and the count value group selection signal is in a failed state.

[0022] Specifically, in the spatiotemporal discretization control method, when the count value group selection signal is valid, the number of selected count values ​​in the count value group is the decimal number corresponding to the value of the second part of the time configuration value plus 1; or, when the count value group selection signal is invalid, the number of selected count values ​​in the count value group is the decimal number corresponding to the value of the second part of the time configuration value.

[0023] Specifically, the spatiotemporal discretization control method further includes the following: when the working mode control signal requires the selection of the count value in the count value group in a bit-reversed manner and the count value group selection signal is valid, if the first part of the count value after bit reversal is greater than or equal to the value of the second part of the time configuration value plus 1, the count value is not selected and the count value selection signal is valid.

[0024] Specifically, the spatiotemporal discretization control method further includes, when the working mode control signal requires the selection of a count value in the count value group in a bit-reversed manner and the count value group selection signal is invalid, obtaining a first part of the bit-reversed count value and a second part of the time configuration value; when the first part of the bit-reversed count value is less than the second part of the time configuration value, the count value is selected and the count value selection signal is valid; when the first part of the bit-reversed count value is greater than or equal to the second part of the time configuration value, the count value is not selected and the count value selection signal is invalid.

[0025] This application also relates to a spatiotemporal discretization control circuit, comprising a spatial discretization module configured to receive spatial configuration values ​​and spatial grouping values; wherein the spatial configuration value represents the workload that the spatiotemporal discretization control circuit needs to output, the spatial configuration value is an I-bit binary number, where I is a positive integer greater than or equal to 1; the spatial grouping value is used to divide the workload into 2... NThe space group consists of several sub-workload groups; each sub-workload group includes a different number of sub-workloads; the space group value is N, where N is a positive integer less than or equal to 1 and greater than or equal to 1; including: an address register configured to store and provide the address value of the channel; an address value grouping unit electrically connected to the address register, configured to receive the address value of the channel, and under the action of the space group value, divide the address value of the channel into a first part and a second part and output them respectively; wherein, the first part of the address value of the channel includes the remaining bits of the address value of the channel except for the high N bits, representing the sequence number of the channel in the channel group; the second part of the address value of the channel includes the high N bits of the address value of the channel, representing the sequence number of the channel group to which the channel belongs; a space configuration value grouping unit configured to receive the space configuration value, and under the action of the space group value, divide the space configuration value into a first part and a second part; wherein, the first part of the space configuration value includes the low N bits of the space configuration value, which are related to the sequence number of the channel group. Related; the second part of the spatial configuration value includes the remaining bits of the spatial configuration value excluding the lower N bits, which is related to the number of selected channels in the channel group; a first address comparator, electrically connected to the spatial configuration value grouping unit and the address grouping unit, is configured to compare the first part of the spatial configuration value with the second part of the address value of the channel after bit reversal and generate a first channel selection signal based on the comparison result; an incremental selection unit, electrically connected to the output of the spatial configuration value grouping unit and the first address comparator, is configured to increment the second part of the spatial configuration value by 1, and under the control of the first channel selection signal, select the second part of the spatial configuration value or the value of the second part of the spatial configuration value plus 1 for output; wherein, when the second part of the address value of the channel after bit reversal is less than or equal to the first part of the spatial configuration value, the first channel selection signal is valid, and the output of the incremental selection unit is the value of the second part of the spatial configuration value plus 1.

[0026] Specifically, in the spatiotemporal discretization control circuit, the ports of the second output terminal of the address grouping unit are electrically connected to the ports of the second input terminal of the first address comparator in reverse order.

[0027] Specifically, in the aforementioned spatiotemporal discretization control circuit, when the second part of the address value of the channel after bit reversal is greater than the first part of the spatial configuration value, the first channel selection signal generated by the first address comparator is in a failed state, and the output of the incremental selectable unit is the second part of the spatial configuration value.

[0028] Specifically, in the spatiotemporal discretization control method, when the first channel selection signal is valid, the number of channels selected in the channel group is the decimal number corresponding to the value of the second part of the spatial configuration value plus 1; or, when the first channel selection signal is invalid, the number of channels selected in the channel group is the decimal number corresponding to the value of the second part of the spatial configuration value.

[0029] Specifically, the spatiotemporal discretization control circuit further includes a second address comparator electrically connected to the output of the address grouping unit and the incremental selectable unit, configured to compare the first part of the address value of the channel with the output of the incremental selectable unit and generate a second channel selection signal based on the comparison result; wherein, when the first channel selection signal is valid, the second channel selection signal generated by the second address comparator is valid when the first part of the address value of the channel is less than the value of the second part of the spatial configuration value plus 1; or, the second channel selection signal generated by the second address comparator is invalid when the first part of the address value of the channel is greater than or equal to the value of the second part of the spatial configuration value plus 1.

[0030] Specifically, in the aforementioned spatiotemporal discretization control circuit, when the first channel selection signal is in a failed state, the second channel selection signal generated by the second address comparator is in a valid state when the first part of the channel address value is less than the second part of the spatial configuration value; when the first part of the channel address value is greater than or equal to the second part of the spatial configuration value, the second channel selection signal generated by the second address comparator is in a failed state.

[0031] Specifically, the spatiotemporal discretization control circuit further includes: a reverse selection unit electrically connected to the address grouping unit, configured to perform a bit-reversal operation on a first part of the address value of the channel, and under the control of the working mode control signal, select the first part of the address value of the channel or the first part of the bit-reversed channel address value for output; and a second address comparator electrically connected to the output terminals of the reverse selection unit and the incremental selection unit, configured to compare the output of the reverse selection unit with the output of the incremental selection unit and generate a second channel selection signal based on the comparison result; wherein, when the working mode control signal requires the channel to be selected in a bit-reversal manner, the output of the reverse selection unit is the first part of the bit-reversed address value of the channel; or, when the working mode control signal requires the channel to be selected in a sequential manner, the output of the reverse selection unit is the first part of the address value of the channel.

[0032] Specifically, in the aforementioned spatiotemporal discretization control circuit, when the operating mode control signal requires the channel to be selected in a bit-reversed manner and the first channel selection signal is valid, the second channel selection signal generated by the second address comparator is valid when the first part of the address value of the bit-reversed channel is less than the value of the second part of the spatial configuration value plus 1; the second channel selection signal generated by the second address comparator is invalid when the first part of the address value of the bit-reversed channel is greater than or equal to the value of the second part of the spatial configuration value plus 1.

[0033] Specifically, in the aforementioned spatiotemporal discretization control circuit, when the operating mode control signal requires the channel to be selected in a bit-reversed manner and the first channel selection signal is invalid, the second channel selection signal generated by the second address comparator is valid when the first part of the address value of the bit-reversed channel is less than the second part of the spatial configuration value; the second channel selection signal generated by the second address comparator is invalid when the first part of the address value of the bit-reversed channel is greater than or equal to the second part of the spatial configuration value.

[0034] Specifically, in the spatiotemporal discretization control circuit, the reverse order selection unit includes a reverse order component electrically connected to the address grouping unit, configured to perform a bit-reverse operation on a first portion of the address value of the channel; and a first multiplexer electrically connected to the address grouping unit and the reverse order component, configured to select one of the first portion of the address value of the channel or the first portion of the address value of the channel after bit reversal, and output it under the control of the operating mode control signal.

[0035] Specifically, in the spatiotemporal discretization control circuit, the incremental selectable unit includes an adder electrically connected to the spatial configuration value grouping unit, configured to increment the second part of the spatial configuration value by 1; and a second multiplexer electrically connected between the spatial configuration value grouping unit and the adder and electrically connected to the output of the first address comparator, configured to select, under the control of the first channel selection signal, either the second part of the spatial configuration value or the value obtained by incrementing the second part of the spatial configuration value by 1 for output.

[0036] Specifically, the spatiotemporal discretization control circuit further includes a mode selection unit electrically connected to the output of the incremental selectable unit, configured to transmit the output of the incremental selectable unit under the control of a coupling enable signal; and a data selector electrically connected to the mode selection unit, configured to receive an optional time configuration value and the output of the incremental selectable unit transmitted by the mode selection unit, and select one of the optional time configuration value or the output of the mode selection unit under the control of the data selection signal.

[0037] Specifically, the spatiotemporal discretization control circuit further includes a time discretization module electrically connected to the data selector, configured to receive time grouping values ​​and the output of the data selector, and use the output of the data selector as a time configuration value to generate a count value selection signal based on the time configuration value; wherein, the time configuration value corresponds to the duty cycle of the target PWM signal; the time configuration value is a J-bit binary number, where J is a positive integer greater than or equal to 1; the time grouping value is used to determine the number corresponding to when the target PWM signal is equivalent to a sub-PWM signal, and the duty cycle of the target PWM signal is equal to 2. AThe sum of the duty cycles of the sub-PWM signals; the time grouping value is A; where A is a positive integer less than or equal to J and greater than or equal to 1; including a counter configured to perform cyclic counting and output a count value; wherein the count value range of the counter corresponds to the period of the target PWM signal; a count value grouping unit electrically connected to the counter, configured to divide the count value into a first part and a second part based on the time grouping value and output them respectively; the first part of the count value includes the remaining bits of the count value except for the high A bits; the second part of the count value includes the high A bits of the count value; wherein the first part of the count value represents the sequence number of the count value in the count value group, and the first part of the count value represents the sequence number of the count value in the count value group. The second part represents the sequence number of the count value group to which the count value belongs; the time configuration value grouping unit, electrically connected to the data selector, is configured to divide the time configuration value into a first part and a second part based on the time grouping value and output them respectively; wherein, the first part of the time configuration value includes the low A bits of the time configuration value, which are related to the sequence number of the count value group; the second part of the time configuration value includes the remaining bits other than the low A bits of the time configuration value, which are related to the duty cycle of the sub-PWM signal; the first count value comparator, electrically connected to the time configuration value grouping unit and the count value grouping unit, is configured to compare the first part of the time configuration value with the count value after bit reversal. The second part compares and generates a count value grouping selection signal based on the comparison result; the incremental selection unit, electrically connected to the time configuration value grouping unit and the first count value comparator, is configured to increment the second part of the time configuration value by 1, and under the control of the count value grouping selection signal, selects the value of the second part of the time configuration value after incrementing by 1 or the second part of the time configuration value for output; the reverse selection unit, electrically connected to the count value grouping unit, is configured to reverse the bit order of the first part of the count value, and under the control of the working mode control signal, selects the first part of the count value or the bit-reversed first part of the count value for output; the third Two counter value comparators, electrically connected to the reverse selection unit and the incremental selection unit, are configured to compare the output of the reverse selection unit with the output of the incremental selection unit and generate a counter value selection signal based on the comparison result. Specifically, when the second part of the bit-reversed counter value is less than or equal to the first part of the time configuration value, the counter value group selection signal generated by the first counter value comparator is valid. Furthermore, the output of the incremental selection unit is the value obtained by adding 1 to the second part of the time configuration value. When the operating mode control signal requires the selection of a counter value in a counter value group in a bit-reversed manner, the output of the reverse selection unit is the first part of the bit-reversed counter value.The second counter comparator compares the first part of the bit-reversed counter value with the second part of the time configuration value incremented by 1. When the first part of the bit-reversed counter value is less than the second part of the time configuration value incremented by 1, the counter selection signal generated by the second counter comparator is valid.

[0038] Specifically, in the spatiotemporal discretization control circuit, the port of the second output terminal of the counting value grouping unit is electrically connected to the port of the second input terminal of the first counting value comparator in reverse order.

[0039] Specifically, in the aforementioned spatiotemporal discretization control circuit, the first counter value comparator compares the first part of the time configuration value with the second part of the counter value after bit reversal. When the second part of the counter value after bit reversal is greater than the first part of the time configuration value, the counter value grouping selection signal is in a failed state.

[0040] Specifically, in the aforementioned spatiotemporal discretization control circuit, when the count value grouping selection signal is in a failed state, the output of the incremental selection unit is the value of the second part of the time configuration value.

[0041] Specifically, in the aforementioned spatiotemporal discretization control circuit, when the operating mode control signal requires the selection of the count value in the count value group in a sequential manner, the output of the reverse selection unit is the first part of the count value after bit reversal.

[0042] Specifically, in the spatiotemporal discretization control circuit, when the count value group selection signal is valid, the number of selected count values ​​in the count value group is the decimal number corresponding to the value of the second part of the time configuration value plus 1; or, when the count value group selection signal is invalid, the number of selected count values ​​in the count value group is the decimal number corresponding to the value of the second part of the time configuration value.

[0043] Specifically, in the aforementioned spatiotemporal discretization control circuit, when the operating mode control signal requires the selection of the count value in the count value group in a bit-reversed manner and the count value selection signal is valid, the count value selection signal generated by the second count value comparator is valid when the first part of the bit-reversed count value is less than the value of the second part of the time configuration value plus 1; the count value selection signal generated by the second count value comparator is invalid when the first part of the bit-reversed count value is greater than or equal to the value of the second part of the time configuration value plus 1.

[0044] Specifically, in the aforementioned spatiotemporal discretization control circuit, when the operating mode control signal requires the selection of the count value in the count value group in a bit-reversed manner and the count value selection signal is invalid, the count value selection signal generated by the second count value comparator is valid when the first part of the bit-reversed count value is less than the second part of the time configuration value; and the count value selection signal generated by the second count value comparator is invalid when the first part of the bit-reversed count value is greater than or equal to the second part of the time configuration value.

[0045] This application also relates to an electronic device including a spatiotemporal discretization control circuit as described in any of the preceding claims.

[0046] This application also relates to a spatiotemporal discretization control circuit, including a time discretization module configured to receive time grouping values ​​and time configuration values, and generate a count value selection signal based on the time configuration values; wherein, the time configuration value corresponds to the duty cycle of the target PWM signal; the time configuration value is a J-bit binary number, where J is a positive integer greater than or equal to 1; the time grouping value is used to determine the number of sub-PWM signals corresponding to when the target PWM signal is equivalent to a sub-PWM signal, and the duty cycle of the target PWM signal is equal to 2. AThe sum of the duty cycles of the sub-PWM signals; the time grouping value is A; where A is a positive integer less than or equal to J and greater than or equal to 1; including a counter configured to perform cyclic counting and output a count value; wherein the count value range of the counter corresponds to the period of the target PWM signal; a count value grouping unit electrically connected to the counter, configured to divide the count value into a first part and a second part based on the time grouping value and output them respectively; the first part of the count value includes the remaining bits of the count value except for the high A bits; the second part of the count value includes the high A bits of the count value; wherein the first part of the count value represents the sequence number of the count value in the count value group, and the first part of the count value represents the sequence number of the count value in the count value group. The second part represents the sequence number of the count value group to which the count value belongs; the time configuration value grouping unit, electrically connected to the data selector, is configured to divide the time configuration value into a first part and a second part based on the time grouping value and output them respectively; wherein, the first part of the time configuration value includes the low A bits of the time configuration value, which are related to the sequence number of the count value group; the second part of the time configuration value includes the remaining bits other than the low A bits of the time configuration value, which are related to the duty cycle of the sub-PWM signal; the first count value comparator, electrically connected to the time configuration value grouping unit and the count value grouping unit, is configured to compare the first part of the time configuration value with the count value after bit reversal. The second part compares and generates a count value grouping selection signal based on the comparison result; the incremental selection unit, electrically connected to the time configuration value grouping unit and the first count value comparator, is configured to increment the second part of the time configuration value by 1, and under the control of the count value grouping selection signal, selects the value of the second part of the time configuration value after incrementing by 1 or the second part of the time configuration value for output; the reverse selection unit, electrically connected to the count value grouping unit, is configured to reverse the bit order of the first part of the count value, and under the control of the working mode control signal, selects the first part of the count value or the bit-reversed first part of the count value for output; the third Two counter value comparators, electrically connected to the reverse selection unit and the incremental selection unit, are configured to compare the output of the reverse selection unit with the output of the incremental selection unit and generate a counter value selection signal based on the comparison result. Specifically, when the second part of the bit-reversed counter value is less than or equal to the first part of the time configuration value, the counter value group selection signal generated by the first counter value comparator is valid. Furthermore, the output of the incremental selection unit is the value obtained by adding 1 to the second part of the time configuration value. When the operating mode control signal requires the selection of a counter value in a counter value group in a bit-reversed manner, the output of the reverse selection unit is the first part of the bit-reversed counter value.The second counter comparator compares the first part of the bit-reversed counter value with the second part of the time configuration value incremented by 1. When the first part of the bit-reversed counter value is less than the second part of the time configuration value incremented by 1, the counter selection signal generated by the second counter comparator is valid.

[0047] Specifically, in the spatiotemporal discretization control circuit, the port of the second output terminal of the counting value grouping unit is electrically connected to the port of the second input terminal of the first counting value comparator in reverse order.

[0048] Specifically, in the aforementioned spatiotemporal discretization control circuit, the first counter value comparator compares the first part of the time configuration value with the second part of the counter value after bit reversal. When the second part of the counter value after bit reversal is greater than the first part of the time configuration value, the counter value grouping selection signal is in a failed state.

[0049] Specifically, in the aforementioned spatiotemporal discretization control circuit, when the count value grouping selection signal is in a failed state, the output of the incremental selection unit is the value of the second part of the time configuration value.

[0050] Specifically, in the aforementioned spatiotemporal discretization control circuit, when the operating mode control signal requires the selection of the count value in the count value group in a sequential manner, the output of the reverse selection unit is the first part of the count value after bit reversal.

[0051] Specifically, in the spatiotemporal discretization control circuit, when the count value group selection signal is valid, the number of selected count values ​​in the count value group is the decimal number corresponding to the value of the second part of the time configuration value plus 1; or, when the count value group selection signal is invalid, the number of selected count values ​​in the count value group is the decimal number corresponding to the value of the second part of the time configuration value.

[0052] Specifically, in the aforementioned spatiotemporal discretization control circuit, when the operating mode control signal requires the selection of the count value in the count value group in a bit-reversed manner and the count value selection signal is valid, the count value selection signal generated by the second count value comparator is valid when the first part of the bit-reversed count value is less than the value of the second part of the time configuration value plus 1; the count value selection signal generated by the second count value comparator is invalid when the first part of the bit-reversed count value is greater than or equal to the value of the second part of the time configuration value plus 1.

[0053] Specifically, in the aforementioned spatiotemporal discretization control circuit, when the operating mode control signal requires the selection of the count value in the count value group in a bit-reversed manner and the count value selection signal is invalid, the count value selection signal generated by the second count value comparator is valid when the first part of the bit-reversed count value is less than the second part of the time configuration value; and the count value selection signal generated by the second count value comparator is invalid when the first part of the bit-reversed count value is greater than or equal to the second part of the time configuration value.

[0054] Specifically, in the spatiotemporal discretization control circuit, the reverse selection unit includes a reverse component electrically connected to the count value grouping unit, configured to perform a bit-reverse operation on a first part of the count value; and a first selector electrically connected to the count value grouping unit and the reverse component, configured to select one of the first part of the count value or the bit-reverse first part of the count value and output it under the control of the working mode control signal.

[0055] Specifically, in the spatiotemporal discretization control circuit, the incremental selection unit includes an adder electrically connected to the time configuration value grouping unit and configured to increment the second part of the time configuration value by 1; and a second selector electrically connected between the time configuration value grouping unit and the adder and electrically connected to the output of the first count value comparator, configured to select, under the control of the count value grouping selection signal, either the second part of the time configuration value or the value obtained by incrementing the second part of the time configuration value by 1 for output.

[0056] This application also relates to an electronic device including a spatiotemporal discretization control circuit as described in any of the preceding claims.

[0057] The spatiotemporal discretization control circuit and method proposed in this application can achieve uniform discretization of the dissipated energy of the power consumption unit array in both time and space dimensions, avoiding the concentration effect of dissipated energy in time and / or space dimensions and solving the problems of hot spot concentration and interference superposition in the system. Utilizing a more optimized algorithm, the hardware and dispersion algorithm overhead are significantly reduced. Attached Figure Description

[0058] The preferred embodiments of this application will now be described in further detail with reference to the accompanying drawings, wherein: Figure 1 The figure shown is a spatiotemporal discretization control method according to an embodiment of this application; Figure 2 The diagram shown is a schematic representation of the discrete effect of a PWM signal according to an embodiment of this application. Figure 3The image shows a spatiotemporal discretization control method according to another embodiment of this application; Figure 4 The diagram shows a spatiotemporal discretization control circuit according to an embodiment of this application; Figure 5 The diagram shown is a schematic diagram of the electrical connections of a local circuit in a spatiotemporal discretization control circuit according to an embodiment of this application; Figure 6 The diagram shown is a schematic representation of an application scenario of a spatiotemporal discretization control circuit according to an embodiment of this application. Figure 7 The diagram shown is a schematic representation of an application scenario for a spatiotemporal discretization control circuit according to another embodiment of this application. Figure 8 The figure shown is a simulation diagram of the thermodynamic distribution of the junction temperature of the power consumption unit array in the existing scheme; Figure 9 The figure shown is a simulation diagram of the junction temperature thermodynamic distribution of a power consumption cell array according to an embodiment of this application; Figure 10 The diagram shown is an EMI / spectrum simulation diagram according to an embodiment of this application. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0060] In the following detailed description, reference can be made to the accompanying drawings, which form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to implement the technical solutions of the present application. It should be understood that other embodiments may also be utilized, or structural, logical, or electrical changes may be made to the embodiments of the present application.

[0061] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. The lines connecting the units in the accompanying drawings are merely for illustrative purposes, indicating that at least the units at both ends of the line are communicating with each other, and are not intended to prevent unconnected units from communicating. Furthermore, the number of lines between two units is intended to indicate at least the number of signals involved in communication between the two units or at least the number of output terminals, and is not intended to limit communication between the two units to only the signals shown in the figures.

[0062] Existing thermal management solutions (such as CPU thermal throttling and intelligent power modules (IPMs)) rely on integrated temperature sensors (TSVs / TMUs) to monitor hotspots in real time. Once overheating is detected, power is reduced through a negative feedback loop. This solution is relatively large in terms of circuit area and power consumption. Furthermore, embedding a large number of sensors in a high-density array significantly increases chip area and wiring complexity, resulting in high costs. In addition, by the time the sensors detect a temperature rise, hotspots have often already formed or even spread. This passive adjustment mechanism is lag-dependent, making the system unable to cope with nanosecond-level transient thermal shocks and failing to fundamentally alleviate the formation of hotspots.

[0063] To reduce EMI, existing solutions employ multi-pulse PWM or phase-shift PWM techniques. These solutions typically require independent high-precision counters, comparators, or complex waveform lookup tables for each sub-pulse or output channel, resulting in significant hardware overhead. While some existing solutions offer random generation algorithms for discrete PWM signals to mitigate EMI, these algorithms are costly, and even when implemented, they cannot completely eliminate the risk of random energy accumulation. Moreover, when the power consumption unit array is a two-dimensional array of tens or even hundreds of units, this complex "one-to-one" control logic leads to a linear or even exponential increase in hardware resources (number of logic gates, register resources), resulting in extremely high costs and making it difficult to apply in low-cost MCUs or high-density SoCs. Furthermore, in existing solutions, the spatial and temporal control of energy dissipation in the power consumption units requires two independent sets of logic circuits, leading to circuit redundancy.

[0064] The spatiotemporal discretization control circuit and method proposed in this application can achieve uniform discretization of the dissipated energy of the power consumption unit in the time and / or spatial dimensions, avoiding the concentration effect of dissipated energy in the time and / or spatial dimensions, and solving the problems of hot spot concentration and interference superposition in the system. This application greatly reduces the overhead of hardware and dispersion algorithms, enabling the system to have thermal and noise management capabilities. The spatiotemporal discretization control circuit proposed in this application can be implemented as an independent chip or circuit without consuming logic gates.

[0065] The spatiotemporal discretization control method proposed in this application may include a spatial discretization mode configured to disperse dissipated energy in the spatial dimension to achieve thermal efficiency management of the power consumption unit array; and / or may also include a time discretization mode configured to disperse dissipated energy in the time dimension to achieve EMI management of the power consumption unit array.

[0066] The power consumption unit array involved in this application may include, for example, an LED driver array, a multi-core processor array, an IO driver array, an array of devices such as resistors, or a power MOSFET array.

[0067] According to one embodiment of this application, the spatiotemporal discretization control method can be executed by a control circuit of a power consumption unit array (hereinafter referred to as the control circuit). The control circuit determines its operating mode under the control of an operating mode control signal.

[0068] According to one embodiment, when the control circuit operates in spatial discretization mode, it receives spatial configuration values ​​and spatial grouping values. The spatial configuration values ​​represent the workload that the control circuit needs to output, which can be analog quantities such as current or voltage. The spatial grouping values ​​are used to determine the degree of discretization of the workload, equivalent to 2-1. N Each sub-workload group contains sub-workloads with different values, 2 N The sum of the sub-workloads included in each sub-workload group equals the total workload. The space grouping value is set by the user according to actual needs, and the space grouping value is N, where N is a positive integer greater than or equal to 1 and less than or equal to 1. The space configuration value is an I-bit binary number, where I is a positive integer greater than or equal to 1.

[0069] According to one embodiment, the control circuit can obtain the address value of the channel, which is an I-bit binary number.

[0070] In one embodiment of this application, the channels of the control circuit are divided into 2 according to the spatial grouping value. N There are 2 channel groups, each channel group includes 2 I-N There are 2 channels, each corresponding one-to-one with a power consumption unit. N The sum of the sub-workloads output by each channel group is the workload.

[0071] According to one embodiment of this application, bit reversal processing can be implemented by a lookup table or by using processing software with bit reversal processing capabilities.

[0072] According to one embodiment of this application, the address value of a channel is divided into a first part and a second part based on a spatial grouping value. The first part of the channel's address value includes the remaining bits of the channel's address value excluding the high N bits, representing the channel's sequence number in the channel group. The second part of the channel's address value includes the high N bits of the channel's address value, representing the sequence number of the channel group to which the channel belongs.

[0073] According to one embodiment of this application, a spatial configuration value is divided into a first part and a second part based on a spatial grouping value. The first part of the spatial configuration value includes the lower N bits of the spatial configuration value, which are related to the sequence number of the channel group. The second part of the spatial configuration value includes the remaining bits of the spatial configuration value excluding the lower N bits, which are related to the number of selected channels in the channel group.

[0074] Both channel and spatial configuration values ​​are divided using the same spatial grouping value, ensuring that the number of channel groups is the same as the number of subworkload groups. The number of channels included in a channel group corresponds to the number of subworkloads included in a subworkload group.

[0075] The space configuration value increases with workload, with different workloads corresponding to different space configuration values. Sub-workload groups are selected sequentially, and the workload increase is allocated to them. The first part of the space configuration value is related to the number of selected sub-workload groups. The second part of the space configuration value is related to the number of sub-workloads within the selected sub-workload groups. The channel address value is obtained, and the second part of the channel address value is bit-reversed to find the corresponding channel group's available location in physical space. The first part of the space configuration value is compared with the bit-reversed second part of the channel address value. Channel groups that meet the criteria are selected, distributing the workload increase to channel groups with relatively low energy concentration effects in physical space, thus avoiding localized thermal concentration in the power consumption unit array. During this process, the sequence numbers of the selected and unselected channel groups are also determined. In both the selected and unselected channel groups, the first part of the spatial configuration value is compared with the second part of the channel address value after bit reversal. Channels that meet the criteria are selected. Channels are selected in a discrete manner, placing the selected channels in idle positions within the channel group, further enhancing the dispersion of energy dissipation by the power consumption unit. In one embodiment, the number of selected channels in the selected channel group is one more than the number of selected channels in the unselected channel group.

[0076] According to one embodiment, when the second part of the address value of the channel after bit reversal is less than or equal to the first part of the spatial configuration value, the channel group is selected, and the first channel selection signal is in an active state. When the second part of the address value of the channel after bit reversal is greater than the first part of the spatial configuration value, the channel group is not selected, and the first channel selection signal is in an inactive state.

[0077] According to one embodiment, when the first channel selection signal is active, the number of channels selected in the selected channel group is the decimal value corresponding to the second part of the spatial configuration value plus 1. When the first channel selection signal is inactive, the number of channels selected in the unselected channel group is the decimal value corresponding to the second part of the spatial configuration value. By selecting different numbers of channels in the selected and unselected channel groups, the increase in workload is evenly distributed among the channel groups.

[0078] In one embodiment, a first portion of the channel address value is compared with a second portion of the spatial configuration value. When the first portion of the channel address value is less than or equal to the second portion of the spatial configuration value, the channel is selected, and the second channel selection signal is active. When the first portion of the channel address value is greater than the second portion of the spatial configuration value, the channel is not selected, and the second channel selection signal is inactive. The control circuitry selects channels sequentially from the selected channel groups. In another embodiment, when the first portion of the channel address value is less than the second portion of the spatial configuration value, the channel is selected, and the second channel selection signal is active. When the first portion of the channel address value is greater than or equal to the second portion of the spatial configuration value, the channel is not selected, and the second channel selection signal is inactive. The control circuitry selects channels sequentially from the unselected channel groups.

[0079] According to one embodiment, the control circuit can also select channels in a sequential manner from the selected or unselected channel groups under the control of the operating mode control signal. In another embodiment, the control circuit can also select channels in a bit-reverse manner from the selected or unselected channel groups under the control of the operating mode control signal, such that the selected channels in the channel group are located in empty positions in the physical space of the channel group, further distributing the sub-workload.

[0080] In one embodiment, the second channel selection signal is active when a channel is selected, and inactive when a channel is not selected.

[0081] According to one embodiment of this application, the operating mode control signal requires the selection of a corresponding number of channels in a selected channel group in a sequential manner. A comparison is made between the first part of the channel address value and the second part of the spatial configuration value plus 1. When the first part of the channel address value is less than the second part of the spatial configuration value plus 1, the channel is selected, and the second channel selection signal is active. Alternatively, when the first part of the channel address value is greater than or equal to the second part of the spatial configuration value plus 1, the channel is not selected, and the second channel selection signal is inactive.

[0082] According to one embodiment of this application, the operating mode control signal requires the selection of a corresponding number of channels in the selected channel group in a bit-reversed manner. The first part of the bit-reversed channel address value is compared with the value of the second part of the spatial configuration value plus 1. When the first part of the bit-reversed channel address value is less than the value of the second part of the spatial configuration value plus 1, the channel is selected, and the second channel selection signal is active. Alternatively, when the first part of the bit-reversed channel address value is greater than or equal to the value of the second part of the spatial configuration value plus 1, the channel is not selected, and the second channel selection signal is inactive.

[0083] According to another embodiment, a corresponding number of channels are selected sequentially from the unselected channel groups. A first portion of the channel address value is compared with a second portion of the spatial configuration value. When the first portion of the channel address value is less than the second portion of the spatial configuration value, the channel is selected, and the second channel selection signal is active. Alternatively, when the first portion of the channel address value is greater than or equal to the second portion of the spatial configuration value, the channel is not selected, and the second channel selection signal is inactive.

[0084] According to one embodiment, a corresponding number of channels are selected from the unselected channel group using a bit-reversed method. The first part of the bit-reversed channel address value is compared with the second part of the spatial configuration value. When the first part of the bit-reversed channel address value is less than the second part of the spatial configuration value, the channel is selected, and the second channel selection signal is active. Alternatively, when the first part of the bit-reversed channel address value is greater than or equal to the second part of the spatial configuration value, the channel is not selected, and the second channel selection signal is inactive.

[0085] In the following description, the spatiotemporal discretization control method proposed in this application is illustrated using an 8-bit binary number as the spatial configuration value received by the control circuit and a spatial grouping value of 4 as an example. However, this does not imply any limitation on the spatial configuration values ​​or the number of channels involved in the spatiotemporal discretization control method proposed in this application; these can be set by the user according to actual needs.

[0086] The spatiotemporal discretization control method proposed in this application will be described below based on Table 1.

[0087] Table 1 Table 1 is a list of spatial configuration value dispersion in a spatiotemporal discretization control method according to an embodiment of this application. The first column of Table 1 is the decimal number corresponding to the spatial configuration value received by the control circuit; the second column is the spatial configuration value. Columns 3 to 18 are the number of channels selected in each channel group corresponding to the spatial configuration value, that is, the dispersion of the spatial configuration value.

[0088] In the embodiment of Table 1, when the control circuit receives a space configuration value of 00100001 (i.e., decimal number 33), the first part of the space configuration value includes the lower 4 bits (i.e., 0001), and the second part includes the remaining bits excluding the lower 4 bits (i.e., 0010). The control circuit includes 256 channels, and the channel address value is an 8-bit binary number. The channels of the control circuit are divided into 16 (2... 4 There are 15 channel groups. The high 4 bits of the channel address value constitute the first part of the channel address value, which increases from 0000 to 1111 with a step size of 1. Each binary number represents the sequence number of channel group G0 to channel group G15. Furthermore, within each channel group, the low 4 bits of the channel address value constitute the first part of the channel address value, which increases from 0000 to 1111 with a step size of 1. Each binary number represents a channel within that channel group. For channel address value 00000000, if the value of the second part (0000) after reversing its bits is less than the value of the first part of the space configuration value, then channel G0, containing this channel, is the selected channel group. Additionally, if the first part of the channel address value is also less than the second part of the space configuration value, then the channel is selected. Similarly, channel address values ​​00000001 and 00000010 are also selected channels. For channel address value 00000011, the value of its second part (0000) after reversing the bit order is less than the value of the first part of the space configuration value, while the first part of the channel address value (0011) is greater than the second part of the space configuration value (0001). Therefore, the channel is not selected. And so on. Therefore, the number of selected channels in channel group G0 is 3.

[0089] When the channel address value is 00010000, the second part of the channel address value, after reversing the bits (1000), is greater than the first part of the space configuration value (0001). Therefore, channel group G1, to which this channel belongs, is not selected. When the first part of the channel address value is less than the second part of the space configuration value, the channel is selected. Similarly, when the channel address value is 00010001, the channel remains in channel group G1 and is selected. For the channel address value 00010010, the second part of the channel address value, after reversing the bits, is greater than the first part of the space configuration value, while the first part of the channel address value is equal to the second part of the space configuration value; therefore, the channel is not selected. And so on. Therefore, the number of selected channels in channel group G1 is 2.

[0090] In the embodiment of Table 1, the second part of the channel address value after bit reversal is compared with the first part of the space configuration value, thereby realizing the selection of channel groups in a discrete manner and the selection of channels in the channel groups in a sequential manner, and distributing the increase in the space configuration value to the selected channel groups in a discrete manner.

[0091] Figure 1The illustration shows a spatiotemporal discretization control method according to an embodiment of this application. It should be understood that the flowchart in the accompanying drawings is merely illustrative. Those skilled in the art can adjust, combine, or split the order of steps without altering the technical effects of this application, and all such adjustments fall within the scope of protection of this application.

[0092] Step 101: Obtain the spatial grouping value.

[0093] Step 102: Obtain the channel address value. Based on the spatial grouping value, divide the channel address value into a first part and a second part.

[0094] Step 103: Obtain the space configuration value. Based on the space grouping value, divide the space configuration value into a first part and a second part.

[0095] Step 104: Obtain the operating mode control signal.

[0096] Step 105: Determine whether the second part of the channel address value after bit reversal is less than or equal to the first part of the space configuration value. If yes, proceed to step 106; otherwise, proceed to step 107.

[0097] Step 106: The channel group is selected, the first channel selection signal is set to active, and step 108 is executed.

[0098] Step 107: The channel group is not selected. Set the first channel selection signal to the invalid state and jump to step 113.

[0099] Step 108: Determine whether the operating mode control signal requires channel selection in reverse bit order. If yes, proceed to step 109; otherwise, proceed to step 110.

[0100] Step 109: Obtain the first part of the bit-reversed channel address value and the value of the second part of the space configuration value plus 1. Determine whether the first part of the bit-reversed channel address value is less than the value of the second part of the space configuration value plus 1. If yes, jump to step 111; otherwise, jump to step 112.

[0101] Step 110: Obtain the value of the second part of the space configuration value plus 1. Determine whether the first part of the channel address value is less than the value of the second part of the space configuration value plus 1. If yes, proceed to step 111; otherwise, proceed to step 112.

[0102] Step 111: The channel is selected, and the second channel selection signal is set to the active state.

[0103] Step 112: The channel is not selected, and the second channel selection signal is set to an invalid state.

[0104] Step 113: Determine whether the operating mode control signal requires channel selection in reverse bit order. If yes, proceed to step 114; otherwise, proceed to step 115.

[0105] Step 114: Obtain the first part of the channel address value after bit reversal. Determine whether the first part of the channel address value after bit reversal is less than the second part of the space configuration value. If yes, jump to step 111; otherwise, jump to step 112.

[0106] Step 115: Determine if the first part of the channel address value is less than the second part of the space configuration value. If yes, proceed to step 111; otherwise, proceed to step 112.

[0107] According to one embodiment, when the second channel selection signal is valid, the control circuit selects the corresponding channel and provides a sub-workload. Alternatively, when the second channel selection signal is invalid, the control circuit does not provide a sub-workload.

[0108] Optionally, under the control of the coupling enable signal, the control circuit can also ensure coordinated operation with other circuits and meet the corresponding requirements for the normal operation of other circuits by providing a first channel selection signal and providing the value of the second part of the spatial configuration value plus 1, or the value of the second part of the spatial configuration value. In this case, Figure 1 The spatiotemporal discretization control method shown further executes steps 117 to 119 after executing step 106 or step 107.

[0109] According to one embodiment of this application, in step 106, the channel group is selected, the first channel selection signal is set to an active state, and the process jumps to step 117. In step 107, the channel group is not selected, the first channel selection signal is set to an inactive state, and the process jumps to step 117.

[0110] Step 117: Determine if the coupling enable signal is valid. If yes, proceed to step 118; otherwise, proceed to step 119.

[0111] Step 118: Obtain the value of the second part of the spatial configuration value plus 1, and provide the first channel selection signal and the value of the second part of the spatial configuration value plus 1 or the second part of the spatial configuration value.

[0112] Step 119: Determine if the first channel selection signal is valid. If yes, proceed to step 108; otherwise, proceed to step 113.

[0113] In this application, the selected channel group is located in a currently idle physical position, and the number of selected channels in different channel groups can also be different. This makes the workload increment method discrete, effectively avoiding the thermal aggregation effect in the spatial dimension. Furthermore, the selected channels in the channel group are uniformly distributed in space, thereby optimizing the balance of energy dissipation distribution of the power unit array and significantly reducing the peak energy dissipation.

[0114] The spatiotemporal discretization method proposed in this application can also include a time discretization mode for discretizing the PWM signal, so that the energy dissipated by the power consumption unit array is uniformly distributed in the time dimension. This process can be understood as equivalently dividing the complete target PWM signal into multiple sub-PWM signals, so that the PWM signal output by the control circuit no longer consists of only a large pulse width, but is cut into multiple short pulses distributed throughout the entire period of the target PWM signal. This equivalent segmentation does not require additional circuitry and can be implemented using comparison logic, allowing energy to be concentrated at high frequencies and filtered out by filters, thereby reducing system EMI.

[0115] The period of the target PWM signal is used as the range of count values, and the duty cycle of the target PWM signal is used as the time configuration value. The duty cycle of the target PWM signal is the duration of the high level within a complete target PWM signal cycle.

[0116] When the target PWM signal is equivalent to 2 A When there is a sub-PWM signal, the count value range is divided into 2. A There are 2 count value groups, each count value group includes 2 B There are several count values. Where A is a positive integer greater than or equal to 1 and less than or equal to J, B is a positive integer greater than 0 and less than J, and the duty cycle of the target PWM signal is also divided into 2... A The duty cycle of each sub-PWM signal is distributed across 2. A Grouped into 2 count values. A The sub-PWM signal is obtained by selecting a number of count values ​​corresponding to the duty cycle of the sub-PWM signal from each count value group. During this process, the count value groups are selected in reverse bit order to maximize the time interval between the selected count value groups. As the duty cycle of the target PWM signal increases, different numbers of count values ​​are selected from both the selected and unselected count value groups. This discretizes the increase in the target PWM signal's duty cycle across the count value groups, reducing noise generated by the high-frequency PWM signal. Furthermore, by discretizing the selected count values ​​within the count value groups, the duty cycle of the sub-PWM signal can be further distributed, preventing continuous high levels within the sub-PWM signal and optimizing EMI performance.

[0117] According to one embodiment, when the control circuit operates in time discretization mode, it can acquire time grouping values. These time grouping values ​​determine the number of sub-PWM signals that the target PWM signal is equivalent to, and thus determine the degree of discretization of the target PWM signal. When the time grouping value is A, the target PWM signal is divided into 2... A The duty cycle of the target PWM signal is equal to 2. A The sum of the duty cycles of each sub-PWM signal. The time grouping value can be specified by the user according to actual needs.

[0118] According to one embodiment, the control circuit can also receive a timing configuration value. The timing configuration value corresponds to the duty cycle of the target PWM signal. The timing configuration value may include a J-bit binary number, where J is a positive integer greater than or equal to 1.

[0119] According to one embodiment, the control circuit can also acquire a count value, which is a J-bit binary number.

[0120] According to one embodiment, a time configuration value is divided into a first part and a second part based on a time grouping value. The first part of the time configuration value includes the lower A bits of the time configuration value, used to determine the count value grouping sequence number. The second part of the time configuration value includes the remaining bits of the time configuration value excluding the lower A bits, used to determine the duty cycle of the sub-PWM signal.

[0121] In one embodiment, the count value is divided into two parts based on the time grouping value. The first part of the count value includes the remaining bits except for the high A bits, representing the sequence number of the count value in the count value group. The second part of the count value includes the high A bits, representing the sequence number of the count value group to which the count value belongs.

[0122] According to one embodiment, when the second part of the bit-reversed count value is less than or equal to the first part of the time configuration value, the count value group containing the count value is selected, and the count value group selection signal is in a valid state. Alternatively, when the second part of the bit-reversed count value is greater than the first part of the time configuration value, the count value group containing the count value is not selected, and the count value group selection signal is in a disabled state.

[0123] According to one embodiment, when a count value group is selected, the number of selected count values ​​in the count value group is the decimal number corresponding to the value of the second part of the time configuration value plus 1. When a count value group is not selected, the number of selected count values ​​in the count value group is the decimal number corresponding to the second part of the time configuration value. By selecting different numbers of count values ​​in the selected and unselected count value groups, the increase in the duty cycle of the target PWM signal is evenly distributed among the count value groups, and the increase in the duty cycle of the sub-PWM signal also exhibits uniform dispersion.

[0124] According to one embodiment, a first portion of the count value is compared with a second portion of the time configuration value. When the first portion of the count value is less than or equal to the second portion of the time configuration value, the count value is selected, and the count value selection signal is active. When the first portion of the count value is greater than the second portion of the time configuration value, the count value is not selected, and the count value selection signal is inactive. The control circuit selects count values ​​sequentially from the selected count value groups. In one embodiment, when the first portion of the count value is less than the second portion of the time configuration value, the count value is selected, and the count value selection signal is active. When the first portion of the count value is greater than or equal to the second portion of the time configuration value, the count value is not selected, and the count value selection signal is inactive. The control circuit selects count values ​​sequentially from the unselected count value groups.

[0125] According to one embodiment, the control circuit can also select count values ​​sequentially from the selected count value group or the unselected count value group under the control of the operating mode control signal. In another embodiment, the control circuit can also select count values ​​in a bit-reverse manner from the selected count value group or the unselected count value group under the control of the operating mode control signal, such that the selected count values ​​in the count value group are spaced apart in the time dimension, further dispersing the duty cycle of the sub-PWM signal.

[0126] In one embodiment, the count value selection signal is active when a count value is selected, and inactive when a count value is not selected.

[0127] According to one embodiment, the operating mode control signal requires the selection of a corresponding number of count values ​​from a selected group of count values ​​in a sequential manner. A first portion of the count value is compared to the value of a second portion of the time configuration value plus one. When the first portion of the count value is less than the value of the second portion of the time configuration value plus one, the count value is selected, and the count value selection signal is active. Alternatively, when the first portion of the count value is greater than or equal to the value of the second portion of the time configuration value plus one, the count value is not selected, and the count value selection signal is inactive.

[0128] According to one embodiment of this application, the operating mode control signal requires selecting a corresponding number of count values ​​from a selected group of count values ​​in a bit-reversed manner. The first part of the bit-reversed count value is compared with the value obtained by adding 1 to the second part of the time configuration value. When the first part of the bit-reversed count value is less than the value obtained by adding 1 to the second part of the time configuration value, the count value is selected, and the count value selection signal is active. Alternatively, when the first part of the bit-reversed count value is greater than or equal to the value obtained by adding 1 to the second part of the time configuration value, the count value is not selected, and the count value selection signal is inactive.

[0129] In one embodiment, the operating mode control signal requires selecting a count value from an unselected group of count values ​​in a bit-reversed manner. A first portion of the bit-reversed count value is compared to a second portion of the time configuration value. When the first portion of the bit-reversed count value is less than the second portion of the time configuration value, the count value is selected, and the count value selection signal is active. Alternatively, when the first portion of the bit-reversed count value is greater than or equal to the second portion of the time configuration value, the count value is not selected, and the count value selection signal is inactive.

[0130] In another embodiment, the operating mode control signal requires the selection of a count value from a group of unselected count values ​​in a sequential manner. A first portion of the count value is compared with a second portion of the time configuration value. When the first portion of the count value is less than the second portion of the time configuration value, the count value is selected, and the count value selection signal is active. Alternatively, when the first portion of the count value is greater than or equal to the second portion of the time configuration value, the count value is not selected, and the count value selection signal is inactive.

[0131] In one embodiment, the control circuit outputs a high level when a count value is selected. Alternatively, the control circuit outputs a low level when a count value is not selected.

[0132] Figure 2 The diagram shown is a schematic representation of the discrete effect of a PWM signal according to an embodiment of this application. Figure 2 In the diagram, the first row represents the target PWM signal. The numbers 1-18 marked on the high level of the target PWM signal indicate a duty cycle of 18 and a period of 4096. Correspondingly, the count value ranges from 2... 12 In the second row, groups 0 to 15 represent 16 count value groups. The target PWM signal is equivalent to 16 sub-PWM signals. The duty cycle of the target PWM signal is divided into the duty cycles of the 16 sub-PWM signals and discretely distributed into the 16 count value groups.

[0133] The following is based on only... Figure 2 For example, this application illustrates the time discretization mode proposed in this application, without limiting the counting range, time grouping value, or number of bits in the time configuration value.

[0134] exist Figure 2 In the illustrated embodiment, the time grouping value is 4. The time configuration value received by the control circuit is a 12-bit binary number 000000010010, corresponding to a duty cycle of 18 for the target PWM signal. Based on the time grouping value, the time configuration value is divided. The first part of the time configuration value includes the lower 4 bits (binary number 0010), and the second part includes the higher 8 bits (binary number 00000001). Correspondingly, the count value is a 12-bit binary number. The count value is divided into 16 (24 The count is divided into groups of 15. The high 4 bits of the count value constitute the second part of the count value, which increments by 1 from 0000 to 1111. Each binary number represents the sequence number of the count value group from 0 to 15. Furthermore, within each count value group, the low 8 bits of the count value constitute the first part of the count value, and each binary number represents the sequence number of that count value within the count value group.

[0135] The count values ​​are retrieved sequentially and divided into two parts according to the time grouping value. For the count value 000000000000, the second part of the count value includes its high 4 bits. This count value is within count value group 0, and the reversed value of the second part of the count value is less than the first part of the time configuration value. Therefore, count value group 0 containing this count value is selected. The first part of the count value includes the remaining bits excluding the high 4 bits. The first part of the count value is less than the second part of the time configuration value, and this count value is selected. For the count value 000000000001, the reversed value of the second part of the count value is less than the first part of the time configuration value, and the first part of the count value is equal to the second part of the time configuration value. Accordingly, this count value is also selected. For the count value 000000000010, based on the reversed value of the second part of the count value, it is determined that it is within count value group 0. The first part of the count value is greater than the second part of the time configuration value, and this count value is not selected. And so on. Within count value group 0, the number of selected count values ​​is 2, and correspondingly, the duty cycle of the sub-PWM signal within count value group 0 is 2. For count value 000100000000, the value of the second part of this count value after reversing the bit order is greater than the first part of the time configuration value, so count value group 1 containing this count value is not selected. The first part of this count value is less than the second part of the time configuration value, so the count value is selected. For count value 000100000001, this count value is still within count value group 1, and its first part is equal to the second part of the time configuration value, so the count value is not selected. And so on, the duty cycle of the sub-PWM signal within count value group 1 is 1.

[0136] Through the above discretization process, a total of 16 sub-PWM signals are output within the counting range of the counter. Each counter value group outputs a sub-PWM signal with a different duty cycle, and the total duty cycle of the sub-PWM signals is equivalent to the duty cycle of the target PWM. This can be understood as the target PWM signal being discretely distributed across 16 counter value groups.

[0137] The time discretization mode proposed in this application, where the sequentially arranged count value groups lose their continuity after bit reversal, exhibits higher uniformity, determinism, and flexibility. This results in a uniformly distributed temporal distribution of the selected count value groups and their corresponding sub-PWM signals. For different time configuration values, the number of count values ​​selected in the count value groups varies, ensuring that the duty cycle of the target PWM signal is evenly distributed across different time periods, avoiding the problems of gaps or duplicate samples common in existing random algorithms.

[0138] Figure 3 The illustration shows a spatiotemporal discretization control method according to another embodiment of this application. It should be understood that the flowchart in the accompanying drawings is merely illustrative. Those skilled in the art can adjust, combine, or split the order of steps without altering the technical effects of this application, and all such adjustments fall within the scope of protection of this application.

[0139] Step 301: Obtain the time grouping value.

[0140] Step 302: Obtain the count value. Based on the time grouping value, divide the count value into a first part and a second part.

[0141] Step 303: Obtain the time configuration value. Based on the time grouping value, divide the time configuration value into a first part and a second part.

[0142] Step 304: Obtain the operating mode control signal.

[0143] Step 305: Obtain the second part of the count value after bit reversal. Determine whether the second part of the count value after bit reversal is less than or equal to the first part of the time configuration value. If yes, proceed to step 306; otherwise, proceed to step 307.

[0144] Step 306: The count value group is selected, the count value group selection signal is set to the valid state, and step 308 is executed.

[0145] Step 307: The count value group is not selected, so the count value group selection signal is set to an invalid state. Then proceed to step 313.

[0146] Step 308: Determine whether the operating mode control signal requires the counter value to be selected in reverse bit order. If yes, proceed to step 309; otherwise, proceed to step 310.

[0147] Step 309: Obtain the first part of the reversed count value and the value of the second part of the time configuration value plus 1. Determine whether the first part of the reversed count value is less than the value of the second part of the time configuration value plus 1. If so, proceed to step 311; otherwise, proceed to step 312.

[0148] Step 310: Obtain the value after adding 1 to the second part of the time configuration value. Determine whether the first part of the count value is less than the value after adding 1 to the second part of the time configuration value. If so, proceed to step 311; otherwise, proceed to step 312.

[0149] Step 311: The count value is selected, and the count value selection signal is set to the valid state.

[0150] Step 312: The count value is not selected, so the count value selection signal is set to an invalid state.

[0151] Step 313: Determine whether the operating mode control signal requires the counter value to be selected in reverse bit order. If yes, proceed to step 314; otherwise, proceed to step 315.

[0152] Step 314: Obtain the first part of the count value after bit reversal. Determine whether the first part of the count value after bit reversal is less than the second part of the time configuration value. If yes, jump to step 311; otherwise, jump to step 312.

[0153] Step 315: Determine whether the first part of the count value is less than the second part of the time configuration value. If yes, proceed to step 311; otherwise, proceed to step 312.

[0154] Step 316: Determine whether the first part of the count value is less than the second part of the time configuration value. If yes, proceed to step 311; otherwise, proceed to step 312.

[0155] According to one embodiment of this application, the control circuit can also be in both spatial discretization mode and time discretization mode simultaneously under the control of the coupling enable signal, so that the control circuit can perform thermal management and noise management linkage control on the power consumption unit array, which has stronger synergy.

[0156] According to one embodiment of this application, in this case, the spatiotemporal discrete control method further includes acquiring a coupling enable signal, a data selection signal, and an optional time configuration value.

[0157] In one embodiment, it is determined whether the coupling enable signal is valid. When the coupling enable signal is valid, the second part of the spatial configuration value obtained through the spatial discretization mode, or the value of the second part of the spatial configuration value plus 1, is acquired, and it is determined whether the data selection signal is valid. When the coupling enable signal is invalid, the signal provided by the spatial discretization mode is not acquired.

[0158] In one embodiment, when the data selection signal is valid, the second part of the spatial configuration value plus 1 or the second part of the spatial configuration value is provided; when the data selection signal is invalid, an optional time configuration value is provided.

[0159] In this case, the control circuit executes a spatial discretization mode, obtaining a first channel selection signal based on a first part of the spatial configuration value and a second part of the spatial configuration value or the value of the second part of the spatial configuration value plus 1. Furthermore, the control circuit executes a time discretization mode, using the second part of the spatial configuration value obtained through the spatial discretization mode or the value of the second part of the spatial configuration value plus 1 as the time configuration value to obtain a sub-PWM signal; alternatively, it uses an optional time configuration value as the time configuration value to obtain a sub-PWM signal.

[0160] Figure 4 The diagram shows a spatiotemporal discretization control circuit according to an embodiment of this application. This spatiotemporal discretization control circuit can serve as a power consumption unit array control circuit to execute the above-described spatiotemporal discretization control method.

[0161] According to one embodiment, the spatiotemporal discretization control circuit may include a spatial discretization module 41, configured to receive spatial configuration values ​​and spatial component values, and generate and provide a first channel selection signal Sel1 or generate and provide a second channel selection signal Sel based on the spatial configuration values.

[0162] According to one embodiment, the spatiotemporal discretization control circuit may further include a channel control module 42 electrically connected to the spatial discretization module 41. The channel control module 42 is electrically connected to the spatial discretization module 41 and configured to receive a first channel selection signal Sel1, and select a corresponding channel based on the first channel selection signal Sel1. Alternatively, in another embodiment, the channel control module 42 is configured to receive a second channel selection signal Sel, select a corresponding channel based on the second channel selection signal Sel, and provide a corresponding sub-workload.

[0163] According to one embodiment, the spatial discretization module 41 may include an address register 411 configured to store and provide address values ​​for channels.

[0164] According to one embodiment, the spatial discretization module 41 may further include an address grouping unit 412 electrically connected to the address register 411. The address grouping unit 412 is configured to receive the address value of the channel and a spatial grouping value, and to divide the address value of the channel into a first part and a second part based on the spatial grouping value and output them respectively.

[0165] According to one embodiment, the spatial discretization module 41 may further include a spatial configuration value grouping unit 413, configured to receive spatial configuration values ​​and spatial grouping values, and to divide the spatial configuration values ​​into a first part and a second part based on the spatial grouping values ​​and output them respectively.

[0166] According to one embodiment, the spatial discretization module 41 may further include a first address comparator 414 electrically connected to the spatial configuration value grouping unit 413 and the address grouping unit 412. A first input of the first address comparator 414 is electrically connected to a first output port of the spatial configuration value grouping unit 413, and a second input of the first address comparator 414 is electrically connected to a second output port of the address grouping unit 412. The first address comparator 414 is configured to receive a first portion of the spatial configuration value and a second portion of the bit-reversed channel address value, compare the two, and generate a first channel selection signal Sel1 based on the comparison result.

[0167] In one embodiment, the first channel selection signal Sel1 is related to the number of selected channels in the selected channel group and the unselected channel group.

[0168] In one embodiment, the address grouping unit 412 may include a module with bit reversal processing capability or a bit reversal processing algorithm to perform bit reversal processing on the second part of the address value of the channel.

[0169] In one embodiment, the port of the second output terminal of the address grouping unit 412 is electrically connected to the port of the second input terminal of the first address comparator 414 in reverse order, configured to receive the second part of the channel address value after bit reversal. This reverse order connection method implements bit reversal processing with hardware wiring, reducing the cost and layout area of ​​the control circuit.

[0170] According to one embodiment, the spatial discretization module 41 may further include a second address comparator 415. A first input of the second address comparator 415 is electrically connected to a first output of the address grouping unit 412, and a second input of the second address comparator 415 is electrically connected to a second output of the spatial configuration value grouping unit 413. The second address comparator 415 is configured to compare a first portion of the channel address value with a second portion of the spatial configuration value and generate a second channel selection signal Sel.

[0171] According to one embodiment, the controller (not shown) controls the comparison conditions of the second address comparator 415.

[0172] In one embodiment, when the first channel selection signal Sel1 is valid, the channel is selected when the first part of the channel address value is less than or equal to the second part of the spatial configuration value. The channel is not selected when the first part of the channel address value is greater than the second part of the spatial configuration value. The spatial discretization module selects channels sequentially from the selected channel group.

[0173] In another embodiment, when the first channel selection signal Sel1 fails, the channel is selected when the first part of the channel address value is less than the second part of the spatial configuration value. Alternatively, the channel is not selected when the first part of the channel address value is greater than or equal to the second part of the spatial configuration value. The spatial discretization module selects a corresponding number of channels from the unselected channel group in a sequential manner.

[0174] Alternatively, according to one embodiment, the spatial discretization module 41 may further include a reverse selection unit 416 and / or an incremental selection unit 417. Under the control of the operating mode control signal, the reverse selection unit 416 enables the spatial discretization module to select channels in the channel group in a bit-reverse or sequential manner. Under the control of the first channel selection signal, the spatial discretization module 41 controls the number of selected channels in the selected channel group and the unselected channel group.

[0175] According to one embodiment, a reversal selection unit 416 is electrically connected between the first output terminal of the address grouping unit 412 and the first input terminal of the second address comparator 415. The reversal selection unit 416 is configured to receive a first portion of a channel address value, and under the control of a working mode control signal, perform a bit reversal operation on the first portion of the channel address value, selecting either the first portion of the channel address value or the bit-reversed first portion of the channel address value and outputting it. The reversal selection unit 416 may include a reversal component 4161 electrically connected to the first output terminal of the address grouping unit 412, and a first multiplexer 4162 electrically connected to the first output terminal of the address grouping unit 412 and the output terminal of the reversal component 4161. The reversal component 4161 is configured to perform a bit reversal operation on the first portion of the channel address value. The first multiplexer 4162 is configured to, under the control of a working mode control signal, select either the first portion of the channel address value or the bit-reversed first portion of the channel address value and output it.

[0176] According to one embodiment, when the operating mode control signal requires the spatial discretization module to select a channel in bit-reversed order, the output of the bit-reversed selection unit 416 is the first part of the bit-reversed channel address value. The second address comparator 415 compares the first part of the bit-reversed channel address value with the second part of the spatial configuration value to generate a second channel selection signal. According to one embodiment, when the first channel selection signal is valid, the channel is selected when the first part of the bit-reversed channel address value is less than or equal to the second part of the spatial configuration value. The channel is not selected when the first part of the bit-reversed channel address value is greater than the second part of the spatial configuration value. According to another embodiment, when the first channel selection signal is invalid, the channel is selected when the first part of the bit-reversed channel address value is less than the second part of the spatial configuration value. The channel is not selected when the first part of the bit-reversed channel address value is greater than or equal to the second part of the spatial configuration value.

[0177] According to another embodiment, when the operating mode control signal requires the spatial discretization module to select channels sequentially, the output of the reverse selection unit 416 is the first part of the channel address value. The second address comparator 415 compares the first part of the channel address value with the second part of the spatial configuration value to generate a second channel selection signal. According to one embodiment, when the first channel selection signal is valid, the channel is selected when the first part of the channel address value is less than or equal to the second part of the spatial configuration value. The channel is not selected when the first part of the channel address value is greater than the second part of the spatial configuration value. According to another embodiment, when the first channel selection signal is invalid, the channel is selected when the first part of the channel address value is less than the second part of the spatial configuration value; the channel is not selected when the first part of the channel address value is greater than or equal to the second part of the spatial configuration value.

[0178] Alternatively, according to one embodiment, the spatial discretization module 41 may further include an incremental selection unit 417 electrically connected between the second output of the spatial configuration value grouping unit 413 and the second input of the second address comparator 415, and electrically connected to the output of the first address comparator 414. The incremental selection unit 417 is configured to receive a second portion of the spatial configuration value, increment the second portion of the spatial configuration value by 1, and, under the control of the first channel selection signal Sel1, select either the second portion of the spatial configuration value or the value of the second portion of the spatial configuration value incremented by 1 for output. The incremental selection unit 417 may include an adder 4171 electrically connected to the second output of the spatial configuration value grouping unit 413, and a second multiplexer 4172 electrically connected between the second output of the spatial configuration value grouping unit 413 and the output of the adder 4171. The second multiplexer 4172 is also electrically connected to the output of the first address comparator 414. The adder 4171 is configured to increment the second portion of the spatial configuration value by 1. The second multiplexer 4172 is configured to, under the control of the first channel selection signal Sel1, select one of the second part of the spatial configuration value or the value of the second part of the spatial configuration value plus 1 for output.

[0179] According to one embodiment, when the first channel selection signal Sel1 is valid, the output of the incremental selection unit 417 is the second part of the spatial configuration value plus 1. In another embodiment, when the first channel selection signal Sel1 is invalid, the output of the incremental selection unit 417 is the second part of the spatial configuration value.

[0180] According to one embodiment, when the first channel selection signal is valid, the channel is selected if the first part of the channel address value is less than the value of the second part of the spatial configuration value plus 1. The channel is not selected if the first part of the channel address value is greater than or equal to the value of the second part of the spatial configuration value plus 1. The spatial discretization module selects channels from the selected channel group sequentially.

[0181] According to another embodiment, when the first channel selection signal fails, the channel is selected if the first part of the channel address value is less than the second part of the spatial configuration value; the channel is not selected if the first part of the channel address value is greater than or equal to the second part of the spatial configuration value. The spatial discretization module selects channels from the unselected channel group in a sequential manner.

[0182] According to one embodiment of this application, the spatial discretization module 41 may include a reverse selection unit 416 and an incremental selection unit 417, and the working mode control signal may require the selection of channels in a sequential or bit-reverse manner.

[0183] In one embodiment, the operating mode control signal requires the spatial discretization module 41 to select a channel in bit-reversed order and for the first channel selection signal to be valid. The channel is selected when the first part of the bit-reversed channel address value is less than the value of the second part of the spatial configuration value plus 1. The channel is not selected when the first part of the bit-reversed channel address value is greater than or equal to the value of the second part of the spatial configuration value plus 1.

[0184] In one embodiment, the operating mode control signal requires channel selection in bit-reversed order and the first channel selection signal to be disabled. The channel is selected when the first part of the bit-reversed channel address value is less than the second part of the spatial configuration value. The channel is not selected when the first part of the bit-reversed channel address value is greater than or equal to the second part of the spatial configuration value.

[0185] In another embodiment, the operating mode control signal requires the spatial discretization module 41 to select channels sequentially and for the first channel selection signal to be valid. A channel is selected when the first part of the channel address value is less than the value of the second part of the spatial configuration value plus 1. A channel is not selected when the first part of the channel address value is greater than or equal to the value of the second part of the spatial configuration value plus 1.

[0186] In another embodiment, the operating mode control signal requires channels to be selected sequentially, and the first channel selection signal is disabled. A channel is selected when the first portion of the channel address value is less than the second portion of the spatial configuration value. A channel is not selected when the first portion of the channel address value is greater than or equal to the second portion of the spatial configuration value.

[0187] According to one embodiment, the spatiotemporal discretization control circuit may further include a time discretization module 45 configured to generate a count value selection signal based on a time configuration value. In this case, the channel control module 42 may also be electrically connected to the time discretization module 45 and configured to receive the count value selection signal from the time discretization module 45, and output a sub-PWM signal based on the count value selection signal. The spatiotemporal discretization control circuit can operate in time discretization mode, realizing the discretization of the target PWM signal into a cluster of sub-PWM signals, thereby dispersing the EMI effect of energy dissipation.

[0188] According to one embodiment, the spatial discretization module 41 and the time discretization module 45 can simultaneously operate under the control of a coupling enable signal. The spatial discretization module 41 generates a first channel selection signal Sel1 based on a first portion of the spatial configuration value. The channel control module 42 is configured to receive the first channel selection signal Sel1 and determine the operating state of the corresponding channel. The spatiotemporal discretization control circuit provides the second portion of the spatial configuration value, or the value of the second portion of the spatial configuration value plus 1, as the time configuration value to the time discretization module 45. The time discretization module 45 generates a sub-PWM signal corresponding to the time configuration value, outputting a sub-PWM signal corresponding to the selected count value group in the selected channel, and outputting a sub-PWM signal corresponding to the unselected count value group in the unselected channel. In this case, under the control of the coupling enable signal, the spatial discretization module 41 does not provide the second channel selection signal Sel1 to the channel control module 42.

[0189] Alternatively, according to one embodiment, the spatiotemporal discretization control circuit may further include a mode selection unit 43 electrically connected to the output of the incremental selectable unit 417. The mode selection unit 43 is configured to receive the output of the incremental selectable unit 417 and output it under the control of the coupling enable signal EN.

[0190] Alternatively, according to one embodiment, the spatiotemporal discretization control circuit may further include a data selector 44 electrically connected to the mode selection unit 43, configured to receive an optional time configuration value and the output of the mode selection unit 43, and select one of the optional time configuration value or the output of the mode selection unit 43 under the control of the data selection signal DS.

[0191] According to one embodiment, when the coupling enable signal is valid, if the first channel selection signal Sel1 is valid, the output of the mode selection unit 43 is the value of the second part of the spatial configuration value plus 1; if the first channel selection signal Sel1 is invalid, the output of the mode selection unit 43 is the second part of the spatial configuration value.

[0192] According to one embodiment, when the data selection signal DS requests the output of the spatial discretization module 41 as the time configuration value, the data selection signal DS is valid, and the data selector 44 selects the output of the mode selection unit 43 for output. In another embodiment, when the data selection signal DS requests an optional time configuration value as the time configuration value, the data selection signal DS is invalid, and the data selector 44 selects the optional time configuration value for output.

[0193] By electrically connecting the time discretization module to the spatial discretization module, the spatiotemporal discretization control circuit realizes the discretization of dissipated energy in both time and space dimensions, comprehensively solves the spatiotemporal dual concentration effect of dissipated energy in the power consumption unit array during operation, and collaboratively solves the problems of hot spot concentration and interference superposition in the system.

[0194] According to one embodiment, the time discretization module 45 further includes a time configuration value grouping unit 450 electrically connected to the data selector 44, configured to receive time grouping values ​​and the output of the data selector 44, use the output of the data selector 44 as the time configuration value, and divide the time configuration value into a first part of the time configuration value and a second part of the time configuration value based on the time grouping value and output them respectively.

[0195] According to one embodiment, the time discretization module 45 may include a counter 451 configured to perform cyclic counting and output a count value, the range of which corresponds to the period of the target PWM signal. The counter 451 is also configured to receive a clock frequency signal PWM_CLK, which ensures that the counter 451 has a clock frequency corresponding to the target PWM signal.

[0196] According to one embodiment, the time discretization module 45 may further include a count value grouping unit 452 electrically connected to the counter 451. The count value grouping unit 452 is configured to receive a count value and a time grouping value, divide the count value into a first part and a second part based on the time grouping value, and output them respectively.

[0197] According to one embodiment, the time discretization module 45 may further include a first count value comparator 454. A first input of the first count value comparator 454 is electrically connected to a first output of the time configuration value grouping unit 450, and a second input of the first count value comparator 454 is electrically connected to a second output of the count value grouping unit 452. The first count value comparator 454 is configured to receive a first portion of the time configuration value and a second portion of the bit-reversed counter value, compare the two, and generate a count value grouping selection signal Tsel1 based on the comparison result. The count value grouping selection signal Tsel1 is related to the number of selected count values ​​in the selected count value group and the unselected count value group.

[0198] According to one embodiment, when the count value group selection signal Tsel1 is valid, the number of selected count values ​​in the selected count value group is the decimal number corresponding to the second part of the time configuration value plus 1. When the count value group selection signal Tsel1 is invalid, the number of selected count values ​​in the unselected count value group is the decimal number corresponding to the second part of the time configuration value.

[0199] In one embodiment, the count value grouping unit 452 may include a module with bit reversal processing capability or a bit reversal processing algorithm to perform bit reversal processing on a second part of the count value.

[0200] In one embodiment of this application, the port of the second output terminal of the counting value grouping unit 452 can be electrically connected to the port of the second input terminal of the first counting value comparator 454 in reverse order.

[0201] According to one embodiment, the time discretization module 45 may further include a second count value comparator 455. A first input of the second count value comparator 455 is electrically connected to a first output of the count value grouping unit 452, and a second input of the second count value comparator 455 is electrically connected to a second output of the time configuration value grouping unit 450. The second count value comparator 455 is configured to receive a first portion of the count value and a second portion of the time configuration value and compare the two, generating a count value selection signal Tsel based on the comparison result.

[0202] According to one embodiment, the controller (not shown) controls the comparison conditions of the second count value comparator 455.

[0203] In one embodiment, the count value group selection signal Tsel1 is active. When the first part of the count value is less than or equal to the second part of the time configuration value, the count value is selected, and the count value selection signal Tsel1 is active. When the first part of the count value is greater than the second part of the time configuration value, the count value is not selected, and the count value selection signal Tsel1 is inactive. The time discretization module selects the count values ​​in the selected count value group in a sequential manner.

[0204] In another embodiment, when the count value group selection signal Tsel1 fails, if the first part of the count value is less than the second part of the time configuration value, the count value is selected, and the count value selection signal Tsel1 is active. If the first part of the count value is greater than or equal to the second part of the time configuration value, the count value is not selected, and the count value selection signal Tsel1 fails. The time discretization module selects count values ​​sequentially from the unselected count value groups.

[0205] Alternatively, according to one embodiment, the time discretization module 45 may further include a reverse selection unit 456 and / or an incremental selection unit 457. Under the control of the operating mode control signal, the reverse selection unit 456 enables the time discretization module to select count values ​​in a bit-reverse or sequential manner. Under the control of the count value group selection signal, the time discretization module 45 controls the number of selected count values ​​in the selected and unselected count value groups.

[0206] According to one embodiment, the time discretization module 45 may further include a reverse selection unit 456 electrically connected between the first output of the count value grouping unit 452 and the first input of the second count value comparator 455. The reverse selection unit 456 is configured to receive a first portion of the count value, perform a bit-reversal operation on the first portion of the count value, and, under the control of a working mode control signal, select either the first portion of the count value or the bit-reversed first portion of the count value for output. The reverse selection unit 456 may include a reverse component 4561 electrically connected to the first output of the count value grouping unit 452, and a first selector 4562 electrically connected to the first output of the count value grouping unit 452 and the output of the reverse component 4561. The reverse component 4561 is configured to perform a bit-reversal operation on the first portion of the count value. The first selector 4562 is configured, under the control of a working mode control signal, to select either the first portion of the count value or the bit-reversed first portion of the count value for output.

[0207] According to one embodiment, when the operating mode control signal requires the time discretization module to select a count value in bit-reversed order, the reverse selection unit 456 outputs the first part of the bit-reversed count value. The second count value comparator 455 compares the first part of the bit-reversed count value with the second part of the time configuration value to generate a count value selection signal. According to one embodiment, when the count value group selection signal is valid, if the first part of the bit-reversed count value is less than or equal to the second part of the time configuration value, the count value is selected, and the count value selection signal Tsel is valid. If the first part of the bit-reversed count value is greater than the second part of the time configuration value, the count value is not selected, and the count value selection signal Tsel is invalid. In another embodiment, when the count value group selection signal Tsel1 is invalid, if the first part of the bit-reversed count value is less than the second part of the time configuration value, the count value is selected, and the count value selection signal Tsel is valid. If the first part of the bit-reversed count value is greater than or equal to the second part of the time configuration value, the count value is not selected, and the count value selection signal Tsel is invalid.

[0208] According to another embodiment, when the operating mode control signal requires the time discretization module to select a count value sequentially, the output of the reverse selection unit 456 is the first part of the count value. The second count value comparator 455 compares the first part of the count value with the second part of the time configuration value to generate a count value selection signal. According to one embodiment, when the count value group selection signal is valid, if the first part of the count value is less than or equal to the second part of the time configuration value, the count value is selected, and the count value selection signal Tsel is valid; if the first part of the count value is greater than the second part of the time configuration value, the count value is not selected, and the count value selection signal Tsel is invalid. In another embodiment, when the count value group selection signal Tsel1 is invalid, if the first part of the count value is less than the second part of the time configuration value, the count value is selected, and the count value selection signal Tsel is valid; if the first part of the count value is greater than or equal to the second part of the time configuration value, the count value is not selected, and the count value selection signal Tsel is invalid.

[0209] Alternatively, according to one embodiment, the time discretization module 45 may further include an incremental selection unit 457 electrically connected between the second output of the time configuration value grouping unit 450 and the second input of the second count value comparator 455, and electrically connected to the output of the first count value comparator 454. The incremental selection unit 458 is configured to receive a second portion of the time configuration value, increment the second portion of the time configuration value by 1, and, under the control of the count value grouping selection signal Tsel1, select either the value of the second portion of the time configuration value after incrementing by 1 or the output of the second portion of the time configuration value. The incremental selection unit 458 may include an adder 4571 electrically connected to the second output of the time configuration value grouping unit 450, and a second selector 4572 electrically connected to the second output of the time configuration value grouping unit 450 and the output of the adder 4571. The second selector 4572 is also electrically connected to the output of the first count value comparator 454. The adder 4571 is configured to increment the second portion of the time configuration value by 1. The second selector 4572 is configured to select, under the control of the count value grouping selection signal Tsel1, either the second part of the time configuration value or the value of the second part of the time configuration value plus 1 as an output.

[0210] In one embodiment, when the count value group selection signal Tsel1 is valid, the incremental selection unit 457 outputs the value of the second part of the time configuration value plus 1. In another embodiment, when the count value group selection signal Tsel1 is invalid, the incremental selection unit 457 outputs the value of the second part of the time configuration value.

[0211] According to one embodiment, when the time group selection signal is valid, if the first part of the count value is less than the value of the second part of the time configuration value plus 1, the count value is selected, and the count value selection signal is valid. If the first part of the count value is greater than or equal to the value of the second part of the time configuration value plus 1, the count value is not selected, and the count value selection signal is invalid. The spatial discretization module selects the count value from the selected count value groups in a sequential manner.

[0212] In another embodiment, when the count value group selection signal fails, if the first part of the count value is less than the second part of the time configuration value, the count value is selected and the count value selection signal is valid. If the first part of the count value is greater than or equal to the second part of the time configuration value, the count value is not selected and the count value selection signal fails. The spatial discretization module selects count values ​​sequentially from the unselected count value groups.

[0213] According to one embodiment, the time discretization module 45 may include a reverse selection unit 456 and an incremental selection unit 457, and the operating mode control signal may require the time discretization module 45 to select the count value in a sequential or bit-reverse manner.

[0214] In one embodiment, the operating mode control signal requires the time discretization module 45 to select the count value in bit-reversed order and for the count value grouping selection signal to be valid. When the first part of the bit-reversed count value is less than the value of the second part of the time configuration value plus 1, the count value is selected and the count value selection signal is valid; when the first part of the bit-reversed count value is greater than or equal to the value of the second part of the time configuration value plus 1, the count value is not selected and the count value selection signal is invalid.

[0215] In one embodiment, the operating mode control signal requires the time discretization module 45 to select a count value in bit-reversed order and disables the count value grouping selection signal. When the first part of the bit-reversed count value is less than the second part of the time configuration value, the count value is selected, and the count value selection signal is active. When the first part of the bit-reversed count value is greater than or equal to the second part of the time configuration value, the count value is not selected, and the count value selection signal is disabled.

[0216] In another embodiment, the operating mode control signal requires the time discretization module 45 to select count values ​​sequentially and for the count value grouping selection signal to be valid. When the first part of the count value is less than the value of the second part of the time configuration value plus 1, the count value is selected and the count value selection signal is valid; when the first part of the count value is greater than or equal to the value of the second part of the time configuration value plus 1, the count value is not selected and the count value selection signal is invalid.

[0217] In another embodiment, the operating mode control signal requires the time discretization module 45 to select count values ​​sequentially and disable the count value grouping selection signal. When the first part of the count value is less than the second part of the time configuration value, the count value is selected and the count value selection signal is valid; when the first part of the count value is greater than or equal to the second part of the time configuration value, the count value is not selected and the count value selection signal is invalid.

[0218] Figure 5 The diagram shown is a schematic diagram of the electrical connections of a local circuit in a spatiotemporal discretization control circuit according to an embodiment of this application.

[0219] According to one embodiment, the first output of the space configuration value grouping unit 513 includes ports P5131 to P5134, configured to output a first portion of the space configuration value.

[0220] According to one embodiment, the second output of the address grouping unit 512 includes ports P5121 to P5124, configured as the second part of the address value of the output channel.

[0221] According to one embodiment, the first input terminal of the first address comparator 514 includes ports P5141 to P5144, and the second input terminal of the first address comparator 514 includes ports P5145 to P5148. Ports P5121 to P5124 of the second output terminal of the address grouping unit 512 are electrically connected to ports P5145 to P5148 of the second input terminal of the first address comparator 514 in reverse order, thereby reversing the bit order of the second portion of the channel address value.

[0222] In one embodiment of this application, Figure 5 The structure shown is also applicable to Figure 4 The time discretization module 45 shown is used to electrically connect the port of the second input terminal of the first count value comparator 454 to the port of the second output terminal of the count value grouping unit 452 in reverse order.

[0223] This application achieves energy dissipation uniformity of power unit arrays, which is typically achieved only with high-end random PWM, at zero cost by connecting the relevant ports in reverse order, thus greatly reducing the discretization cost of energy dissipation.

[0224] Figure 6 and Figure 7 The diagram illustrates application scenarios of the spatiotemporal discretization control circuit according to some embodiments. These embodiments are used to demonstrate that the spatiotemporal discretization control circuit and control method proposed in this application are applicable to various power consumption unit array arrangements, without limiting the applicable scenarios of the spatiotemporal discretization control circuit.

[0225] Figure 6The diagram illustrates an application scenario of a spatiotemporal discretization control circuit according to an embodiment of this application. The spatiotemporal discretization control circuit 601 controls 16 groups of power consumption units via channels. When the spatiotemporal discretization control circuit 601 is in spatial discretization mode, as the spatial configuration value increases, the channels furthest apart are selected sequentially. For example, channels G0, G8, G4, G12...G7, G15 are selected sequentially, and the change in the spatial configuration value is evenly distributed to each power consumption unit.

[0226] Figure 7 The diagram illustrates an application scenario of a spatiotemporal discretization control circuit according to another embodiment of this application. Based on requirements, k spatiotemporal discretization control circuits (spatiotemporal discretization control circuit 701, spatiotemporal discretization control circuit 702, and spatiotemporal discretization control circuit 70k) proposed in this application are linearly expanded, and the corresponding channel of the corresponding spatiotemporal discretization control circuit is selected under the control of the controller. Here, k is a positive integer greater than or equal to 1.

[0227] Figure 8 The figure shown is a simulation diagram of the junction temperature thermodynamic distribution of the power consumption unit array in the existing scheme. Figure 9 The diagram shown is a simulation of the junction temperature thermodynamic distribution of a power consumption cell array according to an embodiment of this application. Under simulation conditions of 25°C, a thermal diffusivity of 0.35, and a heat dissipation coefficient of 0.12, both the prior art and the present application include 512 independent power consumption cells. Figure 8 and Figure 9 The horizontal axis represents the spatial configuration value, and the vertical axis represents the linearly arranged power consumption cells, meaning the power consumption cells are arranged linearly along the vertical axis. The color represents the junction temperature of the power consumption cells, gradually increasing from 25℃ to 125℃ from dark purple to red. Figure 8 As the spatial configuration value increases, power consumption units are activated sequentially. These activated units are physically adjacent to each other, leading to concentrated hotspots, poor heat dissipation of the entire array, and persistently high temperatures. Figure 9 In this array, as the space configuration value increases, the power consumption units are activated in a dispersed manner, and the hot spots are distributed in a dispersed manner with a low degree of concentration, which gives the entire array good heat dissipation capabilities and thus suppresses the rapid rise in junction temperature.

[0228] Figure 10The diagram shown is an EMI / spectral simulation diagram according to an embodiment of this application. In the frequency domain, the PWM signal output by the prior art (red line) exhibits a concentrated large pulse width waveform with a sharp peak of -11.83 dB at the fundamental frequency, which is the main source of excessive electromagnetic radiation in the system. This application (green line) divides the energy into multiple small pulses, shifting the fundamental frequency energy to the high-frequency band, and reducing the maximum interference peak value across the entire frequency band to -54.16 dB. Simulation results show that, under the same load conditions, the conducted interference peak value of this application is reduced by approximately 42 dB compared to the prior art.

[0229] The above embodiments are for illustrative purposes only and are not intended to limit the scope of this application. Those skilled in the art can make various changes and modifications without departing from the scope of this application. Therefore, all equivalent technical solutions should also fall within the scope of this application.

Claims

1. A spatiotemporal discretization control method, comprising a spatial discretization mode, including... Obtain the space configuration value; the space configuration value represents the workload that the control circuit of the power consumption unit array needs to output, and the space configuration value is an I-bit binary number, where I is a positive integer greater than or equal to 1; Obtain the spatial grouping value; the spatial grouping value is used to divide the workload into 2 N Each sub-workload group contains a different number of sub-workloads; The spatial grouping value is N, where N is a positive integer less than or equal to 1 and greater than or equal to 1; Get the address value of the channel; where the address value of the channel is I bits. Based on the spatial grouping value, the address value of the channel is divided into a first part and a second part; wherein, the first part of the address value of the channel includes the remaining bits of the address value of the channel except for the high N bits, representing the sequence number of the channel in the channel group; the second part of the address value of the channel includes the high N bits of the address value of the channel, representing the sequence number of the channel group to which the channel belongs; Based on the spatial grouping value, the spatial configuration value is divided into a first part and a second part; wherein, the first part of the spatial configuration value includes the lower N bits of the spatial configuration value, which is related to the sequence number of the channel group; the second part of the spatial configuration value includes the remaining bits of the spatial configuration value other than the lower N bits, which is related to the number of channels selected in the channel group; The second part of the address value of the channel after bit reversal is compared with the first part of the spatial configuration value; wherein, when the second part of the address value of the channel after bit reversal is less than or equal to the first part of the spatial configuration value, the channel group is selected, the first channel selection signal is valid and the second part of the spatial configuration value plus 1 is provided.

2. The spatiotemporal discretization control method according to claim 1, wherein, Compare the second part of the address value of the channel after bit reversal with the first part of the spatial configuration value; When the second part of the address value of the channel after bit reversal is greater than the first part of the space configuration value, the channel group is not selected, the first channel selection signal is in an invalid state and the second part of the space configuration value is provided.

3. The spatiotemporal discretization control method according to claim 2, wherein, When the first channel selection signal is valid, the number of channels selected in the channel group is the decimal number corresponding to the second part of the spatial configuration value plus 1; or, When the first channel selection signal fails, the number of channels selected in the channel group is the decimal number corresponding to the second part of the spatial configuration value.

4. The spatiotemporal discretization control method according to claim 3 further includes, when the first channel selection signal is valid, obtaining the value of the second part of the spatial configuration value plus 1 and comparing it with the sum of the first part of the channel address value; wherein, When the first part of the address value of the channel is less than the value of the second part of the spatial configuration value plus 1, the channel is selected and the second channel selection signal is valid; When the first part of the channel's address value is greater than or equal to the value of the second part of the spatial configuration value plus 1, the channel is not selected, and the second channel selection signal is invalid.

5. The spatiotemporal discretization control method according to claim 4 further includes, when the first channel selection signal fails, obtaining a second part of the spatial configuration value and comparing it with a first part of the channel address value; wherein, When the first part of the address value of the channel is less than the second part of the spatial configuration value, the channel is selected and the second channel selection signal is valid; When the first part of the address value of the channel is greater than or equal to the second part of the spatial configuration value, the channel is not selected, and the second channel selection signal is invalid.

6. The spatiotemporal discretization control method according to claim 3 further includes, Acquire operating mode control signals; When the operating mode control signal requires the channel in the channel group to be selected in reverse bit order, the first part of the address value of the channel after bit reversal is obtained; or, when the operating mode control signal requires the channel in the channel group to be selected in sequence, the first part of the address value of the channel is obtained.

7. The spatiotemporal discretization control method according to claim 6 further includes, when the working mode control signal requires the selection of a channel in the channel group in a bit-reversed manner and the first channel selection signal is valid, comparing the value of the second part of the spatial configuration value plus 1 with the first part of the address value of the channel after bit reversal; wherein, When the first part of the address value of the channel after bit reversal is less than the value of the second part of the spatial configuration value plus 1, the channel is selected and the second channel selection signal is valid; When the first part of the address value of the channel after bit reversal is greater than or equal to the value of the second part of the space configuration value plus 1, the channel is not selected and the second channel selection signal is invalid.

8. The spatiotemporal discretization control method according to claim 7 further includes, when the working mode control signal requires the selection of a channel in the channel group in a bit-reversed manner and the first channel selection signal fails, comparing the second part of the spatial configuration value with the first part of the address value of the bit-reversed channel; wherein, When the first part of the address value of the channel after bit reversal is less than the second part of the spatial configuration value, the channel is selected and the second channel selection signal is valid; or, When the first part of the address value of the channel after bit reversal is greater than or equal to the second part of the space configuration value, the channel is not selected, and the second channel selection signal is invalid.

9. The spatiotemporal discretization control method according to claim 2 further includes, Acquire the coupling enable signal, data selection signal, and optional time configuration value; When the coupling enable signal fails, the optional time configuration value is provided; When the coupling enable signal is valid, the second part of the spatial configuration value or the value of the second part of the spatial configuration value plus 1 is obtained; If the data selection signal is valid, provide the value of the second part of the spatial configuration value plus 1 or the second part of the spatial configuration value; if the data selection signal is invalid, provide the optional time configuration value.

10. The spatiotemporal discretization control method according to claim 9 further includes a time discretization mode, comprising, The optional time configuration value is obtained as the time configuration value; or, the second part of the spatial configuration value plus 1 or the second part of the spatial configuration value is obtained as the time configuration value; wherein, the time configuration value corresponds to the duty cycle of the target PWM signal; the time configuration value is a J-bit binary number, where J is a positive integer greater than or equal to 1; Obtain time grouping values; these values ​​are used to determine the number of sub-PWM signals equivalent to the target PWM signal, where the duty cycle of the target PWM signal is equal to 2. A The sum of the duty cycles of the individual PWM signals; the time grouping value is A; where A is a positive integer less than or equal to J and greater than or equal to 1; Obtain the count value; based on the time grouping value, divide the count value into a first part and a second part; wherein the first part of the count value includes the remaining bits of the count value except for the high A bit, representing the sequence number of the count value in the count value group; the second part of the count value includes the high A bit of the count value, representing the sequence number of the count value group in which the count value is located; Based on the time grouping value, the time configuration value is divided into a first part and a second part; wherein, the first part of the time configuration value includes the lower A bits of the time configuration value, which are used to determine the sequence number of the count value group; the second part of the time configuration value includes the remaining bits of the time configuration value other than the lower A bits, which are related to the duty cycle of the sub-PWM signal; Acquire operating mode control signals; The second part of the bit-reversed count value is compared with the first part of the time configuration value; wherein, when the second part of the bit-reversed count value is less than or equal to the first part of the time configuration value, the count value group is selected, and the count value group selection signal is in a valid state; and... When the operating mode control signal requires the selection of a count value in the count value group in a bit-reversed manner and the count value group selection signal is valid, the first part of the bit-reversed count value and the value of the second part of the time configuration value plus 1 are obtained, and the first part of the bit-reversed count value and the value of the second part of the time configuration value plus 1 are compared; wherein, when the first part of the bit-reversed count value is less than the value of the second part of the time configuration value plus 1, the count value is selected and the count value selection signal is valid.

11. The spatiotemporal discretization control method according to claim 10, wherein, The second part of the bit-reversed count value is compared with the first part of the time configuration value; it also includes, When the second part of the count value after bit reversal is greater than the first part of the time configuration value, the count value group is not selected, and the count value group selection signal is in an invalid state.

12. The spatiotemporal discretization control method according to claim 11, wherein, When the count value group selection signal is valid, the number of count values ​​selected in the count value group is the decimal number corresponding to the second part of the time configuration value plus 1; or, When the count value group selection signal fails, the number of count values ​​selected in the count value group is the decimal number corresponding to the value of the second part of the time configuration value.

13. The spatiotemporal discretization control method according to claim 12 further includes, when the working mode control signal requires the selection of a count value in the count value group in a bit-reverse manner and the count value group selection signal is valid, When the first part of the count value after bit reversal is greater than or equal to the value of the second part of the time configuration value plus 1, the count value is not selected and the count value selection signal is invalid.

14. The spatiotemporal discretization control method according to claim 13 further includes, when the working mode control signal requires the selection of the count value in the count value group in a bit-reversed manner and the count value group selection signal fails, obtaining the first part of the bit-reversed count value and the second part of the time configuration value; When the first part of the bit-reversed count value is less than the second part of the time configuration value, the count value is selected and the count value selection signal is valid; when the first part of the bit-reversed count value is greater than or equal to the second part of the time configuration value, the count value is not selected and the count value selection signal is invalid.

15. A spatiotemporal discretization control method, comprising a time discretization mode, including, Obtain the time configuration value; the time configuration value corresponds to the duty cycle of the target PWM signal; wherein, the time configuration value is a J-bit binary number, where J is a positive integer greater than or equal to 1; Obtain time grouping values; these values ​​are used to determine the number of sub-PWM signals equivalent to the target PWM signal, where the duty cycle of the target PWM signal is equal to 2. A The sum of the duty cycles of the individual PWM signals; the time grouping value is A; where A is a positive integer less than or equal to J and greater than or equal to 1; Obtain the count value; based on the time grouping value, divide the count value into a first part and a second part; wherein the first part of the count value includes the remaining bits of the count value except for the high A bit, representing the sequence number of the count value in the count value group; the second part of the count value includes the high A bit of the count value, representing the sequence number of the count value group in which the count value is located; Based on the time grouping value, the time configuration value is divided into a first part and a second part; wherein, the first part of the time configuration value includes the lower A bits of the time configuration value, which are used to determine the sequence number of the count value group; the second part of the time configuration value includes the remaining bits of the time configuration value other than the lower A bits, which are related to the duty cycle of the sub-PWM signal; The second part of the bit-reversed count value is compared with the first part of the time configuration value; wherein, when the second part of the bit-reversed count value is less than or equal to the first part of the time configuration value, the count value group is selected, and the count value group selection signal is in a valid state; and When the operating mode control signal requires the selection of a count value in the count value group in a bit-reversed manner and the count value group selection signal is valid, the first part of the bit-reversed count value and the value of the second part of the time configuration value plus 1 are obtained, and the first part of the bit-reversed count value and the value of the second part of the time configuration value plus 1 are compared; wherein, when the first part of the bit-reversed count value is less than the value of the second part of the time configuration value plus 1, the count value is selected and the count value selection signal is valid.

16. The spatiotemporal discretization control method according to claim 15, wherein, The second part of the bit-reversed count value is compared with the first part of the time configuration value; it also includes, When the second part of the count value after bit reversal is greater than the first part of the time configuration value, the count value group is not selected, and the count value group selection signal is in an invalid state.

17. The spatiotemporal discretization control method according to claim 16, wherein, When the count value group selection signal is valid, the number of count values ​​selected in the count value group is the decimal number corresponding to the second part of the time configuration value plus 1; or, When the count value group selection signal fails, the number of count values ​​selected in the count value group is the decimal number corresponding to the value of the second part of the time configuration value.

18. The spatiotemporal discretization control method according to claim 17 further includes, when the working mode control signal requires the selection of a count value in the count value group in a bit-reverse manner and the count value group selection signal is valid, When the first part of the count value after bit reversal is greater than or equal to the value of the second part of the time configuration value plus 1, the count value is not selected, and the count value selection signal is valid.

19. The spatiotemporal discretization control method according to claim 18 further includes, when the working mode control signal requires the selection of the count value in the count value group in a bit-reversed manner and the count value group selection signal fails, obtaining the first part of the bit-reversed count value and the second part of the time configuration value; When the first part of the bit-reversed count value is less than the second part of the time configuration value, the count value is selected and the count value selection signal is valid; when the first part of the bit-reversed count value is greater than or equal to the second part of the time configuration value, the count value is not selected and the count value selection signal is invalid.

20. A spatiotemporal discretization control circuit, comprising: The spatial discretization module is configured to receive spatial configuration values ​​and spatial grouping values; wherein... The spatial configuration value represents the workload that the spatiotemporal discretization control circuit needs to output. The spatial configuration value is an I-bit binary number, where I is a positive integer greater than or equal to 1. The spatial grouping value is used to divide the workload into 2... N Each sub-workload group contains a different number of sub-workloads. The spatial grouping value is N, where N is a positive integer less than or equal to 1 and greater than or equal to 1; including, The address register is configured to store and provide the address value of the channel; The address value grouping unit, electrically connected to the address register, is configured to receive the address value of the channel. Under the action of the spatial grouping value, it divides the address value of the channel into a first part and a second part and outputs them respectively. The first part of the address value of the channel includes the remaining bits of the address value of the channel except for the high N bits, representing the sequence number of the channel in the channel group. The second part of the address value of the channel includes the high N bits of the address value of the channel, representing the sequence number of the channel group to which the channel belongs. A spatial configuration value grouping unit is configured to receive the spatial configuration value and, under the action of the spatial grouping value, divide the spatial configuration value into a first part and a second part; wherein, the first part of the spatial configuration value includes the lower N bits of the spatial configuration value, which is related to the sequence number of the channel group; the second part of the spatial configuration value includes the remaining bits of the spatial configuration value other than the lower N bits, which is related to the number of selected channels in the channel group; A first address comparator, electrically connected to the spatial configuration value grouping unit and the address grouping unit, is configured to compare a first part of the spatial configuration value with a second part of the address value of the channel after bit reversal and generate a first channel selection signal based on the comparison result. An incremental selectable unit is electrically connected to the spatial configuration value grouping unit and the output of the first address comparator. It is configured to increment the second part of the spatial configuration value by 1. Under the control of the first channel selection signal, it selects the second part of the spatial configuration value or the value of the second part of the spatial configuration value incremented by 1 for output. Specifically, when the second part of the address value of the channel after bit reversal is less than or equal to the first part of the spatial configuration value, the first channel selection signal is valid, and the output of the incremental selectable unit is the value of the second part of the spatial configuration value plus 1.

21. The spatiotemporal discretization control circuit according to claim 20, wherein, The ports of the second output terminal of the address grouping unit are electrically connected to the ports of the second input terminal of the first address comparator in reverse order.

22. The spatiotemporal discretization control circuit according to claim 21, wherein, When the second part of the address value of the channel after bit reversal is greater than the first part of the spatial configuration value, the first channel selection signal generated by the first address comparator is in a failed state, and the output of the incremental selectable unit is the second part of the spatial configuration value.

23. The spatiotemporal discretization control method according to claim 22, wherein, When the first channel selection signal is valid, the number of channels selected in the channel group is the decimal number corresponding to the second part of the spatial configuration value plus 1; or, When the first channel selection signal fails, the number of channels selected in the channel group is the decimal number corresponding to the second part of the spatial configuration value.

24. The spatiotemporal discretization control circuit according to claim 23 further includes, A second address comparator, electrically connected to the outputs of the address grouping unit and the incremental selection unit, is configured to compare a first portion of the channel's address value with the output of the incremental selection unit and generate a second channel selection signal based on the comparison result; wherein, When the first channel selection signal is active. When the first part of the address value of the channel is less than the value of the second part of the spatial configuration value plus 1, the second channel selection signal generated by the second address comparator is in a valid state; or, When the first part of the address value of the channel is greater than or equal to the value of the second part of the spatial configuration value plus 1, the second channel selection signal generated by the second address comparator becomes invalid.

25. The spatiotemporal discretization control circuit according to claim 24, wherein, When the first channel selection signal is in a failed state When the first part of the address value of the channel is less than the second part of the spatial configuration value, the second channel selection signal generated by the second address comparator is valid. When the first part of the address value of the channel is greater than or equal to the second part of the spatial configuration value, the second channel selection signal generated by the second address comparator becomes invalid.

26. The spatiotemporal discretization control circuit according to claim 23 further includes, A bit-reversal selectable unit, electrically connected to the address grouping unit, is configured to perform a bit-reversal operation on the first part of the address value of the channel, and under the control of the operating mode control signal, selects either the first part of the address value of the channel or the first part of the bit-reversed channel address value for output; and The second address comparator is electrically connected to the outputs of the reverse selection unit and the incremental selection unit, and is configured to compare the output of the reverse selection unit with the output of the incremental selection unit and generate a second channel selection signal based on the comparison result. in, When the operating mode control signal requires the channel to be selected in reverse bit order, the output of the reverse order selection unit is the first part of the address value of the channel after bit reversal; or, when the operating mode control signal requires the channel to be selected in sequence, the output of the reverse order selection unit is the first part of the address value of the channel.

27. The spatiotemporal discretization control circuit according to claim 26, wherein, When the operating mode control signal requires the channel to be selected in reverse bit order and the first channel selection signal is valid. When the first part of the address value of the channel after bit reversal is less than the value of the second part of the spatial configuration value plus 1, the second channel selection signal generated by the second address comparator is in a valid state; When the first part of the address value of the channel after bit reversal is greater than or equal to the value of the second part of the space configuration value plus 1, the second channel selection signal generated by the second address comparator becomes invalid.

28. The spatiotemporal discretization control circuit according to claim 27, wherein, When the operating mode control signal requires the channel to be selected in reverse bit order and the first channel selection signal is invalid. When the first part of the address value of the channel after bit reversal is less than the second part of the space configuration value, the second channel selection signal generated by the second address comparator is in a valid state. When the first part of the address value of the channel after bit reversal is greater than or equal to the second part of the space configuration value, the second channel selection signal generated by the second address comparator is in a failed state.

29. The spatiotemporal discretization control circuit according to claim 26, wherein, The reverse order optional units include, A bit reversal component, electrically connected to the address grouping unit, is configured to perform a bit reversal operation on the first part of the address value of the channel; as well as A first multiplexer, electrically connected to the address grouping unit and the reversal component, is configured to select and output either the first part of the address value of the channel or the first part of the address value of the channel after bit reversal, under the control of the operating mode control signal.

30. The spatiotemporal discretization control circuit according to claim 20, wherein, Incremental optional units include, An addition component, electrically connected to the spatial configuration value grouping unit, is configured to increment the second part of the spatial configuration value by 1. as well as The second multiplexer is electrically connected between the spatial configuration value grouping unit and the addition component, and electrically connected to the output of the first address comparator. It is configured to select one of the second part of the spatial configuration value or the value of the second part of the spatial configuration value plus 1 for output under the control of the first channel selection signal.

31. The spatiotemporal discretization control circuit according to claim 22, further comprising: A mode selection unit, electrically connected to the output of the incremental selectable unit, is configured to transmit the output of the incremental selectable unit under the control of a coupling enable signal; and A data selector, electrically connected to the mode selection unit, is configured to receive an optional time configuration value and the output of an incremental selectable unit transmitted by the mode selection unit, and, under the control of the data selection signal, select one of the optional time configuration value or the output of the mode selection unit.

32. The spatiotemporal discretization control circuit according to claim 31, further comprising: A time discretization module, electrically connected to the data selector, is configured to receive time grouping values ​​and the output of the data selector, and use the output of the data selector as a time configuration value to generate a count value selection signal based on the time configuration value; wherein... The time configuration value corresponds to the duty cycle of the target PWM signal; The time configuration value is a J-bit binary number, where J is a positive integer greater than or equal to 1; the time grouping value is used to determine the number of sub-PWM signals that the target PWM signal is equivalent to, and the duty cycle of the target PWM signal is equal to 2. A The sum of the duty cycles of the sub-PWM signals; the time grouping value is A; where A is a positive integer less than or equal to J and greater than or equal to 1; including, A counter is configured to perform cyclic counting and output a count value; wherein the range of the counter's count value corresponds to the period of the target PWM signal; A counting value grouping unit, electrically connected to the counter, is configured to divide the counting value into a first part and a second part based on time grouping values ​​and output them respectively; the first part of the counting value includes the remaining bits of the counting value except for the high A bit; the second part of the counting value includes the high A bit of the counting value; wherein, the first part of the counting value represents the sequence number of the counting value in the counting value group, and the second part of the counting value represents the sequence number of the counting value group in which the counting value belongs; A time configuration value grouping unit, electrically connected to the data selector, is configured to divide the time configuration value into a first part and a second part based on the time grouping value and output them respectively; wherein, the first part of the time configuration value includes the low A bits of the time configuration value, which are related to the sequence number of the count value group; the second part of the time configuration value includes the remaining bits other than the low A bits of the time configuration value, which are related to the duty cycle of the sub-PWM signal; A first counter value comparator is electrically connected to the time configuration value grouping unit and the counter value grouping unit, and is configured to compare a first part of the time configuration value with a second part of the counter value after bit reversal and generate a counter value grouping selection signal based on the comparison result. An incremental selection unit, electrically connected to the time configuration value grouping unit and the first count value comparator, is configured to increment the second part of the time configuration value by 1, and under the control of the count value grouping selection signal, selects the value after incrementing the second part of the time configuration value or the second part of the time configuration value for output; The reverse selection unit is electrically connected to the count value grouping unit and is configured to perform a bit reversal operation on the first part of the count value. Under the control of the working mode control signal, it selects the first part of the count value or the first part of the count value after bit reversal for output. A second counter value comparator is electrically connected to the reverse selection unit and the incremental selection unit, and is configured to compare the output of the reverse selection unit with the output of the incremental selection unit and generate a counter value selection signal based on the comparison result. Specifically, when the second part of the bit-reversed count value is less than or equal to the first part of the time configuration value, the count value group selection signal generated by the first count value comparator is valid; and the output of the incremental selection unit is the value obtained by adding 1 to the second part of the time configuration value; when the working mode control signal requires the count value in the count value group to be selected in bit-reversed manner, the output of the reverse selection unit is the first part of the bit-reversed count value; the second count value comparator compares the first part of the bit-reversed count value with the value obtained by adding 1 to the second part of the time configuration value, and when the first part of the bit-reversed count value is less than the value obtained by adding 1 to the second part of the time configuration value, the count value selection signal generated by the second count value comparator is valid.

33. The spatiotemporal discretization control circuit according to claim 32, wherein, The ports of the second output terminal of the counting value grouping unit are electrically connected to the ports of the second input terminal of the first counting value comparator in reverse order.

34. The spatiotemporal discretization control circuit according to claim 33, wherein, The first counter value comparator compares the first part of the time configuration value with the second part of the counter value after bit reversal. When the second part of the counter value after bit reversal is greater than the first part of the time configuration value, the counter value grouping selection signal is in a failed state.

35. The spatiotemporal discretization control circuit according to claim 34, wherein, When the count value group selection signal is in a failed state, the output of the incremental selection unit is the value of the second part of the time configuration value.

36. The spatiotemporal discretization control circuit according to claim 35, wherein, When the operating mode control signal requires the count value in the count value group to be selected in a sequential manner, the output of the reverse selection unit is the first part of the count value after bit reversal.

37. The spatiotemporal discretization control circuit according to claim 36, wherein, When the count value group selection signal is valid, the number of count values ​​selected in the count value group is the decimal number corresponding to the second part of the time configuration value plus 1; or, When the count value group selection signal fails, the number of count values ​​selected in the count value group is the decimal number corresponding to the value of the second part of the time configuration value.

38. The spatiotemporal discretization control circuit according to claim 37, wherein, The operating mode control signal requires that the count value in the count value group be selected in reverse bit order, and the count value selection signal is valid. When the first part of the count value after bit reversal is less than the value of the second part of the time configuration value plus 1, the count value selection signal generated by the second count value comparator is in a valid state. When the first part of the count value after bit reversal is greater than or equal to the value of the second part of the time configuration value plus 1, the count value selection signal generated by the second count value comparator is in a failure state.

39. The spatiotemporal discretization control circuit according to claim 38, wherein, The operating mode control signal requires the count value in the count value group to be selected in reverse bit order, and the count value selection signal is ineffective. When the first part of the bit-reversed count value is less than the second part of the time configuration value, the count value selection signal generated by the second count value comparator is in a valid state. When the first part of the bit-reversed count value is greater than or equal to the second part of the time configuration value, the count value selection signal generated by the second count value comparator is in a failure state.

40. An electronic device comprising the spatiotemporal discretization control circuit according to any one of claims 20-39.

41. A spatiotemporal discretization control circuit, comprising: The time discretization module is configured to receive time group values ​​and time configuration values, and generate a count value selection signal based on the time configuration values; wherein... The time configuration value corresponds to the duty cycle of the target PWM signal; The time configuration value is a J-bit binary number, where J is a positive integer greater than or equal to 1; the time grouping value is used to determine the number of sub-PWM signals that the target PWM signal is equivalent to, and the duty cycle of the target PWM signal is equal to 2. A The sum of the duty cycles of the sub-PWM signals; the time grouping value is A; where A is a positive integer less than or equal to J and greater than or equal to 1; including, A counter is configured to perform cyclic counting and output a count value; wherein the range of the counter's count value corresponds to the period of the target PWM signal; A counting value grouping unit, electrically connected to the counter, is configured to divide the counting value into a first part and a second part based on time grouping values ​​and output them respectively; the first part of the counting value includes the remaining bits of the counting value except for the high A bit; the second part of the counting value includes the high A bit of the counting value; wherein, the first part of the counting value represents the sequence number of the counting value in the counting value group, and the second part of the counting value represents the sequence number of the counting value group in which the counting value belongs; A time configuration value grouping unit, electrically connected to the data selector, is configured to divide the time configuration value into a first part and a second part based on the time grouping value and output them respectively; wherein, the first part of the time configuration value includes the low A bits of the time configuration value, which are related to the sequence number of the count value group; the second part of the time configuration value includes the remaining bits other than the low A bits of the time configuration value, which are related to the duty cycle of the sub-PWM signal; A first counter value comparator is electrically connected to the time configuration value grouping unit and the counter value grouping unit, and is configured to compare a first part of the time configuration value with a second part of the counter value after bit reversal and generate a counter value grouping selection signal based on the comparison result. An incremental selection unit, electrically connected to the time configuration value grouping unit and the first count value comparator, is configured to increment the second part of the time configuration value by 1, and under the control of the count value grouping selection signal, selects the value after incrementing the second part of the time configuration value or the second part of the time configuration value for output; The reverse selection unit is electrically connected to the count value grouping unit and is configured to perform a bit reversal operation on the first part of the count value. Under the control of the working mode control signal, it selects the first part of the count value or the first part of the count value after bit reversal for output. A second counter value comparator is electrically connected to the reverse selection unit and the incremental selection unit, and is configured to compare the output of the reverse selection unit with the output of the incremental selection unit and generate a counter value selection signal based on the comparison result. Specifically, when the second part of the bit-reversed count value is less than or equal to the first part of the time configuration value, the count value group selection signal generated by the first count value comparator is valid; and the output of the incremental selection unit is the value obtained by adding 1 to the second part of the time configuration value; when the working mode control signal requires the count value in the count value group to be selected in bit-reversed manner, the output of the reverse selection unit is the first part of the bit-reversed count value; the second count value comparator compares the first part of the bit-reversed count value with the value obtained by adding 1 to the second part of the time configuration value, and when the first part of the bit-reversed count value is less than the value obtained by adding 1 to the second part of the time configuration value, the count value selection signal generated by the second count value comparator is valid.

42. The spatiotemporal discretization control circuit according to claim 41, wherein, The ports of the second output terminal of the counting value grouping unit are electrically connected to the ports of the second input terminal of the first counting value comparator in reverse order.

43. The spatiotemporal discretization control circuit according to claim 42, wherein, The first counter value comparator compares the first part of the time configuration value with the second part of the counter value after bit reversal. When the second part of the counter value after bit reversal is greater than the first part of the time configuration value, the counter value grouping selection signal is in a failed state.

44. The spatiotemporal discretization control circuit according to claim 43, wherein, When the count value group selection signal is in a failed state, the output of the incremental selection unit is the value of the second part of the time configuration value.

45. The spatiotemporal discretization control circuit according to claim 44, wherein, When the operating mode control signal requires the count value in the count value group to be selected in a sequential manner, the output of the reverse selection unit is the first part of the count value after bit reversal.

46. ​​The spatiotemporal discretization control circuit according to claim 45, wherein, When the count value group selection signal is valid, the number of count values ​​selected in the count value group is the decimal number corresponding to the second part of the time configuration value plus 1; or, When the count value group selection signal fails, the number of count values ​​selected in the count value group is the decimal number corresponding to the value of the second part of the time configuration value.

47. The spatiotemporal discretization control circuit according to claim 46, wherein, The operating mode control signal requires that the count value in the count value group be selected in reverse bit order, and the count value selection signal is valid. When the first part of the count value after bit reversal is less than the value of the second part of the time configuration value plus 1, the count value selection signal generated by the second count value comparator is in a valid state. When the first part of the count value after bit reversal is greater than or equal to the value of the second part of the time configuration value plus 1, the count value selection signal generated by the second count value comparator is in a failure state.

48. The spatiotemporal discretization control circuit according to claim 47, wherein, The operating mode control signal requires the count value in the count value group to be selected in reverse bit order, and the count value selection signal is ineffective. When the first part of the bit-reversed count value is less than the second part of the time configuration value, the count value selection signal generated by the second count value comparator is in a valid state. When the first part of the bit-reversed count value is greater than or equal to the second part of the time configuration value, the count value selection signal generated by the second count value comparator is in a failure state.

49. The spatiotemporal discretization control circuit according to claim 41, wherein, The reverse selection unit includes... A reversal component, electrically connected to the count value grouping unit, is configured to perform a bit reversal operation on a first portion of the count value; as well as A first selector, electrically connected to the count value grouping unit and the reversal component, is configured to select and output either a first portion of the count value or a first portion of the count value after bit reversal, under the control of a working mode control signal.

50. The spatiotemporal discretization control circuit according to claim 41, wherein, The incremental selection unit includes, An adder, electrically connected to the time configuration value grouping unit, is configured to increment the second part of the time configuration value by 1. as well as The second selector, electrically connected between the time configuration value grouping unit and the adder and electrically connected to the output of the first count value comparator, is configured to select, under the control of the count value grouping selection signal, either the second part of the time configuration value or the value of the second part of the time configuration value plus 1 for output.

51. An electronic device comprising the spatiotemporal discretization control circuit according to any one of claims 41-50.

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