A saturated current triode and its manufacturing method
By setting a JFET region between the base regions of the transistor, an additional carrier path is formed, which solves the problems of insufficient current and high on-state voltage drop in the saturation region of the transistor, and achieves high efficiency and low loss in high-frequency and high-power applications.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Filing Date
- 2026-04-22
- Publication Date
- 2026-07-10
Smart Images
Figure CN122373442A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a transistor for improving saturation current and its fabrication method. Background Technology
[0002] In the field of power electronic device technology, transistors, as core semiconductor switching and amplifying devices, are widely used in high-frequency conversion, power drive, and other scenarios. Their three operating states—cutoff region, amplification region, and saturation region—directly determine the system efficiency and reliability. The saturation region is the critical operating range for a transistor to conduct under full load. When the device enters the saturation region, the collector current reaches its extreme value and no longer increases with the base current, resulting in a sharp decrease in current amplification. At the same time, the collector-emitter voltage drop VCE is difficult to further reduce, causing inherent defects such as high conduction losses, slow switching speed, severe heat generation, and limited efficiency. This has become a core bottleneck restricting the development of transistors towards higher frequencies, higher efficiency, and higher power.
[0003] In existing traditional transistor structures, the carrier transport path in the saturation region is singular, and the current output mainly relies on the base-emitter injection efficiency. There is a lack of mechanisms to supplement the saturation current, making it impossible to increase the saturation current without increasing the base current or chip area. Furthermore, traditional structures lack sufficient control over the depletion region distribution and carrier regulation. When VBE exceeds VCE and the collector junction becomes forward biased, they cannot effectively delay the device from entering deep saturation, nor can they effectively reduce the saturation voltage drop VCE. The industry typically improves performance by increasing the device area, improving base injection efficiency, or optimizing doping distribution. However, these methods significantly increase chip size and manufacturing costs, exacerbate charge storage effects, reduce switching speed, and fail to address the fundamental problems of insufficient saturation current and high saturation voltage drop from a structural mechanism perspective.
[0004] In summary, existing transistors generally suffer from technical challenges such as low saturation current under the same base current, high VCE in the saturation region, and high conduction losses. These limitations prevent breakthroughs in saturation performance while maintaining conventional processes, device dimensions, and manufacturing costs. Therefore, innovative designs at the structural mechanism level are urgently needed to construct additional carrier conduction paths, thereby increasing saturation current, delaying deep saturation, and reducing VCE. This will meet the pressing demands of modern power electronic systems for high-efficiency, low-loss, and high-power-density semiconductor devices. Summary of the Invention
[0005] To address the above problems, this invention, without altering existing transistor manufacturing processes and device dimensions, achieves increased saturation current, delayed deep saturation, and reduced VCE, thereby meeting the demands of modern power electronic systems for high efficiency, low loss, and high power density. This invention provides a transistor with improved saturation current and its fabrication method.
[0006] The technical solution of this invention is: Step S100: A first doped base region is prepared in the epitaxial wafer, and several spaced second doped emitter regions are prepared in the first doped base region. Step S200: A trench is formed in the second doped emitter region; below the trench, a second doped JFET region is formed in the first doped base region, connecting the second doped emitter region and the epitaxial drift region. Step S300: An emitter electrode is prepared in the trench, an isolation layer is prepared on the epitaxial wafer, and a window is opened in the isolation layer above the spacer region of a pair of second doped emitter regions to prepare a base electrode. Step S400: Prepare a collector electrode on the back side of the epitaxial wafer.
[0007] Specifically, step S100 includes: Step S110: Using photolithography, a mask is used to protect the outer region of the first doped base region; the first doped base region is formed by diffusion or ion implantation. Step S120: Using photolithography, a mask is used to protect the outer region of the second doped emission region; through diffusion or ion implantation, several spaced second doped emission regions are formed. Specifically, step S200 includes: Step S210: Using photolithography, a mask is used to protect the outer area of the trench; the trench is formed through etching. Step S220: Using photolithography, a mask is used to protect the outer region of the second doped JFET region; the second doped JFET region is formed by ion implantation. Specifically, step S300 includes: Step S310: Using photolithography, a mask is used to protect the external area of the emitter electrode, and a lift-off or etching process is used to fabricate the emitter electrode in the trench. In step S320, an isolation layer is prepared by chemical vapor deposition. The outer area of the base electrode is protected by a mask using photolithography. A window is opened by etching. The base electrode is prepared at the window using a lift-off process or an etching process.
[0008] Specifically, step S400 includes: Step S410: Thin the epitaxial wafer using a thinning process, and fabricate a collector electrode on the back side of the epitaxial wafer using a sputtering or deposition process. A transistor for improving saturation current includes a collector electrode, an epitaxial wafer, and an isolation layer arranged sequentially from bottom to top. The epitaxial wafer contains: The first doped base region extends downward from the top surface of the epitaxial wafer; The second doped emitter region is provided in a plurality of them, which extend downward from the top surface of the first doped base region and are spaced apart from the bottom surface of the first doped base region. The second doped JFET region is provided in several parts, each located below the corresponding second doped emitter region; the upper surface of the second doped JFET region is connected to the second doped emitter region, and the lower surface is connected to the epitaxial wafer drift region. The emitter electrode is provided in several parts, located within the second doped emitter region, and connected to the second doped emitter region to form a good ohmic contact; The base electrode has several portions, each extending downward from the top surface of the isolation layer and connected to the first doped base region to form a good ohmic contact.
[0009] Specifically, the second doped JFET region and the first doped base regions on both sides form PN junctions; When the PN junction is reverse biased and zero biased, a depletion layer extending towards the center is formed in the second doped JFET region; The extended width of the depletion layer within the second-doped JFET region 5 can completely clamp the conductive channel of the second-doped JFET region.
[0010] Specifically, the width of the second doped JFET region is smaller than the width of the emitter electrode.
[0011] Specifically, the first doped base region and the second doped emitter region are heterogeneous doped.
[0012] Specifically, the first doped base region and the second doped emitter region are respectively P-type and N-type doped or N-type and P-type doped.
[0013] Specifically, the epitaxial wafer and the second doped emitter region are doped with the same type of material, either both being P-type doped or both being N-type doped.
[0014] This invention, without altering existing transistor fabrication processes or increasing chip area, employs an innovative structural design to add a JFET region between the base region and directly connect it to the emitter region and the epitaxial wafer drift region. By rationally configuring the doping concentration and critical dimensions of the JFET region, precise control of the device's saturation region characteristics is achieved. When the transistor is in the amplification region and has not entered the saturation state, the JFET region is completely depleted by the base regions on both sides, which does not affect the normal operation of the device's amplification region. As the transistor transitions to the saturation region (VBE > VCE) and the base-collector junction becomes forward biased, the width of the depletion layer formed by the JFET region and the two base regions decreases significantly with increasing forward bias. The conductive channel that was originally blocked by depletion becomes conductive again. Electrons injected into the emitter region can form an additional carrier path through the JFET region, directly transporting to the collector region and effectively supplementing the saturation current. This significantly improves the saturation current capability, delays the device from entering deep saturation, and effectively reduces the collector-emitter voltage VCE when the device enters the saturation region, thus reducing conduction losses. The overall solution, while maintaining compatibility with existing processes and keeping device size and cost constant, overcomes the inherent defects of traditional transistors, such as limited saturation current and high on-state voltage drop, significantly improving the reliability and efficiency of the device in high-frequency, high-power, and low-loss applications. Attached Figure Description
[0015] Figure 1 This is a process flow diagram of the present invention; Figure 2 This is a schematic diagram of the cross-sectional structure of the first doped base region; Figure 3 This is a schematic diagram of the cross-sectional structure for preparing the second-doped emitter region; Figure 4 This is a schematic diagram of the fabricated trench cross-section structure; Figure 5 This is a schematic diagram of the cross-sectional structure of the second-doped JFET region; Figure 6 This is a schematic diagram of the fabrication of the emitter electrode cross-sectional structure. Figure 7 This is a schematic diagram of the fabrication of the isolation layer and the cross-sectional structure of the base electrode; Figure 8 This is a schematic diagram of the cross-sectional structure of the current collector electrode; In the figure, 1 is the epitaxial wafer, 2 is the first doped base region, 3 is the second doped emitter region, 4 is the trench, 5 is the second doped JFET region, 6 is the emitter electrode, 7 is the isolation layer, 8 is the base electrode, and 9 is the collector electrode. Detailed Implementation
[0016] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.
[0017] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0018] The following is for reference. Figure 1-8 Describe the present invention; A transistor for improving saturation current and its fabrication method, comprising the following steps: Step S100: A first doped base region 2 is prepared within the epitaxial wafer 1, and several spaced second doped emitter regions 3 are prepared within the first doped base region 2, as shown in the figure. Figure 2-3 As shown; Step S110: Using photolithography, a mask is used to protect the outer region of the first doped base region 2; the first doped base region 2 is formed by diffusion or ion implantation. Step S120: Using photolithography, a mask is used to protect the outer region of the second doped emission region 3; through diffusion or ion implantation, a number of spaced second doped emission regions 3 are formed. Accordingly, the first doped base region 2 is a P-region, and the doping concentration range is 1e. 15 .cm -3 -1e 20 .cm -3 The second doped emitter region 3 is an N-region, with a doping concentration range of 1e. 14 .cm -3 -1e 20 .cm -3 The doping concentration of the first doped base region 2 is not less than the doping concentration of the second doped emitter region 3. The epitaxial wafer 1 is an N-type epitaxial wafer with a thickness of 100-2000 μm. The thickness of the first doped base region 2 is set to 1-50 μm, the thickness of the second doped emitter region 3 is set to 0.5-49 μm, the width is set to 1-50 μm, and the spacing width is set to 1-50 μm. The relevant parameter settings are related to the electrical design of the device. In this embodiment, the thickness of the epitaxial wafer 1 is 350 μm; the thickness of the first doped base region 2 is 5 μm, and the doping concentration is 1e. 17 .cm -3 The second doped emitter region 3 has a thickness of 3 μm and a doping concentration of 1e. 19. cm -3 The first doped base region 2 and the second doped emitter region 3 are prepared using an ion implantation process with a spacing width of 10 μm.
[0019] Step S200: A trench 4 is prepared in the second doped emitter region 3, and a second doped JFET region 5 is prepared in the first doped base region 2 to connect the second doped emitter region 3 and the drift region of the epitaxial wafer 1. Specifically, in this case, the second doped JFET region 5 is located below the trench 4, with its upper surface connected to the second doped emitter region 3 and its lower surface connected to the drift region of the epitaxial wafer 1. The second doped JFET region 5 and the first doped base regions 2 on both sides form a depletion layer. The second doped JFET region 5 and the first doped base regions 2 on both sides form PN junctions respectively. When the PN junctions are reverse biased and zero biased, a depletion layer extending towards the center is formed in the second doped JFET region 5. The width of the depletion layer extending in the second doped JFET region 5 can completely cut off the conductive channel of the second doped JFET region 5. (Refer to...) Figure 4-5 As shown; Step S210: Using photolithography, a mask is used to protect the outer area of the trench 4; the trench 4 is formed by etching. Step S220: Using photolithography, a mask is used to protect the outer region of the second doped JFET region 5; the second doped JFET region 5 is formed by ion implantation. Accordingly, the trench 4 depth is set to 0.1-48um and the width is set to 0.5-49um, and the width of the second doped JFET region 5 is set to 0.01-5um. The relevant parameter settings are related to the device electrical design. In this embodiment, trench 4 has a depth of 2µm and a width of 10µm, and the second doped JFET region 5 has a width of 0.3µm and a doping concentration of 1e. 16 .cm -3 Trench 4 was prepared using an etching process, and second-doped JFET region 5 was prepared using an ion implantation process.
[0020] In step S300, an emitter electrode 6 is fabricated within the trench 4, and an isolation layer 7 is fabricated on the epitaxial wafer 1; a window is opened within the isolation layer 7 above the spacer region of a pair of second-doped emitter regions 3 to fabricate a base electrode 8, as shown in the reference. Figure 6-7 As shown; Step S310: Using photolithography, a mask is used to protect the external area of the emitter electrode 6, and a lift-off process or an etching process is used to fabricate the emitter electrode 6 in the trench 4. In step S320, an isolation layer 7 is prepared by chemical vapor deposition. The outer area of the base electrode 8 is protected by a mask using photolithography. A window is opened by etching. The base electrode 8 is prepared at the window using a lift-off process or an etching process.
[0021] Correspondingly, the emitter electrode 6 contacts the second doped emitter region 3 to form an ohmic contact, the isolation layer 7 plays a protective role, the material is SiO2 or Si3N4, the thickness is set to 10-5000nm, and the window is opened by ICP dry etching. The window of the base electrode 8 extends downward from the top surface of the isolation layer 7 into the interior of the first doped base region 2, and the base electrode 8 contacts the first doped base region 2 to form an ohmic contact. The relevant parameter settings are related to the electrical design of the device. In this embodiment, a 2µm thick Ti / Al double-layer metal is prepared in the trench 4 as the emitter electrode 6 using a stripping process. Si3N4 is used as the isolation layer 7 with a thickness of 200nm. ICP dry etching is used to open the window with a depth of 200nm. A 200nm thick Ti / Al double-layer metal is prepared as the base electrode 8 using a local heavy doping remetallization process and a stripping process.
[0022] Step S400: Fabricate collector electrode 9 on the back side of the epitaxial wafer, referring to... Figure 8 As shown; Correspondingly, the epitaxial wafer 1 is thinned to the corresponding thickness through a thinning process, and the collector electrode 9 is prepared on the back side of the epitaxial wafer using a deposition process or a sputtering process; In this embodiment, a thinning process is used to reduce the thickness of the 350µm epitaxial wafer 1 to 180µm, and a deposition process is used to prepare a 1µm thick Ti / Ni / Ag as the collector electrode 9.
[0023] A transistor for improving saturation current includes a collector electrode 9, an epitaxial wafer 1, and an isolation layer 7 arranged sequentially from bottom to top. The epitaxial wafer 1 contains: The first doped base region 2 extends downward from the top surface of the epitaxial wafer 1; The second doped emitter region 3 is provided in a plurality of them, which extend downward from the top surface of the first doped base region 2 and are spaced apart from the bottom surface of the first doped base region 2. The second doped JFET region 5 is provided in several places, which are respectively located below the corresponding second doped emitter region 3. Its upper surface is connected to the second doped emitter region 3 and its lower surface is connected to the drift region of the epitaxial wafer 1. The emitter electrode 6 is provided in several parts, which are respectively located in the second doped emitter region 3 and are connected to the second doped emitter region 3 to form a good ohmic contact; The isolation layer 7 contains a plurality of base electrodes 8 located between a pair of second doped emitter regions 3; the base electrodes 8 extend downward from the top surface of the isolation layer 7 and are connected to the first doped base region 2 to form a good ohmic contact.
[0024] The two sides of the second doped JFET region 5 form PN junctions with the first doped base region 2 respectively. When the PN junction is reverse biased and zero biased, a depletion layer extending to both sides will be formed at the PN junction. By optimizing the doping concentration and width of the second doped JFET region 5, the extension width of the depletion layer in the second doped JFET region 5 can completely deplete the conductive area of the JFET region, thereby achieving complete pinch-off of the JFET channel, thus improving the blocking capability and turn-off reliability of the device, without affecting the performance of the device before entering the saturation region.
[0025] The width of the second doped JFET region 5 is smaller than the width of the emitter electrode 6, and the doping concentration of the second doped JFET region 5 is lower than the doping concentration of the first doped base region 2.
[0026] The first doped base region 2 and the second doped emitter region 3 are P- and N-doped or N- and P-doped, and the epitaxial wafer 1 and the second doped emitter region are both P- or N-doped.
[0027] This invention, based on existing conventional transistor process conditions and device size, employs an innovative structural design to create a JFET region between the base regions. The JFET region connects the emitter and collector regions. Through careful design of the doping concentration and size of the JFET region, when the transistor is not in the saturation region, the JFET region is completely depleted by the base regions on both sides. When the transistor enters the saturation region (VBE > VCE), the depletion layer generated by diffusion between the JFET region and the base regions decreases due to the forward bias from the base region to the collector region (VBE > VCE). Electrons from the emitter region then pass through the JFET region. When the FET region enters the collector region, it replenishes the saturation current of the transistor, delaying the transistor's entry into the saturation region and reducing the VCE of the device entering the saturation region. Compared to a normal structure transistor, when a normal structure transistor enters the saturation region, as VCE further decreases, the saturation current of the transistor drops rapidly. The present invention provides a transistor that increases the saturation current. Starting from the VCE of a normal structure transistor entering the saturation region, as VCE further decreases, the current is increased by 10%-80% compared to a normal structure transistor, and finally the VCE of the device entering the saturation region is reduced by 0.5V.
[0028] Regarding the information disclosed in this case, the following points need to be clarified: The accompanying drawings of the embodiments disclosed in this case only relate to the structures involved in the embodiments disclosed in this case; other structures can be referred to with ordinary designs. Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.
Claims
1. A method for fabricating a transistor with improved saturation current, characterized in that, Includes the following steps: Step S100: A first doped base region (2) is prepared in the epitaxial wafer (1), and a plurality of second doped emitter regions (3) are prepared in the first doped base region (2). In step S200, a trench (4) is prepared in the second doped emitter region (3); below the trench, a second doped JFET region (5) is prepared in the first doped base region to connect the second doped emitter region and the epitaxial drift region. Step S300: an emitter electrode (6) is prepared in the trench (4), an isolation layer (7) is prepared on the epitaxial wafer (1), and a window is opened in the isolation layer (7) above the spacer region of a pair of second doped emitter regions (3) to prepare a base electrode (8). Step S400: Prepare a collector electrode (9) on the back side of the epitaxial wafer.
2. The method for fabricating a transistor with improved saturation current according to claim 1, characterized in that, Step S100 includes: Step S110: Using photolithography, a mask is used to protect the outer region of the first doped base region (2); the first doped base region (2) is formed by diffusion or ion implantation. Step S120: Using photolithography, a mask is used to protect the outer region of the second doped emission region (3); through diffusion or ion implantation, several spaced second doped emission regions (3) are formed.
3. The method for fabricating a transistor with improved saturation current according to claim 1, characterized in that, Step S200 includes: Step S210: Using photolithography, a mask is used to protect the outer area of the trench (4); the trench (4) is formed by etching. Step S220: Using photolithography, a mask is used to protect the outer region of the second doped JFET region (5); the second doped JFET region (5) is formed by ion implantation. According to claim 1, the method for fabricating a transistor with improved saturation current is characterized in that step S300 includes: Step S310: Using photolithography, a mask is used to protect the external area of the emitter electrode (6), and the emitter electrode (6) is prepared in the trench (4) using a lift-off process or an etching process. Step S320: Prepare an isolation layer (7) using chemical vapor deposition, protect the outer area of the base electrode (8) using a mask through photolithography, open a window using an etching process, and prepare the base electrode (8) at the window using a lift-off process or an etching process.
4. The method for fabricating a transistor with improved saturation current according to claim 1, characterized in that, Step S400 includes: Step S410: Thin the epitaxial wafer using a thinning process, and prepare a collector electrode (9) on the back side of the epitaxial wafer using a sputtering or deposition process.
5. A transistor for improving saturation current, fabricated by the method for fabricating a transistor for improving saturation current as described in claim 1, characterized in that, It includes a collector electrode (9), an epitaxial wafer (1), and an isolation layer (7) arranged sequentially from bottom to top; The epitaxial wafer (1) contains: The first doped base region (2) extends downward from the top surface of the epitaxial wafer (1); The second doped emitter region (3) is provided in a plurality of such regions, which extend downward from the top surface of the first doped base region (2) and are spaced apart from the bottom surface of the first doped base region (2); The second doped JFET region (5) is provided in several places, which are respectively located below the corresponding second doped emitter region (3); the upper surface of the second doped JFET region (5) is connected to the second doped emitter region (3), and the lower surface is connected to the drift region of the epitaxial wafer (1); The emitter electrode (6) is provided in several places, located in the second doped emitter region (3), connected to the second doped emitter region (3) and forming a good ohmic contact; The base electrode (8) has several portions, which extend downward from the top surface of the isolation layer (7) and are connected to the first doped base region (2) to form a good ohmic contact.
6. A transistor for improving saturation current according to claim 5, characterized in that, The second doped JFET region (5) and the first doped base regions (2) on both sides form PN junctions respectively; When the PN junction is reverse biased and zero biased, a depletion layer extending toward the center is formed in the second doped JFET region (5); The extended width of the depletion layer within the second doped JFET region 5 can completely clamp the conductive channel of the second doped JFET region (5).
7. A transistor for improving saturation current according to claim 5, characterized in that, The width of the second doped JFET region (5) is smaller than the width of the emitter electrode (6).
8. A transistor for improving saturation current according to claim 5, characterized in that, The first doped base region (2) and the second doped emitter region (3) are heterogeneous doped.
9. A transistor for improving saturation current according to claim 8, characterized in that, The first doped base region (2) and the second doped emitter region (3) are respectively P-type and N-type doped or N-type and P-type doped.
10. A transistor for improving saturation current according to claim 5, characterized in that, The epitaxial wafer (1) and the second doped emitter region (3) are doped of the same type, either P-type or N-type.