Universal IOMUX architecture and configuration control method

Abstract

The application discloses a general IOMUX architecture and a configuration control method, and belongs to the technical field of input / output multiplexers.The architecture comprises a port management module, a signal routing module, a configuration control module, a protocol adaptation module and a state monitoring module; the configuration control module adopts a composite configuration mechanism combining static and dynamic modes, receives external configuration instructions, parses the external configuration instructions into configuration parameters of each module, sends the configuration parameters to each module, and stores and dynamically updates the configuration parameters; the protocol adaptation module adopts a two-stage adaptation structure of protocol analysis and timing adjustment to adapt the output signals of the internal functional modules of chips of different communication protocols, so that the protocol requirements of external equipment are met.The application can flexibly adapt to the differentiated requirements of different chip types through modular architecture design; when applied to a new chip, a developer only needs to adjust the configuration parameters, and does not need to modify the internal core logic of each module.

Description

Technical Field

[0001] This invention relates to the field of input / output multiplexer technology, and in particular to a general IOMUX architecture and configuration control method. Background Technology

[0002] In integrated circuit design, the IOMUX (Input / Output Multiplexer) is the core module for realizing multi-functional multiplexing of chip I / O ports. Its core function is to dynamically map signals from different internal functional modules (such as UART, SPI, I2C, GPIO, etc.) to external physical I / O ports through configuration control. This expands the external interface functionality of the chip with a limited number of physical ports, reducing chip packaging costs and hardware design complexity.

[0003] With the rapid development of chip technology, chip architectures are becoming increasingly complex, and functional modules are constantly increasing. This leads to the following characteristics in the demand for IOMUX: First, the requirements for adaptability are increasing. Different types of chips (such as automotive electronic chips, industrial control chips, and consumer electronics chips) have significantly different I / O port numbers and functional requirements. Traditional IOMUXs are mostly custom-developed for specific chips and cannot be directly reused for other chips, resulting in long development cycles and a lot of repetitive work. Second, configuration flexibility is insufficient. The function mapping of traditional IOMUXs is mostly statically configured (i.e., cannot be modified after the chip is powered on), making it difficult to meet the needs of port function adjustment in dynamic scenarios (such as switching port functions based on external device access during chip operation). Third, protocol compatibility is poor. Existing IOMUXs typically only support a few fixed communication protocols. When a chip needs to be compatible with new protocols (such as CAN), further compatibility becomes difficult. When using FD, Ethernet, etc., the signal adaptation logic of IOMUX needs to be redesigned, which significantly increases the development and verification costs; fourth, the verification efficiency is low. Due to the customized nature of traditional IOMUX, the IOMUX of each new chip needs to rebuild the verification environment and design test cases. The verification cycle often accounts for 30%-50% of the overall chip development cycle, which seriously affects the chip's time to market.

[0004] Currently, industry improvements to IOMUX mostly focus on localized optimizations, such as increasing flexibility by adding configuration registers or extending adaptability for specific protocols. However, a universal IOMUX architecture and implementation method that can cover multiple chip types, multiple communication protocols, support dynamic configuration, and is easily reusable has not yet been formed. Specifically, the following shortcomings exist: 1. Limitations of Customized Architecture: Traditional IOMUX architecture is tightly coupled with the specific hardware design of the chip. For example, the number of ports, the definition of internal functional module interfaces, and signal timing parameters all need to be determined according to the specific chip. Once the chip architecture changes, IOMUX needs to be redesigned, and the reuse rate is less than 30%. 2. Limited configuration mechanism: Existing IOMUX mostly adopts a static configuration mode. Once the configuration parameters are written through hardware fuses or initialization code, they cannot be modified. This makes it impossible to cope with scenarios such as dynamic access / disconnection of external devices and switching of functional modules during chip operation. 3. Weak protocol compatibility: IOMUX's signal processing logic is bound to specific protocols. For example, IOMUX that supports the UART protocol cannot be directly adapted to the SPI protocol. It is necessary to redesign modules such as signal timing adjustment and data format parsing, which results in high development costs. 4. High verification complexity: Each customized IOMUX requires a separate verification platform (such as the UVM platform) to be built, and test cases covering port mapping, signal transmission, and fault scenarios to be designed. The verification workload is large, and the verification assets (such as test cases and environment components) of different IOMUXs cannot be reused, which further extends the development cycle.

[0005] Therefore, developing a general-purpose IOMUX architecture with high adaptability, high flexibility, multi-protocol compatibility and low verification cost has become a key requirement to solve the pain points in the current chip design and verification field. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a general IOMUX architecture and configuration control method that adapts to the I / O port reuse requirements of different types of chips, reduces the customized development cost of IOMUX, supports a combination of static and dynamic configuration methods to meet the real-time adjustment of port functions during chip operation, is compatible with multiple mainstream communication protocols, reduces the redesign workload when expanding protocols, improves the reusability of IOMUX and related verification assets, and shortens the chip development and verification cycle.

[0007] The objective of this invention is achieved through the following technical solution: The first aspect of this invention provides: a general IOMUX architecture, including a port management module, wherein the port management module is connected to a signal routing module, a configuration control module and a protocol adaptation module, wherein the configuration control module is connected to a status monitoring module, a signal routing module and a protocol adaptation module, and each module is connected through an internal bus; The port management module is used to configure port attributes and classify ports, thereby enabling unified management of the chip's physical I / O ports. The signal routing module is used to establish a signal path between the internal functional modules of the chip and the external physical port; The configuration control module adopts a composite configuration mechanism that combines static and dynamic methods. It receives external configuration commands, parses the external configuration commands into configuration parameters for each module, sends them to each module, and stores and dynamically updates the configuration parameters. The status monitoring module is used to monitor the operating status of IOMUX in real time, periodically collect status data, identify faults, and generate alarms. The protocol adaptation module employs a two-level adaptation structure of protocol parsing and timing adjustment to adapt the output signals of the internal functional modules of the chip to different communication protocols, thereby meeting the protocol requirements of external devices.

[0008] Preferably, the port management module includes a port attribute configuration unit and a port classification unit; the port attribute configuration unit is used to configure the electrical parameters, timing parameters and operating modes of the chip's physical I / O ports; The port classification unit is used to divide the chip's physical I / O ports into general-purpose port groups, high-speed port groups, and dedicated port groups according to their physical characteristics and functional scenarios, so as to facilitate subsequent signal routing matching.

[0009] Preferably, the signal routing module includes a cross switch and a routing table; the cross switch includes N×M configurable cross switch structures, each cross point corresponds to an independently controllable switch unit, and the connection / disconnection between any internal functional module of the chip and the external physical port is realized by the control signal, where N is the number of internal functional modules of the chip and M is the number of external physical ports; The routing table is used to store the mapping relationship data between the internal functional modules of the chip and the external physical ports. The mapping relationship data includes module ID, port ID, path priority and protocol type. The routing table is dynamically updated by the configuration control module, and the signal routing module automatically completes the path selection according to the routing table.

[0010] Preferably, the configuration control module includes a static configuration unit and a dynamic configuration unit; the static configuration unit is used to read preset configuration parameters from non-volatile memory during the chip power-on initialization phase to complete the initial configuration of each module; The dynamic configuration unit is used to receive external real-time configuration instructions during chip operation, parse the external real-time configuration instructions and update the configuration parameters, send the configuration effective signal to the module associated with the updated configuration parameters, adjust the port functions in real time, and perform configuration conflict detection. When the new configuration conflicts with the existing path, a conflict alarm is triggered and the invalid configuration is rejected.

[0011] Preferably, the status monitoring module includes a status acquisition unit, a fault judgment unit, and an alarm processing unit; the status acquisition unit is used to periodically acquire the electrical status of external physical ports, signal transmission status, and the working status of each module. The fault determination unit is used to compare the collected status data with a preset threshold to determine whether a fault exists. The alarm processing unit is used to generate an alarm signal when a fault is detected, store the fault information in the fault log, and trigger a fault recovery operation according to a preset strategy.

[0012] Preferably, the protocol adaptation module includes a protocol parsing submodule and a timing adjustment submodule; the protocol parsing submodule has pre-set parsing logic for multiple communication protocols, which is used to automatically identify the protocol format of the output signal of the internal functional module of the chip according to the protocol type in the routing table, and perform data frame parsing, check bit processing and protocol field extraction; The timing adjustment submodule is used to perform timing compensation on the parsed signal according to the timing parameters of the external physical port and the timing requirements of the external device, so as to meet the timing constraints.

[0013] The second aspect of this invention provides: a general IOMUX configuration control method, implemented based on a general IOMUX architecture, comprising the following steps: S1. Architecture Initialization: After the chip is powered on, the static configuration unit of the configuration control module reads the initialization configuration file from the non-volatile memory and parses the configuration parameters from the initialization configuration file to complete the initialization settings of the port management module, signal routing module, protocol adaptation module and status monitoring module, so that IOMUX enters the working state; the initialization configuration file includes port basic attributes, default routing table, protocol adaptation parameters and status monitoring threshold; S2. Port Configuration: After initialization, the user initiates a port configuration request through an external configuration tool or software command. The configuration control module receives the port configuration request, parses it to obtain the target port ID and target attribute parameters, updates the attribute parameters of the corresponding port through the port management module, and feeds back the configuration result to the configuration control module. If the configuration parameters exceed the allowed range, the configuration is rejected and an error code is returned. S3. Signal Routing Configuration: Based on the chip's functional requirements, the user initiates a signal routing configuration request. After receiving the request, the dynamic configuration unit queries the current routing table to check for configuration conflicts. If there are no conflicts, it updates the routing table, writing the mapping relationship between the internal functional module ID and the target external port ID, along with the protocol type, into the routing table. It then controls the signal routing module to establish a path between the corresponding internal functional module and the target external port. Simultaneously, it sends a protocol type notification to the protocol adaptation module, which loads the corresponding protocol parsing logic and sequence adjustment parameters to complete the signal adaptation preparation. S4. Dynamic Adjustment: During chip operation, receive dynamic adjustment requests and update port attributes, routing tables and protocol adaptation parameters according to the content of the dynamic adjustment requests to realize real-time adjustment of port functions or mapping relationships. S5. Status Monitoring and Fault Handling: The status monitoring module periodically collects operating status data and compares it with preset thresholds to determine faults; if a fault occurs, an alarm is generated, a fault log is recorded, and fault recovery operations are performed according to preset strategies. S6. Configuration and State Storage: After each configuration update, the current configuration parameters are backed up; and the fault logs are periodically backed up to non-volatile storage.

[0014] Preferably, in step S3, if the target external port ID is already occupied by another internal functional module, a conflict alarm is triggered and conflict information is returned.

[0015] Preferably, the dynamic adjustment request includes a port function adjustment request and a fault response request; When the dynamic adjustment request is a port function adjustment request, update the attribute parameters of the target port and remap the target port to the new internal function module; When a dynamic adjustment request is a fault response request, the internal functional module mapped to the port that failed is remapped to a backup port, and the routing table and protocol adaptation parameters are updated.

[0016] The beneficial effects of this invention are: 1) High Adaptability and Reusability: This invention employs a modular architecture design, clearly dividing IOMUX into five functional modules: port management, signal routing, configuration control, status monitoring, and protocol adaptation. Standardized interfaces for each module allow the architecture to flexibly adapt to the varying requirements of different chip types (such as microprocessors, microcontrollers, and SoCs) regarding the number of I / O ports, electrical characteristics, and communication protocols. When applied to new chips, developers only need to adjust configuration parameters (such as the number of ports and routing tables) without modifying the internal core logic of each module. This increases the overall reusability of the IOMUX design from less than 30% to over 80%, significantly reducing repetitive development work and shortening chip development cycles by 30%-50%.

[0017] 2) High Configuration Flexibility: This invention innovatively employs a composite configuration mechanism combining static and dynamic configurations. The static configuration unit ensures rapid startup based on the default configuration after chip power-on; the dynamic configuration unit supports real-time adjustment of parameters such as port function mapping and electrical attributes via software instructions during chip operation, thereby flexibly responding to dynamic scenarios such as hot-swapping of external devices and switching of functional modules in case of failure. Simultaneously, the built-in conflict detection function of the dynamic configuration unit effectively avoids system anomalies caused by configuration errors. The measured configuration response time is less than 10μs, meeting the requirements of high-speed, real-time applications.

[0018] 3) Strong Multi-Protocol Compatibility: This invention achieves hardware compatibility with multiple mainstream communication protocols (such as UART, SPI, I2C, CAN FD, Ethernet, etc.) through a two-level adaptation structure of "protocol parsing + timing adjustment" in the protocol adaptation module. The protocol parsing submodule can automatically load the corresponding protocol processing logic based on the routing table information to complete data frame parsing and verification; the timing adjustment submodule can perform precise timing compensation based on port parameters. When it is necessary to expand support for new protocols, only the corresponding parsing logic needs to be added to the protocol parsing submodule (which can be implemented through firmware upgrade), without redesigning the hardware circuit, significantly shortening the protocol expansion cycle from the traditional 1-2 months to 1-2 weeks.

[0019] 4) High system reliability and maintainability: This invention achieves comprehensive and periodic monitoring of port electrical status, signal transmission quality, and the operating status of each module through an independent status monitoring module. Its fault diagnosis unit can quickly locate faults such as overvoltage, undervoltage, and excessive signal error rates based on preset thresholds; the alarm processing unit can not only generate interruption alarms and record detailed fault logs, but also trigger fault recovery operations according to preset strategies (such as automatic switching to a backup port), achieving rapid self-healing and significantly improving system reliability and availability. The non-volatile storage mechanism for configuration parameters and fault logs also greatly facilitates subsequent system debugging and maintenance.

[0020] 5) Significantly Reduced Verification Costs: Due to the high versatility and modularity of this architecture, verification environments (such as the UVM verification platform) and test case libraries built upon it are highly reusable. When verifying different chip projects, verification engineers only need to supplement test cases for specific port configurations and routing scenarios, without having to build the verification environment from scratch. The architecture itself supports automated configuration generation and fault injection testing, improving overall verification efficiency by more than 40% and shortening the verification cycle by 20%-30%, thereby significantly reducing the overall verification cost of the chip. Attached Figure Description

[0021] Figure 1 This is a block diagram illustrating the architectural principle of the present invention. Detailed Implementation

[0022] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] See Figure 1The first aspect of the present invention provides: a general IOMUX architecture, including a port management module, wherein the port management module is connected to a signal routing module, a configuration control module and a protocol adaptation module, and the configuration control module is connected to a status monitoring module, a signal routing module and a protocol adaptation module, and each module is connected through an internal bus; The port management module is used to configure port attributes and classify ports, thereby enabling unified management of the chip's physical I / O ports. The signal routing module is used to establish a signal path between the internal functional modules of the chip and the external physical port; The configuration control module adopts a composite configuration mechanism that combines static and dynamic methods. It receives external configuration commands, parses the external configuration commands into configuration parameters for each module, sends them to each module, and stores and dynamically updates the configuration parameters. The status monitoring module is used to monitor the operating status of IOMUX in real time, periodically collect status data, identify faults, and generate alarms. The protocol adaptation module employs a two-level adaptation structure of protocol parsing and timing adjustment to adapt the output signals of the internal functional modules of the chip to different communication protocols, thereby meeting the protocol requirements of external devices.

[0024] In this embodiment, the architecture can flexibly adapt to the I / O port multiplexing requirements of various chips, and has significant application value in chip function verification, performance optimization, and development efficiency improvement. It is especially suitable for chip design and verification scenarios that require frequent adjustments to I / O port function mapping and compatibility with multiple communication protocols. Data and control signals are exchanged between modules via an internal high-speed bus (such as AHB or APB bus): the configuration control module sends configuration parameters and control commands to other modules via the bus; the port management module, signal routing module, status monitoring module, and protocol adaptation module provide feedback status information to the configuration control module via the bus; the signal routing module and the protocol adaptation module transmit adapted signals through a dedicated signal path to ensure signal transmission rate and integrity.

[0025] In some embodiments, the port management module includes a port attribute configuration unit and a port classification unit; the port attribute configuration unit is used to configure the electrical parameters, timing parameters and operating modes of the chip's physical I / O ports; The port classification unit is used to divide the chip's physical I / O ports into general-purpose port groups, high-speed port groups, and dedicated port groups according to their physical characteristics and functional scenarios, so as to facilitate subsequent signal routing matching.

[0026] In this embodiment, the port management module, serving as the interface between the IOMUX and external physical ports, is responsible for the unified management of the chip's physical I / O ports. This module includes a port attribute configuration unit and a port classification unit. Port attribute configuration unit: Supports configuring port electrical parameters (such as voltage level 3.3V / 5V, drive capability 4mA / 8mA), timing parameters (such as setup time, hold time) and operating mode (input / output / bidirectional). Configuration parameters are written through the configuration control module. Port classification unit: Based on the physical characteristics of the ports (such as high-speed / low-speed ports, single-ended / differential ports) and common functional scenarios, the ports are divided into general port groups, high-speed port groups and dedicated port groups to facilitate efficient matching of subsequent signal routing.

[0027] In some embodiments, the signal routing module includes a cross switch and a routing table; the cross switch includes N×M configurable cross switch structures, each cross point corresponds to an independently controllable switch unit, and the path between any internal functional module of the chip and the external physical port is turned on / off by control signals, where N is the number of internal functional modules of the chip and M is the number of external physical ports; The routing table is used to store the mapping relationship data between the internal functional modules of the chip and the external physical ports. The mapping relationship data includes module ID, port ID, path priority and protocol type. The routing table is dynamically updated by the configuration control module, and the signal routing module automatically completes the path selection according to the routing table.

[0028] In this embodiment, the signal routing module establishes signal paths between internal chip functional modules (such as UART controller, SPI controller, I2C controller, GPIO module, etc.) and external physical ports, and is the core data transmission unit of IOMUX. This module adopts a "crossbar + routing table" design. Cross switch: It adopts a configurable N×M cross switch structure (N is the number of internal functional modules and M is the number of external physical ports). Each cross point corresponds to an independently controllable switch unit. The connection / disconnection between any internal functional module and the external physical port can be realized through control signals. Routing table: Stores the mapping relationship between internal functional modules and external physical ports, including module ID, port ID, path priority and protocol type. The routing table is dynamically updated by the configuration control module, and the signal routing module automatically completes path selection according to the routing table.

[0029] In some embodiments, the configuration control module includes a static configuration unit and a dynamic configuration unit; the static configuration unit is used to read preset configuration parameters from non-volatile memory during the chip power-on initialization phase to complete the initial configuration of each module; The dynamic configuration unit is used to receive external real-time configuration instructions during chip operation, parse the external real-time configuration instructions and update the configuration parameters, send the configuration effective signal to the module associated with the updated configuration parameters, adjust the port functions in real time, and perform configuration conflict detection. When the new configuration conflicts with the existing path, a conflict alarm is triggered and the invalid configuration is rejected.

[0030] In this embodiment, the configuration control module, as the control core of IOMUX, is responsible for receiving external configuration instructions (such as software instructions from the CPU and hardware instructions from external configuration tools), parsing these instructions into configuration parameters for each module, and supporting the storage and dynamic updating of these configuration parameters. This module includes a static configuration unit and a dynamic configuration unit. Static configuration unit: During the chip power-on initialization phase, it reads preset configuration parameters (such as default port function mapping and basic electrical parameters) from non-volatile memory (such as EEPROM, Flash) to complete the initial configuration of each module and ensure that the chip can quickly enter the normal working state after power-on. Dynamic Configuration Unit: During chip operation, it receives external real-time configuration instructions (such as configuration updates written by software through registers or triggered by interrupts), parses the instructions, updates parameters such as routing tables and port attributes, and sends configuration activation signals to relevant modules to achieve real-time adjustment of port functions; at the same time, the dynamic configuration unit has a configuration conflict detection function. When a new configuration conflicts with an existing path (such as when the same port is mapped to multiple functional modules), it triggers a conflict alarm and rejects invalid configurations.

[0031] In some embodiments, the status monitoring module includes a status acquisition unit, a fault judgment unit, and an alarm processing unit; the status acquisition unit is used to periodically acquire the electrical status of external physical ports, signal transmission status, and the working status of each module; The fault determination unit is used to compare the collected status data with a preset threshold to determine whether a fault exists. The alarm processing unit is used to generate an alarm signal when a fault is detected, store the fault information in the fault log, and trigger a fault recovery operation according to a preset strategy.

[0032] In this embodiment, the status monitoring module monitors the IOMUX's operating status in real time, including port status, signal transmission status, and module working status, ensuring stable operation of the IOMUX. This module includes a status acquisition unit, a fault diagnosis unit, and an alarm processing unit. Status acquisition unit: Periodically acquires the electrical status (such as port voltage and current), signal transmission status (such as data transmission rate and bit error rate) of external physical ports, and the working status of each module (such as the conduction status of cross switch and the command parsing status of configuration control module). The acquisition period can be set by the configuration control module (range 1μs-100μs). Fault diagnosis unit: Compares the collected status data with preset thresholds (such as port voltage threshold 2.8V-3.6V, bit error rate threshold 10⁻). 6 Compare the results to determine if there is a fault (such as port overvoltage, excessive signal transmission error, or module malfunction). Alarm processing unit: When a fault is detected, it generates an alarm signal (such as an interrupt signal or a status register flag) and stores the fault information (fault type, occurrence time, associated port / module) in the fault log register. It also supports triggering fault recovery operations according to preset strategies (such as automatically disconnecting the fault path or switching to a backup port).

[0033] In some embodiments, the protocol adaptation module includes a protocol parsing submodule and a timing adjustment submodule; the protocol parsing submodule has pre-set parsing logic for multiple communication protocols, which is used to automatically identify the protocol format of the output signal of the internal functional module of the chip according to the protocol type in the routing table, and perform data frame parsing, check bit processing and protocol field extraction; The timing adjustment submodule is used to perform timing compensation on the parsed signal according to the timing parameters of the external physical port and the timing requirements of the external device, so as to meet the timing constraints.

[0034] In this embodiment, the protocol adaptation module adapts signals to different communication protocols, ensuring that signals from internal functional modules, after passing through the IOMUX, meet the protocol requirements of external devices. It is the core unit for IOMUX's multi-protocol compatibility. This module employs a two-level adaptation structure of "protocol parsing + timing adjustment." Protocol parsing submodule: Built-in parsing logic for multiple mainstream communication protocols (such as UART, SPI, I2C, CAN FD, Ethernet, USB). It can automatically identify the protocol format of the output signals of internal functional modules according to the protocol type in the routing table, and complete data frame parsing, check bit processing (such as parity check, CRC check) and protocol field extraction. Timing adjustment submodule: Based on the timing parameters of the external physical port (configured by the port management module) and the timing requirements of the external device, it performs timing compensation (such as delay adjustment and clock synchronization) on the parsed signal to ensure that the signal meets the timing constraints such as setup time and hold time when output to the external port, and avoids data transmission errors caused by timing violations.

[0035] The second aspect of this invention provides: a general IOMUX configuration control method, implemented based on a general IOMUX architecture, comprising the following steps: S1. Architecture Initialization: After the chip is powered on, the static configuration unit of the configuration control module reads the initialization configuration file from the non-volatile memory and parses the configuration parameters from the initialization configuration file to complete the initialization settings of the port management module, signal routing module, protocol adaptation module and status monitoring module, so that IOMUX enters the working state; the initialization configuration file includes port basic attributes, default routing table, protocol adaptation parameters and status monitoring threshold; S2. Port Configuration: After initialization, the user initiates a port configuration request through an external configuration tool or software command. The configuration control module receives the port configuration request, parses it to obtain the target port ID and target attribute parameters, updates the attribute parameters of the corresponding port through the port management module, and feeds back the configuration result to the configuration control module. If the configuration parameters exceed the allowed range, the configuration is rejected and an error code is returned. S3. Signal Routing Configuration: Based on the chip's functional requirements, the user initiates a signal routing configuration request. After receiving the request, the dynamic configuration unit queries the current routing table to check for configuration conflicts. If there are no conflicts, it updates the routing table, writing the mapping relationship between the internal functional module ID and the target external port ID, along with the protocol type, into the routing table. It then controls the signal routing module to establish a path between the corresponding internal functional module and the target external port. Simultaneously, it sends a protocol type notification to the protocol adaptation module, which loads the corresponding protocol parsing logic and sequence adjustment parameters to complete the signal adaptation preparation. S4. Dynamic Adjustment: During chip operation, receive dynamic adjustment requests and update port attributes, routing tables and protocol adaptation parameters according to the content of the dynamic adjustment requests to realize real-time adjustment of port functions or mapping relationships. S5. Status Monitoring and Fault Handling: The status monitoring module periodically collects operating status data and compares it with preset thresholds to determine faults; if a fault occurs, an alarm is generated, a fault log is recorded, and fault recovery operations are performed according to preset strategies. S6. Configuration and State Storage: After each configuration update, the current configuration parameters are backed up; and the fault logs are periodically backed up to non-volatile storage.

[0036] In this embodiment, the specific steps are as follows: Step S1: Architecture Initialization: After the chip is powered on, the static configuration unit of the configuration control module first reads the preset initialization configuration file from the non-volatile memory. This file contains: basic port attributes (such as the number of ports, default voltage level, and operating mode), default routing table (such as UART1 mapping to port P0 and SPI1 mapping to port P1), protocol adaptation parameters (such as default protocol type and timing threshold), and status monitoring thresholds (such as voltage and bit error rate threshold). After the static configuration unit parses the configuration file, it sends the parameters to the port management module, signal routing module, protocol adaptation module, and status monitoring module through the internal bus. Each module completes the initialization settings. The cross switch conducts the corresponding path according to the default routing table, the protocol adaptation module loads the default protocol parsing logic, and the status monitoring module starts the first status acquisition.

[0037] Step S2: Port Configuration: After initialization, the user can initiate a port configuration request via an external configuration tool (such as a JTAG debugging tool) or software instructions (such as writing to the CPU configuration register). Upon receiving the request, the configuration control module parses the port ID and target attribute parameters (such as adjusting the drive capability of port P2 to 8mA and setting the operating mode to bidirectional) and sends them to the port attribute configuration unit of the port management module. The port attribute configuration unit updates the attribute parameters of the corresponding port and simultaneously feeds back the configuration result to the configuration control module. If the configuration parameters exceed the allowed range (such as setting the drive capability to 12mA, exceeding the maximum 10mA limit), the configuration control module rejects the configuration and returns an error code.

[0038] Step S3: Signal Routing Configuration: Based on the chip's functional requirements, the user initiates a signal routing configuration request. This request includes the internal functional module ID (e.g., SPI2), the target external port ID (e.g., P3), and the protocol type (e.g., SPI). Upon receiving the request, the dynamic configuration unit of the configuration control module first queries the current routing table to check for configuration conflicts (e.g., P3 is already mapped to I2C1). If a conflict exists, a conflict alarm is triggered and conflict information is returned. If no conflict exists, the routing table is updated, writing the mapping relationship between SPI2 and P3 and the protocol type into the routing table, and simultaneously sending a route update command to the signal routing module. Upon receiving the command, the signal routing module controls the crossbar switch to connect SPI2 and P3, and sends a protocol type notification to the protocol adaptation module. The protocol adaptation module loads the SPI protocol parsing logic and timing adjustment parameters according to the notification, completing the signal adaptation preparation.

[0039] Step S4: Dynamic Adjustment: During chip operation, if port functions need to be adjusted (e.g., switching an external device from an SPI device to an I2C device) or fault handling (e.g., port P3 failure), the user or system can initiate a dynamic adjustment request. Upon receiving the request, the dynamic configuration unit of the configuration control module repeats the configuration process of steps S2-S3: If it's a function adjustment, update the port attributes (e.g., adjust the timing parameters of P3) and the routing table (e.g., remap P3 to I2C2); if it's a fault handling, based on the fault information from the status monitoring module, remap the functional module (e.g., SPI2) corresponding to the faulty port (e.g., P3) to a spare port (e.g., P4), and update the routing table and protocol adaptation parameters. During dynamic adjustment, the configuration control module sends a "configuration effective" signal to the relevant modules to ensure that the adjusted parameters take effect in real time and do not affect signal transmission in other normal pathways.

[0040] Step S5: Status Monitoring and Fault Handling: The status acquisition unit of the status monitoring module collects the electrical status, signal transmission status, and module operating status of each port according to a preset period (e.g., 10μs), and sends the collected data to the fault judgment unit. The fault judgment unit compares the data with a preset threshold: if the data is normal, it updates the status register and continues monitoring; if the data is abnormal (e.g., the voltage of port P3 is 2.5V, lower than the threshold of 2.8V), it is determined to be a fault, and a fault information is sent to the alarm processing unit. The alarm processing unit generates an alarm interrupt signal, triggers a CPU interrupt response, and stores the fault type (port overvoltage / undervoltage), occurrence time, and associated port (P3) in the fault log register; if the preset fault recovery strategy is "automatic switching", the alarm processing unit sends a "switch to backup port" request to the configuration control module, triggering the dynamic adjustment process in step S4, switching the functional module corresponding to P3 to the backup port P4, thus achieving fault self-healing.

[0041] Step S6: Configuration and Status Storage: After each configuration is completed (including initial configuration and dynamic adjustment), the configuration control module stores the current configuration parameters (port attributes, routing table, protocol adaptation parameters) to the backup register to prevent configuration loss after the chip loses power; at the same time, the status monitoring module periodically backs up the information in the fault log register to non-volatile memory to facilitate subsequent fault analysis and debugging.

[0042] In some embodiments, in S3, if the target external port ID is already occupied by other internal functional modules, a conflict alarm is triggered and conflict information is returned.

[0043] In some embodiments, the dynamic adjustment request includes a port function adjustment request and a fault response request; When the dynamic adjustment request is a port function adjustment request, update the attribute parameters of the target port and remap the target port to the new internal function module; When a dynamic adjustment request is a fault response request, the internal functional module mapped to the port that failed is remapped to a backup port, and the routing table and protocol adaptation parameters are updated.

[0044] To make the technical solution of the present invention clearer and easier to understand, the architecture and configuration control method of the present invention will be described in detail below in conjunction with a specific application scenario (SoC chip verification scenario).

[0045] (I) Scenario setting of the embodiment: The application scenario of this embodiment is a SoC chip for industrial control. The chip includes the following internal functional modules: 2 UART controllers, 2 SPI controllers, 1 I2C controller, 1 CAN FD controller, and 8 GPIO modules; there are a total of 16 external physical I / O ports (numbered P0-P15), which need to support UART, SPI, I2C and CANFD protocols, and are required to be able to switch port functions according to the external device access situation during operation (such as switching P0 from UART to SPI).

[0046] (II) Specific configuration of architecture modules: 1. Port management module: The port classification unit divides the 16 ports into: general port group (P0-P11, supporting low-speed protocols UART, SPI, I2C, GPIO) and high-speed port group (P12-P15, supporting high-speed protocol CAN FD). The port attribute configuration unit supports the following parameter ranges: voltage level 3.3V / 5V, drive capability 4mA / 8mA / 10mA, and operating mode input / output / bidirectional. During initialization, the default configuration for P0-P11 is 3.3V, 4mA, and bidirectional mode, while for P12-P15 it is 5V, 10mA, and bidirectional mode.

[0047] 2. Signal routing module: The cross switch adopts a 13×16 structure (13 is the number of internal functional modules: 2UART+2SPI+1I2C+1CAN FD+8GPIO, 16 is the number of external ports). The switching unit is implemented using CMOS technology, with an on-resistance of less than 5Ω, ensuring low signal transmission loss. The routing table is stored in the RAM of the configuration control module. Each routing entry contains: module ID (e.g., 0x01 for UART1), port ID (e.g., 0x00 for P0), protocol type (e.g., 0x01 for UART), and path priority (levels 1-5, with priority 5 being the highest). The default routing entries during initialization are: UART1→P0 (0x01→0x00, 0x01, priority 3), SPI1→P1 (0x02→0x01, 0x02, priority 3), I2C1→P2 (0x03→0x02, 0x03, priority 3), CAN FD1→P12 (0x04→0x0C, 0x04, priority 5), GPIO1→P3 (0x05→0x03, 0x00, priority 1).

[0048] 3. Configuration control module: The static configuration unit reads the initialization configuration file (stored at address 0x0000_1000) from the internal Flash of the chip. The configuration file is in XML format and includes port attributes, default routing table, protocol parameters and monitoring thresholds. The dynamic configuration unit supports receiving configuration commands from the CPU via the APB bus interface (command format: opcode + module address + parameter value). The configuration conflict detection logic is implemented by comparing the port ID occupancy in the routing table. When a conflict occurs, an error code 0x01 (conflict error) is returned. The actual measured dynamic configuration response time is 8μs, which meets the requirements for real-time adjustment.

[0049] 4. Status monitoring module: The status acquisition period is set to 10μs. The acquired parameters include: port voltage (accuracy ±0.01V), port current (accuracy ±0.1mA), signal transmission bit error rate (based on 1000 frames of data statistics), and cross switch conduction status (conducting / disconnecting). Preset thresholds: Port voltage 3.3V±10% (3.0V-3.6V), 5V±10% (4.5V-5.5V), port current ≤10mA, bit error rate ≤10⁻ 6 ; Fault recovery strategy: When a port fails, it automatically switches to a backup port in the same group (e.g., switches to P4 when P0 fails). When a module fails, it triggers a CPU interrupt, which is handled by software.

[0050] 5. Protocol Adaptation Module: The protocol parsing submodule has built-in parsing logic for UART (supports 9600-115200bps baud rate, parity check), SPI (supports 1-50MHz clock, CPHA / CPOL configurable), I2C (supports 100kHz standard mode, 400kHz fast mode), and CAN FD (supports up to 8Mbps rate, CRC32 check). The timing adjustment submodule supports a delay adjustment range of 0-10ns (step size 1ns) and a clock synchronization accuracy of ±0.5ns, which can meet the timing requirements in the field of industrial control.

[0051] (III) Implementation Process: 1. Architecture Initialization (Step S1): After the chip is powered on, the static configuration unit of the configuration control module reads the configuration file at address 0x0000_1000 in Flash, parses it, sends the default attribute parameters of P0-P15 to the port management module, writes the default routing table to the signal routing module, loads the default protocol parameters of UART, SPI, I2C, and CAN FD to the protocol adaptation module, and sets the threshold to the status monitoring module. After the initialization of each module is completed, the cross switch turns on the default paths such as UART1-P0 and SPI1-P1, the status monitoring module starts the first acquisition, and the chip enters the normal working state.

[0052] 2. Port Configuration (Step S2): In industrial control scenarios, if the drive capability of P3 needs to be increased from 4mA to 8mA, the CPU sends a command to the configuration control module via the APB bus: opcode 0x02 (port configuration) + module address 0x10 (port management module) + parameter 0x03 (port P3) + 0x08 (drive capability 8mA). After parsing the command, the configuration control module sends it to the port management module, updates the drive capability parameters of P3, and returns a configuration success code 0x00, indicating that the port configuration is complete.

[0053] 3. Signal Routing Configuration (Step S3): To map SPI2 (Module ID 0x06) to P4 (Port ID 0x04), the CPU sends the following instruction: Opcode 0x03 (routing configuration) + Module Address 0x20 (configuration control module) + Parameter 0x06 (SPI2) + 0x04 (P4) + 0x02 (SPI protocol). The configuration control module queries the routing table and finds that P4 is currently unoccupied (no conflict). It updates the routing table by adding the 0x06→0x04 route entry, sends a conduction command to the signal routing module, and the crossbar switch conducts the SPI2-P4 path. Simultaneously, it notifies the protocol adaptation module to load the SPI protocol parsing logic, and the routing configuration is complete.

[0054] 4. Dynamic Adjustment (Step S4): If the external device switches from an SPI device to an I2C device, P4 needs to be remapped to I2C1 (module ID 0x03). The CPU sends a dynamic adjustment instruction: opcode 0x04 (dynamic adjustment) + parameter 0x03 (I2C1) + 0x04 (P4) + 0x03 (I2C protocol). The configuration control module detects that P4 is currently mapped to SPI2 (conflict) and returns a conflict error code 0x01. The CPU first sends an instruction to delete the SPI2-P4 routing entry, and then resends the I2C1-P4 configuration instruction. The configuration control module updates the routing table, the signal routing module switches the path, and the protocol adaptation module loads the I2C protocol logic. The dynamic adjustment is completed, and the entire process takes 12μs.

[0055] 5. Status Monitoring and Fault Handling (Step S5): The status acquisition unit acquires a voltage of 2.9V (below the threshold of 3.0V) for P0 within a 10μs period and sends it to the fault judgment unit, which determines it as a "port undervoltage fault". The alarm processing unit generates an interrupt signal (IRQ number 12), triggering a CPU interrupt, and simultaneously stores the fault signal (type 0x01, timestamp, port P0) in the fault log register (address 0x3000_0000). According to the preset strategy, the alarm processing unit sends a switching request to the configuration control module to switch UART1 from P0 to the backup port P5. The configuration control module executes the dynamic adjustment process, and after 10μs, UART1 resumes normal operation on P5, and the fault handling is completed.

[0056] 6. Configuration and Status Storage (Step S6): After each configuration update, the configuration control module backs up the current configuration parameters to the backup register (address 0x4000_0000-0x4000_0FFF); the status monitoring module backs up the information of the fault log register to Flash (address 0x0000_2000) every 100ms to ensure that the configuration and fault information are not lost after the chip is powered off.

[0057] (iv) Verification Results: Based on the general IOMUX architecture of this embodiment, the UVM verification platform was used for verification, covering the following scenarios: 1. Functional Verification: 100 test cases were designed, covering scenarios such as port configuration, routing configuration, dynamic adjustment, and fault handling. Test results showed that all functions were implemented normally, with a configuration conflict detection accuracy of 100% and a fault detection coverage of 98.5%. 2. Performance Verification: Test dynamic configuration response time (average 8μs), signal transmission rate (up to 8Mbps under CAN FD protocol, no frame loss), and timing violation rate (0%, meeting industrial control timing requirements). 3. Compatibility verification: The IOMUX was applied to microcontrollers (STM32 series) and SoCs (Xilinx Zynq series). It worked normally after only adjusting the configuration parameters, with a reuse rate of 85%, and the development cycle was shortened from the traditional 2 months to 2 weeks.

[0058] Verification results show that the general IOMUX architecture and configuration control method of the present invention can meet the needs of multiple chip types and multiple protocol scenarios, and has high adaptability, flexibility and reliability, while significantly reducing verification costs.

[0059] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A general IOMUX architecture, characterized in that: It includes a port management module, which is connected to a signal routing module, a configuration control module, and a protocol adaptation module. The configuration control module is connected to a status monitoring module, a signal routing module, and a protocol adaptation module. All modules are connected via an internal bus. The port management module is used to configure port attributes and classify ports, thereby enabling unified management of the chip's physical I / O ports. The signal routing module is used to establish a signal path between the internal functional modules of the chip and the external physical port; The configuration control module adopts a composite configuration mechanism that combines static and dynamic methods. It receives external configuration commands, parses the external configuration commands into configuration parameters for each module, sends them to each module, and stores and dynamically updates the configuration parameters. The status monitoring module is used to monitor the operating status of IOMUX in real time, periodically collect status data, identify faults, and generate alarms. The protocol adaptation module employs a two-level adaptation structure of protocol parsing and timing adjustment to adapt the output signals of the internal functional modules of the chip to different communication protocols, thereby meeting the protocol requirements of external devices.

2. The general IOMUX architecture according to claim 1, characterized in that: The port management module includes a port attribute configuration unit and a port classification unit; the port attribute configuration unit is used to configure the electrical parameters, timing parameters and operating modes of the chip's physical I / O ports. The port classification unit is used to divide the chip's physical I / O ports into general-purpose port groups, high-speed port groups, and dedicated port groups according to their physical characteristics and functional scenarios, so as to facilitate subsequent signal routing matching.

3. The general IOMUX architecture according to claim 1, characterized in that: The signal routing module includes a cross switch and a routing table; the cross switch includes N×M configurable cross switch structures, each cross point corresponds to an independently controllable switch unit, and the connection / disconnection between any internal functional module of the chip and the external physical port is realized by the control signal, where N is the number of internal functional modules of the chip and M is the number of external physical ports; The routing table is used to store the mapping relationship data between the internal functional modules of the chip and the external physical ports. The mapping relationship data includes module ID, port ID, path priority and protocol type. The routing table is dynamically updated by the configuration control module, and the signal routing module automatically completes the path selection according to the routing table.

4. The general IOMUX architecture according to claim 1, characterized in that: The configuration control module includes a static configuration unit and a dynamic configuration unit; the static configuration unit is used to read preset configuration parameters from non-volatile memory during the chip power-on initialization phase to complete the initial configuration of each module. The dynamic configuration unit is used to receive external real-time configuration instructions during chip operation, parse the external real-time configuration instructions and update the configuration parameters, send the configuration effective signal to the module associated with the updated configuration parameters, adjust the port functions in real time, and perform configuration conflict detection. When the new configuration conflicts with the existing path, a conflict alarm is triggered and the invalid configuration is rejected.

5. The general IOMUX architecture according to claim 1, characterized in that: The status monitoring module includes a status acquisition unit, a fault judgment unit, and an alarm processing unit; the status acquisition unit is used to periodically acquire the electrical status of external physical ports, signal transmission status, and the working status of each module. The fault determination unit is used to compare the collected status data with a preset threshold to determine whether a fault exists. The alarm processing unit is used to generate an alarm signal when a fault is detected, store the fault information in the fault log, and trigger a fault recovery operation according to a preset strategy.

6. The general IOMUX architecture according to claim 1, characterized in that: The protocol adaptation module includes a protocol parsing submodule and a timing adjustment submodule. The protocol parsing submodule has pre-set parsing logic for multiple communication protocols, which is used to automatically identify the protocol format of the output signal of the internal functional module of the chip according to the protocol type in the routing table, and perform data frame parsing, check bit processing and protocol field extraction. The timing adjustment submodule is used to perform timing compensation on the parsed signal according to the timing parameters of the external physical port and the timing requirements of the external device, so as to meet the timing constraints.

7. A general IOMUX configuration control method, characterized in that: Based on the general IOMUX architecture, the implementation includes the following steps: S1. Architecture Initialization: After the chip is powered on, the static configuration unit of the configuration control module reads the initialization configuration file from the non-volatile memory and parses the configuration parameters from the initialization configuration file to complete the initialization settings of the port management module, signal routing module, protocol adaptation module and status monitoring module, so that IOMUX enters the working state; the initialization configuration file includes port basic attributes, default routing table, protocol adaptation parameters and status monitoring threshold; S2. Port Configuration: After initialization, the user initiates a port configuration request through an external configuration tool or software command. The configuration control module receives the port configuration request, parses it to obtain the target port ID and target attribute parameters, updates the attribute parameters of the corresponding port through the port management module, and feeds back the configuration result to the configuration control module. If the configuration parameters exceed the allowed range, the configuration is rejected and an error code is returned. S3. Signal Routing Configuration: Based on the chip's functional requirements, the user initiates a signal routing configuration request. After receiving the request, the dynamic configuration unit queries the current routing table to check for configuration conflicts. If there are no conflicts, it updates the routing table, writing the mapping relationship between the internal functional module ID and the target external port ID, along with the protocol type, into the routing table. It then controls the signal routing module to establish a path between the corresponding internal functional module and the target external port. Simultaneously, it sends a protocol type notification to the protocol adaptation module, which loads the corresponding protocol parsing logic and sequence adjustment parameters to complete the signal adaptation preparation. S4. Dynamic Adjustment: During chip operation, receive dynamic adjustment requests and update port attributes, routing tables and protocol adaptation parameters according to the content of the dynamic adjustment requests to realize real-time adjustment of port functions or mapping relationships. S5. Status Monitoring and Fault Handling: The status monitoring module periodically collects operating status data and compares it with preset thresholds to determine faults; if a fault occurs, an alarm is generated, a fault log is recorded, and fault recovery operations are performed according to preset strategies. S6. Configuration and State Storage: After each configuration update, the current configuration parameters are backed up; and the fault logs are backed up to non-volatile storage periodically.

8. The general IOMUX configuration control method according to claim 7, characterized in that: In S3, if the target external port ID is already occupied by other internal functional modules, a conflict alarm is triggered and conflict information is returned.

9. The general IOMUX configuration control method according to claim 7, characterized in that: The dynamic adjustment requests include port function adjustment requests and fault response requests; When the dynamic adjustment request is a port function adjustment request, update the attribute parameters of the target port and remap the target port to the new internal function module; When a dynamic adjustment request is a fault response request, the internal functional module mapped to the port that failed is remapped to a backup port, and the routing table and protocol adaptation parameters are updated.

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