Fpga layout planning method and device, storage medium and electronic equipment

By dividing the logic units in the FPGA design into modules and constructing a slice tree, the layout of modules within the preset area is ensured, which solves the routing failure and performance degradation problems caused by modules deviating from the preset area and achieves efficient and stable layout planning.

CN122414092APending Publication Date: 2026-07-17CHENGDU UNISCO TONGCHUANG ELECTRONIC TECHNOLOGY CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
CHENGDU UNISCO TONGCHUANG ELECTRONIC TECHNOLOGY CO LTD
Filing Date
2026-04-07
Publication Date
2026-07-17

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Abstract

本申请提供了一种FPGA布图规划方法、装置、存储介质和电子设备。将FPGA设计中的逻辑单元划分为多个模块；根据各模块是否具有预设区域约束，将多个模块分组，得到多个模块组，每个模块组内至多包括一个唯一的预设区域约束；基于模块组和模块构建切片树；根据切片树，在FPGA芯片的物理布局平面中依次求解各模块的物理位置，若模块组中包括具有预设区域约束的模块，则将模块组的布图规划起始定位基准设定为预设区域约束对应的矩形区域的边界顶点，使得具有预设区域约束的模块的最小包围矩形位于对应的矩形区域内，且不超出矩形区域的边界。解决了布图规划难以保证区域约束模块准确置于指定物理区域内的问题。
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