Time-multiplexing for clearing and writing of serial read-write memory
By separating read and write operations in the memory clock cycle and eliminating the clearing step in the write operation, serial read/write memory solves the problem of memory speed limitation in multi-core systems, achieving faster operation speed and lower power consumption.
CN122459871APending Publication Date: 2026-07-24QUALCOMM INC
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Patent Information
- Application Number
- CN202480082248.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-02
- Filing Date
- 2024-12-18
- Publication Date
- 2026-07-24
AI Technical Summary
Technical Problem
In modern multi-core processor systems, memory read and write operations are limited in speed due to sharing a single access port, and traditional pseudo-dual-port memory increases memory complexity and space requirements.
Method used
The serial read/write memory design performs read and write operations at different parts of the memory clock cycle and eliminates the clear operation of the write select column during the write operation. It utilizes a precharge circuit and a write driver to charge and discharge the bit lines, reducing unnecessary precharge steps.
Benefits of technology
This improves memory operating speed and reduces power consumption, while also reducing the need for write driver transistors, thus enhancing overall memory performance.
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Figure CN122459871A_ABST
Abstract
A static random access memory is provided with dual pump operations in which read operations to a multiplexed column group of bit cells can occur in a first portion of a memory clock cycle and in which write operations to a write select column of the multiplexed column group of bit cells can occur in a second portion of the memory clock cycle. The write operations to the write select column occur during the read and write operations without any pre-charge of bit lines in the write select column.
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