An IO module communication control method based on master-slave cooperation

Abstract

The application discloses an IO module communication control method based on master-slave cooperation and relates to the technical field of industrial automation control.The application realizes a double-mode autonomous reporting mechanism of periodic reporting and state change triggering by maintaining an analog-digital counter and a feature pair in a slave station,significantly reduces the response delay of input state change,avoids the waste of bus bandwidth caused by invalid period reporting,substantially improves the throughput capacity of a multi-slave bus system on the premise of ensuring real-time performance,and realizes fair and efficient bus competition resolution without intervention of a master station based on a bit-by-bit arbitration mechanism of an open-drain bus.

Description

Technical Field

[0001] This invention relates to the field of industrial automation control technology, and in particular to a communication control method for I / O modules based on master-slave collaboration. Background Technology

[0002] Industrial fieldbus technology is a critical infrastructure for the reliable operation of distributed control systems (DCS) and programmable logic controllers (PLC) systems. In distributed I / O systems, the communication efficiency between the master station (controller) and multiple slave stations (I / O modules) directly affects the system's real-time performance, determinism, and bus bandwidth utilization. Based on the driving mode of slave data reporting, existing master-slave communication methods are mainly divided into two categories: one is master-station active polling, where the master station periodically queries the status information of each slave station sequentially, and the slave stations passively respond; the other is slave-station active reporting, where the slave station only sends data to the master station when it detects a status change or meets specific conditions. Furthermore, in a topology where multiple slave stations share the same physical bus, coordinating multiple slave stations to initiate communication requests simultaneously to avoid data conflicts is one of the core challenges in master-slave communication protocol design.

[0003] In existing technologies, some master-slave communication methods still use traditional query-based architectures, resulting in limited system real-time performance and low bandwidth utilization. For example, CN117040963B discloses a method and system for fast distributed I / O master-slave communication. This method obtains user-issued instructions to process slave devices, generates interaction instructions based on these instructions and an interaction protocol, and sends these interaction instructions to a queue pool. The master then reads the interaction instructions from the queue pool and completes the processing of the slave device. In this scheme, communication is entirely driven by the master's query and setting instructions; the slave device itself lacks autonomous reporting capabilities. The master passively reads the instructions and executes operations on the slave device only when a user instruction triggers queue pool processing; the slave device's status data cannot be proactively and promptly transmitted to the master. When the states of multiple slave devices change frequently, all state changes must wait for the master to send a corresponding query frame or for the user instruction to enter the queue pool before they can be recognized. This means that the reporting delay of state changes depends entirely on the master's polling cycle and the processing rhythm of the instruction queue. Especially in application scenarios with a large number of slave devices and high frequency of state changes, a large amount of state change information cannot be responded to in a timely manner, fundamentally limiting the system's real-time response capability.

[0004] Another master-slave communication method uses an industrial CAN bus to refresh data between the master and slave stations. For example, CN112929251B discloses a CAN-based slave data refresh method, device, and system. This method assigns slave station numbers, configures and sends a first communication frame based on the assigned slave station number and RS485 communication protocol, and initiates data update functions for multiple slave stations based on this first communication frame. It receives data updated by multiple slave stations according to the data update function within a preset time, and then jumps back and repeats the above process after the preset time. Although this scheme improves the parallelism of data refresh to some extent by synchronously receiving updated data from multiple slave stations through a preset time window, its fundamental communication mode is still question-and-answer: the master station must first send the first communication frame to initiate the slave station's data update process; the slave station cannot report data independently before this. This means that the slave station's data refresh cycle is entirely determined by the master station's first communication frame sending cycle, and changes in the slave station's internal state cannot independently trigger reporting behavior. For rapidly changing input signals (such as encoder pulses or high-speed switching signal transitions), sampling and reporting must wait for the master station's next round of communication frames, resulting in an inherent response delay. Furthermore, the conflict resolution mechanism of this scheme relies entirely on the hardware ID arbitration function of the CAN controller. The slave station itself does not need to have autonomous arbitration capabilities. When there are many slave stations and a large amount of reported data, the hardware arbitration layer cannot perceive the semantic content of the data (such as whether the state change is critical or whether the priority needs to be adjusted), and it also lacks the means for the slave station to actively control the transmission priority at the software level. Summary of the Invention

[0005] The purpose of this section is to outline some aspects of the embodiments of the present invention and to briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section, as well as in the abstract and title of the present application, to avoid obscuring the purpose of this section, the abstract and title of the invention. Such simplifications or omissions shall not be used to limit the scope of the present invention.

[0006] In view of the aforementioned existing problems, the present invention is proposed.

[0007] To solve the above technical problems, the present invention provides the following technical solution: a master-slave collaborative IO module communication control method, characterized in that it includes: the master station obtains the number N of slave stations by polling the hardware address; each slave station maintains an analog-to-digital counter, a feature pair, a previously reported feature pair, and a successful reporting flag, wherein the feature pair includes the current input state and the current output state; when the analog-to-digital counter overflows, or the feature pair changes compared to the previously reported feature pair, or when no feature pair has ever been successfully reported to the master station, the slave station sends response data to the master station, resets the analog-to-digital counter, saves the current feature pair as the previously reported feature pair, and sets the successful reporting flag to the reported state; the master station updates the status record of the corresponding slave station according to the received response data and determines the communication status of the unresponsive slave station.

[0008] In a preferred embodiment of the present invention, the master station obtains the number N of slave stations through hardware address polling, including: after the master station powers on, controlling the bus to enter a low-level state and maintaining it for a first preset duration, forcing all slave stations to remain silent; the master station releases the bus and opens a silent window of a second preset duration, and all slave stations complete initialization before the silent window ends; each slave station is pre-configured with a unique slave station address; the master station sequentially sends address query frames to each slave station address; a slave station that exists and whose address matches replies with an address response frame, and after receiving the correct address response frame, the master station marks the slave station address corresponding to the address response frame as existing and increments the slave station count; after the polling ends, the master station obtains the actual number of slave stations, and if the number of slave stations is zero, the master station reports an error and stops.

[0009] In a preferred embodiment of the present invention, each slave station maintains a modulus counter and a feature pair, including: the master station sets a unified modulus value for all slave stations via broadcast; after each slave station enters normal working mode, it obtains its own slave station address and the modulus value, sets the initial value of the modulus counter to the modulus value, sets the successful reporting flag to the non-reporting state, and sets the last reported feature pair to the initial value; each slave station runs an independent timer to generate a basic clock cycle, and after each basic clock cycle and when the slave station is not in the process of sending a data frame, if the value of the modulus counter is greater than 0, it is decremented by 1; if the value of the modulus counter is equal to 0, it remains unchanged; at the same time, the current input state and the current output state are collected, and the current input state and the current output state are concatenated to form the current feature pair.

[0010] In a preferred embodiment of the present invention, when the analog-to-digital counter overflows or the feature pair changes, the slave station sends response data to the master station and resets the analog-to-digital counter, which includes: each slave station determining whether the value of the analog-to-digital counter is zero at the end of each basic clock cycle and without during transmission; if the value of the analog-to-digital counter is zero, the overflow condition is determined to be met; each slave station compares the current feature pair with the previously reported feature pair; if the successful reporting flag is in a non-reported state or the current feature pair is not equal to the previously reported feature pair, the change condition is determined to be met; when either the overflow condition or the change condition is met, the slave station performs a transmission operation, pausing the decrement and sampling of the basic clock cycle during transmission; after transmission is completed, the analog-to-digital counter is reset, the current feature pair is saved as the previously reported feature pair, the successful reporting flag is set to a reported state, and execution resumes from the beginning of the next basic clock cycle.

[0011] As a preferred embodiment of the present invention, the following steps are included: the master station updates the status record based on the received response data and determines the communication status of the unresponsive slave station: the master station continuously listens to the bus, uses a preset bit synchronization method, and extracts the address and feature pairs from the valid data frame when a valid data frame is detected; the master station maintains a record of the latest feature pairs corresponding to each address, a record of the unresponsive timer, and a record of whether a response has been received; for each valid data frame received, the master station clears the unresponsive timer for the address corresponding to the valid data frame, marks the record of whether a response has been received as received, and updates the feature pairs extracted from the valid data frame to the record of the latest feature pairs; the master station runs an independent timer to generate the same basic clock cycle as the slave station, and accumulates all unresponsive timers once in each basic clock cycle; when the value of a certain unresponsive timer exceeds a preset stable time threshold, the communication of the slave station corresponding to the address of the unresponsive timer is determined to be abnormal, and the abnormality type is distinguished according to the record of whether a response has been received.

[0012] In a preferred embodiment of the present invention, the value of the modulus counter remains unchanged when transmission fails due to a conflict.

[0013] As a preferred embodiment of the present invention, the following is provided: When the slave station sends response data, a bit-by-bit arbitration mechanism is adopted: The slave station constructs a data frame, which sequentially includes a start bit, an address field, a frame type bit, a current feature pair, a check bit, and a stop bit; the value of the address field is equal to the unique slave address preset by the slave station in hardware; the start bit is a first level state, and the stop bit is a second level state; the bus adopts a wired-AND mechanism, and the master station is configured with pull-up components; for each bit in the data frame, the slave station drives the bus at the bit time start point of each bit: if it wants to send the first level state, it actively drives the bus to the first level state; if it wants to send the second level state, it releases the bus; both the slave station and the master station perform bit synchronization by detecting the transition edge of the start bit, and sample the bus level at a predetermined sampling point at each bit time; if the slave station intends to send the second level state but samples the bus as the first level state, a conflict is determined, the current transmission is immediately stopped, the bus is released, the analog-to-digital counter and the previously reported feature pair are not updated, and the trigger condition is re-evaluated in the next basic clock cycle; if no conflict is detected in any bit of the data frame, the transmission is successfully completed.

[0014] In a preferred embodiment of the present invention, the data frame is of fixed length and consists of a start bit, an address field, a frame type bit, a feature pair field, a check bit, and a stop bit in sequence; the check bit is calculated from the address field, the frame type bit, and the feature pair field; the duration of each bit in the data frame is generated by an independent time base and is decoupled from the basic clock cycle.

[0015] In a preferred embodiment of the present invention, the stabilization time threshold is greater than the maximum reporting cycle of the slave station.

[0016] In a preferred embodiment of the present invention, the address query frame and the address response frame adopt the same frame structure rule; the frame structure rule includes a start bit, a check bit, and a stop bit.

[0017] The beneficial effects of this invention are as follows: By maintaining a modulo-digital counter and feature pairs at the slave station, this invention achieves a dual-mode autonomous reporting mechanism that combines periodic reporting and state change triggering. This significantly reduces the response delay to input state changes and avoids wasting bus bandwidth due to invalid periodic reporting. It greatly improves the throughput of multi-slave bus systems while ensuring real-time performance. The bit-by-bit arbitration mechanism based on the open-drain bus enables multiple slave stations to detect conflicts in place and automatically yield during transmission. This resolves bus contention fairly and efficiently without master station intervention. Furthermore, by maintaining an unacknowledged timer and distinguishing acknowledged flags, the master station can accurately diagnose two anomalies: slave stations never going online and communication interruption. This effectively improves the maintainability and fault recovery capabilities of the system. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a flowchart illustrating the process of obtaining the number of slave stations by polling the hardware address of the master station in an embodiment of the present invention.

[0019] Figure 2 This is a flowchart illustrating the slave station trigger condition judgment and response sending process in an embodiment of the present invention. Detailed Implementation

[0020] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0021] Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without inventive effort should fall within the scope of protection of this invention.

[0022] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0023] According to an embodiment of the present invention, in combination Figures 1-2 The flowchart shown illustrates a master-slave collaborative I / O module communication control method, including: S1: The master station obtains the number of slave stations N by polling the hardware address.

[0024] It should be noted that after the master station powers on, it first drives the communication bus to a low level and maintains it for a first preset duration (based on the master station's internal crystal oscillator), for example, 200 microseconds. This duration is longer than the longest power-on initialization time of all slave stations (the startup time of a classic MCU is <100μs) and allows for a margin. During this first preset duration, the communication control logic inside all slave stations is forced into a silent state, that is, any level transitions on the bus are ignored, and no data transmission operations are performed. At the same time, each slave station uses this period to complete power-on preparation work such as hardware address reading and internal register initialization. Subsequently, the master station releases the bus and opens a second preset duration, for example, a silent window of 500 microseconds (based on the master station's internal crystal oscillator). This duration is longer than the sum of the signal propagation delay of the farthest slave station on the bus and the slave station's internal initialization completion time. During the silent window, the bus is kept high by pull-up resistors, and all slave stations are still prohibited from actively sending any data to the bus. It should be noted that the purpose of setting a silent window is to ensure that the bus level stabilizes to a high level and to provide a consistent initial bus state for subsequent address queries; it also gives the slave station sufficient time to complete initialization, ensuring that it can correctly respond to subsequent query frames. The specific operation is as follows: S1.1: Each slave station is pre-set with a unique slave address via a hardware DIP switch or jumper. The slave address ranges from 1 to the maximum number of addresses allowed by the system design, MaxAddr, for example, 255. Compared to software configuration or dynamic allocation, hardware pre-setting eliminates the need for the writability and power-loss retention of non-volatile memory, avoiding address conflicts caused by memory damage or configuration loss. Furthermore, the address is immediately available upon power-up, eliminating the need for additional address allocation protocols and shortening system startup time. Simultaneously, since the address is uniquely determined by a physical switch, there is no possibility of multiple slave stations using the same address, fundamentally eliminating the risk of address conflicts and laying a conflict-free foundation for subsequent polling and normal communication.

[0025] S1.2: After the master station learns the maximum number of addresses, MaxAddr, it sends address query frames sequentially to address 1, address 2, ..., address MaxAddr. The frame structure of each address query frame is as follows: start bit (low level), 8-bit target address (high-order bits first), 1 even parity bit (for calculating even parity for the 8-bit target address), and stop bit (high level). The bus adopts an open-drain / wired-AND mechanism. The master station generates the start bit by actively pulling the bus low, and then releases the bus to allow the slave station to acknowledge.

[0026] For each queried address, if a slave station has an address equal to the target address, the slave station, upon receiving the address query frame, first checks if the even parity bit is correct. If the check passes, the slave station further compares the target address in the frame with its own hardware preset address. If they match, the slave station replies with an address response frame within a preset response time window, for example, one bit's time after the end of the stop bit of the query frame.

[0027] The address response frame adopts the same frame structure rules as the address query frame, specifically a start bit (low level), a fixed response byte (e.g., 0xAA, 8 bits), a 1-bit even parity bit (to calculate even parity for the fixed response byte), and a stop bit (high level).

[0028] Furthermore, after sending each address query frame, the master station opens a response window, the duration of which is set to be sufficient to receive a complete address response frame (e.g., 1.5 milliseconds). If the master station detects a frame with a valid start bit, valid stop bit, and correct even parity within the response window, and the extracted fixed response byte conforms to a preset value (e.g., 0xAA), it determines that a valid slave exists at that address. The master station marks the address as present and increments the slave count counter N by 1. If no valid response frame is received within the response window, or if the received frame has a parity error, it determines that no slave exists at that address, and the master station continues querying the next address.

[0029] Since each slave station has a unique pre-defined hardware address, and the master station queries different addresses sequentially, at most one slave station can match the target address of the current query frame at any given time. This fundamentally avoids bus conflicts caused by multiple slave stations simultaneously replying with response frames. It eliminates the need for random backoff or conflict detection retry mechanisms, simplifying protocol implementation and improving polling efficiency.

[0030] S1.3: After completing all polling of addresses 1 to MaxAddr, the master station obtains the actual number of existing slave stations N and stores N in an internal register. Simultaneously, the master station records a list of all addresses marked as existing for use in subsequent communication phases.

[0031] If N equals zero, meaning no slave station is found, the master station determines that the system connection is abnormal or all slave stations are not powered on. The master station executes an error reporting operation and stops subsequent communication processes. If, during polling, the master station detects a bus conflict in the response window after sending a query frame for a specific address—for example, the bit sampling level after the start bit does not match the expected high level, the parity bit has consecutive errors, or the stop bit fails to go high at the expected position—it indicates that multiple slave stations are responding simultaneously using the same address. The master station immediately terminates polling and reports an error, indicating an address conflict has been detected; please check the slave station's hardware address settings. If the master station receives only one valid address response frame in the response window, it marks that address as present and increments the slave station count. If it receives a frame with a parity error or is incomplete, it determines that there is no valid slave station.

[0032] It should be noted that the polling process utilizes the unique address preset by the slave hardware, eliminating the need for a dynamic address allocation protocol, thus avoiding communication failures caused by address conflicts. It also reduces protocol overhead during startup and improves the initialization speed after the system is powered on.

[0033] S2: Each slave station maintains an analog-to-digital counter, a feature pair, a previously reported feature pair, and a successful reporting flag. The feature pair contains the current input state and the current output state.

[0034] It should be noted that after obtaining the number of slave stations N and the list of existing addresses through polling, the master station uses a broadcast configuration command to set a uniform modulus M for all identified slave stations. The modulus M is a positive integer used to control the interval at which each slave station periodically reports.

[0035] Specifically, the master station constructs a broadcast configuration frame with the following structure: start bit (low level), broadcast target address, command byte (e.g., 0xCC, indicating modulo-digital configuration operation), 16-bit modulo value M (high-order bits first), 1 even parity bit, and stop bit (high level). The master station sends this broadcast configuration frame to the bus, and all slave stations receive and verify the frame's correctness. After successful verification, each slave station stores the modulo value M in its internal non-volatile memory. The broadcast target address, for example, an all-zero address 0x00, is recognized by all slave stations as a broadcast command.

[0036] As can be seen, the module configuration of all slave stations can be completed with just one command, avoiding the communication overhead caused by configuring them one by one, and significantly improving the system initialization efficiency.

[0037] S2.1: After completing the broadcast configuration, the master station sends a command to enter normal working mode, such as a fixed byte 0xBB. Upon receiving this command, each slave station switches from silent or address verification state to normal working mode.

[0038] After entering normal working mode, each slave station performs the following initialization operations: The slave obtains its unique slave address, Addr, by reading the level state of the hardware DIP switches or jumpers; it reads the previously stored modulo value M from its internal non-volatile memory. If an exception occurs and a valid modulo value is not stored in the non-volatile memory, such as when a configuration command has not been received upon initial power-on, the slave automatically uses a default modulo value, such as 1000, until it receives the master's broadcast modulo value M, which then overwrites the default value. Before receiving the broadcast modulo value, the slave does not perform any active reporting, but only listens to the bus. Simultaneously, the slave starts an internal timeout timer (independent of the modulo counter, operating based on the slave's internal crystal oscillator), with a timeout duration set to 10 seconds. If a broadcast configuration frame is received before the timeout, the configured modulo value is used normally; if no frame is received before the timeout, the default modulo value, such as 1000, is automatically adopted, and active reporting begins. Simultaneously, a specific combination of characteristics in the reported feature pair, such as both input and output being 1, indicates that the master configuration is missing.

[0039] The internal 16-bit modulo-digital counter is initialized to the modulus M. A 1-bit success reporting flag is set to 0; this flag is a Boolean variable that takes only two logical values: 0 or 1. In hardware implementation, register latching or double-bit redundant storage can be used to enhance anti-interference capabilities. In software implementation, this flag is only modified during the update operation after successful transmission; its value remains unchanged in any other operation. Specifically, a flag of 0 indicates that the previously reported feature pair has not yet received valid data, meaning no feature pair has been successfully reported. A 2-bit register is set to any initial value, such as binary 00.

[0040] If the slave station does not receive a broadcast configuration frame from the master station within the timeout timer (10 seconds), it automatically adopts the default modulus value, such as 1000, and begins to actively report. Since the data frame length in this embodiment is fixed at 14 bits and does not include an independent configuration status flag, it is agreed that only during the first report after power-on, if the slave station reports a feature pair of 11 (i.e., input status is 1 and output status is 1) and the successful reporting flag is 0, the master station will identify this report as a configuration missing flag, indicating that the slave station is operating using the default modulus value; subsequent received feature pairs of 11 will be considered normal input / output states. Based on this identification result, the master station calculates the stabilization time threshold for slave stations using the default modulus value at 1000.

[0041] The master station independently maintains a no-response timer and a stable time threshold for each slave station. Different slave stations can use different modulus values ​​for timeout judgment. If characteristic pair 11 is still received for 3 consecutive cycles, the master station records a slave station configuration abnormality alarm, but does not mark it as a communication interruption.

[0042] The combination of hardware address reading and non-volatile memory reading ensures both the uniqueness and immediacy of the address, while also providing power-loss retention for the modulo value. The use of the default modulo value enhances system robustness and prevents communication interruptions caused by configuration loss.

[0043] S2.2: Each slave station runs an independent timer that generates a stable base clock cycle. For example, 1 millisecond. Since each slave station uses an independent crystal oscillator, A certain range of manufacturing errors is allowed, such as ±10%, but this error does not affect the overall function of the system because the subsequent conflict arbitration mechanism is independent of absolute time and only depends on the relative bit timing.

[0044] Each time passing one During the period, and when the slave station is not currently in the process of sending a data frame, each slave station sequentially performs the following operations: (1) Read the current value of the modulus counter. If the value is greater than 0, decrement it by 1; if the value is already 0, leave it unchanged. It should be noted that when the modulus counter remains at 0 due to conflicts or other reasons, it will not underflow to 65535 due to periodic decrementing, thus ensuring that the counter always remains in the 0 state, making the overflow condition true in each... The cycle is valid until the conflict is resolved and the transmission is successful, at which point it is reset to M.

[0045] (2) The slave station reads the level status of its own input I / O port. The input I / O port can be connected to an external sensor, switch, or other digital signal source, and its level is 0 (low level) or 1 (high level). The read level is used as the current input status. .

[0046] (3) The slave station reads the level state of its own output latch, where the output latch is used to control the external actuator, and the level is also 0 or 1. The read level is used as the current output state. .

[0047] (4) Set the current input state Compared with the current output state The features are concatenated into a 2-bit binary number, with the most significant bit first and the least significant bit last. This number is denoted as the current feature pair. .Right now The high position is The low position is As can be seen, the feature pairs fully reflect the combined input and output status of the station at that moment, and are the basic data units for subsequent reporting and master station status updates.

[0048] The above data collection operations are performed on each Each cycle is executed once, ensuring the real-time nature of the feature pairs. Meanwhile, the design of mutual exclusion between acquisition and transmission (with acquisition paused during transmission) prevents inconsistencies in feature pairs due to level changes during transmission, guaranteeing the consistency of the reported data.

[0049] Furthermore, the master station modifies the output status of the slave station by constructing an output control frame. The output control frame is of fixed length and consists of the following bits in the order of transmission: start bit, 1 bit, low level; target slave station address, 8 bits, high-order bits first; frame type bit: 1 bit, fixed at 1, indicating a downlink command; command type, 1 bit, 0 indicates reading the current output status, 1 indicates writing a new output status; output status value, 1 bit, only valid when the command type is 1, 0 or 1; parity bit, 1 bit, used to calculate even parity for the 11 bits of the target slave station address, frame type bit, command type, and output status value; stop bit, 1 bit, high level.

[0050] The master station sends the frame to the bus, and all slave stations receive and parse it. After receiving a complete frame, a slave station parses the target slave address and finds that it matches its own address. Then, it reads the frame type bit: if the frame type bit is 0, the frame is an uplink data frame from another slave station, and the slave station ignores the frame content and does not perform any status update; if the frame type bit is 1, the frame is a downlink control frame from the master station, and the slave station continues to parse the subsequent command type and output status value.

[0051] The slave station whose address matches first checks the check bit. If it is correct, it performs the corresponding operation. If the command type is 0, the slave station does not modify the output, but will collect the current output latch state in the next base clock cycle as... The slave station reports normally; if the command type is 1, it updates its output latch to the output status value in the frame, thereby changing the output status bit in subsequent feature pairs. The slave station does not respond additionally after receiving the output control frame, but instead samples the output latch level in the next base clock cycle as the new... If this value changes compared to the output state of the previously reported feature pair, the slave station will trigger a subsequent report.

[0052] After the master station sends an output control frame (command type 1), it starts an independent short-time timer with a timeout period set to [value missing]. ,in, The maximum time required to transmit one frame of data (e.g., 14 bits × 10 ... If a report triggered by a change in output status from the target slave station is received within this short-timer, and the output status bit in the feature pair matches the command, then the control is confirmed to be successful; otherwise, the master station determines that the control has failed and can resend the output control frame. If it fails after three consecutive retries, an error is reported. It should be noted that this short-timer is related to the stabilization time threshold. Irrelevant Used only for periodically reported communication anomaly detection.

[0053] In this way, the master station can actively change the output of the slave station, realizing bidirectional closed-loop control of input and output.

[0054] S2.3: After the slave station successfully sends a frame of response data to the master station, the slave station performs the following update operation: Current feature pair Copy to the previously reported feature pair register In the middle; set the successful reporting flag to 1, indicating that the feature pair has been successfully reported at least once.

[0055] By maintaining the feature pairs reported in the last report and the successful reporting flag, the slave station can perform subsequent reports... During the cycle, the system compares the current feature pair with the previously reported feature pair to see if there are any changes. If a change has occurred, a new report is triggered, ensuring timely response to feature changes. If no change has occurred, periodic reporting is performed solely based on the overflow of the modulo-digital counter, avoiding unnecessary bus usage. This strategy, combining change-triggered reporting with periodic redundancy, ensures low-latency reporting of important state changes while maintaining communication activity at a controllable frequency when the state is stable, achieving a balance between real-time performance and bus load.

[0056] It should be noted that this embodiment uses a decrementing-to-zero overflow mechanism with the modulus counter. This eliminates the need for slave stations to maintain absolute timestamps, relying solely on the local clock cycle for periodic reporting. This reduces the computational burden on slave stations, and the cycles of each slave are independent, preventing synchronization conflicts. Furthermore, a protection logic is added during the decrementing process of the modulus counter, decrementing only when the value is greater than 0. This effectively prevents underflow when the counter remains at 0 for an extended period due to conflicts, ensuring the overflow condition remains valid during conflicts. This allows for immediate retrying of transmission after the conflict is resolved, improving the system's self-recovery capability. Additionally, this embodiment combines input and output states into a single 2-bit data entry, significantly reducing the amount of data reported per instance. This is beneficial for real-time communication between multiple slave stations on low-speed buses.

[0057] S3: When the modulus counter overflows, or the feature pair changes compared to the last reported feature pair, or no feature pair has ever been successfully reported to the master station, the slave station sends response data to the master station, resets the modulus counter, saves the current feature pair as the last reported feature pair, and sets the successful reporting flag to the reported status.

[0058] S3.1: Each slave station in each base clock cycle When the data transmission ends and the process is not currently in the process of sending a data frame, an overflow condition check is performed. Specifically, the current value of the modulus counter is read; if the value is 0, the overflow condition is considered to be true.

[0059] It is important to note that when the analog-to-digital (ADC) counter decreases from 1 to 0, the overflow condition is met in the current cycle, and the slave station immediately prepares to transmit. If transmission fails due to a bus collision, according to subsequent rules, the slave station does not reset the ADC counter, so its value remains 0. In the next base clock cycle, since the counter is still 0, the overflow condition will be met again. This process repeats until transmission is successful. This operation ensures that when the bus is continuously congested or a collision occurs, the slave station will not give up its transmission attempt but will re-initiate the competition in each cycle until successful, thus ensuring that important data, especially changes in feature pairs, can ultimately reach the master station.

[0060] S3.2: Each slave station in each base clock cycle At the end of the process, a change condition judgment is executed simultaneously. Specifically: the successful reporting flag is read; if the successful reporting flag is equal to 0, it means that no successful reporting has ever occurred, and the change condition is directly determined to be true; if the successful reporting flag is equal to 1, the current feature is compared. Features compared to the last reported If the two are not equal, the condition for change is determined to be true; if the two are equal, the condition for change is not true.

[0061] As can be seen from the above operation, the successful reporting flag is 0 at the initial stage of power-on, and a reporting is forcibly triggered once, so that the master station can obtain the initial feature pair of the slave station. Thereafter, reporting is only triggered when the feature pair actually changes, thus avoiding bus waste caused by repeatedly reporting the same data.

[0062] S3.3: When either the overflow condition or the change condition is met, the slave station enters the transmit operation state. During the transmit process, the slave station suspends its response to the basic clock cycle, that is, it no longer performs operations such as decrementing the analog-to-digital counter, acquiring input / output status, and splicing feature pairs.

[0063] After the transmission operation is completed, the slave station resets the value of the analog-to-digital counter to the modulo value M and resumes normal periodic operation from the start of the next base clock cycle, i.e., restarts the decrementing count, acquisition status, etc. Periods paused during transmission are not compensated because of the transmission time. Typically much shorter than a base clock cycle, the paused cycles are at most one cycle, accounting for less than 1% of the total M cycles (M is usually ≥100). The accumulated error is within the acceptable engineering range and does not affect system functionality. Normal operation resumes from the start of the next base clock cycle after transmission is complete. The specific operation is as follows: S3.3.1: The slave station constructs a fixed-length (e.g., 14-bit) data frame, in the following order of transmission: Start bit: 1 bit, low level; Slave address: 8 bits, high-order bits first, taken from the slave station's hardware-preset unique address Addr; Frame type bit: 1 bit, fixed at 0, indicating uplink data; Current feature pair: 2 bits, high-order bits first, taken from the slave station's most recent data acquisition. Even parity bit: 1 bit, used to calculate the even parity value for the 11 bits of data including the slave address, frame type bit, and current feature; Stop bit: 1 bit, high level.

[0064] Duration per person It is generated by an independent baud rate generator inside the slave station. With the basic clock cycle Decoupling. In this embodiment, it is set... =50μs, corresponding to a baud rate of 20000bps, makes the transmission time of a 14-bit data frame... Less than the base clock cycle Those skilled in the art can set it according to the actual bus speed requirements. The specific value.

[0065] The main station and all slave stations use the same In the above operations, the baud rate is unaffected. Precision constraints allow for the use of faster bit rates, increasing bus throughput; simultaneously, due to... It is used only to control the reporting cycle, and the allowable crystal oscillator error will not affect the accuracy of bit synchronization.

[0066] In the above example, the transmission time is much shorter than the basic clock cycle. The cumulative error caused by skipping the cycle without compensation is within the engineering allowable range and does not affect the system function.

[0067] S3.3.2: This embodiment is applicable to bus systems employing wired-AND topology. Preferably, the bus is an open-drain bus, the master station is configured with pull-up resistors (e.g., 1kΩ to 10kΩ), multiple slave stations share the same physical bus, and each slave station can achieve bit-by-bit arbitration by actively pulling the bus low. This embodiment uses an open-drain bus as an example for illustration; those skilled in the art can implement this embodiment of the invention on other buses that support wired-AND topology.

[0068] Each slave station can actively pull the bus low, but cannot force the bus to go high; when all slave stations release the bus, the bus is restored to a high level by the pull-up resistor.

[0069] For each bit in the data frame, the sending slave station performs the following operations: (1) At the beginning of the bit time, drive the bus according to the bit value to be sent: if the bit is 0 (low level), the slave actively pulls the bus low; if the bit is 1 (high level), the slave releases the bus; (2) The slave delays at 50% of the bit time, that is, from the beginning of the bit. / 2, sample bus level; (3) If the slave station intends to send 1, that is, release the bus, but finds that the bus level is low when sampling, it indicates that another slave station is pulling the bus low, and a conflict is determined; for example, slave station A (address 0b00000001) and slave station B (address 0b00000010) start sending the address field at the same time, sending from the highest bit to the lowest bit. Since address 0b0000001 and 0b00000010 are only different in the lowest two bits, when the second to last bit is sent, slave station A intends to send 0 (pull the bus low), and slave station B intends to send 1 (release the bus). At this time, the bus level is kept low because slave station A pulls it low. Slave station B samples that the bus is low and its own intention is high, thus detecting a conflict. Slave station B immediately terminates the transmission, and slave station A continues to send the remaining bits until success. (4) Once a conflict occurs, the slave station immediately terminates the transmission, releases the bus, and does not perform any post-processing actions, that is, it does not reset the modulus counter, and does not update The successful reporting flag is not changed. Then the slave station exits the sending state and waits for the next basic clock cycle to re-determine the trigger condition; (5) If the slave station successfully sends all bits, including the start bit, address, feature pair, parity bit, and stop bit, and no conflict is detected, then the sending is considered successful.

[0070] It should be noted that in the above operations, if multiple slave stations trigger transmission simultaneously, they will compete for the bus by comparing the bits they wish to send during the transmission of address or feature pairs. Since each slave station has a unique address, and priority is determined bit by bit from high to low (0 has higher priority than 1), only one slave station will ultimately be able to transmit the entire frame; other slave stations will immediately exit at the bit where a conflict occurs. This distributed arbitration method requires no master station intervention and is entirely autonomously completed by the slave stations, greatly reducing the overhead of bus conflict resolution and ensuring high priority—that is, the slave station with the smaller address value or zero high-order bits of the feature pair obtains the bus first—meets the real-time requirements of industrial environments.

[0071] Furthermore, the strategy of not resetting the modulus counter after a conflict ensures that slaves that exit due to the conflict remain in the triggered state in the next cycle, i.e., the counter is 0 or the feature pair is still active. Because they are different, they will immediately rejoin the competition until the transmission is successful. This avoids starvation and ensures that every slave station waiting to send a message can eventually successfully report.

[0072] Both the slave and master stations perform bit synchronization by detecting the falling edge of the start bit. Each station has an internal high-precision bit timer, with a clock source that is a local oscillator independent of the base clock cycle, and the oscillator frequency is 16 times the bit rate. When the falling edge of the start bit is detected, the bit timer is cleared and starts counting. The rising edge of the 8th counting clock (corresponding to 50% of the bit time) is used as the sampling point for that bit. Subsequent bits are sampled at the 8th counting clock of each bit time using a 16x oversampling method. This oversampling mechanism allows for a synchronization deviation of ±3 counting clocks (approximately ±18.75% of the bit time) per bit time, thus tolerating ±10% manufacturing error of the slave station's crystal oscillator and phase jitter during transmission. The master station uses the same oversampling and bit synchronization method. The master station and all slave stations agree on the same nominal bit rate, and the actual deviation is absorbed by the oversampling window, requiring no additional calibration.

[0073] S3.3.3: After the slave station successfully sends a data frame (including stop bits) and no collisions are detected, perform the following operations: Reset the modulus counter to the modulus value M; set the current feature pair Copy the feature pairs from the last report In the middle; set the successful reporting flag to 1.

[0074] After completing the above operations, the slave station exits the transmitting state and resumes normal periodic operations from the start of the next base clock cycle, i.e., resuming the decrementing, acquisition, and splicing actions of S2.2. Since the counter is reset to M, subsequent overflows will occur after M clock cycles, thus achieving control over the periodic reporting interval; simultaneously, because... If the current feature pair remains unchanged after being updated, no change reporting will be triggered, thus avoiding the repeated sending of the same data.

[0075] It should be noted that the embodiments of the present invention are based on the dual triggering conditions of analog-to-digital counter overflow and feature pair change, enabling slave stations to report immediately when their state changes (low latency) and report at fixed intervals when their state remains unchanged for a long time (maintaining communication activity), thus balancing real-time performance and bus load. Furthermore, the combination of bit-by-bit arbitration and open-drain bus achieves decentralized conflict resolution for multiple slave stations. Conflict detection is completed in-situ during transmission, requiring no additional handshake or backoff algorithms; the arbitration time is proportional to the frame length, resulting in extremely high efficiency.

[0076] S4: The master station updates the status record of the corresponding slave station based on the received response data and determines the communication status of the slave station that did not respond.

[0077] S4.1: The master station continuously monitors changes in bus level, using the exact same bit timing as the slave station. And the midpoint sampling method. The master station performs bit synchronization by detecting the falling edge of the bus, i.e. the start point of the start bit, and samples the level at 50% of the bit time, and parses the start bit, address field, frame type bit, feature pair field, check bit and stop bit in sequence.

[0078] A valid data frame is considered received when the master station detects that the following conditions are met simultaneously: a low level is detected and the length meets the specified criteria. When the start bit is detected, the stop bit is valid; when a high level is detected at the expected position, the stop bit is valid; when the even parity value calculated from the extracted address field, frame type bit, and feature pair field (a total of 11 bits) matches the received parity bit, the even parity is considered correct.

[0079] If any of the above conditions are not met, the master station discards the frame, does not perform any status update, and continues to monitor subsequent bus activity. This operation effectively filters out erroneous frames caused by collisions, noise, or bit synchronization deviations, ensuring the reliability of the master station's status updates.

[0080] Upon receiving a valid data frame, the master station extracts the 8-bit slave address (Addr) and the 2-bit feature pair (F) from the frame and then enters the status update process.

[0081] S4.2: During the initialization phase, after completing the polling in S1 and obtaining the actual number of slave stations N and the address list, the master station allocates and maintains three arrays for each existing address. The array length is the maximum address range (e.g., 1 to MaxAddr), but only operates on the addresses confirmed to exist in S1.

[0082] Specifically, the latest feature pair array `State[Addr]` stores the latest feature pairs reported by each slave station. The initial values ​​are all set to preset values ​​(e.g., binary 00). This array reflects the overall input / output status of each slave station as known to the master station. The non-acknowledgment timer array `Timer[Addr]` records the time elapsed since the last successful report from each slave station. The timing unit is consistent with the slave station's base clock cycle, e.g., 1 millisecond, and the initial value is 0. The acknowledged flag array `Received[Addr]` is a boolean array used to identify whether the master station has received at least one valid acknowledgement from the corresponding slave station; the initial value is false.

[0083] S4.3: Whenever the master station receives a valid data frame from the bus, after extracting the address Addr and feature pair F, the master station performs the following atomic operation: Clear the Timer[Addr] at the corresponding address in the unacknowledged timer array to zero. This operation indicates that the time of the last successful report by the slave station has been refreshed to the current time. Set the Received[Addr] at the corresponding address in the acknowledged flag array to true, indicating that the slave station has successfully reported at least once. Update the State[Addr] at the corresponding address in the latest feature pair array to the feature pair F received this time.

[0084] In the above operations, resetting the timer is crucial for subsequent timeout judgment, while updating the feature pairs maintains consistency between the master station's state and the slave station's actual state. It's important to note that the master station does not need to maintain a copy of the previously reported feature pairs, because timeout judgment is based solely on whether a response has been received, without comparing whether the feature pairs have changed (change detection has been handled by the slave station). This simplified design reduces the master station's computational and storage burden.

[0085] S4.4: The master station runs an independent timer, the timing period of which is the same as the slave station's base clock period. Consistent. Although there are manufacturing errors (e.g., ±10%) in the crystal oscillators of the master station and each slave station, the stabilization time threshold of the master station is consistent. The following formula incorporates a safety factor K (K≥2), which is sufficient to cover the maximum cumulative deviation caused by clock drift:

[0086] in, This represents the maximum reporting cycle from the station under conflict-free conditions.

[0087] Each time the master station completes its own timing cycle, it increments the unresponsive timer[Addr] for each existing slave station by 1. The modulo value broadcast from the master station to the slave station. A constant safety factor greater than 1 is used; in this embodiment, a fixed value of 2.5 is adopted. This value already accounts for the maximum ±10% error of the slave station's crystal oscillator and the timing error of the master station. The master station accumulates the unanswered timer based on its own timer. When the unanswered timer value of a slave station exceeds... If this occurs, a communication anomaly is detected.

[0088] It can be seen that the master station does not require precise synchronization with the slave station's clock, but only relies on... The generous design ensures the reliability of timeout judgment.

[0089] Meanwhile, each time the master station receives a response from a slave station, it not only resets the unanswered timer but also records the actual interval between responses. If multiple consecutive intervals significantly deviate from the expected range, such as exceeding ±20%, the master station determines that the slave station's clock is abnormal and issues an alarm, but does not immediately mark it as a communication interruption. Instead, it allows the slave station to continue reporting using the conflict retry mechanism. Furthermore, the slave station uses fixed-bit timing when sending data frames. (Generated by an independent baud rate generator), this bit time is... Decoupling ensures that clock errors do not affect the bus bit synchronization accuracy.

[0090] It should be noted that the master station independently maintains a non-response timer and a corresponding stable time threshold for each slave station. For slave stations with a configuration status flag of 0 (or those reporting feature pair 11 for the first time after power-on), the time threshold is calculated using the default modulus value of 1000; for slave stations that have received broadcast configuration, it is calculated using the broadcast value M.

[0091] The method also includes one or more processors and memory.

[0092] The memory is used to store operable instructions that, when executed by the one or more processors, cause the one or more processors to perform operations, including the flow of a master-slave cooperative I / O module communication control method according to the foregoing embodiments, especially... Figure 1 The flowchart of the method is shown.

[0093] Other aspects disclosed in the embodiments of the present invention also propose a computer-readable medium for storing software including instructions executable by one or more computers, which, upon execution, cause the one or more computers to perform operations including the flow of a master-slave cooperative I / O module communication control method of the foregoing embodiments, particularly... Figure 1 The flowchart of the method is shown.

[0094] It should be recognized that embodiments of the present invention may be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable storage medium.

[0095] The method can be implemented using standard programming techniques, including a non-transitory computer-readable storage medium configured with a computer program in the computer program, wherein the storage medium is configured such that the computer operates in a specific and predefined manner.

[0096] Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system; however, if required, the program can be implemented in assembly or machine language.

[0097] In any case, the language can be either compiled or interpreted.

[0098] Furthermore, for this purpose, the program can run on programmed application-specific integrated circuits.

[0099] The processes described herein (or variations and / or combinations thereof) can be executed under the control of one or more computer systems configured with executable instructions, and can be implemented by hardware or a combination thereof as code (e.g., executable instructions, one or more computer programs, or one or more applications) that commonly executes on one or more processors. The computer program includes a plurality of instructions executable by one or more processors.

[0100] Furthermore, the method can be implemented in any suitable computing platform, including but not limited to personal computers, minicomputers, mainframes, workstations, networked or distributed computing environments, standalone or integrated computer platforms, or in communication with charged particle tools or other imaging devices.

[0101] Various aspects of the present invention can be implemented in machine-readable code stored on a non-transitory storage medium or device, whether portable or integrated into a computing platform, such as a hard disk, optical read and / or write storage medium, RAM, ROM, etc., such that it can be read by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the processes described herein.

[0102] Furthermore, machine-readable code, or parts thereof, can be transmitted via wired or wireless networks.

[0103] When such media includes instructions or programs that combine with a microprocessor or other data processor to implement the steps described above, the invention described herein includes these and other different types of non-transitory computer-readable storage media.

[0104] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A communication control method for I / O modules based on master-slave collaboration, characterized in that: include: The master station obtains the number N of slave stations by polling the hardware addresses. Each slave station maintains an analog-to-digital counter, a feature pair, a previously reported feature pair, and a successful reporting flag. The feature pair includes the current input state and the current output state. Each slave station runs an independent timer to generate a base clock cycle; When the modulus counter overflows, or the feature pair changes compared to the previously reported feature pair, or no feature pair has ever been successfully reported to the master station, the slave station sends response data to the master station, resets the modulus counter, saves the current feature pair as the previously reported feature pair, and sets the successful reporting flag to the reported state. The master station updates the status record of the corresponding slave station based on the received response data and determines the communication status of the slave station that did not respond. When the slave station sends response data, it adopts a bit-by-bit arbitration mechanism: the slave station constructs a data frame, which contains, in sequence, a start bit, an address field, a frame type bit, a current feature pair, a check bit, and a stop bit; the value of the address field is equal to the unique slave address preset by the slave station in hardware. The start bit is in a first level state, and the stop bit is in a second level state; The bus uses a wired-AND mechanism, and the master station is equipped with pull-up components; For each bit in the data frame, the slave station drives the bus at the start point of the bit time of each bit: if it wants to send the first level state, it actively drives the bus to the first level state; if it wants to send the second level state, it releases the bus. Both the slave and the master station perform bit synchronization by detecting the transition edge of the start bit and sample the bus level at a predetermined sampling point in each bit time. If the slave station intends to send a second level state but samples the bus as a first level state, a conflict is determined, the current transmission is immediately stopped, the bus is released, the analog-to-digital counter and the previously reported feature pair are not updated, and the trigger condition is re-evaluated in the next basic clock cycle. If no collisions are detected in any of the bits in the data frame, the transmission is successfully completed.

2. The I / O module communication control method based on master-slave collaboration as described in claim 1, characterized in that: The master station obtains the number N of slave stations through hardware address polling, including: After the master station is powered on, the control bus enters a low-level state and remains in a first preset duration, forcing all slave stations to remain silent; the master station releases the bus and opens a silence window of a second preset duration, and all slave stations complete initialization before the end of the silence window. Each slave station is pre-configured with a unique slave station address via hardware configuration. The master station sequentially sends address query frames to each slave station address; If a slave station that exists and has a matching address replies with an address response frame, the master station will mark the slave station address corresponding to the address response frame as existing and increment the slave station count. After the polling is completed, the master station obtains the actual number of slave stations. If the number of slave stations is zero, the master station will report an error and stop.

3. The I / O module communication control method based on master-slave collaboration as described in claim 1, characterized in that: Each slave station maintains a modular counter and a pair of features, including: The master station sets a uniform modulus value for all slave stations via broadcast. After each slave station enters normal working mode, it obtains its own slave station address and the modulus value, sets the initial value of the modulus counter to the modulus value, sets the successful reporting flag to the non-reporting state, and sets the feature pair of the last reported data to the initial value. Every time a basic clock cycle passes and the slave station is not in the process of sending data frames, if the value of the analog-to-digital counter is greater than 0, it is decremented by 1; if the value of the analog-to-digital counter is equal to 0, it remains unchanged. At the same time, the current input state and the current output state are collected, and the current input state and the current output state are concatenated to form the current feature pair.

4. The I / O module communication control method based on master-slave collaboration as described in claim 3, characterized in that: When the modulus counter overflows or the feature pair changes, the slave station sends response data to the master station and resets the modulus counter, including: At the end of each of the basic clock cycles and not during the transmission process, each slave station checks whether the value of the analog-to-digital counter is zero. If the value of the analog-to-digital counter is zero, the overflow condition is determined to be met. Each slave station compares the current feature pair with the previously reported feature pair. If the successful reporting flag is in the no-reporting state or the current feature pair is not equal to the previously reported feature pair, then the change condition is determined to be met. When either the overflow condition or the change condition is met, the slave station performs a transmission operation. During transmission, the decrement and sampling of the base clock cycle are paused. After transmission is completed, the analog-to-digital counter is reset, the current feature pair is saved as the feature pair reported last time, the successful reporting flag is set to the reported state, and execution resumes from the start of the next base clock cycle.

5. The I / O module communication control method based on master-slave collaboration as described in claim 1, characterized in that: The master station updates the status record based on the received response data and determines the communication status of the unresponsive slave station, including: The master station continuously monitors the bus and uses a preset bit synchronization method. When a valid data frame is detected, it extracts the address and feature pairs from the valid data frame. The main station maintains the latest feature pair records, non-response timer records, and records of whether a response has been received for each address; For each valid data frame received, the master station clears the non-acknowledgment timer of the address corresponding to the valid data frame, marks the record of whether an acknowledgment has been received as received, and updates the latest feature pair record with the feature pair extracted from the valid data frame. The master station runs an independent timer that generates the same base clock cycle as the slave station. Each base clock cycle increments all unresponsive timers once. When the value of a certain unanswered timer exceeds a preset stable time threshold, it is determined that the slave communication corresponding to the address of the unanswered timer is abnormal, and the abnormality type is distinguished according to whether a response has been received.

6. The I / O module communication control method based on master-slave collaboration as described in claim 4, characterized in that: When a transmission fails due to a collision, the value of the modulus counter remains unchanged.

7. The I / O module communication control method based on master-slave collaboration as described in claim 1, characterized in that: The data frame is of fixed length and consists of, in order, a start bit, an address field, a frame type bit, a feature pair field, a check bit, and a stop bit. The check bit is calculated from the address field, the frame type bit, and the feature pair field; The duration of each bit in the data frame is generated by an independent time base, decoupled from the basic clock cycle.

8. The I / O module communication control method based on master-slave collaboration as described in claim 5, characterized in that: The stability time threshold is greater than the maximum reporting cycle of the slave station.

9. The I / O module communication control method based on master-slave collaboration as described in claim 2, characterized in that: The address query frame and the address response frame adopt the same frame structure rules; The frame structure rules include start bit, check bit, and stop bit.

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