Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The method comprises: forming a drift layer on a substrate; forming a first epitaxial layer on the drift layer, doping a partial region of the first epitaxial layer to form a shielding region, and the first epitaxial layer not doped is a first doped region; forming a second epitaxial layer on the first epitaxial layer, doping a partial region of the second epitaxial layer to form a first contact region, and the second epitaxial layer not doped is a second doped region; forming a third epitaxial layer on the second epitaxial layer, doping a first region of the third epitaxial layer to form a second contact region, doping a second region of the third epitaxial layer to form a source region, and the third epitaxial layer not doped is a body region; forming a trench gate structure, an interlayer dielectric layer and a source metal layer. The application makes the shielding region electrically connected with the source metal layer, so that the shielding region potential is clamped by the source, thereby effectively inhibiting the electric field peak at the trench corner in the blocking state.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Silicon carbide (SiC), as a third-generation wide-bandgap semiconductor material, has become the preferred material for high-voltage, high-frequency, and high-power devices due to its high critical breakdown electric field, high thermal conductivity, and excellent carrier transport characteristics. Among them, SiC trench metal-oxide-semiconductor field-effect transistors (TMOS, also known as SiC trench MOSFETs) are expected to achieve lower specific on-resistance (Ron,sp) due to their smaller cell spacing and higher channel mobility on the trench sidewalls, making them extremely valuable for applications in power electronics fields such as new energy vehicles, photovoltaic inverters, and rail transportation.

[0003] However, in the blocked state, SiC trench MOSFET devices are prone to electric field concentration at the gate oxide layer at the trench corners. Over long-term use, this can lead to reliability issues such as gate oxide breakdown and threshold voltage drift, severely limiting the device's lifespan and stability. To alleviate the electric field concentration effect at the trench corners, the industry commonly employs a P+ shielding structure. However, existing mainstream P-well shielding structures all suffer from technical bottlenecks that make it difficult to balance conduction performance and reliability. Furthermore, forming a P+ shielding region deeper than 1µm requires a high-energy ion implantation process, which is technically challenging and expensive. Summary of the Invention

[0004] In view of the above problems, the purpose of this application is to provide a semiconductor device and a method for manufacturing the same, which reduces ion implantation energy and improves device conductivity and reliability by using a multilayer epitaxial growth method.

[0005] According to one aspect of this application, a method for manufacturing a semiconductor device is provided, comprising: providing a substrate; forming a drift layer of a first conductivity type on the substrate; forming a first epitaxial layer of the first conductivity type on the drift layer; doping a portion of the first epitaxial layer to form a shielding region of a second conductivity type, wherein the undoped first epitaxial layer is a first doped region; forming a second epitaxial layer of the first conductivity type on the first epitaxial layer; doping a portion of the second epitaxial layer to form a first contact region of the second conductivity type, wherein the undoped second epitaxial layer is a second doped region; forming a third epitaxial layer of the second conductivity type on the second epitaxial layer; doping a first region of the third epitaxial layer to form a second contact region of the second conductivity type; doping a second region of the third epitaxial layer to form a source region of the first conductivity type, wherein the undoped third epitaxial layer is a body region; and forming a trench gate structure, an interlayer dielectric layer, and a source metal layer.

[0006] In some embodiments, the steps of forming the second contact region, source region, and body region include: forming a first mask layer on a first region of the third epitaxial layer, and performing ion implantation on the third epitaxial layer through the first mask layer to form a second contact region of a second conductivity type; removing the first mask layer; forming a second mask layer on a second region of the third epitaxial layer, and performing ion implantation on the third epitaxial layer through the second mask layer to form a source region of a first conductivity type, the source region extending from a first surface to a second surface of the third epitaxial layer, the second surface of the source region being located in the third epitaxial layer, and the region of the third epitaxial layer not subjected to ion implantation being a body region; removing the second mask layer, wherein the first region of the third epitaxial layer corresponds to the source region, the second region corresponds to the second contact region, and the second contact region is correspondingly connected to the first contact region.

[0007] In some embodiments, the ion implantation energy for forming the second contact region is greater than the ion implantation energy for forming the source region.

[0008] In some embodiments, a portion of the second epitaxial layer is doped using ion implantation to form a first contact region of a second conductivity type; a portion of the first epitaxial layer is doped using ion implantation to form a shielding region of a second conductivity type; wherein the ion implantation energy for forming the shielding region is less than the energy for forming the first contact region.

[0009] In some embodiments, the first region of the third epitaxial layer is doped by ion implantation to form a second contact region of a second conductivity type, wherein the ion implantation energy for forming the shielding region is less than the ion implantation energy for forming the second contact region.

[0010] In some embodiments, along the first direction, the width of the first contact area is smaller than the width of the shielding area.

[0011] In some embodiments, the doping concentration of the shielding region, the first contact region, and the second contact region is greater than the doping concentration of the body region.

[0012] According to another aspect of the present invention, a semiconductor device is provided, comprising a plurality of cell units, each cell unit comprising: a trench gate structure extending along a second direction; a source region of a first conductivity type located on both sides of the trench gate structure and adjacent to the sidewalls of the trench gate structure; a body region of a second conductivity type located on both sides of the trench gate structure and adjacent to the sidewalls of the trench gate structure, and the body region being located below the source region; a contact region of a second conductivity type located on both sides of the trench gate structure and adjacent to the sidewalls of the source region and the body region away from the trench gate structure, and the contact region extending along the depth direction of the trench gate structure below the bottom surface of the trench gate structure; a shielding region of a second conductivity type located below the two contact regions; a doped region of a first conductivity type located below the body region and in the region between the contact region and the shielding region, the bottom surface of the doped region having the same depth as the bottom surface of the shielding region; wherein, along a first direction, the shielding region extends toward the sidewalls of the trench gate structure beyond the contact region, and its end is adjacent to the sidewalls of the trench gate structure.

[0013] In some embodiments, along a third direction, the side surface of the end of the shielding area is coplanar with the sidewalls on both sides of the trench grid structure.

[0014] According to another aspect of the present invention, a semiconductor device is provided, wherein the semiconductor device is manufactured by the manufacturing method described above.

[0015] The semiconductor device and its manufacturing method provided in this application form a shielding region, a contact region, a source region and a body region by successively doping three epitaxial layers. This method has strong process compatibility, avoids complex etching steps, improves yield and reduces costs.

[0016] In some embodiments, by electrically connecting the shielding region to the source metal layer (via a contact region), the potential of the shielding region is clamped by the source. When the device is in a blocking state (high-voltage turn-off), the electric field peak at the bottom corner of the trench gate structure is effectively suppressed, preventing the gate oxide layer from breaking down due to electric field concentration, thus significantly improving the reliability and lifespan of the device. At the same time, the direct connection between the shielding region and the source avoids the gate leakage current problem that may be caused by traditional "floating" shielding regions.

[0017] In some embodiments, both the contact region and the shielding region are of a second conductivity type (such as P-type) and have the same doping concentration, thereby forming a low-resistance path. This ensures efficient coupling of the source potential to the shielding region and enhances the electric field modulation effect. Furthermore, it avoids abrupt changes in interface potential or carrier scattering due to differences in doping, thus improving device stability.

[0018] In some embodiments, the shielding area is extended laterally to be wider, bringing it closer to the bottom corner of the trench, directly dispersing the electric field concentration at that location, while avoiding an excessively large contact area that would increase the cell spacing, thus balancing device compactness and electric field optimization.

[0019] In some embodiments, the positional relationship between the drift layer and the doped region is defined. The doped region is located below the body region and the trench gate, separating adjacent shielding regions. The higher doping concentration in the doped region compared to the drift region reduces the JFET region resistance and improves conduction efficiency. The shielding regions are separated by the doped region, which on the one hand realizes the channel path, on the other hand prevents mutual interference of electric fields, and optimizes the breakdown voltage capability.

[0020] In some embodiments, the third dimension of the trench grid is equal to the fourth dimension of the adjacent shielding area, that is, the sidewall of the trench is aligned with the sidewall of the shielding area, so that the electric field distribution is more uniform and local distortion is avoided.

[0021] In some embodiments, the third dimension of the trench gate is larger than the fourth dimension of the adjacent shielding region, such that the sidewall of the shielding region is located between the two sidewalls of the trench gate structure, further smoothing the electric field gradient and reducing the risk of gate oxide interface defects.

[0022] In some embodiments, the drift layer is of a low concentration first conductivity type, and the doped region is of a high concentration first conductivity type. The drift layer ensures a high breakdown voltage, and the doped region reduces the on-resistance, thereby achieving synergistic optimization of breakdown voltage and efficiency. Attached Figure Description

[0023] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0024] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this application is shown;

[0025] Figures 2a to 2i Vertical cross-sectional views of each stage of a method for manufacturing a semiconductor structure according to an embodiment of this application are shown;

[0026] Figure 3 A three-dimensional structural diagram of a semiconductor device according to an embodiment of this application is shown;

[0027] Figure 4 A vertical cross-sectional view of a semiconductor structure according to an embodiment of this application is shown;

[0028] Figures 5a to 5c It shows that according to Figure 4 A horizontal cross-sectional view of the semiconductor structure obtained by the dashed line. Detailed Implementation

[0029] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, the semiconductor structure obtained after several steps can be depicted in a single figure.

[0030] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0031] To describe a situation where it is directly above another layer or another area, this article will use expressions such as "directly above" or "above and adjacent to".

[0032] Many specific details of this application, such as the structure, materials, dimensions, processing techniques, and methods of the devices, are described below to provide a clearer understanding of the application. However, as those skilled in the art will understand, this application may be implemented without adhering to these specific details.

[0033] The specific implementation methods of this application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0034] In the embodiments of this application, for the sake of clarity in describing the specific implementation of this application, the first direction is defined as the X direction, the second direction as the Y direction, and the third direction as the Z direction, and the first direction, the second direction, and the third direction are mutually perpendicular. The plane containing the first and second directions is a horizontal plane, and the plane containing the third direction is a vertical plane.

[0035] The semiconductor device of this application includes multiple cell units. Figure 2i and Figure 3 For example, an example diagram with two cell units is shown. In the following description, an exemplary description will be given with a structure of one cell unit.

[0036] like Figure 1 and Figures 2a to 2i As shown, the method for manufacturing the semiconductor device illustrated in this application includes the following steps.

[0037] Step S10: Provide a substrate and form a drift layer of a first conductivity type on the substrate.

[0038] In this step, an epitaxial growth process is used to form a drift layer 120 of a first conductivity type on the first surface of the substrate 110, such as... Figure 2a As shown.

[0039] The substrate 110 is provided with opposing first surface S1 and second surface S2, and serves as the drain region of the final semiconductor device.

[0040] The drift layer 120 is located on the first surface S1 of the substrate 110, and its thickness H2 is greater than the thickness H1 of the substrate 110.

[0041] The substrate 110 has the same conductivity type as the drift layer 120, both being of the first conductivity type, and the doping concentration of the substrate 110 is higher than that of the drift layer 120. In this embodiment, the conventional doping concentration of the drift layer 120 is, for example, 5 × 10⁻⁶. 15 ~1.2×10 16 cm -3 .

[0042] Step S20: A first epitaxial layer of a first conductivity type is formed on the drift layer, and a portion of the first epitaxial layer is doped to form a shielding region of a second conductivity type. The undoped first epitaxial layer is the first doped region.

[0043] In this step, an epitaxial growth process is used to form a first epitaxial layer 101 on the first surface of the drift layer 120, such as... Figure 2a As shown.

[0044] The first epitaxial layer 101 is of the first conductivity type, and its doping concentration is higher than that of the drift layer 120, but lower than that of the substrate 110, so as to balance the breakdown voltage and the on-resistance.

[0045] In some embodiments, the thickness H3 of the first epitaxial layer 101 is less than the thickness H2 of the drift layer 120.

[0046] In some embodiments, the thickness H3 of the first epitaxial layer 101 is less than the thickness H1 of the substrate 110.

[0047] After forming the first epitaxial layer 101, the process further includes forming a patterned mask layer on the first surface of the first epitaxial layer 101, then performing ion implantation on the first epitaxial layer 101 through the mask layer to form a shielding region 152 of a second conductivity type in the area of ​​the first epitaxial layer 101 not covered by the mask layer, and then removing the mask layer, as shown below. Figure 2b As shown.

[0048] The shielding region 152 extends from the first surface of the first epitaxial layer 101 to the second surface, such that the second surface of the shielding region 152 is adjacent to the first surface of the drift layer 120.

[0049] In this process, the portion of the first epitaxial layer 101 covered by the mask layer retains the first conductivity type after ion implantation to form the shielding region 152, thus serving as the first doped region 143a.

[0050] In this embodiment, the conventional doping concentration of the shielding region 152 of the second conductivity type is, for example, 1 × 10⁻⁶. 18 ~3×10 18 cm -3 The doping concentration of the first doped region 143a of the first conductivity type is, for example, 1 × 10⁻⁶. 17 ~5×10 17 cm -3 .

[0051] In this embodiment, since ion implantation is performed directly on the first epitaxial layer 101 located on the surface of the semiconductor structure in this step to form the shielding region 152, the ion implantation depth is significantly reduced compared to the ion implantation depth in conventional methods, thereby significantly reducing the ion implantation energy. In some embodiments, the shielding region 152 requires an ion implantation depth exceeding 1 μm and an ion implantation energy exceeding 1 MeV in conventional methods; while in this application, the shielding region 152 requires an ion implantation depth of 0.2~0.4 μm and only requires an energy of 30~220 keV.

[0052] Step S30: A second epitaxial layer of a first conductivity type is formed on the first epitaxial layer. A portion of the second epitaxial layer is doped to form a first contact region of a second conductivity type. The undoped second epitaxial layer is the second doped region.

[0053] In this step, an epitaxial growth process is used to form a second epitaxial layer 102 on the first surface of the first epitaxial layer 101, such as... Figure 2c As shown.

[0054] The second epitaxial layer 102 is of the first conductivity type, and its doping concentration is the same as that of the first epitaxial layer 101.

[0055] In some embodiments, the thickness H4 of the second epitaxial layer 102 is greater than the thickness H3 of the first epitaxial layer 101.

[0056] After forming the second epitaxial layer 102, a patterned mask layer is formed on the first surface of the second epitaxial layer 102. Then, ion implantation is performed on the second epitaxial layer 102 through the mask layer to form a first contact region 151a of a second conductivity type in the area of ​​the second epitaxial layer 102 not covered by the mask layer. The mask layer is then removed. Figure 2d As shown.

[0057] The first contact area 151a extends from the first surface of the second epitaxial layer 102 to its second surface, and the projection of the first contact area 151a on the first surface S1 of the substrate 110 falls into the projection of the shielding area 152 on the first surface S1 of the substrate 110, thereby making the second surface of the first contact area 151a adjacent to the first surface of the shielding area 152.

[0058] In this process, a portion of the second epitaxial layer 102 covered by the mask layer retains the first conductivity type after ion implantation, serving as the second doped region 143b. A portion of the second surface of the second doped region 143b is adjacent to the first surface of the first doped region 143a, and the two together serve as the doped region 143.

[0059] In this embodiment, the ion implantation energy for forming the shielding region 152 is less than the ion implantation energy for forming the first contact region 151a. The conventional doping concentration of the first contact region 151a of the second conductivity type is, for example, 1 × 10⁻⁶. 18 ~5×10 18 cm -3 The doping concentration of the second doped region 143b of the first conductivity type is, for example, 1 × 10⁻⁶. 17 ~5×10 17 cm -3 .

[0060] Step S40: A third epitaxial layer of the second conductivity type is formed on the second epitaxial layer. The first region of the third epitaxial layer is doped to form a second contact region of the second conductivity type. The second region of the third epitaxial layer is doped to form a source region of the first conductivity type. The undoped third epitaxial layer is the body region.

[0061] In this step, an epitaxial growth process is used to form a third epitaxial layer 103 on the first surface of the second epitaxial layer 102, such as... Figure 2e As shown.

[0062] The third epitaxial layer 103 is of the second conductivity type, and its doping concentration is lower than that of the shielding region 152 and the first contact region 151a.

[0063] In some embodiments, the thickness H5 of the third epitaxial layer 103 is greater than the thickness H4 of the second epitaxial layer 102 to ensure that the source region and the body region have sufficient junction depth and doping gradient.

[0064] After forming the third epitaxial layer 103, a patterned first mask layer is formed on the first surface of the third epitaxial layer 103. No first mask layer is formed in the first region. Ion implantation is then performed in the third epitaxial layer 103 via the first mask layer, thereby forming a second contact region 151b of a second conductivity type in the first region of the third epitaxial layer 103. Subsequently, the first mask layer is removed. Figure 2f As shown.

[0065] The second contact area 151b extends from the first surface of the third epitaxial layer 103 to its second surface, and the projection of the second contact area 151b on the first surface S1 of the substrate 110 coincides with the projection of the first contact area 151b on the first surface S1 of the substrate 110, so that the second surface of the second contact area 151b is adjacent to the first surface of the first contact area 151a.

[0066] The second contact area 151b is electrically connected to the first contact area 151a, and the dimension D11 of the first contact area 151a along the first direction is equal to the dimension D12 of the second contact area 151b along the first direction. The sidewalls of the two are located on the same vertical plane, so the first contact area 151a and the second contact area 151b together constitute the contact area 151 of a continuous low-resistance path.

[0067] After forming the second contact region 151b, a patterned second mask layer is formed on the first surface of the third epitaxial layer 103. No second mask layer is formed in the second region. Ion implantation is then performed in the third epitaxial layer 103 via the second mask layer, thereby forming a source region 141 of a first conductivity type in the second region of the third epitaxial layer 103. The second mask layer is then removed. Figure 2g As shown.

[0068] The source region 141 extends from the first surface of the third epitaxial layer 103 to the second surface to a certain depth, but does not extend to the second surface of the third epitaxial layer 103. That is, the second surface of the source region 141 is located inside the third epitaxial layer 103.

[0069] The first surface of the third epitaxial layer 103 includes a first region and a second region. The first region corresponds to the second contact region 151b, and the second region corresponds to the source region 141. After forming the first mask layer, ion implantation is performed on the third epitaxial layer 103 to form the second contact region 151b in the first region. After forming the second mask layer, ion implantation is performed on the third epitaxial layer 103 to form the source region 141 in the second region. Furthermore, the ion implantation energy for forming the second contact region 151b is greater than the ion implantation energy for forming the source region 141, and the ion implantation energy for forming the shielding region 152 is less than the ion implantation energy for forming the second contact region 151b.

[0070] In the first region of the third epitaxial layer 103, the portion of the third epitaxial layer 103 that has not been ion implanted between the second surface of the source region 141 and the first surface of the doped region 143 serves as the body region 142. The source region 141, the body region 142, and the doped region 143 are located together between two adjacent contact regions 151.

[0071] In this embodiment, the conventional doping concentration of the second contact region 151b of the second conductivity type is, for example, 1×10¹⁸~5×10¹⁸ cm⁻³. The doping concentration of the source region 141 of the first conductivity type is, for example, 5×10¹⁸~2×10¹⁹ cm⁻³. The doping concentration of the body region 142 of the second conductivity type is 1×10¹⁷~1×10¹⁸ cm⁻³.

[0072] In this embodiment, the contact region 151 is divided into a first contact region 151a and a second contact region 151b, which significantly reduces the depth of ion implantation in a single operation. In some embodiments, the maximum depth of the complete contact region 151 exceeds 0.8 μm, and the energy required for ion implantation is 700-1100 keV. However, in this application, after dividing the contact region into a first contact region 151a and a second contact region 151b, the maximum depth does not exceed 0.4 μm, and the ion implantation energy is significantly reduced to 200-300 keV.

[0073] In some embodiments, the source region 141 requires an ion implantation energy of 30~220 keV. The body region 142 is formed by epitaxially growing a third epitaxial layer 103 without additional ion implantation, resulting in better doping uniformity, more uniform doping concentration in both depth and width directions, no obvious concentration gradient, and more precise control over the depth of the body region 142, leading to better channel quality.

[0074] Step S50: Etch to form trenches and form a trench gate structure in the trenches.

[0075] In this step, a patterned mask layer is formed on the first surface of the third epitaxial layer 103, and then an etching process is performed through the mask layer, such as dry etching, to form a trench penetrating the source region 141, the body region 142, and part of the doped region 143. Then, a gate dielectric layer 131 and a gate conductor 132 are sequentially deposited in the trench to form a complete trench gate structure 130. Figure 2h As shown.

[0076] The bottom of the trench gate structure 130 is located within the doped region 143 and is completely isolated from the shielding region 152 by the doped region 143, ensuring that the gate electric field is not directly coupled to the shielding region 152.

[0077] Step S60: Form an interlayer dielectric layer, a source metal layer, and a drain metal layer.

[0078] In this step, a deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), is used to form an interlayer dielectric layer 161 on the first surface of the trench gate structure 130. Then, a source metal layer 162 is formed on the contact region 151, the source region 141, and the first surface of the interlayer dielectric layer 161 using a deposition process. Finally, a drain metal layer 163 is formed on the second surface of the substrate 110 using a deposition process. Figure 2i As shown.

[0079] The interlayer dielectric layer 161 completely covers the top of the trench gate structure 130 and can also cover part of the source region 141 near the first surface area of ​​the trench gate structure 130 to achieve electrical isolation between the gate and the source.

[0080] Reference Appendix Figure 2i Along the first direction, the contact area 151 has a first dimension D1, the shielding area 152 has a second dimension D2, the trench gate structure 130 has a third dimension D3, and the portion of the doped area 143 adjacent to the first surface of the drift layer 120 has a fourth dimension D4, which is also the dimension between two adjacent shielding areas 152.

[0081] In some embodiments, the second dimension D2 is larger than the first dimension D1, so that the end of the shielding region 152 is as close as possible to the bottom corner of the trench gate structure 130, thereby more effectively dispersing the electric field concentration at the trench corner and improving the gate oxide reliability.

[0082] In some embodiments, the third dimension D3 is equal to the fourth dimension D4, such that the sidewall of the shielding region 152 and the sidewall of the trench gate structure 130 are located in the same vertical plane, that is, the sidewall at the end of the shielding region 142 is coplanar with the sidewalls on both sides of the trench gate structure 130, so as to ensure that the concentrated electric field at the bottom corner of the trench gate structure 130 is directly and uniformly dispersed by the shielding region 152, thereby significantly suppressing the risk of local breakdown of the gate oxide layer.

[0083] In some embodiments, the fourth dimension D4 is smaller than the third dimension D3, so that the vertical plane containing the sidewall of the shielding region 152 is located inside the sidewall of the trench gate structure 130, further optimizing the symmetry and smoothness of the electric field distribution and reducing the probability of gate oxide interface defect generation.

[0084] In some embodiments, the shielding region 152 does not directly contact the sidewall of the trench gate structure 130, but by precisely controlling the dimensional relationship between D2 and D4, effective modulation of the electric field at the bottom corner can still be achieved. At the same time, channels can be formed on both sidewalls of the trench gate structure 130, which significantly increases the conduction current density and reduces the conduction resistance. Compared with other structures, it is more conducive to reducing the cell spacing and reducing manufacturing costs.

[0085] Figure 5a For example, along Figure 4 A horizontal cross-sectional view obtained in the direction indicated by the dashed line A; Figure 5b For example, along Figure 4 A horizontal cross-sectional view obtained in the direction indicated by the dashed line B; Figure 5c For example, along Figure 4 A horizontal cross-sectional view obtained in the direction indicated by the dashed line C.

[0086] like Figure 3 and Figure 4 As shown, the semiconductor device 100 of this application includes: a substrate 110, a drift layer 120, a trench gate structure 130, a source region 141, a body region 142, a doped region 143, a contact region 151, a shielding region 152, an interlayer dielectric layer 161, a source metal layer 162, and a drain metal layer 163.

[0087] The substrate 110 has a first surface S1 and a second surface S2 disposed opposite to each other, and the substrate 110 serves as the drain region of the semiconductor device 100. In the following description, the first surface of each layer is the surface located above the second surface along a third direction in the figure.

[0088] In this embodiment, the substrate 110 is made of silicon carbide (SiC), for example. In other embodiments, the substrate 110 may also be made of elemental semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon-germanium (SiGe), binary, ternary, or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide phosphide (InGaAsP). However, this embodiment is not limited to these, and those skilled in the art can make other settings for the material of the substrate 110 as needed.

[0089] The substrate 110 is of the first conductivity type. The crystal orientation of the substrate 110 may include the m-plane (1-100) or the a-plane (11-20).

[0090] The drift layer 120 is located on the first surface S1 of the substrate 110 and has a first surface and a second surface disposed opposite to each other. The second surface of the drift layer 120 is adjacent to the first surface S1 of the substrate 110, and the first surface of the drift layer 120 is away from the first surface S1 of the substrate 110.

[0091] The drift layer 120 may be made of the same or different semiconductor material as the substrate 110.

[0092] The drift layer 120 is of the first conductivity type, and the doping concentration of the drift layer 120 is less than that of the substrate 110. In other embodiments, the thickness and doping concentration of the drift layer 120 can be designed according to the device's breakdown voltage and on-resistance requirements.

[0093] The trench gate structure 130 is located in the trench on the drift layer 120, and the bottom of the trench gate structure 130 is separated from the first surface of the drift layer 120 by a certain distance.

[0094] The trench gate structure 130 includes a gate dielectric layer 131 and a gate conductor 132.

[0095] The gate dielectric layer 131 covers the sidewalls and bottom of the trench, and its material can be selected from silicon oxide, silicon nitride or high-k dielectric material to improve gate control capability and reduce leakage current.

[0096] The gate conductor 132 fills the cavity enclosed by the gate dielectric layer 131. Its material can be polysilicon, metal, or metal-polysilicon composite structure to achieve low contact resistance and high thermal stability.

[0097] The gate dielectric layer 131 separates the gate conductor 132 from the doped region 143 to prevent leakage and ensure effective control of the gate over the channel region.

[0098] The trench gate structure 130 includes multiple trench gate structures 130, which are spaced apart along a first direction and extend parallel to each other along a second direction to form a regularly arranged trench gate array, such as... Figure 3 As shown.

[0099] Source region 141 is located on both sides of trench gate structure 130. One side wall of source region 141 is adjacent to the side wall of trench gate structure 130, and the first surface of source region 141 and the first surface of trench gate structure 130 are located on the same horizontal plane.

[0100] The source region 141 is of the first conductivity type, and its doping concentration is higher than that of the drift layer 120.

[0101] The depth of the source region 141 extending from the first surface to the second surface is less than the depth of the trench gate structure 130 extending from the first surface to the second surface.

[0102] The first surface of the body region 142 is adjacent to the second surface of the source region 141, one sidewall of the body region 142 is adjacent to the sidewall of the trench grid structure 130, and the horizontal plane containing the second surface of the body region 142 passes through the trench grid structure 130.

[0103] Body region 142 is of the second conductivity type. The first conductivity type is the opposite of the second conductivity type; the first conductivity type is either P-type or N-type, and the second conductivity type is either P-type or N-type.

[0104] The first surface of the doped region 143 is adjacent to the second surface of the body region 142, the bottom of the trench gate structure 130, and part of the sidewall, such that the sidewall of the trench gate structure 130 is adjacent to the source region 141, the body region 142, and the doped region 143 in sequence from the first surface to the second surface; part of the second surface of the doped region 143 is adjacent to the first surface of the drift layer 120.

[0105] The doped region 143 is adjacent to at least a portion of the sidewalls of the trench gate structure 130 to form an effective channel region, thereby precisely controlling the current path under gate voltage drive, such as... Figure 4 and Figure 5a As shown.

[0106] The doped region 143 is of the first conductivity type. The doping concentration of the doped region 143 is greater than that of the drift layer 120, but less than that of the source region 141.

[0107] In some embodiments, the sidewall of the doped region 143 adjacent to the trench gate structure 130 forms the main control interface of the channel, and its doping concentration is greater than that of the drift layer 120, thereby reducing the JFET region resistance and improving the device switching speed while ensuring sufficient channel conduction capability.

[0108] Contact region 151 is located between two adjacent trench gate structures 130, specifically on the side of source region 141 away from trench gate structure 130. The sidewall of contact region 151 is adjacent to source region 141, body region 142 and doped region 143 sequentially along the first surface to the second surface, as shown below. Figure 4 and Figure 5b As shown, the first surface of the contact area 151 and the first surface of the source area 141 are located on the same horizontal plane.

[0109] Contact region 151 is of the second conductivity type, and its doping concentration is greater than that of the bulk region.

[0110] The shielding area 152 is located on the first surface of the drift layer 120, and the second surface of the contact area 151 is adjacent to a portion of the first surface of the shielding area 152.

[0111] A portion of the first surface and sidewalls of the shielding region 152 are also adjacent to the second surface of the doped region 143. Adjacent shielding regions 152 are separated by the doped region 143, as shown below. Figure 4 and Figure 5c As shown.

[0112] The shielding region 152 is of the second conductivity type, and its doping concentration is higher than that of the body region 142 and equal to that of the contact region 151.

[0113] Reference Appendix Figure 2iAlong the first direction, the contact area 151 has a first dimension D1, the shielding area 152 has a second dimension D2, the trench gate structure 130 has a third dimension D3, and the portion of the doped area 143 adjacent to the first surface of the drift layer 120 has a fourth dimension D4, which is also the dimension between two adjacent shielding areas 152.

[0114] In some embodiments, the second dimension D2 is larger than the first dimension D1, so that the shielding area 152 is as close as possible to the bottom corner of the trench gate structure 130, thereby more effectively dispersing the electric field concentration at the trench corner and improving the gate oxide reliability.

[0115] In some embodiments, the third dimension D3 is equal to the fourth dimension D4, such that the sidewall of the shielding region 152 and the sidewall of the trench gate structure 130 are located in the same vertical plane, so as to ensure that the concentrated electric field at the bottom corner of the trench gate structure 130 is directly and uniformly dispersed by the shielding region 152, thereby significantly suppressing the risk of local breakdown of the gate oxide layer.

[0116] In some embodiments, the fourth dimension D4 is smaller than the third dimension D3, so that the vertical plane containing the sidewall of the shielding region 152 is located inside the sidewall of the trench gate structure 130, further optimizing the symmetry and smoothness of the electric field distribution and reducing the probability of gate oxide interface defect generation.

[0117] In some embodiments, the shielding region 152 does not directly contact the sidewall of the trench gate structure 130, but by precisely controlling the dimensional relationship between D2 and D4, effective modulation of the electric field at the bottom corner can still be achieved. At the same time, channels can be formed on both sidewalls of the trench gate structure 130, which significantly increases the conduction current density and reduces the conduction resistance. Compared with other structures, it is more conducive to reducing the cell spacing and reducing manufacturing costs.

[0118] The interlayer dielectric layer 161 is located on the first surface of the trench gate structure 130, and it shields the first surface of the trench gate structure 130 and partially shields the first surface of the source region 141, such as Figure 4 As shown.

[0119] The material of the interlayer dielectric layer 161 is an oxide, such as silicon dioxide or silicon oxynitride.

[0120] The source metal layer 162 is located above the source region 141 and the contact region 142, forming an ohmic contact with the source region 141 and the contact region 142, and extends to cover the surface of the interlayer dielectric layer 161. As an insulating layer, the interlayer dielectric layer 161 effectively isolates the direct electrical connection between the source metal layer 162 and the trench gate structure 130, preventing the risk of short circuit.

[0121] The source metal layer 162 is made of aluminum, titanium, nickel or a stacked structure thereof, which balances low contact resistance and high temperature stability.

[0122] In some embodiments, the source metal layer 162 forms a low-resistance path with the shielding region 152 via the contact region 151, enabling the source potential to be coupled more uniformly to the bottom of the trench, further suppressing the electric field distortion at the gate edge. This structure significantly reduces the peak electric field at the bottom of the trench under reverse bias. Combined with the deep bottom P-well and direct connection design to the source pad, the bottom corner of the trench gate structure 130 can better withstand high electric field stress under reverse bias.

[0123] The drain metal layer 163 is located on the second surface S2 of the substrate 110 and forms an ohmic contact with the drift layer 120 and the substrate 110 to enable current conduction in the vertical direction of the device.

[0124] The drain metal layer 163 uses a highly conductive metal material, such as a copper / titanium / nickel / silver stack, to ensure low contact resistance and thermal stability.

[0125] As described above, these embodiments of the present application do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to make good use of the present application and modifications based on it. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A method of manufacturing a semiconductor device, wherein, include: A substrate is provided, and a drift layer of a first conductivity type is formed on the substrate; A first epitaxial layer of a first conductivity type is formed on the drift layer, and a portion of the first epitaxial layer is doped to form a shielding region of a second conductivity type. The undoped first epitaxial layer is the first doped region. A second epitaxial layer of a first conductivity type is formed on the first epitaxial layer, and a portion of the second epitaxial layer is doped to form a first contact region of a second conductivity type. The undoped second epitaxial layer is the second doped region. A third epitaxial layer of a second conductivity type is formed on the second epitaxial layer. A first region of the third epitaxial layer is doped to form a second contact region of the second conductivity type. A second region of the third epitaxial layer is doped to form a source region of the first conductivity type. The undoped third epitaxial layer is the body region. A trench gate structure, an interlayer dielectric layer, and a source metal layer are formed.

2. The manufacturing method according to claim 1, wherein, The steps for forming the second contact region, source region, and volume region include: A first mask layer is formed on the third epitaxial layer. No first mask layer is formed in the first region. Ion implantation is performed on the third epitaxial layer through the first mask layer to form a second contact region of the second conductivity type. Remove the first mask layer; A second mask layer is formed on the third epitaxial layer. No second mask layer is formed in the second region. Ion implantation is performed on the third epitaxial layer through the second mask layer to form a source region of a first conductivity type. The source region extends from the first surface of the third epitaxial layer to the second surface. The second surface of the source region is located in the third epitaxial layer. The region of the third epitaxial layer that is not ion implanted is the bulk region. Remove the second mask layer. Wherein, the first region of the third epitaxial layer corresponds to the first contact region, the second region corresponds to the source region, and the second contact region is connected to the first contact region.

3. The manufacturing method according to claim 2, wherein, The ion implantation energy for forming the second contact region is greater than the ion implantation energy for forming the source region.

4. The manufacturing method according to claim 1, wherein, A portion of the second epitaxial layer is doped using ion implantation to form a first contact region of a second conductivity type. A portion of the first epitaxial layer is doped using ion implantation to form a shielding region of the second conductivity type. The ion implantation energy for forming the shielding region is less than the energy for forming the first contact region.

5. The manufacturing method according to claim 1, wherein, The first region of the third epitaxial layer is doped using ion implantation to form a second contact region of the second conductivity type. The ion implantation energy forming the shielding region is less than the ion implantation energy forming the second contact region.

6. The manufacturing method according to any one of claims 1 to 5, wherein, Along the first direction, the width of the first contact area is smaller than the width of the shielding area.

7. The manufacturing method according to any one of claims 1 to 5, wherein, The doping concentration of the shielding region, the first contact region, and the second contact region is greater than the doping concentration of the body region.

8. A semiconductor device, wherein, It includes multiple cellular units, wherein the cellular units include: A trench gate structure, wherein the trench gate structure extends along a second direction; The source region of the first conductivity type is located on both sides of the trench gate structure and adjacent to the sidewall of the trench gate structure; The body region of the second conductivity type is located on both sides of the trench gate structure and adjacent to the sidewall of the trench gate structure, and the body region is located below the source region; The contact area of ​​the second conductivity type is located on both sides of the trench gate structure and is adjacent to the side of the source region and the body region away from the trench gate structure. The contact area extends along the depth direction of the trench gate structure below the bottom surface of the trench gate structure. The shielding area of ​​the second conductivity type is located below the contact areas on both sides; A doped region of the first conductivity type is located below the body region and in the region between the contact region and the shielding region, wherein the bottom surface of the doped region has the same depth as the bottom surface of the shielding region; Wherein, along the first direction, the shielding area extends beyond the contact area toward the sidewall of the trench grid structure, and its end is adjacent to the sidewall of the trench grid structure.

9. The semiconductor device according to claim 8, wherein, Along a third direction, the side of the end of the shielding area is coplanar with the sidewalls on both sides of the trench grid structure.

10. A semiconductor device, wherein, The semiconductor device is manufactured by the manufacturing method according to any one of claims 1 to 7.

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