A general radar array element level multi-target simulation method

Abstract

The application provides a general radar array element level multi-target simulation method. After target echo signals received by a radar array surface are converted by an analog-to-digital converter, the target echo signals are usually digital intermediate frequency echo signals. The application can simultaneously simulate digital intermediate frequency signals of multiple targets under the condition that a radar array front end or an external test environment is not provided, and the digital intermediate frequency signals are subjected to digital down-conversion processing to obtain baseband signals. The baseband signals are multiplied by a steering vector of the targets on different array elements to obtain radar array element level multi-target simulation signals. The number of targets, amplitudes, angles, distances, speeds and array element information can be parameterized and configured, the verification and development efficiency of subsequent algorithms is greatly improved, the research and development cost is reduced, and the application has the characteristics of strong universality, high flexibility, fast development efficiency and wide adaptation to scenarios.

Description

Technical Field

[0001] The embodiments of this application relate to the field of digital signal processing technology in radar signal processing, and particularly to a general radar array element-level multi-target simulation method. Background Technology

[0002] Radar array element-level multi-target simulation refers to the process of simulating radar operation in real-world scenarios. This involves processing the received digital intermediate frequency (IF) echo signals from multiple targets using digital down-conversion algorithms (including at least mixing, decimation, and filtering) to obtain baseband echo signals. The angle information of different targets is multiplied by the coordinate information of each array element to obtain a steering vector. Finally, the baseband echo signal is multiplied by the target steering vector to obtain the array element-level multi-target baseband echo signal. When the radar array front-end components are not yet fully prepared, technicians cannot verify the reliability and real-time performance of the back-end algorithms, resulting in significant waiting time costs. Targets that radar may detect in actual operation typically have different numbers, amplitudes, angles, distances, and velocities, and the array surface also has different sizes and coordinate positions. To verify radar monitoring performance under different information, different field test environments are usually required, which consumes a large amount of manpower, material resources, and financial resources. Therefore, radar array element-level multi-target simulation is particularly important when radar array front-end or field test environments are unavailable.

[0003] To verify the accuracy and precision of radar detection and identification performance, the system needs to precisely control the time difference of the target signal arriving at each array element. Therefore, array element-level multi-target simulation is generally implemented using FPGA. However, development using only FPGA faces challenges such as difficulty in upgrading and replacement, and long development cycles when target or array element information changes. Therefore, there is an urgent need in this field to propose a general radar array element-level multi-target simulation method to achieve parameterized configuration of target and array element information, thereby improving the flexibility of array element-level multi-target simulation, increasing the development efficiency of subsequent algorithms, shortening the debugging cycle, and saving human, material, and financial costs. Summary of the Invention

[0004] In view of this, the embodiments of this application propose a general radar array element-level multi-target simulation method, which can generate target echo information with different characteristics received under different array sizes in actual radar operation in the laboratory without the front end of the radar array or the field test environment. This does not affect the development and verification of subsequent algorithms, improves debugging efficiency, and reduces R&D costs.

[0005] To achieve the above objectives, embodiments of this application propose a general radar array element-level multi-target simulation method, implemented based on host computer software and FPGA. The method includes the following steps: S1, storing the baseband linear frequency modulated echo signals of multiple simulated targets in the FPGA's buffer area; multiplying the baseband linear frequency modulated echo signals of each target with the Doppler intermediate frequency parameters and target amplitude parameters sent by the host computer software to obtain the intermediate frequency echo signals of each target; then performing digital down-conversion processing, including mixing, decimation, and filtering, on the intermediate frequency echo signals of each target to obtain the baseband echo signals of each target; S2, receiving the array element coordinate information and the angle information of each target sent by the host computer software; generating complex weighting coefficients corresponding to each target; rearranging the data; and buffering the complex weighting coefficients corresponding to each target using a ping-pong method; S3, storing the baseband echo signals of each target... The system reads the data rate of a single array element based on the configured data rate. Simultaneously, based on the number of channels and the number of array elements within a single channel, it cyclically reads the complex weighting coefficients corresponding to each channel. The baseband echo signal of each target is multiplied by the complex weighting coefficients corresponding to each channel to obtain the array element-level baseband echo signals of multiple targets within each channel. In step S4, the data validity of the array element-level baseband echo signals of multiple targets within each channel is judged, and an alignment pulse is generated. The aligned array element-level baseband echo signals of all targets are then superimposed, and bit-width overflow protection is performed to obtain the final array element-level multi-target simulation result. The number of targets, amplitude, angle, range, and velocity can all be parameterized. The array surface, number of channels, number of array elements within a subarray, and data rate can also be parameterized. Repeating steps S1 to S4 completes the general radar array element-level multi-target simulation.

[0006] To achieve the above objectives, embodiments of this application also propose an electronic device, including a processor and a memory, wherein the memory stores instructions executable by the processor, and the processor is configured to execute the instructions such that the electronic device can implement a general radar array element-level multi-target simulation method as described above.

[0007] To achieve the above objectives, embodiments of this application also propose a computer-readable storage medium storing a computer program that, when executed by a processor, enables the implementation of a general radar array element-level multi-target simulation method as described above.

[0008] Optionally, the host computer software configures the signal center frequency as F, the mixing signal frequency as H, and the decimation rate as C; configures the number of targets as L, the amplitude as A, the angle as Q, the distance as R, and the velocity as V; configures the antenna array position coordinates as P, the number of input channels of the array as N, the number of array elements in a single input channel as M, the data rate transmitted by a single array element as T, and the number of data items as K. Then, the input data rate of a single input channel is T×M, and the FPGA's operating clock frequency U satisfies U>T×M.

[0009] Optionally, in S1, the FPGA obtains the multi-target manifold baseband linear frequency modulated echo signal matrix according to the number L of targets configured by the host computer software. The matrix is ​​arranged as follows: K sampling point data of target 1, K sampling point data of target 2, and so on up to K sampling point data of target L. The baseband linear frequency modulated echo signal of each target is stored in its corresponding dual-port RAM buffer. The time delay of each target relative to the radar center is calculated according to the distance R and velocity V of each target. The intermediate frequency Doppler signal is generated by the IP core of the DDS signal generator according to the signal center frequency F. When the PRF pulse arrives, the baseband linear frequency modulated echo signal is read from the corresponding dual-port RAM buffer according to the time delay of each target relative to the radar center. The signal is then multiplied by the intermediate frequency Doppler signal and the target amplitude A configured for each target to obtain the intermediate frequency echo signals of L targets relative to the radar.

[0010] Optionally, when performing digital down-conversion processing on the intermediate frequency (IF) echo signals of L targets, a mixing signal is first generated through the IP core of a DDS signal generator. The IF echo signals of the L targets are all mixed with the mixing signal to obtain the mixed IF echo signals. Then, the filter design tool built into MATLAB software is opened, and the filter response type, design method, filter order, window type, sampling frequency, and cutoff frequency are set to generate filter coefficients. These coefficients are then sent by the host computer software to the storage area inside the IP core of the FIR filter. The mixed IF echo signals of the L targets are convolved with their respective filter coefficients to obtain the filtered baseband echo signals of the L targets. Finally, based on the decimation rate C, the filtered baseband echo signals of the L targets are decimated using a counter to obtain the digital down-conversion processing result of the IF echo signals of the L targets. The number of sampling points for each target is K / C.

[0011] Optionally, in S2, to generate the complex weighted coefficients corresponding to each target, it is necessary to receive the array surface position coordinates P and the angle information Q of multiple targets sent by the host computer software. The number of array elements is M×N, each element has an array surface position coordinate P with components on the X-axis and Z-axis, and each target has an angle information Q with components on the X-axis and Z-axis. The angle component of each target on the X-axis is multiplied by the coordinate components of the M×N array elements on the X-axis, and the angle component of each target on the Z-axis is multiplied by the coordinate components of the M×N array elements on the Z-axis. The coordinate components are multiplied, the results are added together, and then complex exponentiation is performed to obtain the complex weighted coefficients of the entire array corresponding to L targets. The total length of the complex weighted coefficient data is M×N×L, and its arrangement is as follows: M×N complex weighted coefficients of target 1, M×N complex weighted coefficients of target 2, and so on up to M×N complex weighted coefficients of target L. The angle information Q of the target is updated with the PRF pulse. Therefore, the complex weighted coefficients of each target are cached in their respective dual-port RAM cache area in a ping-pong manner according to the PRF pulse.

[0012] Optionally, in S3, the baseband echo signal of each target is buffered via a FIFO. Based on the configured data rate T for downlink from a single array element, the baseband echo signal and complex weighting coefficients of each target are read out. The read-out baseband echo signal and corresponding complex weighting coefficients are then sent to a single-target array element-level simulation processing unit for processing. For target 1, the baseband echo signal of target 1 is copied N times and input into N channel modules. Each channel module reads out the M complex weighting coefficients corresponding to target 1 in a loop. The first channel reads out coefficients 1 to M of target 1. The second channel reads the M+1 to M×2 complex weighting coefficients of target 1, and so on, with the Nth channel reading the (N-1)×M+1 to M×N complex weighting coefficients of target 1. The number of times the corresponding M complex weighting coefficients in each channel are read out is the number of data points in the baseband echo signal. The data of each baseband echo sampling point of target 1 is multiplied by the complex weighting coefficients corresponding to the M array elements in the N channels to obtain the array element-level target simulation signal of target 1. This reading and calculation is repeated until the array element-level target simulation signal of L targets is obtained.

[0013] Optionally, in S4, different targets have different echo delays, which may cause the array element-level multi-target simulation results to have situations where the same array element may not be aligned at the same time. Based on this, the array element-level baseband echo signals of L targets in each channel are buffered, and an alignment read pulse is generated according to the array element position. The array element-level baseband echo signals of each target are read from the buffer and sent to the summing module. The array element-level baseband echo signals of L targets are superimposed and summed in each channel. When there are many targets, the superposition amplitude is also large, and bit width overflow protection is required. The final output method of the array element-level multi-target simulation results is as follows: there are N data channels, each channel contains M array elements, and each array element is formed by superimposing and summing the array element-level baseband echo signals corresponding to L targets. The number of sampling points of each array element is K / C.

[0014] Optionally, when target information changes, the host computer software configures the number of targets, amplitude, angle, distance, and velocity according to the latest target status; when signal waveform information changes, the host computer software regenerates the baseband linear frequency modulated echo signal and filter coefficients according to the time width and bandwidth, and configures the center frequency and decimation rate; when the radar array expands, the host computer software reconfigures the array position coordinates, the number of array input channels, and the number of array elements in each input channel; if it is necessary to adjust the data rate transmitted by a single array element, the host computer software configures the corresponding parameters according to the latest array element number and array data rate requirements, provided that the FPGA operating frequency is greater than the product of the number of array elements in a single channel and the data rate of the single array element.

[0015] This application proposes a general radar array element-level multi-target simulation method, which achieves the following improvements compared to traditional target simulation methods.

[0016] First, it eliminates hardware and field environment limitations, supporting early algorithm development and verification. This application does not rely on front-end radar array hardware or real field testing environments, and can complete multi-target echo signal simulation at the array element level in a laboratory environment. Even when front-end devices such as radar antennas and T / R components are not ready, the development, debugging, and performance verification of back-end radar signal processing and data processing algorithms can still be carried out normally, effectively connecting the R&D process and avoiding project delays.

[0017] Secondly, it achieves full-dimensional parameterization configuration, significantly improving versatility and flexibility. This application enables the configurability of two core parameters: target characteristics and radar array surface. Target parameters such as the number of targets, amplitude, angle, range, and velocity, as well as array parameters such as array size, number of channels, number of elements per channel, and data rate of the array data, can all be flexibly configured by the host computer software. It can quickly simulate various working scenarios with different target characteristics, different radar arrays, and different transmission rates, adapting to multiple radar models and various test conditions, and has a wide range of applications.

[0018] Third, it reduces R&D investment and saves manpower, material resources, and time costs. This application eliminates the need for repeated construction and modification of field test scenarios, as well as repeated modification of underlying logic code for different targets and arrays, significantly reducing the workload of field testing, hardware modification, and code iteration, effectively reducing manpower, material, and time costs, and shortening the overall development and debugging cycle.

[0019] Fourth, this application is based on FPGA implementation, which provides strong real-time signal processing. In this application, the core signal operation, data buffering, weighted operation, signal superposition and other processes are all implemented using FPGA hardware, which has strong parallel processing capabilities and low operation latency. It can meet the real-time requirements of radar system for phasor-level echo signal simulation. The timing, delay and phase characteristics of the simulated signal closely match the actual working state of the radar, and the simulation accuracy is high.

[0020] Fifth, the architecture is standardized, making expansion and maintenance convenient. The overall processing flow of this application is highly modular and universal. When facing requirements such as radar array expansion, array element layout adjustment, and target simulation scenario changes, only the corresponding parameters need to be modified on the host computer to complete the adaptation. There is no need to change the underlying hardware logic. The system upgrade, function expansion and subsequent maintenance are easy and highly reusable.

[0021] Sixth, it has signal fault tolerance protection and the simulation results are stable and reliable. This application adds a bit width overflow protection mechanism in the multi-target signal superposition stage, which can effectively avoid the data overflow problem caused by the superposition of multi-target signals, and ensure that the final output array element-level simulation signal is complete and accurate, which greatly improves the operational stability and output reliability of radar array element-level multi-target simulation. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies of this application will be briefly introduced below. Obviously, the following drawings are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The drawings described herein are only used to explain this application and are not intended to limit this application.

[0023] Figure 1 This is a flowchart of a general radar array element-level multi-target simulation method provided in one embodiment of this application; Figure 2 This is a detailed schematic diagram of a general radar array element-level multi-target simulation method provided in one embodiment of this application; Figure 3 This is a schematic diagram of echo delay for multiple targets provided in one embodiment of this application; Figure 4 This is a schematic diagram of the arrangement of the complex weighting coefficients provided in one embodiment of this application; Figure 5 This is a schematic diagram of single-target array element-level simulation processing provided in one embodiment of this application; Figure 6 This is a schematic diagram of the structure of an electronic device provided in another embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. Those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate better understanding. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this application. The following embodiments can be combined with and referenced by each other without contradiction.

[0025] Radar typically includes front-end components, digital signal processing, and data processing. When the front-end components are not yet fully developed, target echo signals cannot be acquired, hindering subsequent data signal processing and data processing. To address this technical problem, this application proposes a general radar array element-level multi-target simulation method. This method simulates target echo signals received by each array element of an outdoor radar antenna in a laboratory setting. Parameters are used to configure element and target information, resulting in a method that is highly versatile, flexible, and adaptable to a wide range of scenarios.

[0026] One embodiment of this application proposes a general radar array element-level multi-target simulation method, implemented based on host computer software and FPGA. The implementation details of the general radar array element-level multi-target simulation method proposed in this embodiment are described below. The following content is only for the convenience of understanding the relevant implementation details and is not necessary for implementing this solution.

[0027] The specific process of the general radar array element-level multi-target simulation method proposed in this embodiment can be described as follows: Figure 1 As shown, its visual details are as follows Figure 2 As shown, the method includes: S1. The baseband linear frequency modulated echo signals of multiple simulated targets are stored in the buffer area of ​​the FPGA. The baseband linear frequency modulated echo signals of each target are multiplied with the Doppler intermediate frequency parameters and target amplitude parameters sent by the host computer software to obtain the intermediate frequency echo signals of each target. Then, the intermediate frequency echo signals of each target are subjected to digital down-conversion processing including mixing, decimation and filtering to obtain the baseband echo signals of each target.

[0028] Specifically, the first step in performing multi-target simulation at the element level of a general radar array is to store the baseband linear frequency modulated (LFM) echo signals of multiple simulated targets in the buffer of the FPGA (FPGA processing platform). Then, the host computer software sends Doppler intermediate frequency (IF) parameters and target amplitude parameters to the FPGA. The FPGA multiplies the baseband LFM echo signals of each target with the Doppler IF parameters and target amplitude parameters sent by the host computer software to obtain the IF echo signal of each target. Next, the FPGA performs digital down-conversion processing on the IF echo signals of each target, including mixing, decimation, and filtering, to finally obtain the baseband echo signal of each target.

[0029] In one example, the host computer software configures the signal center frequency as F, the mixer signal frequency as H, and the decimation rate as C; configures the number of targets as L, the amplitude as A, the angle as Q, the distance as R, and the velocity as V; configures the antenna array position coordinates as P, the number of input channels of the array as N, the number of array elements in a single input channel as M, the data rate transmitted by a single array element as T, and the number of data items as K. Then, the input data rate of a single input channel is T×M, and the FPGA's operating clock frequency U satisfies U>T×M.

[0030] In one example, the FPGA obtains a multi-target manifold baseband linear frequency modulated echo signal matrix based on the number L of targets configured by the host computer software. This manifold array is arranged as follows: K sampling points for target 1, K sampling points for target 2, and so on, up to K sampling points for target L. The FPGA stores the baseband linear frequency modulated echo signal of each target into its corresponding dual-port RAM buffer. Then, based on the distance R and velocity V of each target, the time delay of each target relative to the radar center is calculated. Based on the signal center frequency F, an intermediate frequency Doppler signal is generated by the IP core of the DDS signal generator. When the PRF pulse arrives, the baseband linear frequency modulated echo signal (e.g., ...) is read from its corresponding dual-port RAM buffer based on the time delay of each target relative to the radar center. Figure 3 As shown), and multiplied by the intermediate frequency Doppler signal and the target amplitude A of each target configuration, to obtain L intermediate frequency echo signals of the targets relative to the radar.

[0031] In one example, when performing digital down-conversion processing on the intermediate frequency (IF) echo signals of L targets, a mixing signal is first generated using the IP core of a DDS signal generator. The IF echo signals of all L targets are then mixed with this mixing signal (the input mixing frequency H is also configured by the host computer software), resulting in the mixed IF echo signals. Next, the filter design tool built into the MATLAB software on the host computer is used to set the filter response type, design method, filter order, window type, sampling frequency, and cutoff frequency to generate filter coefficients. These coefficients are then sent from the host computer software to the storage area within the IP core of the FIR filter. The mixed IF echo signals of the L targets are convolved with their respective filter coefficients to obtain the filtered baseband echo signals of the L targets. Finally, based on the decimation rate C, a counter is used to decimate the filtered baseband echo signals of the L targets, resulting in the digital down-conversion processing result of the IF echo signals of the L targets. The number of sampling points for each target is K / C.

[0032] S2 receives the array element coordinate information and the angle information of each target from the host computer software, generates the complex weighted coefficients corresponding to each target, rearranges the data, and caches the complex weighted coefficients corresponding to each target in a ping-pong manner.

[0033] Specifically, after obtaining the baseband echo signals of each target, it is also necessary to receive the array element coordinate information and the angle information of each target sent by the host computer software, generate the complex weighting coefficients corresponding to each target, rearrange the data, and cache the complex weighting coefficients corresponding to each target in a ping-pong manner.

[0034] In S2, to generate the complex weighted coefficients for each target, the FPGA needs to receive the array surface position coordinates P and the angle information Q of multiple targets from the host computer software. The number of array elements is M×N, and each element has an X-axis component and a Z-axis component for its array surface position coordinate P. Each target (L targets) has an X-axis component and a Z-axis component for its angle information Q. The X-axis angle component of each target is multiplied by the X-axis coordinate components of the M×N array elements, and the Z-axis angle component of each target is multiplied by the Z-axis coordinate components of the M×N array elements. The results are added together and then subjected to complex exponentiation to obtain the complex weighted coefficients for the entire array surface corresponding to the L targets. The total data length of the complex weighted coefficients is M×N×L, and their arrangement (e.g., ...) Figure 4 As shown, the M×N complex weighted coefficients are for target 1, target 2, and so on, up to target L. The angle information Q of the target is updated with the PRF pulse, so the complex weighted coefficients of each target need to be cached in their respective dual-port RAM cache area in a ping-pong manner according to the PRF pulse.

[0035] S3 reads out the baseband echo signal of each target according to the data rate of the configured single array element. At the same time, according to the number of channels and the number of array elements in a single channel, the complex weighting coefficients corresponding to each channel are read out cyclically. The baseband echo signal of each target is multiplied by the complex weighting coefficients corresponding to each channel to obtain the array element-level baseband echo signal of multiple targets in each channel.

[0036] Specifically, after generating and caching the complex weighting coefficients, the FPGA needs to read out the baseband echo signal of each target according to the data rate of the configured individual array element. At the same time, based on the number of channels and the number of array elements in a single channel, the complex weighting coefficients corresponding to each channel are read out cyclically. The baseband echo signal of each target is multiplied by the complex weighting coefficients corresponding to each channel to obtain the array element-level baseband echo signal of multiple targets in each channel.

[0037] In S3, the baseband echo signal of each target is buffered through FIFO. The baseband echo signal and complex weighting coefficients of each target are read out according to the configured data rate T of the downlink of a single array element until all the baseband echo signals output by each digital downconversion process are read out. The read baseband echo signals and corresponding complex weighting coefficients are sent to the single target array element-level analog processing unit for formation.

[0038] Taking target 1 as an example, the baseband echo signal of target 1 is copied N times and input into N channel modules respectively. Each channel module reads out the M complex weighting coefficients corresponding to target 1 in a loop. The first channel reads out 1 to M complex weighting coefficients of target 1, the second channel reads out M+1 to M×2 complex weighting coefficients of target 1, and so on. The Nth channel reads out (N-1)×M+1 to M×N complex weighting coefficients of target 1. The number of times the M complex weighting coefficients corresponding to each channel are read out in a loop is the number of data in the baseband echo signal.

[0039] like Figure 5 As shown, by multiplying the data of each baseband echo sampling point of target 1 with the complex weighting coefficients corresponding to the M array elements in the N channels, the array element-level target simulation signal of target 1 can be obtained. The corresponding array element-level target simulation signals generated by L targets are obtained by repeating the reading and calculation.

[0040] It should be noted that the input data rate of a single input channel is T×M, and the operating clock frequency U of the FPGA processing platform must be selected to satisfy: U>T×M.

[0041] S4 performs data validity judgment on the array element-level baseband echo signals of multiple targets in each channel and generates alignment pulses. The array element-level baseband echo signals of all aligned targets are superimposed on the data, and bit width overflow protection is performed to obtain the final array element-level multi-target simulation results.

[0042] Specifically, after obtaining the array element-level baseband echo signals of multiple targets in each channel, the FPGA needs to determine the data validity of the array element-level baseband echo signals of multiple targets in each channel and generate an alignment pulse. The array element-level baseband echo signals of all targets after alignment are superimposed, and bit width overflow protection is performed to obtain the final array element-level multi-target simulation results.

[0043] In S4, the different echo delays between targets lead to misalignment of the same array element at the same time in the multi-target simulation results. Therefore, it is necessary to align the output results of the corresponding channels in each target before performing superposition and summation. In this embodiment, the FPGA buffers the array element-level baseband echo signals of L targets in each channel, generates an alignment read pulse based on the array element position, reads the array element-level baseband echo signals of each target from the buffer, and sends them to the summation module. The array element-level baseband echo signals of L targets are superimposed and summed in each channel. When the number of targets is large, the superposition amplitude is also large, so bit width overflow protection is required. The final output of the array element-level multi-target simulation results is as follows: there are N data channels, each channel contains M array elements, and each array element is formed by superimposing and summing the array element-level baseband echo signals corresponding to L targets. The number of sampling points for each array element is K / C.

[0044] It should be noted that the number of targets, amplitude, angle, distance, and velocity can all be parameterized. The array surface, number of channels, number of array elements in subarrays, and data rate can also be parameterized. By repeating S1 to S4 above, a general radar array element-level multi-target simulation can be completed.

[0045] When the target information changes, the host computer software configures the number of targets, amplitude, angle, distance, and speed according to the latest target status.

[0046] When the signal waveform information changes, the host computer software regenerates the baseband linear frequency modulated echo signal and filter coefficients based on the time width and bandwidth, and configures the center frequency and decimation rate.

[0047] When the radar array is expanded or changed, the array position coordinates, the number of array input channels, and the number of array elements in each input channel are reconfigured through the host computer software.

[0048] If it is necessary to adjust the data rate of a single array element, then, provided that the FPGA's operating frequency is greater than the product of the number of single-channel array elements and the data rate of a single array element, the corresponding parameters can be configured through the host computer software according to the latest array array's single-channel array element number and data rate requirements.

[0049] This embodiment proposes a general radar array element-level multi-target simulation method, which achieves the following improvements compared to traditional target simulation methods.

[0050] First, it eliminates hardware and field environment limitations, supporting early algorithm development and verification. This embodiment does not rely on front-end radar array hardware or real field testing environments, and can complete radar array element-level multi-target echo signal simulation in a laboratory environment. Even when front-end devices such as radar antennas and T / R components are not ready, the development, debugging, and performance verification of back-end radar signal processing and data processing algorithms can still be carried out normally, effectively connecting the R&D process and avoiding project delays.

[0051] Secondly, it achieves full-dimensional parameterization configuration, enhancing versatility and flexibility. This embodiment enables the configurability of two core parameters: target characteristics and radar array surface. Target parameters such as the number of targets, amplitude, angle, range, and velocity, as well as array parameters such as array size, number of channels, number of elements per channel, and data rate of the array data, can all be flexibly configured by the host computer software. It can quickly simulate various working scenarios with different target characteristics, different radar arrays, and different transmission rates, adapting to multiple radar models and various test conditions, and has a wide range of applications.

[0052] Third, it reduces R&D investment and saves manpower, material resources, and time costs. This embodiment eliminates the need for repeated construction and modification of field test scenarios, as well as repeated modification of underlying logic code for different targets and arrays. This significantly reduces the workload of field testing, hardware modification, and code iteration, effectively reducing manpower, material, and time costs, and shortening the overall development and debugging cycle.

[0053] Fourth, this embodiment is implemented based on FPGA, which provides strong real-time signal processing. In this embodiment, the core signal calculation, data buffering, weighted calculation, signal superposition and other processes are all implemented using FPGA hardware, which has strong parallel processing capabilities and low computational latency. It can meet the real-time requirements of radar system for array-level echo signal simulation. The timing, delay and phase characteristics of the simulated signal closely match the actual working state of the radar, and the simulation accuracy is high.

[0054] Fifth, it achieves standardized architecture, making expansion and maintenance more convenient. The overall processing flow of this embodiment is highly modular and universal. When facing requirements such as radar array expansion, array element layout adjustment, and target simulation scenario change, only the corresponding parameters need to be modified in the host computer software to complete the adaptation. There is no need to change the underlying hardware logic. The system upgrade, function expansion and subsequent maintenance are easy and highly reusable.

[0055] Sixth, it has signal fault tolerance protection and the simulation results are stable and reliable. This embodiment adds a bit width overflow protection mechanism in the multi-target signal superposition stage, which can effectively avoid the data overflow problem caused by the superposition of multi-target signals, and ensure that the final output array element-level simulation signal is complete and accurate, which greatly improves the operational stability and output reliability of radar array element-level multi-target simulation.

[0056] The steps described above are merely for clarity in describing the technical solution. In actual implementation, they can be combined into one step, or certain steps can be broken down into multiple steps, as long as they involve the same logical relationship, they are all within the scope of protection of this application. Any insignificant modifications or designs added to the algorithm or process, as long as they do not change the core of the algorithm or process, are also within the scope of protection of this application.

[0057] Another embodiment of this application proposes an electronic device, such as Figure 6 As shown, it includes a processor H1 and a memory H2. The memory H2 stores instructions that the processor H1 can execute. When the processor H1 is configured to execute the instructions, the electronic device can implement a general radar array element-level multi-target simulation method as described in the above method embodiment.

[0058] The memory and processor are connected via a bus, which includes any number of interconnecting buses and bridges. The bus can connect various circuits of one or more processors and memories, as well as other circuits such as peripherals, voltage regulators, and power management circuits—all well-known in the art and therefore not described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single component or multiple components, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor is transmitted over the wireless medium via an antenna, which also receives and transmits data to the processor.

[0059] The processor manages the bus and handles general processing, providing various functions, including but not limited to timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory, on the other hand, is used to store data used by the processor during operation.

[0060] Another embodiment of this application proposes a computer-readable storage medium storing a computer program that, when executed by a processor, can implement a general radar array element-level multi-target simulation method as described in the above method embodiments.

[0061] That is, those skilled in the art will understand that all or part of the steps in the above method embodiments can be implemented by a program instructing related hardware. The program is stored in a storage medium and includes several instructions to cause a device (such as a microcontroller, chip, etc.) or processor to execute all or part of the steps of the method described in the method embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.

[0062] It will be understood by those skilled in the art that the above embodiments are specific implementations of this application, and various changes in form and detail can be made in practical applications without departing from the spirit and scope of this application. For those skilled in the art, several improvements and modifications can be made without departing from the principles of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.

Claims

1. A general radar array element-level multi-target simulation method, implemented based on host computer software and FPGA, characterized in that, The method includes: S1. Store the baseband linear frequency modulated echo signals of multiple simulated targets in the FPGA's buffer area. Multiply the baseband linear frequency modulated echo signals of each target with the Doppler intermediate frequency parameters and target amplitude parameters sent by the host computer software to obtain the intermediate frequency echo signals of each target. Then, perform digital down-conversion processing, including mixing, decimation, and filtering, on the intermediate frequency echo signals of each target to obtain the baseband echo signals of each target. S2 receives the array element coordinate information and the angle information of each target sent by the host computer software, generates the complex weighted coefficients corresponding to each target, rearranges the data, and caches the complex weighted coefficients corresponding to each target in a ping-pong manner. S3, read out the baseband echo signal of each target according to the data rate of the configured single array element, and read out the complex weighting coefficients corresponding to each channel in a loop according to the number of channels and the number of array elements in a single channel. Multiply the baseband echo signal of each target with the complex weighting coefficients corresponding to each channel to obtain the array element-level baseband echo signal of multiple targets in each channel. S4, performs data validity judgment on the array element-level baseband echo signals of multiple targets in each channel, generates alignment pulses, superimposes the array element-level baseband echo signals of all aligned targets, and performs bit width overflow protection to obtain the final array element-level multi-target simulation results. The number of targets, amplitude, angle, distance, and velocity can all be parameterized. The array surface, number of channels, number of array elements in subarrays, and data rate can also be parameterized. By repeating S1 to S4, multi-target simulation at the general radar array element level can be completed.

2. The general radar array element-level multi-target simulation method as described in claim 1, characterized in that, The host computer software configures the signal center frequency as F, the mixer signal frequency as H, and the decimation rate as C; it configures the number of targets as L, the amplitude as A, the angle as Q, the distance as R, and the velocity as V; it configures the antenna array position coordinates as P, the number of input channels of the array as N, the number of array elements in a single input channel as M, the data rate transmitted by a single array element as T, and the number of data items as K. Then, the input data rate of a single input channel is T×M, and the FPGA's operating clock frequency U satisfies U>T×M.

3. The general radar array element-level multi-target simulation method as described in claim 2, characterized in that, In S1, the FPGA obtains the multi-target manifold baseband linear frequency modulated echo signal matrix according to the number of targets L configured by the host computer software. The arrangement is as follows: K sampling point data of target 1, K sampling point data of target 2, up to K sampling point data of target L. The baseband linear frequency modulated echo signal of each target is stored in its corresponding dual-port RAM buffer area. Based on the distance R and velocity V of each target, the time delay of each target relative to the radar center is calculated, and an intermediate frequency Doppler signal is generated by the IP core of the DDS signal generator according to the signal center frequency F. When the PRF pulse arrives, based on the time delay of each target relative to the radar center, the baseband linear frequency modulated echo signal is read from the corresponding dual-port RAM buffer interval, and multiplied with the intermediate frequency Doppler signal and the target amplitude A configured for each target to obtain L intermediate frequency echo signals of the target relative to the radar.

4. The general radar array element-level multi-target simulation method as described in claim 3, characterized in that, When performing digital down-conversion processing on the intermediate frequency (IF) echo signals of L targets, a mixing signal is first generated by the IP core of a DDS signal generator. The IF echo signals of the L targets are all mixed with this mixing signal to obtain the mixed IF echo signals. Then, the filter design tool built into MATLAB is opened, and the filter response type, design method, filter order, window type, sampling frequency, and cutoff frequency are set to generate filter coefficients. These coefficients are then sent from the host computer software to the storage area inside the IP core of the FIR filter. The mixed IF echo signals of the L targets are convolved with their respective filter coefficients to obtain the filtered baseband echo signals of the L targets. Finally, based on the decimation rate C, a counter is used to decimate the filtered baseband echo signals of the L targets to obtain the digital down-conversion processing result of the IF echo signals of the L targets. The number of sampling points for each target is K / C.

5. The general radar array element-level multi-target simulation method as described in claim 4, characterized in that, In S2, to generate the complex weighted coefficients for each target, it is necessary to receive the array surface position coordinates P and the angle information Q of multiple targets from the host computer software. The number of array elements is M×N. Each array element has an array surface position coordinate P with components on the X-axis and Z-axis. Each target has an angle information Q with components on the X-axis and Z-axis. The X-axis angle component of each target is multiplied by the X-axis coordinate components of the M×N array elements, and the Z-axis angle component of each target is multiplied by the X-axis coordinate components of the M×N array elements. The standard components are multiplied, and the results are added together and then subjected to complex exponentiation to obtain the complex weighted coefficients of the entire array corresponding to L targets. The total length of the complex weighted coefficient data is M×N×L, and its arrangement is as follows: M×N complex weighted coefficients of target 1, M×N complex weighted coefficients of target 2, and so on up to M×N complex weighted coefficients of target L. The angle information Q of the target is updated with the PRF pulse. Therefore, the complex weighted coefficients of each target are cached in their respective dual-port RAM cache area in a ping-pong manner according to the PRF pulse.

6. The general radar array element-level multi-target simulation method as described in claim 5, characterized in that, In S3, the baseband echo signal of each target is buffered by FIFO. According to the configured data rate T of the downlink of a single array element, the baseband echo signal and the complex weighting coefficient of each target are read out. The read baseband echo signal and the corresponding complex weighting coefficient are sent to the single target array element-level simulation processing unit for formation. For target 1, the baseband echo signal of target 1 is copied N times and input into N channel modules respectively. Each channel module reads out the M complex weighting coefficients corresponding to target 1 in a loop. The first channel reads out 1 to M complex weighting coefficients of target 1, the second channel reads out M+1 to M×2 complex weighting coefficients of target 1, and so on. The Nth channel reads out (N-1)×M+1 to M×N complex weighting coefficients of target 1. The number of times the M complex weighting coefficients corresponding to each channel are read out in a loop is the number of data in the baseband echo signal. Each baseband echo sampling point data of target 1 is multiplied by the complex weighting coefficients corresponding to M array elements in N channels to obtain the array element-level target simulation signal of target 1. This process is repeated until the array element-level target simulation signals of L targets are obtained.

7. The general radar array element-level multi-target simulation method as described in claim 6, characterized in that, In S4, different targets have different echo delays, which may cause the array element-level multi-target simulation results to have misalignment at the same array element time. Based on this, the array element-level baseband echo signals of L targets in each channel are buffered. An alignment read pulse is generated according to the array element position to read the array element-level baseband echo signals of each target from the buffer and send them to the summing module. The array element-level baseband echo signals of L targets are superimposed and summed in each channel. When there are many targets, the superposition amplitude is also large, so bit width overflow protection is required. The final output method of the array element-level multi-target simulation results is as follows: there are N data channels, each channel contains M array elements, and each array element is formed by superimposing and summing the array element-level baseband echo signals corresponding to L targets. The number of sampling points of each array element is K / C.

8. The general radar array element-level multi-target simulation method as described in claim 7, characterized in that, When the target information changes, the host computer software configures the number of targets, amplitude, angle, distance, and speed according to the latest target status. When the signal waveform information changes, the host computer software regenerates the baseband linear frequency modulation echo signal and filter coefficients according to the time width and bandwidth, and configures the center frequency and decimation rate. When the radar array is expanded or changed, the array position coordinates, the number of array input channels, and the number of array elements in each input channel are reconfigured through the host computer software. If it is necessary to adjust the data rate of a single array element, then, provided that the FPGA's operating frequency is greater than the product of the number of single-channel array elements and the data rate of a single array element, the corresponding parameters can be configured through the host computer software according to the latest array array's single-channel array element number and data rate requirements.

9. An electronic device, characterized in that, include: The processor and memory, wherein the memory stores instructions that the processor can execute, and the processor is configured to, when executing the instructions, enable the electronic device to implement a general radar array element-level multi-target simulation method as described in any one of claims 1 to 8.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it can implement a general radar array element-level multi-target simulation method as described in any one of claims 1 to 8.

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