Multi-order variable bandwidth high-pass filter and design method thereof

Abstract

The application provides a multi-gear variable bandwidth high-pass filter and a design method thereof. The filter comprises a gear control module, a delay module, a shift operation module and an addition and subtraction operation module. Through coefficient customization design, the multiplication operation of the filter of the first-order high-pass IIR is converted into shift and addition and subtraction operation, and the multiplier is completely removed. When FPGA / ASIC is implemented, the logic unit occupation amount is significantly reduced, the power consumption of the embedded device is greatly reduced, the resource-limited scene is adapted, and the resource consumption is extremely optimized.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing technology, and in particular to a multi-level variable bandwidth high-pass filter and its design method. Background Technology

[0002] In digital signal processing, high-pass filters are core modules for eliminating low-frequency noise and extracting high-frequency effective signals, and are widely used in industrial sensor signal preprocessing, IoT device data acquisition, audio signal enhancement, and other scenarios. Among them, IIR (Infinite Impulse Response) filters are the preferred solution for resource-constrained scenarios due to their low order and small computational cost.

[0003] In the existing technology, variable bandwidth IIR high-pass filters have the following drawbacks:

[0004] 1. High hardware resource consumption: The coefficients of traditional IIR filters are mostly floating-point numbers or integers that are not powers of 2. Hardware implementation requires multipliers to perform multiplication operations between the coefficients and the signal. Multipliers consume valuable hardware resources in FPGA / ASIC and require multiple clock cycles in embedded microprocessors, occupying a large number of logic units and consuming a lot of power, which cannot meet the design requirements of low power consumption and small area;

[0005] 2. The contradiction between bandwidth adjustment flexibility and resource consumption: To achieve multi-level bandwidth adjustment, multiple sets of filter coefficients need to be pre-stored, and the multiplication operation of each set of coefficients requires independent hardware support, which leads to a significant increase in hardware complexity as the number of levels increases.

[0006] 3. Stability and implementation complexity are difficult to balance: Some simplified designs reduce hardware costs by approximating coefficients, but this can easily cause the filter poles to shift out of the unit circle, destroying stability, or causing the cutoff frequency to deviate from the target value, resulting in a decrease in filtering performance.

[0007] Therefore, there is an urgent need for an IIR high-pass filter design scheme that requires no multiplier, consumes very little resources, has multiple adjustable bandwidths, and is stable and reliable. Summary of the Invention

[0008] The purpose of this invention is to provide a multi-level variable bandwidth high-pass filter and its design method, so as to solve the problems of high hardware resource consumption, contradiction between bandwidth adjustment flexibility and resource occupation, and difficulty in balancing stability and implementation complexity in the existing IIR high-pass filter.

[0009] To address the aforementioned technical problems, based on one aspect of the present invention, the present invention provides a multi-level variable bandwidth high-pass filter, comprising:

[0010] The gear control module is used to configure the gear parameter N in positive integer form.

[0011] The delay module is used to delay the input signal x(n) by one sampling period and output it as the historical input signal x(n-1), and to delay the output signal y(n) by one sampling period and output it as the historical output signal y(n-1).

[0012] The shift operation module is used to right-shift the input signal x(n) by K bits to obtain the shift result of x(n), right-shift the historical input signal x(n-1) by K bits to obtain the shift result of x(n-1), and right-shift the historical output signal y(n-1) by N bits to obtain the shift result of y(n-1), where K is a positive integer greater than or equal to N;

[0013] The addition and subtraction module performs addition and subtraction operations on the input signals x(n), the shift results of x(n), the historical input signals x(n-1), the shift results of x(n-1), the historical output signals y(n-1), and the shift results of y(n-1) to obtain the time-domain difference equation of the filter.

[0014] Optionally, the time-domain difference equation of the filter is:

[0015]

[0016] Where (x(n)>>>K) is the shift result of x(n), (x(n-1)>>>K) is the shift result of x(n-1), and (y(n-1)>>>N) is the shift result of y(n-1).

[0017] Optional, 1≤N≤W-1, where W is the data bit width.

[0018] Optional, K=N+1.

[0019] Optionally, the multi-level variable bandwidth high-pass filter further includes a coefficient configuration unit, which is used to configure the denominator coefficient a of the filter according to the level parameter N and the numerator coefficient b of the filter according to K.

[0020] Optional, ; .

[0021] Optionally, the digital cutoff angular frequency of the filter is negatively correlated with the range parameter N.

[0022] Based on another aspect of the present invention, the present invention also provides a design method for a multi-level variable bandwidth high-pass filter, comprising:

[0023] Configure the gear parameter N in positive integer form;

[0024] The input signal x(n) is delayed by one sampling period and output as the historical input signal x(n-1), and the output signal y(n) is delayed by one sampling period and output as the historical output signal y(n-1).

[0025] The input signal x(n) is shifted right by K bits to obtain the shifted result of x(n), the historical input signal x(n-1) is shifted right by K bits to obtain the shifted result of x(n-1), and the historical output signal y(n-1) is shifted right by N bits to obtain the shifted result of y(n-1), where K is a positive integer greater than or equal to N;

[0026] The time-domain difference equation of the filter is obtained by performing addition and subtraction operations on the shift results of input signals x(n), x(n), the shift results of historical input signals x(n-1), x(n-1), the shift results of historical output signals y(n-1) and y(n-1).

[0027] Optionally, the design method further includes:

[0028] Configure the denominator coefficient a of the filter based on the gear parameter N, and configure the numerator coefficient b of the filter based on K.

[0029] The multi-bandwidth high-pass filter described above has at least the following technical advantages:

[0030] 1. Extreme optimization of resource consumption: Through customized coefficient design, the multiplication operation of the first-order high-pass IIR filter is transformed into shift and addition / subtraction operations, completely eliminating the multiplier. The logic unit occupancy is significantly reduced when implementing FPGA / ASIC, the power consumption of embedded devices is greatly reduced, and it is suitable for resource-constrained scenarios.

[0031] 2. Flexible and adjustable bandwidth across multiple levels: adjustable via single-level parameters. By linking the digital cutoff angular frequency with the filter coefficients, multiple bandwidth adjustments can be achieved without the need to pre-store multiple sets of complex coefficients, and the hardware control logic is simple.

[0032] 3. Stable and reliable: Through rigorous mathematical proof, the poles of all bandwidth levels are located inside the unit circle, ensuring the unconditional stability of the filter.

[0033] 4. Filtering performance meets standards: The amplitude-frequency response of each bandwidth range meets the characteristics of a high-pass filter, with zero-point... It effectively suppresses DC components and has a significant filtering effect.

[0034] 5. High scalability: the gear parameters The range of values ​​can be flexibly expanded according to the system data bit width, and it is applicable to everything from low-cost 8-bit / 16-bit microcontrollers to high-precision 32-bit processors, providing a high degree of design flexibility.

[0035] It should be noted that since the design method of the multi-level variable bandwidth high-pass filter and the multi-level variable bandwidth high-pass filter are based on the same inventive concept and have the same or similar specific technical features, they also have the same technical effects, so they will not be repeated here. Attached Figure Description

[0036] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0037] Figure 1 This is a schematic diagram of a first-order high-pass IIR filter in the prior art;

[0038] Figure 2 This is a schematic diagram of a multi-stage variable bandwidth high-pass filter according to an embodiment of the present invention;

[0039] Figure 3 This is the pole distribution diagram of the filter. Detailed Implementation

[0040] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0041] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature. “One end” and “the other end,” as well as “proximal end” and “distal end,” generally refer to two corresponding parts, including not only endpoints. The terms “installed,” “connected,” and “joined” should be interpreted broadly, for example, as a fixed connection, a detachable connection, or an integral part; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium; or a connection within two elements or an interaction between two elements. Furthermore, as used in this invention, the phrase "one element is disposed on another element" generally only indicates that there is a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of the other element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0042] Figure 1 This is a schematic diagram of a first-order high-pass IIR filter in the prior art. (See also...) Figure 1 The filter includes two delay units D, three multipliers, subtractors, adders, parameter selection module A, and parameter selection module B. One delay unit D delays the input signal x(n) by one sampling period and outputs the historical input signal x(n-1). The other delay unit D delays the output signal y(n) by one sampling period and outputs the historical output signal y(n-1). Parameter selection module B configures the coefficients b of x(n) and x(n-1), and parameter selection module A configures the coefficients a of y(n-1). The configuration of the general time-domain difference equation for the first-order high-pass IIR is achieved through the multipliers, adders, and subtractors.

[0043] Specifically, as will be understood by those skilled in the art, the z-domain transfer function of a first-order high-pass IIR filter is typically:

[0044]

[0045] Among them, molecules Corresponding to 1 zero point (Used to suppress DC signals), denominator Corresponding to 1 pole .

[0046] The general time-domain difference equation for a first-order high-pass IIR is:

[0047]

[0048] in, The current input signal, To delay the historical input signal by one sampling period, This is the current output signal. This is the historical output signal delayed by one sampling period.

[0049] The existing design method of configuring filters using three multipliers consumes a lot of hardware resources, there is a contradiction between bandwidth adjustment flexibility and resource consumption, and it is difficult to balance stability and implementation complexity.

[0050] The purpose of this invention is to overcome the shortcomings of existing variable bandwidth IIR high-pass filters, such as high hardware resource consumption and complex implementation, and to provide a multi-level variable bandwidth IIR high-pass filter based on "shift instead of multiplication", which minimizes hardware resource consumption and power consumption while ensuring filtering performance and stability.

[0051] Figure 2 This is a schematic diagram of a multi-stage variable bandwidth high-pass filter according to an embodiment of the present invention. (See attached diagram.) Figure 2The multi-level variable bandwidth high-pass filter in this embodiment includes a level control module 10, a delay module, a shift operation module, and an addition / subtraction operation module. The level control module 10 is used to configure the level parameter N in positive integer form. The delay module is used to delay the input signal x(n) by one sampling period and output it as the historical input signal x(n-1), and to delay the output signal y(n) by one sampling period and output it as the historical output signal y(n-1). Specifically, the delay module includes a first delay unit 21 and a second delay unit 22. The first delay unit 21 delays the input signal x(n) by one sampling period and outputs it as the historical input signal x(n-1), and the second delay unit 22 delays the output signal y(n) by one sampling period and outputs it as the historical output signal y(n-1). The shift operation module is used to right-shift the input signal x(n) by K bits to obtain the shifted result of x(n), right-shift the historical input signal x(n-1) by K bits to obtain the shifted result of x(n-1), and right-shift the historical output signal y(n-1) by N bits to obtain the shifted result of y(n-1), where K is a positive integer greater than or equal to N. Specifically, the shift operation module includes a first shift operation unit 31, a second shift operation unit 32, and a third shift operation unit 33. The first shift operation unit 31 right-shifts the input signal x(n) by K bits to obtain the shifted result of x(n), the second shift operation unit 32 right-shifts the historical input signal x(n-1) by K bits to obtain the shifted result of x(n-1), and the third shift operation unit 33 right-shifts the historical output signal y(n-1) by N bits to obtain the shifted result of y(n-1). The addition and subtraction module includes an adder 42 and a subtractor 41, which perform addition and subtraction operations on the input signals x(n), the shift results of x(n), the historical input signals x(n-1), the shift results of x(n-1), the historical output signals y(n-1) and the shift results of y(n-1) to obtain the time-domain difference equation of the filter.

[0052] Furthermore, 1 ≤ N ≤ W-1, where W is the data bit width, to ensure... The accuracy of the calculation.

[0053] Furthermore, the multi-level variable bandwidth high-pass filter also includes a coefficient configuration unit, which is used to configure the denominator coefficient a of the filter according to the level parameter N and the numerator coefficient b of the filter according to K.

[0054] in, ; K is a positive integer based on N, where K is greater than or equal to N, for example, K = N + 1. The configuration of parameters K and N here mainly considers the following two points:

[0055] 1. Simplified computation. This parameter form is naturally adapted to binary shift operations, which can transform multiplication into simple shift and addition / subtraction operations;

[0056] 2. Stability guarantee. For example... Figure 3 The diagram shows the pole distribution of the filter. It displays the filter poles at all bandwidth levels (for all values ​​of N). .because Therefore The poles are strictly located within the unit circle in the z-plane, ensuring that the filter can operate stably at all bandwidth levels.

[0057] In this embodiment, the digital cutoff angular frequency of the filter is negatively correlated with the range parameter N. The digital cutoff angular frequency of the filter... From coefficients and A joint decision. Because... and All by The only certainty is that, therefore, through adjustment This allows for continuous adjustment. . The smaller the value, The larger; The larger the value, The smaller. Set different The value can be adapted to different bandwidth requirements.

[0058] In the aforementioned general time-domain difference equation for a first-order high-pass IIR, based on the coefficients... and In this special form, multiplication in difference equations can be completely transformed into "shifting + addition / subtraction" operations, specifically:

[0059] 1) ;

[0060] 2) ;

[0061] 3) .

[0062] Where (x(n)>>>K) is the shift result of x(n), (x(n-1)>>>K) is the shift result of x(n-1), and (y(n-1)>>>N) is the shift result of y(n-1).

[0063] Therefore, the time-domain difference equation of the filter of this invention is:

[0064]

[0065] Therefore, the filter of the present invention does not require any multipliers in hardware implementation, only a delay unit (storage). , It includes a shift operation module, an adder, and a subtractor, with extremely low resource consumption. The gear control module can select multiple bandwidths through a single parameter N.

[0066] Compared with the prior art, the present invention has the following beneficial effects:

[0067] Extreme optimization of resource consumption: Through customized coefficient design, multiplication operations are transformed into shift + addition operations, completely eliminating the multiplier. The number of logic units occupied during FPGA / ASIC implementation is significantly reduced, the power consumption of embedded devices is greatly reduced, and it is suitable for resource-constrained scenarios.

[0068] Multiple bandwidth levels are flexibly adjustable: via single-level parameters By linking the cutoff angular frequency and filter coefficients, multiple bandwidth adjustments can be achieved without pre-storing multiple sets of complex coefficients, resulting in simple hardware control logic.

[0069] Stable and reliable: Through rigorous mathematical proof, the poles of all bandwidth levels are located inside the unit circle, ensuring the unconditional stability of the filter.

[0070] Filtering performance meets standards: the amplitude-frequency response at each bandwidth level meets the characteristics of a high-pass filter, and the zero-point... It effectively suppresses DC components and has a significant filtering effect.

[0071] Highly scalable: the gear parameters The range of values ​​can be flexibly expanded according to the system data bit width, and it is applicable to everything from low-cost 8-bit / 16-bit microcontrollers to high-precision 32-bit processors, providing a high degree of design flexibility.

[0072] This embodiment uses sampling frequency For example, with a data width W=16 bits.

[0073] Coefficient calculation: , (Right now ).

[0074] Hardware implementation:

[0075] 1) ;

[0076] 2) ;

[0077] 3) .

[0078] 4) Difference equations:

[0079]

[0080]

[0081] Filtering effect: This setting has the highest cutoff frequency and can effectively suppress low-frequency interference and DC components.

[0082] Based on the same inventive concept as the aforementioned multi-stage variable bandwidth high-pass filter, this embodiment of the invention also provides a design method for a multi-stage variable bandwidth high-pass filter, the design method comprising:

[0083] Configure the gear parameter N in positive integer form;

[0084] The input signal x(n) is delayed by one sampling period and output as the historical input signal x(n-1), and the output signal y(n) is delayed by one sampling period and output as the historical output signal y(n-1).

[0085] The input signal x(n) is shifted right by K bits to obtain the shifted result of x(n), the historical input signal x(n-1) is shifted right by K bits to obtain the shifted result of x(n-1), and the historical output signal y(n-1) is shifted right by N bits to obtain the shifted result of y(n-1), where K is a positive integer greater than or equal to N;

[0086] The time-domain difference equation of the filter is obtained by performing addition and subtraction operations on the shift results of input signals x(n), x(n), the shift results of historical input signals x(n-1), x(n-1), the shift results of historical output signals y(n-1) and y(n-1).

[0087] Furthermore, the denominator coefficient a of the filter is configured according to the gear parameter N, and the numerator coefficient b of the filter is configured according to K.

[0088] It should be noted that those skilled in the art can understand the design method of the aforementioned multi-level variable bandwidth high-pass filter based on the above-mentioned multi-level variable bandwidth high-pass filter, and will not be elaborated here.

[0089] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A multi-level variable bandwidth high-pass filter, characterized in that, include: The gear control module is used to configure the gear parameter N in positive integer form. The delay module is used to delay the input signal x(n) by one sampling period and output it as the historical input signal x(n-1), and to delay the output signal y(n) by one sampling period and output it as the historical output signal y(n-1). The shift operation module is used to right-shift the input signal x(n) by K bits to obtain the shift result of x(n), right-shift the historical input signal x(n-1) by K bits to obtain the shift result of x(n-1), and right-shift the historical output signal y(n-1) by N bits to obtain the shift result of y(n-1), where K is a positive integer greater than or equal to N; The addition and subtraction module performs addition and subtraction operations on the input signals x(n), the shift results of x(n), the historical input signals x(n-1), the shift results of x(n-1), the historical output signals y(n-1), and the shift results of y(n-1) to obtain the time-domain difference equation of the filter.

2. The multi-level variable bandwidth high-pass filter according to claim 1, characterized in that, The time-domain difference equation of the filter is: Where (x(n)>>>K) is the shift result of x(n), (x(n-1)>>>K) is the shift result of x(n-1), and (y(n-1)>>>N) is the shift result of y(n-1).

3. The multi-level variable bandwidth high-pass filter according to claim 1, characterized in that, 1≤N≤W-1, where W is the data bit width.

4. The multi-level variable bandwidth high-pass filter according to claim 1, characterized in that, K=N+1.

5. The multi-level variable bandwidth high-pass filter according to claim 1, characterized in that, The multi-level variable bandwidth high-pass filter also includes a coefficient configuration unit, which is used to configure the denominator coefficient a of the filter according to the level parameter N and the numerator coefficient b of the filter according to K.

6. The multi-level variable bandwidth high-pass filter according to claim 5, characterized in that, ； 。 7. The multi-level variable bandwidth high-pass filter according to claim 1, characterized in that, The digital cutoff angular frequency of the filter is negatively correlated with the range parameter N.

8. A design method for a multi-stage variable bandwidth high-pass filter, characterized in that, include: Configure the gear parameter N in positive integer form; The input signal x(n) is delayed by one sampling period and output as the historical input signal x(n-1), and the output signal y(n) is delayed by one sampling period and output as the historical output signal y(n-1). The input signal x(n) is shifted right by K bits to obtain the shifted result of x(n), the historical input signal x(n-1) is shifted right by K bits to obtain the shifted result of x(n-1), and the historical output signal y(n-1) is shifted right by N bits to obtain the shifted result of y(n-1), where K is a positive integer greater than or equal to N; The time-domain difference equation of the filter is obtained by performing addition and subtraction operations on the shift results of input signals x(n), x(n), the shift results of historical input signals x(n-1), x(n-1), the shift results of historical output signals y(n-1) and y(n-1).

9. The design method of a multi-stage variable bandwidth high-pass filter according to claim 8, characterized in that, The design method further includes: configuring the denominator coefficient a of the filter according to the gear parameter N and configuring the numerator coefficient b of the filter according to K.

10. The design method of a multi-stage variable bandwidth high-pass filter according to claim 8, characterized in that, The time-domain difference equation of the filter is: Where (x(n)>>>K) is the shift result of x(n), (x(n-1)>>>K) is the shift result of x(n-1), and (y(n-1)>>>N) is the shift result of y(n-1).

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