A method for manufacturing a gate oxide layer

Abstract

The embodiment of the present application discloses a preparation method of a gate oxide layer. The preparation method of the gate oxide layer comprises the following steps: providing a semiconductor body; the semiconductor body comprises a first surface and a second surface arranged oppositely; forming a first gate oxide layer on the first surface of the semiconductor body; annealing the first gate oxide layer by using a first gas; forming a second gate oxide layer on the side of the first gate oxide layer away from the first surface; the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer; annealing the first gate oxide layer and the second gate oxide layer by using a second gas; the second gas is different from the first gas. The technical scheme of the embodiment of the present application can improve the quality of the gate oxide layer and the interface quality of the semiconductor body.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for preparing a gate oxide layer. Background Technology

[0002] The formation of silicon oxide thin films by thermal oxidation of silicon carbide is currently the mainstream gate oxide process. Silicon carbide begins to oxidize at temperatures above 900°C. Considering the oxidation rate, the general process range for silicon carbide oxidation is 1200°C to 1400°C, and a dedicated high-temperature furnace is used to introduce oxygen for dry oxidation.

[0003] However, since silicon carbide oxidation consumes silicon carbide to generate silicon oxide, as the oxidation reaction proceeds, oxygen needs to pass through a thicker layer of silicon oxide to reach the silicon carbide surface to react. Therefore, oxygen and silicon carbide may not react completely, resulting in a large number of interface defects, which leads to a decrease in the performance of the semiconductor device formed. Summary of the Invention

[0004] This application provides a method for preparing a gate oxide layer to improve the quality of the gate oxide layer and the interface quality of the semiconductor body.

[0005] According to one aspect of this application, a method for fabricating a gate oxide layer is provided, the method comprising: A semiconductor body is provided; the semiconductor body includes a first surface and a second surface disposed opposite to each other; A first gate oxide layer is formed on the first surface of the semiconductor body; The first gate oxide layer is annealed using a first gas; A second gate oxide layer is formed on the side of the first gate oxide layer away from the first surface; the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer. The first gate oxide layer and the second gate oxide layer are annealed using a second gas; the second gas is different from the first gas.

[0006] Optionally, a first gate oxide layer is formed on the first surface of the semiconductor body, including: A first gate oxide layer is formed on the first surface of the semiconductor body by applying low-pressure chemical vapor deposition, plasma chemical vapor deposition, atomic layer deposition, or plasma atomic layer deposition.

[0007] Optionally, a first gate oxide layer is formed on the first surface of the semiconductor body, including: A first gate oxide layer with a dielectric constant greater than or equal to 3.9 is formed on the first surface of the semiconductor body.

[0008] Optionally, a first gate oxide layer with a dielectric constant greater than or equal to 3.9 is formed on the first surface of the semiconductor body, including: A first gate oxide layer comprising silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, or titanium oxide is formed on the first surface of the semiconductor body.

[0009] Optionally, a first gate oxide layer is formed on the first surface of the semiconductor body, including: A first gate oxide layer with a thickness greater than zero and less than or equal to 200 angstroms is formed on the first surface of the semiconductor body.

[0010] Optionally, the first gas includes nitric oxide, nitrous oxide, oxygen, or phosphorus trichloride; the second gas includes nitrogen or argon.

[0011] Optionally, a second gate oxide layer is formed on the side of the first gate oxide layer away from the first surface, including: A second gate oxide layer comprising silicon oxide is formed on the side of the first gate oxide layer away from the first surface by applying low-pressure chemical vapor deposition, plasma chemical vapor deposition, atomic layer deposition, or plasma atomic layer deposition.

[0012] Optionally, a second gate oxide layer is formed on the side of the first gate oxide layer away from the first surface, including: A second gate oxide layer with a thickness greater than 0 and less than or equal to 2000 angstroms is formed on the side of the first gate oxide layer away from the first surface.

[0013] Optionally, annealing the first gate oxide layer and the second gate oxide layer with a second gas includes: Annealing of the first gate oxide layer and the second gate oxide layer is performed using a second gas at a temperature greater than or equal to 1100°C and less than or equal to 1500°C.

[0014] Optionally, a semiconductor body is provided, including: Provide a semiconductor body including a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0015] The technical solution of this application provides a method for preparing a gate oxide layer. First, a thin first gate oxide layer is formed on the first surface of a semiconductor body as an interface gate oxide layer. A first gas is used to anneal the interface between the semiconductor body and the first gate oxide layer to obtain a high-quality interface and eliminate interface defects. Then, a second gate oxide layer with a thickness greater than that of the first gate oxide layer is formed on the side of the first gate oxide layer away from the first surface as a breakdown layer to improve the breakdown voltage of the overall gate oxide layer. Finally, a second gas is used to anneal the first and second gate oxide layers to improve the density of the overall gate oxide layer composed of the first and second gate oxide layers, thus completing the preparation of the overall gate oxide layer and improving the quality of the overall gate oxide layer and the interface quality of the semiconductor body.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic flowchart of a method for preparing a gate oxide layer according to an embodiment of this application; Figures 2-4 Provided according to the embodiments of this application Figure 1 A schematic diagram of the structure corresponding to each step. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] Figure 1 This is a schematic flowchart of a method for fabricating a gate oxide layer according to an embodiment of this application. Figure 1 As shown, the method for fabricating the gate oxide layer includes: S110, Provide a semiconductor body; the semiconductor body includes a first surface and a second surface disposed opposite to each other.

[0022] refer to Figure 2 A semiconductor body 100 is provided; the semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite to each other.

[0023] In the embodiments of this application, the semiconductor body 100 can be used to form a planar metal-oxide-semiconductor field-effect transistor (MOSFET) in subsequent processes, or it can be used to form a trench MOSFET. The embodiments of this application do not specifically limit it here.

[0024] This application embodiment uses the formation of a planar MOSFET as an example for illustration. The semiconductor body 100 may further include a well region 103, a source region 104, and a first region 105 located on the first surface 101. The source region 104 is configured with a first conductivity type, while the well region 103 and the first region 105 are both configured with a second conductivity type. The first conductivity type and the second conductivity type are different.

[0025] For an N-type planar MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-type planar MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type. For regions with N-type conductivity, N-type doping can be used, and the dopant ions can be phosphorus (P) ions or nitrogen (N) ions. For regions with P-type conductivity, P-type doping can be used, and the dopant ions can be aluminum (Al) ions or boron (B) ions. This application uses an N-type planar MOSFET as an example for illustration. Well region 103 is a P-well region. P-type dopant ions in the P-well region can be aluminum (Al) ions or boron (B) ions. Source region 104 is an N+ doped region. N+ dopant ions in the N+ doped region can be phosphorus (P) ions or nitrogen (N) ions. First region 105 is a P+ doped region.

[0026] like Figure 2 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of this application, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of this application, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 by one or more epitaxial processes, including chemical vapor deposition (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE).

[0027] In optional embodiments of this application, providing a semiconductor body includes providing a semiconductor body comprising a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0028] In this embodiment, the semiconductor body 100 includes a wide-bandgap or ultra-wide-bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. If the semiconductor body 100 includes a silicon carbide semiconductor body, the resulting semiconductor device is a silicon carbide semiconductor device. If the semiconductor body 100 includes a gallium nitride semiconductor body, the resulting semiconductor device is a gallium nitride semiconductor device.

[0029] Silicon carbide semiconductor devices or gallium nitride semiconductor devices have the advantages of high voltage resistance, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0030] S120, A first gate oxide layer is formed on the first surface of the semiconductor body.

[0031] refer to Figure 3 A first gate oxide layer 11 is formed on the first surface 101 of the semiconductor body 100.

[0032] In this embodiment, a first gate oxide layer 11 is formed on the first surface 101 of the semiconductor body 100 by a deposition process or a thermal oxidation process, serving as the bottom layer structure of the double gate oxide layer and connecting the semiconductor body 100 and the upper gate oxide layer. The first gate oxide layer 11 includes, but is not limited to, a silicon oxide layer.

[0033] In an optional embodiment of this application, S120, forming a first gate oxide layer on the first surface of the semiconductor body includes: applying low-pressure chemical vapor deposition, plasma chemical vapor deposition, atomic layer deposition, or plasma atomic layer deposition to form a first gate oxide layer on the first surface of the semiconductor body.

[0034] Continue to refer to Figure 3 A first gate oxide layer 11 is formed on the first surface 101 of the semiconductor body 100 by applying low-pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD), atomic layer deposition (ALD), or plasma atomic layer deposition (PEALD).

[0035] In the embodiments of this application, the advantages of using LPCVD technology are that it allows for vapor-phase reaction film formation under low pressure, resulting in good film uniformity and excellent step coverage. The advantages of using PECVD technology are that it utilizes plasma-activated reactions, resulting in low deposition temperatures and avoiding damage to the semiconductor substrate at temperatures exceeding 100°C. The advantages of using ALD technology are that it allows for single-atom-level layer-by-layer growth, resulting in precisely controllable film thickness, extremely high density, and excellent interface smoothness. The advantages of using PEALD technology are that it combines the advantages of plasma and ALD processes, achieving a balance between low temperature, high precision, and high density.

[0036] By applying LPCVD, PECVD, ALD, or PEALD, a first gate oxide layer 11 can be formed on the first surface 101 of the semiconductor body 100. This can prepare an ultra-thin and uniform thin film, reduce the native defects of the first gate oxide layer 11, optimize the interface morphology between the semiconductor body 100 and the first gate oxide layer 11, and reduce the interface roughness.

[0037] In an optional embodiment of this application, S120, forming a first gate oxide layer on the first surface of the semiconductor body, includes: forming a first gate oxide layer on the first surface of the semiconductor body with a dielectric constant greater than or equal to 3.9.

[0038] In the embodiments of this application, reference continues to be made to Figure 3A first gate oxide layer 11 with a dielectric constant greater than or equal to 3.9 is formed on the first surface 101 of the semiconductor body 100. A conventional material with a dielectric constant of 3.9 is silicon oxide. In this embodiment, the materials used to form the first gate oxide layer 11 include, but are not limited to, silicon oxide and high-dielectric-constant materials. The material of the first gate oxide layer 11 can be selected according to the breakdown voltage or threshold voltage requirements of the semiconductor device. High-dielectric-constant materials can achieve a larger gate capacitance with the same film thickness, improving the gate control capability of the semiconductor device and optimizing the switching characteristics of the semiconductor device.

[0039] In an optional embodiment of this application, forming a first gate oxide layer with a dielectric constant greater than or equal to 3.9 on the first surface of the semiconductor body includes: forming a first gate oxide layer comprising silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, or titanium oxide on the first surface of the semiconductor body.

[0040] In the embodiments of this application, the material of the first gate oxide layer includes, but is not limited to, silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, or titanium oxide. These materials have stable chemical properties, excellent insulating properties, and are suitable for the needs of different semiconductor devices.

[0041] In an optional embodiment of this application, S120, forming a first gate oxide layer on the first surface of the semiconductor body includes: forming a first gate oxide layer with a thickness greater than zero and less than or equal to 200 angstroms on the first surface of the semiconductor body.

[0042] In the embodiments of this application, reference continues to be made to Figure 3 A first gate oxide layer 11 with a thickness greater than zero and less than or equal to 200 angstroms is formed on the first surface 101 of the semiconductor body 100. The thinner first gate oxide layer 11 makes it easier for carbon on the first surface 101 of the semiconductor body 100 to combine with oxygen to form carbon monoxide and escape, effectively reducing the interface defects between the semiconductor body 100 and the first gate oxide layer 11, improving the mobility of the formed semiconductor device, and reducing the on-resistance of the semiconductor device.

[0043] S130. Anneal the first gate oxide layer using the first gas.

[0044] In this embodiment, the newly deposited first gate oxide layer is annealed by introducing a first gas to perform interface repair, precisely passivate the interface defects between the semiconductor body and the first gate oxide layer, and improve the quality of the first gate oxide layer and the interface quality of the semiconductor body.

[0045] In optional embodiments of this application, the first gas includes nitric oxide, nitrous oxide, oxygen, or phosphorus trichloride. Nitric oxide and nitrous oxide can decompose to produce nitrogen atoms, which embed into the interface between the semiconductor body and the first gate oxide layer, passivating carbon residues at the interface. Introducing oxygen can perform oxygen-replenishing annealing, repairing oxygen vacancy defects inside the first gate oxide layer. Phosphorus trichloride has the functions of oxygen replenishment, doping, and interface passivation, and can further neutralize the interface charge between the semiconductor body and the first gate oxide layer.

[0046] S140, a second gate oxide layer is formed on the side of the first gate oxide layer away from the first surface; the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer.

[0047] refer to Figure 4 A second gate oxide layer 12 is formed on the side of the first gate oxide layer 11 away from the first surface 101; the thickness of the second gate oxide layer 12 is greater than the thickness of the first gate oxide layer 11.

[0048] In this embodiment, a second gate oxide layer 12 with a thickness greater than that of the first gate oxide layer 11 is deposited on the side of the first gate oxide layer 11 away from the first surface 101. The second gate oxide layer 12 can serve as a breakdown layer to ensure that the breakdown voltage of the overall gate oxide layer is sufficiently high.

[0049] In an optional embodiment of this application, S140, forming a second gate oxide layer on the side of the first gate oxide layer away from the first surface includes: applying low-pressure chemical vapor deposition, plasma chemical vapor deposition, atomic layer deposition, or plasma atomic layer deposition to form a second gate oxide layer including silicon oxide on the side of the first gate oxide layer away from the first surface.

[0050] In the embodiments of this application, reference continues to be made to Figure 4 A second gate oxide layer 12 comprising silicon oxide is formed on the side of the first gate oxide layer 11 away from the first surface 101 by applying low-pressure chemical vapor deposition, plasma chemical vapor deposition, atomic layer deposition or plasma atomic layer deposition.

[0051] In this embodiment, any one of the deposition processes selected from low-pressure chemical vapor deposition, plasma chemical vapor deposition, atomic layer deposition, or plasma atomic layer deposition can be used, maintaining consistency with the formation process of the first gate oxide layer 11. This eliminates the need to switch production line equipment, thereby improving production efficiency. The material of the second gate oxide layer 12 includes, but is not limited to, silicon oxide. Silicon oxide has excellent insulation and withstand voltage properties, low cost, and high reliability.

[0052] In an optional embodiment of this application, S140, forming a second gate oxide layer on the side of the first gate oxide layer away from the first surface includes: forming a second gate oxide layer with a thickness greater than 0 and less than or equal to 2000 angstroms on the side of the first gate oxide layer away from the first surface.

[0053] In the embodiments of this application, reference continues to be made to Figure 4 The thickness of the second gate oxide layer 12 is greater than 0 and less than or equal to 2000 angstroms, which is greater than the thickness of the first gate oxide layer 11. As a breakdown layer, the second gate oxide layer 12 can improve the overall breakdown voltage of the gate oxide layer, making it suitable for medium and high voltage semiconductor devices. Setting the thickness of the second gate oxide layer 12 to be greater than 0 and less than or equal to 2000 angstroms satisfies the breakdown voltage requirement without reducing the gate control capability due to excessive thickness, thus avoiding excessive parasitic capacitance.

[0054] S150, Anneal the first gate oxide layer and the second gate oxide layer using a second gas; the second gas is different from the first gas.

[0055] In optional embodiments of this application, the second gas includes nitrogen or argon.

[0056] In this embodiment, after the second gate oxide layer is deposited, the overall gate oxide layer composed of the first and second gate oxide layers is annealed to improve the density of the overall gate oxide layer. The gases used for annealing the first and second gate oxide layers include, but are not limited to, inert gases such as nitrogen or argon, and there are no additional doping elements, thus improving the interface passivation effect.

[0057] The technical solution of this application provides a method for preparing a gate oxide layer. First, a thin first gate oxide layer is formed on the first surface of a semiconductor body as an interface gate oxide layer. A first gas is used to anneal the interface between the semiconductor body and the first gate oxide layer to obtain a high-quality interface and eliminate interface defects. Then, a second gate oxide layer with a thickness greater than that of the first gate oxide layer is formed on the side of the first gate oxide layer away from the first surface as a breakdown layer to improve the breakdown voltage of the overall gate oxide layer. Finally, a second gas is used to anneal the first and second gate oxide layers to improve the density of the overall gate oxide layer composed of the first and second gate oxide layers, thus completing the preparation of the overall gate oxide layer and improving the quality of the overall gate oxide layer and the interface quality of the semiconductor body.

[0058] In an optional embodiment of this application, S150, annealing the first gate oxide layer and the second gate oxide layer with a second gas, includes: annealing the first gate oxide layer and the second gate oxide layer with a second gas at a temperature greater than or equal to 1100°C and less than or equal to 1500°C.

[0059] In this embodiment, the annealing temperature range is set to 1100℃-1500℃, which falls within the high-temperature process window. Under high-temperature conditions, the atoms within the first and second gate oxide layers rearrange, eliminating micropores or gaps generated during deposition and improving film density. Simultaneously, it releases stress between the first and second gate oxide layers, and between the first gate oxide layer and the semiconductor body, preventing long-term stress-induced cracking or failure of the semiconductor device and improving the reliability of subsequently formed semiconductor devices.

[0060] In optional embodiments of this application, after forming an integral gate oxide layer including a first gate oxide layer and a second gate oxide layer, polysilicon can be deposited to form the gate, silicon oxide can be deposited on the side of the gate away from the second gate oxide layer to form an interlayer insulating layer, metal can be deposited on the first surface to form the source, and metal can be deposited on the second surface to form the drain, thereby forming a planar silicon carbide MOSFET. In other optional embodiments of this application, MOSFETs with other structures can also be formed, and the embodiments of this application are not specifically limited here.

[0061] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

[0062] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for preparing a gate oxide layer, characterized in that, include: A semiconductor body is provided; the semiconductor body includes a first surface and a second surface disposed opposite to each other; A first gate oxide layer is formed on the first surface of the semiconductor body; The first gate oxide layer is annealed using a first gas; A second gate oxide layer is formed on the side of the first gate oxide layer away from the first surface; the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer. The first gate oxide layer and the second gate oxide layer are annealed using a second gas; the second gas is different from the first gas.

2. The method for preparing the gate oxide layer according to claim 1, characterized in that, A first gate oxide layer is formed on the first surface of the semiconductor body, comprising: A first gate oxide layer is formed on the first surface of the semiconductor body using low-pressure chemical vapor deposition, plasma chemical vapor deposition, atomic layer deposition, or plasma atomic layer deposition.

3. The method for preparing the gate oxide layer according to claim 1, characterized in that, A first gate oxide layer is formed on the first surface of the semiconductor body, comprising: A first gate oxide layer with a dielectric constant greater than or equal to 3.9 is formed on the first surface of the semiconductor body.

4. The method for preparing the gate oxide layer according to claim 3, characterized in that, A first gate oxide layer with a dielectric constant greater than or equal to 3.9 is formed on the first surface of the semiconductor body, comprising: A first gate oxide layer comprising silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, or titanium oxide is formed on the first surface of the semiconductor body.

5. The method for preparing the gate oxide layer according to claim 1, characterized in that, A first gate oxide layer is formed on the first surface of the semiconductor body, comprising: A first gate oxide layer with a thickness greater than zero and less than or equal to 200 angstroms is formed on the first surface of the semiconductor body.

6. The method for preparing the gate oxide layer according to claim 1, characterized in that, The first gas includes nitric oxide, nitrous oxide, oxygen, or phosphorus trichloride; the second gas includes nitrogen or argon.

7. The method for preparing the gate oxide layer according to claim 1, characterized in that, A second gate oxide layer is formed on the side of the first gate oxide layer away from the first surface, comprising: A second gate oxide layer comprising silicon oxide is formed on the side of the first gate oxide layer away from the first surface by applying low-pressure chemical vapor deposition, plasma chemical vapor deposition, atomic layer deposition, or plasma atomic layer deposition.

8. The method for preparing the gate oxide layer according to claim 1, characterized in that, A second gate oxide layer is formed on the side of the first gate oxide layer away from the first surface, comprising: A second gate oxide layer with a thickness greater than 0 and less than or equal to 2000 angstroms is formed on the side of the first gate oxide layer away from the first surface.

9. The method for preparing the gate oxide layer according to claim 1, characterized in that, Annealing the first gate oxide layer and the second gate oxide layer using a second gas includes: Annealing of the first gate oxide layer and the second gate oxide layer using a second gas at a temperature greater than or equal to 1100°C and less than or equal to 1500°C.

10. The method for preparing the gate oxide layer according to claim 1, characterized in that, Provide semiconductor bodies, including: Provide a semiconductor body including a silicon carbide semiconductor body or a gallium nitride semiconductor body.

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