Method for protecting ups device, controller, ups device and storage medium

Abstract

Embodiments of the present application disclose a UPS device protection method. The protection method comprises: acquiring a first bus voltage applied to a main inverter circuit; in response to the first bus voltage being less than or equal to a first voltage threshold, reducing an output current of the main inverter circuit; acquiring a second bus voltage applied to the main inverter circuit after current-limiting operation of the main inverter circuit; and in response to the second bus voltage being greater than or equal to a second voltage threshold, controlling the output current of the main inverter circuit to return to a normal current, the second voltage threshold being greater than the first voltage threshold. In the case of rapid drop of the first bus voltage of the UPS device, the embodiments of the present application can quickly limit the output current of the main inverter circuit to gradually increase the bus voltage applied to the main inverter circuit, reduce the voltage difference between the bus voltage and the battery voltage of the battery, avoid damage to the switching tube of the direct current conversion circuit, the power factor correction circuit or the main inverter circuit due to the large current, and further improve the working reliability and safety of the UPS device.

Description

Technical Field

[0001] This application relates to the field of UPS equipment technology, and in particular to a UPS equipment protection method, controller, UPS equipment and storage medium. Background Technology

[0002] UPS (Uninterruptible Power Supply) equipment can switch back to battery operation mode and continue to supply power to the load via batteries when mains power is lost. However, under severe operating conditions, the UPS bus voltage can drop rapidly. Because the battery voltage is higher than the bus voltage, a large current can be generated instantaneously, potentially damaging the UPS's circuit components. Summary of the Invention

[0003] One objective of this application is to provide a UPS equipment protection method, controller, UPS equipment, and storage medium to solve the technical problem that the circuit components of the UPS equipment are easily damaged when the bus voltage drops rapidly.

[0004] In a first aspect, embodiments of this application provide a UPS equipment protection method. The UPS equipment includes a first switching switch, a power factor correction circuit, a main inverter circuit, a second switching switch, a DC-DC conversion circuit, a battery, a sampling circuit, and a controller. The first switching switch, the power factor correction circuit, and the main inverter circuit are electrically connected in sequence. The second switching switch is electrically connected between the power factor correction circuit and the DC-DC conversion circuit. The DC-DC conversion circuit is electrically connected to the battery. The sampling circuit is electrically connected to the main inverter circuit. The controller is electrically connected to the first switching switch, the power factor correction circuit, the main inverter circuit, the second switching switch, the DC-DC conversion circuit, and the sampling circuit. The protection method includes: acquiring a first bus voltage applied to the main inverter circuit; responding that the first bus voltage is less than or equal to a first voltage threshold, controlling the main inverter circuit to perform a current limiting operation to reduce the output current of the main inverter circuit; acquiring a second bus voltage applied to the main inverter circuit after the current limiting operation; responding that the second bus voltage is greater than or equal to a second voltage threshold, controlling the main inverter circuit to perform a current recovery operation to restore the output current of the main inverter circuit to a normal current. The second voltage threshold is greater than the first voltage threshold.

[0005] In the event of a rapid drop in the first bus voltage of the UPS equipment, this embodiment can quickly limit the output current of the main inverter circuit to gradually increase the bus voltage applied to the main inverter circuit, reduce the voltage difference between the bus voltage of the main inverter circuit and the battery voltage, and reduce the current flowing through the DC-DC conversion circuit, the second switching switch, the power factor correction circuit, and the main inverter circuit. This avoids damage to the switching transistors of the DC-DC conversion circuit, the power factor correction circuit, or the main inverter circuit due to excessive current, thereby improving the operational reliability and safety of the UPS equipment.

[0006] Optionally, in response to the first bus voltage being less than or equal to a first voltage threshold, controlling the main inverter circuit to perform a current limiting operation to reduce the output current of the main inverter circuit includes: in response to the first bus voltage being less than or equal to the first voltage threshold, determining a current limiting mode matching the first bus voltage as a target current limiting mode among at least two preset current limiting modes, and controlling the main inverter circuit to perform a current limiting operation to reduce the output current of the main inverter circuit based on the target current limiting mode.

[0007] Based on the first bus voltage, this application embodiment adaptively selects a suitable current limiting mode as the target current limiting mode, and then controls the main inverter circuit to perform current limiting operation based on the target current limiting mode. This ensures that the main inverter circuit can provide the maximum output power to the load, and also ensures that the bus voltage applied to the main inverter circuit is not in an abnormal state for a long time. In other words, it can efficiently promote the bus voltage applied to the main inverter circuit to recover to the normal bus voltage as soon as possible.

[0008] Optionally, the at least two current limiting modes include a first type of current limiting mode and a second type of current limiting mode. Responding to a first bus voltage being less than or equal to a first voltage threshold, determining the current limiting mode matching the first bus voltage as the target current limiting mode among the at least two preset current limiting modes includes: responding to a first bus voltage being less than or equal to the first voltage threshold, detecting whether the first bus voltage is less than or equal to a third voltage threshold, where the third voltage threshold is less than the first voltage threshold; if the first bus voltage is greater than the third voltage threshold and less than the first voltage threshold, determining the first type of current limiting mode as the target current limiting mode among the at least two preset current limiting modes; the first type of current limiting mode is a mode that limits the output current of the main inverter circuit to a specified current limiting value; if the first bus voltage is less than or equal to the third voltage threshold, determining the second type of current limiting mode as the target current limiting mode among the at least two preset current limiting modes; the second type of current limiting mode is a mode that controls the main inverter circuit to stop operating.

[0009] When the main inverter circuit has a first bus voltage greater than the third voltage threshold and less than the first voltage threshold, it indicates that the first bus voltage is not significantly deviating from the normal bus voltage. Therefore, this embodiment enters the first type of current limiting mode and does not use a fixed value to limit the output current of the main inverter circuit. Instead, it adaptively selects an appropriate current limiting value to limit the output current of the main inverter circuit based on the first bus voltage. This ensures that the main inverter circuit can output maximum power to the load.

[0010] When the main inverter circuit's first bus voltage is less than or equal to the third voltage threshold, it indicates that the first bus voltage has deviated significantly from the normal bus voltage. Therefore, in this embodiment, the main inverter circuit enters the second type of current limiting mode, controlling the main inverter circuit to stop working, so that the main inverter circuit's bus voltage can quickly recover to the normal bus voltage. This can prevent the main inverter circuit's bus voltage from being in an abnormal state for a long time, thereby ensuring that the main inverter circuit can efficiently provide normal power to the load.

[0011] Optionally, at least two current limiting modes include a first type of current limiting mode. Based on the target current limiting mode, controlling the main inverter circuit to perform current limiting operation to reduce the output current of the main inverter circuit includes: responding to the target current limiting mode as the first type of current limiting mode, determining the current limiting value, and controlling the main inverter circuit to output a target current consistent with the current limiting value.

[0012] The embodiments of this application can flexibly determine the current limiting value in the first type of current limiting mode, thus ensuring that the main inverter circuit outputs the maximum power to the load.

[0013] Optionally, in response to the target current limiting mode being the first type of current limiting mode, determining the current limiting value includes: in response to the target current limiting mode being the first type of current limiting mode, using the first bus voltage as the input of a preset current limiting model, so that the current limiting model outputs a current limiting value.

[0014] Optionally, at least two current limiting modes include a second type of current limiting mode. Based on the target current limiting mode, controlling the main inverter circuit to perform current limiting operations to reduce the output current of the main inverter circuit includes: responding to the target current limiting mode being the second type of current limiting mode, controlling the main inverter circuit to stop working.

[0015] In this embodiment of the application, the main inverter circuit is controlled to stop working under the second type of current limiting mode, so that the bus voltage of the main inverter circuit can be quickly restored to the normal bus voltage, ensuring that the main inverter circuit can quickly provide normal power to the load.

[0016] Optionally, obtaining the first bus voltage applied to the main inverter circuit includes: determining the target operating mode of the UPS equipment, responding to the target operating mode as battery operating mode, and controlling the sampling circuit to sample the first bus voltage applied to the main inverter circuit.

[0017] In a second aspect, embodiments of this application provide a controller, characterized in that it includes a memory and a processor, the memory being connected to the processor, the processor being used to execute one or more computer programs stored in the memory, and the processor, when executing one or more computer programs, causing the controller to implement the above-described UPS equipment protection method.

[0018] In a third aspect, embodiments of this application provide a UPS device, including a first switching switch, a power factor correction circuit, a main inverter circuit, a second switching switch, a DC-DC conversion circuit, a battery, a sampling circuit, and the aforementioned controller. The first switching switch, the power factor correction circuit, and the main inverter circuit are electrically connected in sequence. The second switching switch is electrically connected between the power factor correction circuit and the DC-DC conversion circuit. The DC-DC conversion circuit is electrically connected to the battery. The sampling circuit is electrically connected to the main inverter circuit. The controller is electrically connected to the first switching switch, the power factor correction circuit, the main inverter circuit, the second switching switch, the DC-DC conversion circuit, and the sampling circuit.

[0019] In a fourth aspect, embodiments of this application provide a computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, the computer program including program instructions, which, when executed by a processor, cause the processor to perform the aforementioned UPS equipment protection method. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the circuit structure of a UPS device provided in an embodiment of this application;

[0022] Figure 2 This is a schematic diagram of the specific circuit structure of a UPS device provided in an embodiment of this application;

[0023] Figure 3 A circuit structure diagram of a UPS device is provided for another embodiment of this application;

[0024] Figure 4 A flowchart illustrating a UPS equipment protection method provided in an embodiment of this application;

[0025] Figure 5 A flowchart illustrating a UPS device protection method according to another embodiment of this application;

[0026] Figure 6 This is a schematic diagram of the structure of a UPS equipment protection device provided in an embodiment of this application;

[0027] Figure 7 This is a schematic diagram of the structure of a controller provided in an embodiment of this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0029] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Moreover, the terms "first," "second," and "third" used in this application do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.

[0030] UPS (Uninterruptible Power Supply) devices can switch to battery operation mode in the event of a loss of mains power, providing power to the load via batteries. For UPS devices requiring an output of 1kW-3kW in battery operation mode, existing batteries typically have a voltage range of 24V-96V, while the UPS bus voltage is generally 360V or 380V. It is usually difficult to increase the battery output voltage to 360V or 380V using a single-stage boost circuit. Therefore, UPS devices based on related technologies require a two-stage boost circuit to increase the battery output voltage to 360V or 380V. The bus voltage refers to the voltage of the internal DC bus of the UPS device, which is the line in the UPS device capable of transmitting DC power.

[0031] The related technologies provide two-stage boost circuits, including LLC boost circuits and boost circuits. These technologies employ closed-loop control to separately control the LLC and boost circuits; however, the software control logic for this closed-loop control is quite complex. Furthermore, in the LLC boost circuit, K = Lm / Lr, where Lr is the resonant inductance and Lm is the magnetizing inductance. A larger K value results in a flatter gain characteristic curve for the LLC boost circuit, making it impossible to adjust the gain through frequency modulation. To achieve frequency conversion voltage regulation of the LLC boost circuit, K needs to be as small as possible, i.e., Lm should be as small as possible and Lr as large as possible. If Lm is small, the losses in the LLC boost circuit tend to increase, leading to an imbalance in both magnetizing current and current stress. To ensure Lr meets high-frequency requirements, a ferrite core needs to be used, which increases costs. Additionally, a larger Lr value increases the size of the resonant inductor.

[0032] Considering the above-mentioned adverse factors, the relevant technology selects open-loop control to control the LLC boost circuit and closed-loop control to control the boost circuit. The K value is set to be relatively large, and the conduction angle of each switch in the LLC boost circuit is controlled by a fixed frequency and maximum gain to adjust the output voltage of the battery.

[0033] While these technologies have reduced costs, losses, and the size of resonant inductors, they still present some challenges. UPS systems operate under complex and varied conditions. For example, a UPS outputs a large current to drive the load. When the UPS loses mains power, it needs to switch from mains operation mode to battery operation mode, with the battery providing a large current to the load. During this switch, the large current demanded by the load causes a rapid drop in the UPS bus voltage. As mentioned earlier, since the battery voltage is higher than the bus voltage, a large instantaneous current can easily be generated, potentially damaging the UPS circuitry, especially the switching transistors on the auxiliary power supply side. It's understandable that many other operating conditions can cause a rapid drop in the UPS bus voltage, not just during the switch from mains to battery operation.

[0034] In the event of a rapid drop in the first bus voltage of the UPS equipment, the embodiments of this application can quickly limit the output current of the main inverter circuit to gradually increase the applied bus voltage of the main inverter circuit, reduce the voltage difference between the bus voltage and the battery voltage provided by the battery, and reduce the current flowing through the DC-DC conversion circuit, the second switching switch, the power factor correction circuit, and the main inverter circuit. This avoids damage to the switching transistors of the DC-DC conversion circuit, the power factor correction circuit, or the main inverter circuit due to excessive current, thereby improving the operational reliability and safety of the UPS equipment.

[0035] The following embodiment of this application provides a UPS device. Please refer to [link / reference]. Figure 1 The UPS device 100 includes a first switching switch 11, a power factor correction circuit 12, a main inverter circuit 13, a second switching switch 14, a DC-DC conversion circuit 15, a battery 16, a sampling circuit 17, and a controller 18.

[0036] One end of the first switching switch 11 is used to electrically connect to the mains power grid, and the other end is electrically connected to the power factor correction circuit 12. The first switching switch 11 is also electrically connected to the controller 18 and is used to control the input of the mains power supply under the control of the controller 18.

[0037] The power factor correction circuit 12 is used to boost the DC power supplied by the AC power supply to the DC-DC converter circuit 15 and perform power factor correction. It is understood that the circuit structure of the power factor correction circuit 12 is relatively complex. For an example, please refer to [link to example circuit]. Figure 2 The power factor correction circuit 12 consists of a first inductor L1, a first switching transistor Q1, a second switching transistor Q2, and a first capacitor C1. One end of the first inductor L1 is electrically connected to the positive terminal of the mains power supply, and the other end of the first inductor L1 is electrically connected to the source of the first switching transistor Q1 and the drain of the second switching transistor Q2. The drain of the first switching transistor Q1 is electrically connected to one end of the first capacitor C1, and the source of the second switching transistor Q2 is electrically connected to the other end of the first capacitor C1.

[0038] The main inverter circuit 13 is electrically connected to the power factor correction circuit 12, and is used to invert the DC power output from the power factor correction circuit 12. It is understood that the circuit structure of the main inverter circuit 13 is relatively complex. For an example, please refer to... Figure 2 The main inverter circuit 13 includes a third switch Q3, a fourth switch Q4, a fifth switch Q5, a sixth switch Q6, and a second inductor L2. The drain of the third switch Q3 is electrically connected to one end of the first capacitor C1. The source of the third switch Q3 and the drain of the fifth switch Q5 are both electrically connected to the negative terminal of the mains power supply. The drain of the fourth switch Q4 is electrically connected to one end of the first capacitor C1. The source of the fourth switch Q4 and the drain of the sixth switch Q6 are both electrically connected to the second inductor L2. The source of the fifth switch Q5 and the source of the sixth switch Q6 are electrically connected to the other end of the first capacitor C1.

[0039] When the mains power supply is in the positive half-cycle, the controller 18 controls the switching states of the second switch Q2, the fourth switch Q4, and the fifth switch Q5 respectively in boost mode to boost the voltage of the mains power supply. When the mains power supply is in the negative half-cycle, the controller 18 controls the switching states of the first switch Q1, the third switch Q3, and the sixth switch Q6 respectively in boost mode to boost the voltage of the mains power supply.

[0040] The following embodiments of this application are combined with Figure 2 The working principles of the power factor correction circuit 12 and the main inverter circuit 13 are described in detail below. Specifically, the power factor correction process and the inverter process are described in the embodiments of this application as follows:

[0041] ① Power factor correction process:

[0042] When the mains power supply is in its positive half-cycle, during this period, the first switch Q1 and the third switch Q3 are off, while the fifth switch Q5 remains on. When the second switch Q2 is on, the mains power supply current flows sequentially through the first inductor L1, the second switch Q2, and the fifth switch Q5, before returning to the negative terminal of the mains power supply. The first inductor L1 stores energy during this process. When the second switch Q2 is off, since the current in the first inductor L1 cannot change abruptly, the current flows sequentially through the body diode of the first switch Q1, the first capacitor C1, the fifth switch Q5, and the mains power supply, before returning to the first inductor L1, forming its freewheeling circuit. During this process, the first capacitor C1 is charged to replenish its energy.

[0043] When the mains power supply is in the negative half-cycle, during this period, the second switch Q2 and the fifth switch Q5 are off, while the third switch Q3 remains on. When the first switch Q1 is on, the mains power supply current flows sequentially from the negative terminal through the third switch Q3, the first switch Q1, and the first inductor L1, before returning to the positive terminal. The first inductor L1 stores energy during this process. When the first switch Q1 is off, since the current in the first inductor L1 cannot change abruptly, the current flows sequentially through the negative terminal of the mains power supply, the body diode of the third switch Q3, the first capacitor C1, and the body diode of the second switch Q2, before returning to the first inductor L1, forming its freewheeling circuit. During this process, the first capacitor C1 is charged to replenish its energy.

[0044] ②Inverter process:

[0045] When the mains power supply is in its positive half-cycle, during this period, the sixth switch Q6 and the third switch Q3 are off, while the fifth switch Q5 remains on. When the fourth switch Q4 is on, the current flows from the positive terminal of the first capacitor C1, through the fourth switch Q4, the second inductor L2, and the fifth switch Q5, before returning to the negative terminal of the first capacitor C1. During this process, the energy of the first capacitor C1 is consumed. When the fourth switch Q4 is off, since the current in the second inductor L2 cannot change abruptly, the inductor current flows from the second inductor L2 to the right through the load, the fifth switch Q5, and the body diode of the sixth switch Q6, forming a freewheeling circuit.

[0046] When the mains power supply is in the negative half-cycle, during this period, the fourth switch Q4 and the fifth switch Q5 are off, while the third switch Q3 remains on. When the sixth switch Q6 is on, the current flows from the positive terminal of the first capacitor C1, through the third switch Q3, the load, the second inductor L2, and the sixth switch Q6, before returning to the negative terminal of the first capacitor C1. During this process, the energy of the first capacitor C1 is consumed. When the sixth switch Q6 is off, since the current in the second inductor L2 cannot change abruptly, the inductor current flows from the second inductor L2 to the left, through the body diode of the fourth switch Q4, the third switch Q3, and the load, before returning to the second inductor L2, forming a freewheeling circuit.

[0047] The second switching switch 14 is electrically connected between the power factor correction circuit 12 and the DC-DC conversion circuit 15, and is also electrically connected to the controller 18 for controlling the current output of the battery under the control of the controller 18.

[0048] The UPS device 100 has two operating modes: AC power mode and battery power mode. The AC power mode is the mode in which the UPS device supplies power to the load. In battery power mode, the UPS device controls the battery to supply power to the load. In AC power mode, the UPS device processes AC power and then supplies it to the load.

[0049] When the controller 18 detects the input of mains power, it controls the first switching switch 11 to enter the closed state. Therefore, the UPS equipment 100 enters the mains power operation mode. The mains power can be transmitted to the power factor correction circuit 12 through the first switching switch 11 for rectification, boosting and power factor correction, thereby obtaining DC power that has undergone power factor correction. The DC power that has undergone power factor correction is transmitted to the main inverter circuit 13. The main inverter circuit 13 inverts the DC power that has undergone power factor correction into AC power and transmits the AC power to the load for operation.

[0050] When the UPS device 100 enters the mains power operation mode, if the controller 18 detects that no mains power is input to the UPS device, the controller 18 controls the first switching switch 11 to open and the second switching switch 14 to close. Therefore, the UPS device 100 switches from the mains power operation mode to the battery operation mode. The DC power from the battery 16 side is transmitted to the power factor correction circuit 12 through the second switching switch 14 for rectification, boosting, and power factor correction, thereby obtaining DC power that has undergone power factor correction. The DC power that has undergone power factor correction is transmitted to the main inverter circuit 13, which inverts the DC power that has undergone power factor correction into AC power and transmits the AC power to the load for operation.

[0051] When the UPS device 100 enters battery operation mode, and the controller 18 detects the input of mains power, the controller 18 performs a phase-locked loop operation to ensure that the AC power output from the main inverter circuit 13 is consistent with the mains power in frequency and phase. After the controller 18 completes the phase-locked loop operation, the controller 18 controls the first switching switch 11 to enter the closed state and controls the second switching switch 14 to enter the open state. The mains power is transmitted to the UPS device 100 through the first switching switch 11, and the current loop on the battery side is disconnected, thus realizing the purpose of switching the UPS device from battery operation mode back to mains operation mode.

[0052] The DC-DC converter circuit 15 is electrically connected to the battery 16 and also to the controller 18. Controlled by the controller 18, the DC-DC converter circuit 15 boosts the voltage of the battery 16 and then applies it to the power factor correction circuit 12 via the second switching switch 14. The power factor correction circuit 12 boosts the voltage output from the DC-DC converter circuit 15 to obtain a boosted DC voltage. This boosted DC voltage is then inverted by the inverter circuit 13 to obtain an AC voltage, which is then applied to the load to drive it.

[0053] Please see Figure 3 The DC-DC conversion circuit 15 includes a bridge inverter circuit 151, a resonant circuit 152, and a bridge rectifier circuit 153. The bridge inverter circuit 151 inverts the DC power output from the battery 16 into AC power. The resonant circuit 152 resonates the power output from the bridge inverter circuit 151, outputting a sine wave power supply. The bridge rectifier circuit 153 rectifies the sine wave power supply, outputting DC power.

[0054] Please combine Figure 2 The bridge inverter circuit 151 includes a first inverter Q7, a second inverter Q8, a third inverter Q9, and a fourth inverter Q10. The first inverter Q7 and the third inverter Q9 are connected in series and then electrically connected between a preset first parallel node N1 and a preset second parallel node N2. The second inverter Q8 and the fourth inverter Q10 are connected in series and then electrically connected between the first parallel node and the second parallel node. The controller 18 is electrically connected to the first inverter Q7, the second inverter Q8, the third inverter Q9, and the fourth inverter Q10 respectively. The controller 18 controls the switching states of the first inverter Q7, the second inverter Q8, the third inverter Q9, and the fourth inverter Q10 according to the inverter mode, to invert the DC power supply from the battery 16 into AC pulses.

[0055] Please combine Figure 2The resonant circuit 152 is electrically connected between the first parallel node N1 and the second parallel node N2. The resonant circuit 152 includes a resonant coil S1, a second capacitor C2, a resonant inductor L3, and a magnetizing inductor (not shown). The resonant coil S1, the second capacitor C2, the resonant inductor L3, and the magnetizing inductor work together to resonate the AC pulse and output a sinusoidal power supply.

[0056] Please combine Figure 2 One end of the bridge rectifier circuit 153 is electrically connected to the resonant circuit 152, and the other end of the bridge rectifier circuit 153 is electrically connected to the other end of the second switching switch 14. The bridge rectifier circuit 153 includes a first rectifier tube Q11, a second rectifier tube Q12, a third rectifier tube Q13, and a fourth rectifier tube Q14. The controller 18 controls the switching states of the first rectifier tube Q11, the second rectifier tube Q12, the third rectifier tube Q13, and the fourth rectifier tube Q14 according to the rectification mode, so as to rectify the sine wave power supply into DC power supply.

[0057] The battery 16 provides DC power when the UPS device 100 enters battery operation mode. This DC power is processed by the DC-DC conversion circuit 15 to output battery voltage. The battery voltage is transmitted to the power factor correction circuit 12 via the second switching switch 14 for boosting and power factor correction, and then inverted by the main inverter circuit 13 to obtain AC voltage Vout. The main inverter circuit 13 transmits the AC voltage Vout to the load.

[0058] The sampling circuit 17 is electrically connected to the main inverter circuit 13 and is used to sample the first bus voltage output by the main inverter circuit. In some embodiments, the sampling circuit 17 is a circuit consisting of one or more resistors. In other embodiments, the sampling circuit 17 is a circuit consisting of a resistor and a capacitor. In still other embodiments, the sampling circuit 17 is a Hall sensor or other type of sensor.

[0059] The controller 18 is electrically connected to the first switching switch 11, the power factor correction circuit 12, the main inverter circuit 13, the second switching switch 14, the DC-DC conversion circuit 15, the battery 16, and the sampling circuit 17. The controller 18 serves as the control core of the UPS equipment 100, used to control the operating status of the UPS equipment 100 and handle various tasks.

[0060] The following embodiments of this application provide a UPS device protection method, wherein the UPS device is the UPS device described in the above embodiments. Please refer to... Figure 4 The protection method includes steps S41 to S44.

[0061] In this embodiment of the application, step S41 is performed to obtain the first bus voltage applied to the main inverter circuit.

[0062] In this embodiment, the control sampling circuit samples the main inverter circuit to obtain the first bus voltage. Please refer to... Figure 2 In this embodiment, the voltage across the first capacitor C1 is sampled to obtain the first bus voltage. In some embodiments, this embodiment does not need to distinguish the operating mode of the UPS equipment; it controls the sampling circuit to sample the first bus voltage output by the main inverter circuit according to a preset frequency. In other embodiments, this embodiment determines the target operating mode of the UPS equipment. Responding to the target operating mode being battery operating mode, it controls the sampling circuit to sample the first bus voltage output by the main inverter circuit. Thus, this embodiment does not need to continuously control the sampling circuit to sample the first bus voltage output by the main inverter circuit, saving energy.

[0063] This application embodiment obtains mode marking information and determines the target operating mode of the UPS device based on the mode marking information. The mode marking information includes first marking information and second marking information. The first marking information indicates that the UPS device is operating in battery operation mode, and the second marking information indicates that the UPS device is operating in AC power operation mode. If the mode marking information is the first marking information, the target operating mode is battery operation mode. If the mode marking information is the second marking information, the target operating mode is AC power operation mode.

[0064] When the UPS does not detect the input of mains power, the UPS generates a first flag; when the UPS detects the input of mains power, the UPS generates a second flag.

[0065] In the embodiment of this application, step S42 is executed. In response to the first bus voltage being less than or equal to the first voltage threshold, the main inverter circuit is controlled to perform a current limiting operation to reduce the output current of the main inverter circuit.

[0066] In some embodiments, the present application implements a method to control the main inverter circuit to maintain normal operation in response to the first bus voltage being greater than a first voltage threshold.

[0067] The first voltage threshold is defined by the designer based on engineering experience.

[0068] The first voltage threshold cannot be selected too low. For example, if the first voltage threshold is 200V, the first bus voltage needs to drop below 200V for the main inverter circuit to perform current limiting operation. However, the voltage difference between the battery voltage and the first bus voltage at this time is large. For example, if the battery voltage is 260V, the voltage difference between the battery voltage and the first bus voltage is 60V. The equivalent resistance between the DC-DC conversion circuit 15 and the power factor correction circuit 12 is small. Under the action of a 60V voltage difference, the current flowing through the DC-DC conversion circuit 15 and the power factor correction circuit 12 is as high as 15A. That is, a 60V voltage difference is enough to generate a large current. A large current can easily damage the circuit components of the UPS equipment. For example, a current of 15A can easily damage the switching transistors of the DC-DC conversion circuit 15 or the power factor correction circuit 12. Therefore, when the first voltage threshold is selected too low, the present application embodiment cannot protect the UPS equipment in a timely manner.

[0069] The first voltage threshold should not be too high. For example, if the first voltage threshold is 350V, the first bus voltage can reach 380V during normal operation. The first voltage threshold will affect the first bus voltage above 350V. When the first bus voltage is greater than 350V, this embodiment of the application needs to limit the first bus voltage to be lower than 350V. This can easily cause the waveform of the first bus voltage to be clipped, and it cannot form a relatively normal sine wave, affecting the quality of the output waveform.

[0070] In some embodiments, the first voltage threshold is any value between [310V, 330V], for example, the first voltage threshold is 320V.

[0071] Current limiting operation refers to the operation of reducing the output current of the main inverter circuit. In the embodiments of this application, the duty cycle of the PWM signal used to control the switching transistors of the main inverter circuit (e.g., any one of the third switching transistors Q3 to the sixth switching transistor Q6) can be reduced, thereby achieving the purpose of reducing the output current of the main inverter circuit. For example, under normal conditions, the output current of the main inverter circuit is 10A, and the duty cycle of the switching transistors acting on the main inverter circuit is 60%. After the current limiting operation, the duty cycle of the switching transistors acting on the main inverter circuit is adjusted to 15%, and the output current of the main inverter circuit is 2.5A.

[0072] Assuming the UPS equipment switches from AC power operation mode to battery operation mode:

[0073] ① Under normal circumstances where the voltage of the first bus is greater than the first voltage threshold.

[0074] The DC-DC converter outputs battery voltage to the power factor correction circuit in normal operating mode. The power factor correction circuit performs boosting and power factor correction on the battery voltage, thereby increasing the voltage across the first capacitor C1 (i.e., the bus voltage). After the bus voltage is inverted by the main inverter circuit, it becomes AC voltage, which is then applied to the load.

[0075] ② Abnormal situation where the voltage of the first bus is less than or equal to the first voltage threshold.

[0076] Even if the controller detects an abnormality due to a low first bus voltage, the DC-DC converter circuit uses open-loop control instead of closed-loop control. Therefore, the controller cannot control the DC-DC converter circuit to reduce the battery voltage to prevent high current. Consequently, the DC-DC converter circuit continues to output battery voltage to the power factor correction circuit according to normal operating mode. In this situation, without protective measures, the voltage difference between the battery voltage and the first bus voltage becomes too large, easily leading to high current. High current can easily damage the switching transistors of the DC-DC converter circuit or the power factor correction circuit. To avoid high current, the controller controls the main inverter circuit to perform current limiting operation. Please refer to... Figure 2 After the current limiting operation, the output current of the main inverter circuit is reduced, that is, the current drawn by the load from the first capacitor C1 is reduced. Since the current output by the first capacitor C1 is reduced and the battery voltage provided by the DC-DC conversion circuit remains unchanged, the voltage across the first capacitor C1 (i.e., the bus voltage) will gradually increase under the influence of the battery voltage.

[0077] In this embodiment of the application, step S43 is performed to obtain the second bus voltage applied to the main inverter circuit after the current limiting operation.

[0078] After the main inverter circuit undergoes a current-limiting operation, the sampling circuit in this embodiment continues to sample the applied bus voltage of the main inverter circuit to obtain the second bus voltage. As mentioned above, the second bus voltage output by the main inverter circuit is higher than the first bus voltage compared to the first bus voltage.

[0079] In the embodiment of this application, step S44 is executed: in response to the second bus voltage being greater than or equal to the second voltage threshold, the main inverter circuit is controlled to perform a current recovery operation to restore the output current of the main inverter circuit to the normal current.

[0080] Current recovery operation refers to the operation of restoring the output current of the main inverter circuit to the normal current. In this embodiment, the duty cycle of the PWM signal used to control the switching transistor of the main inverter circuit is increased, thereby achieving the purpose of restoring the output current of the main inverter circuit. For example, after the current limiting operation, the output current of the main inverter circuit is 2.5A. In this embodiment, the duty cycle of the PWM signal is increased so that the output current of the main inverter circuit is 10A.

[0081] The second voltage threshold is greater than the first voltage threshold. The second voltage threshold is any value between [320V, 340V]. For example, the second voltage threshold is 330V.

[0082] If the second voltage threshold is equal to the first voltage threshold, the main inverter circuit may switch back and forth between current limiting and current recovery operations. For example, as mentioned earlier, when the first bus voltage is below 320V (i.e., the first voltage threshold), this embodiment requires the main inverter circuit to perform a current limiting operation. After the current limiting operation, the bus voltage will gradually rise. When the second bus voltage is greater than 320V (i.e., the second voltage threshold), this embodiment requires the main inverter circuit to perform a current recovery operation. Therefore, when the second bus voltage fluctuates around 320V and is unstable, this embodiment requires the main inverter circuit to switch back and forth between current limiting and current recovery operations, which can easily damage the switching transistors of the main inverter circuit.

[0083] When the second voltage threshold is greater than the first voltage threshold, and the second bus voltage fluctuates unstablely around 320V, this embodiment of the application does not require controlling the main inverter circuit to perform a current recovery operation. Only when the second bus voltage is greater than 330V (i.e., the second voltage threshold) can this embodiment control the main inverter circuit to perform a current recovery operation. This avoids frequent switching of the main inverter circuit's switching transistors and improves their lifespan.

[0084] In general, when the applied bus voltage to the main inverter circuit drops rapidly, causing the first bus voltage of the main inverter circuit to fall below the first voltage threshold, the embodiments of this application can quickly limit the output current of the main inverter circuit. As the output current of the main inverter circuit decreases, the applied bus voltage to the main inverter circuit gradually rises, thereby reducing the voltage difference between the bus voltage and the battery voltage provided by the battery. This reduces the current flowing through the DC-DC conversion circuit, the second switching switch, the power factor correction circuit, and the main inverter circuit, preventing damage to the DC-DC conversion circuit, the power factor correction circuit, or the switching transistors of the main inverter circuit due to excessive current, thus improving the operational reliability and safety of the UPS equipment. When the second bus voltage of the main inverter circuit exceeds the second voltage threshold, the embodiments of this application restore the output current of the main inverter circuit.

[0085] As mentioned earlier, regardless of the value to which the first bus voltage drops, as long as the first bus voltage is less than the first voltage threshold, the embodiments of this application require controlling the main inverter circuit to perform a current limiting operation. In this case, during the current limiting operation, regardless of the value to which the first bus voltage drops, the output current of the main inverter circuit is limited to a fixed value. This can easily lead to a mismatch between the first bus voltage and the limited output current of the main inverter circuit. For example, under normal circumstances, the output current of the main inverter circuit is 10A, and the waveform of the output voltage is a sine wave.

[0086] In one scenario, the first bus voltage is 300V, lower than the first voltage threshold of 320V. In this embodiment, the output current of the main inverter circuit is limited to 2.5A. In another scenario, the first bus voltage is 280V, lower than the first voltage threshold of 320V. In this embodiment, the output current of the main inverter circuit is also limited to 2.5A. Compared to the normal output voltage, the waveform of the output voltage in the "first scenario with a first bus voltage of 300V" is approximately a sine wave, while the waveform of the output voltage in the "second scenario with a first bus voltage of 280V" differs significantly from a sine wave. If the output current of the main inverter circuit is limited to 2.5A in both scenarios, this approach is unreasonable for the first scenario.

[0087] Understandably, in the first scenario, the voltage drop of the first bus is relatively small compared to the normal bus voltage. The embodiments of this application can provide the load with an output power formed by an output current of 8A or 9A and a first bus voltage of 300V, ensuring that the UPS equipment can provide the load with an output power close to the normal power. However, the above approach limits the output current of the main inverter circuit to 2.5A, which causes the UPS equipment to be unable to provide the load with an output power close to the normal power, thus reducing the power supply efficiency.

[0088] In the second scenario, if the output power is supplied to the load with an output current of 8A or 9A and a first bus voltage of 280V, the first bus voltage has already dropped too much compared to the normal bus voltage. If the output current is still supplied to the load at 8A or 9A, the load will draw a large current from the main inverter circuit side. This will cause the bus voltage of the main inverter circuit to be unable to reach the normal bus voltage for a long time, which will in turn cause the main inverter circuit to be unable to supply power to the load normally.

[0089] This application embodiment sets at least two current limiting modes, and flexibly selects the appropriate current limiting mode to perform current limiting operation based on the first bus voltage. Specifically, responding to the first bus voltage being less than or equal to a first voltage threshold, controlling the main inverter circuit to perform current limiting operation to reduce the output current of the main inverter circuit includes the following steps: responding to the first bus voltage being less than or equal to the first voltage threshold, determining the current limiting mode matching the first bus voltage as the target current limiting mode among the at least two preset current limiting modes, and controlling the main inverter circuit to perform current limiting operation to reduce the output current of the main inverter circuit based on the target current limiting mode.

[0090] The current limiting mode restricts the output current of the main inverter circuit according to predetermined rules. At least two current limiting modes are included: a first type of current limiting mode and a second type of current limiting mode. The first type of current limiting mode restricts the output current of the main inverter circuit to a specified current limiting value, while the second type of current limiting mode controls the main inverter circuit to stop operating. In this embodiment, based on the first bus voltage, an appropriate current limiting mode is adaptively selected as the target current limiting mode. Then, based on the target current limiting mode, the main inverter circuit is controlled to perform current limiting operations. This ensures that the main inverter circuit can provide maximum output power to the load while preventing the bus voltage of the main inverter circuit from remaining in an abnormal state for an extended period, thus efficiently restoring the bus voltage of the main inverter circuit to a normal bus voltage as quickly as possible.

[0091] Responding to a first bus voltage being less than or equal to a first voltage threshold, determining a current limiting mode matching the first bus voltage as the target current limiting mode among at least two preset current limiting modes includes the following steps: responding to a first bus voltage being less than or equal to the first voltage threshold, detecting whether the first bus voltage is less than or equal to a third voltage threshold, wherein the third voltage threshold is less than the first voltage threshold; if the first bus voltage is greater than the third voltage threshold and less than or equal to the first voltage threshold, determining a first type of current limiting mode as the target current limiting mode among at least two preset current limiting modes; if the first bus voltage is less than or equal to the third voltage threshold, determining a second type of current limiting mode as the target current limiting mode among at least two preset current limiting modes.

[0092] When the main inverter circuit has a first bus voltage greater than the third voltage threshold and less than the first voltage threshold, it indicates that the first bus voltage is not significantly deviating from the normal bus voltage. Therefore, this embodiment enters the first type of current limiting mode and does not use a fixed value to limit the output current of the main inverter circuit. Instead, it adaptively selects an appropriate current limiting value to limit the output current of the main inverter circuit based on the first bus voltage. This ensures that the main inverter circuit can output maximum power to the load.

[0093] When the main inverter circuit's first bus voltage is less than or equal to the third voltage threshold, it indicates that the first bus voltage has deviated significantly from the normal bus voltage. Therefore, in this embodiment, the main inverter circuit enters the second type of current limiting mode, controlling the main inverter circuit to stop working, so that the main inverter circuit's bus voltage can quickly recover to the normal bus voltage. This can prevent the main inverter circuit's bus voltage from being in an abnormal state for a long time, thereby ensuring that the main inverter circuit can efficiently provide normal power to the load.

[0094] In some embodiments, controlling the main inverter circuit to perform a current-limiting operation to reduce the output current of the main inverter circuit based on a target current-limiting mode includes the following steps: responding to the target current-limiting mode being a first type of current-limiting mode, determining the current-limiting value, and controlling the main inverter circuit to output a target current consistent with the current-limiting value. The embodiments of this application can flexibly determine the current-limiting value under the first type of current-limiting mode, thus ensuring that the main inverter circuit outputs maximum power to the load.

[0095] When the target current limiting mode is the first type of current limiting mode, the current limiting value is determined by the following steps: When the target current limiting mode is the first type of current limiting mode, the first bus voltage is used as the input of the preset current limiting model so that the current limiting model outputs the current limiting value.

[0096] The current limiting model uses one or more of the following functional relationships to express the relationship between the first bus voltage and the current limiting value: monotonically increasing, linearly increasing, step-increasing, or exponentially increasing.

[0097] In some embodiments, controlling the main inverter circuit to perform current limiting operations to reduce the output current of the main inverter circuit based on the target current limiting mode includes the following steps: responding to the target current limiting mode being a second type of current limiting mode, controlling the main inverter circuit to stop working. In this embodiment, controlling the main inverter circuit to stop working under the second type of current limiting mode allows the bus voltage of the main inverter circuit to quickly recover to the normal bus voltage, ensuring that the main inverter circuit can quickly provide normal power to the load.

[0098] To illustrate in detail the UPS device protection method provided in the embodiments of this application, the embodiments of this application are combined with... Figure 5 This will be explained in detail, and the specific process is as follows:

[0099] S51, obtain the first bus voltage applied to the main inverter circuit.

[0100] S52, determine whether the voltage of the first bus is less than or equal to the first voltage threshold. If it is less than or equal to the first voltage threshold, execute S53. If it is greater than the first voltage threshold, execute S59.

[0101] S53, determine whether the voltage of the first bus is less than or equal to the third voltage threshold. If it is greater than, execute S54; if it is less than or equal to, execute S510.

[0102] S54, determine the first type of rate limiting mode as the target rate limiting mode among at least two preset rate limiting modes, and execute S55.

[0103] S55, based on the target current limiting mode, controls the main inverter circuit to perform current limiting operation to reduce the output current of the main inverter circuit, and executes S56.

[0104] S56: Obtain the second bus voltage applied to the main inverter circuit after the current limiting operation, and execute S57.

[0105] S57, determine whether the second bus voltage is greater than or equal to the second voltage threshold. If it is greater than or equal to the threshold, proceed to S58. If it is less than the threshold, return to S55.

[0106] S58 controls the main inverter circuit to perform a current recovery operation to restore the output current of the main inverter circuit to the normal current.

[0107] S59 controls the main inverter circuit to maintain normal operation.

[0108] S510, determine the second type of rate limiting mode as the target rate limiting mode among at least two preset rate limiting modes, and execute S55.

[0109] The embodiments of this application can not only quickly and reliably restore the bus voltage of the main inverter circuit to the normal bus voltage in the event of a rapid drop in the first bus voltage, but also, during the recovery period, take into account the situation where the main inverter circuit faces a drop in the first bus voltage, and can also maximize the output power to the load.

[0110] It should be noted that in the above embodiments, there is no necessarily a certain order between the steps. Those skilled in the art can understand from the description of the embodiments of this application that the above steps may have different execution orders in different embodiments, that is, they may be executed in parallel or in turn, etc.

[0111] As another aspect of the embodiments of this application, this application provides a UPS equipment protection device. The UPS equipment protection device can be a software module, which includes several instructions stored in a memory. A processor can access the memory, call the instructions, and execute them to complete the UPS equipment protection method described in the various embodiments above.

[0112] In some implementations, the UPS equipment protection device can also be constructed from hardware components. For example, the UPS equipment protection device can be constructed from one or more chips, which can work in coordination to complete the UPS equipment protection method described in the various implementations above. As another example, the UPS equipment protection device can also be constructed from various logic devices, such as general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), microcontrollers, ARM (Acorn RISC Machine) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination of these components.

[0113] Please see Figure 6 The UPS equipment protection device 600 includes a first voltage acquisition module 61, a current limiting operation module 62, a second voltage acquisition module 63, and a current recovery module 64.

[0114] The first voltage acquisition module 61 is used to acquire the first bus voltage applied to the main inverter circuit. The current limiting operation module 62 is used to control the main inverter circuit to perform a current limiting operation to reduce the output current of the main inverter circuit when the first bus voltage is less than or equal to a first voltage threshold. The second voltage acquisition module 63 is used to acquire the second bus voltage applied to the main inverter circuit after the current limiting operation. The current recovery module 64 is used to control the main inverter circuit to perform a current recovery operation to restore the output current of the main inverter circuit to normal current when the second bus voltage is greater than or equal to a second voltage threshold, wherein the second voltage threshold is greater than the first voltage threshold.

[0115] In the event of a rapid drop in the first bus voltage of the UPS equipment, this embodiment can quickly limit the output current of the main inverter circuit to gradually increase the applied bus voltage to the main inverter circuit. The voltage difference between the bus voltage and the battery voltage provided by the battery reduces the current flowing through the DC-DC conversion circuit, the second switching switch, the power factor correction circuit, and the main inverter circuit, thereby preventing damage to the switching transistors of the DC-DC conversion circuit, the power factor correction circuit, or the main inverter circuit due to excessive current, and thus improving the operational reliability and safety of the UPS equipment.

[0116] In some embodiments, the current limiting operation module 62 is specifically used to: respond to a first bus voltage being less than or equal to a first voltage threshold, determine a current limiting mode that matches the first bus voltage as a target current limiting mode among at least two preset current limiting modes, and control the main inverter circuit to perform a current limiting operation to reduce the output current of the main inverter circuit based on the target current limiting mode.

[0117] In some embodiments, at least two current limiting modes include a first type of current limiting mode and a second type of current limiting mode. The current limiting operation module 62 is specifically used to: respond to a first bus voltage being less than or equal to a first voltage threshold; detect whether the first bus voltage is less than or equal to a third voltage threshold; if the third voltage threshold is less than the first voltage threshold; if the first bus voltage is greater than the third voltage threshold and less than or equal to the first voltage threshold; determine the first type of current limiting mode as the target current limiting mode among at least two preset current limiting modes; the first type of current limiting mode is a mode that limits the output current of the main inverter circuit to a specified current limiting value; if the first bus voltage is less than or equal to the third voltage threshold; determine the second type of current limiting mode as the target current limiting mode among at least two preset current limiting modes; the second type of current limiting mode is a mode that controls the main inverter circuit to stop working.

[0118] In some embodiments, at least two current limiting modes include a first type of current limiting mode. The current limiting operation module 62 is specifically used to: respond to the target current limiting mode being the first type of current limiting mode, determine the current limiting value, and control the main inverter circuit to output a target current that is consistent with the current limiting value.

[0119] In some embodiments, the current limiting operation module 62 is specifically used to: respond to the target current limiting mode being the first type of current limiting mode, and use the first bus voltage as the input of a preset current limiting model so that the current limiting model outputs a current limiting value.

[0120] In some embodiments, at least two current limiting modes include a second type of current limiting mode, and the current limiting operation module 62 is specifically used to: respond to the target current limiting mode being the second type of current limiting mode, and control the main inverter circuit to stop working.

[0121] In some embodiments, the first voltage acquisition module 61 is specifically used to: determine the target operating mode of the UPS device, respond to the target operating mode as battery operating mode, and control the sampling circuit to sample the first bus voltage applied to the main inverter circuit.

[0122] It should be noted that the above-mentioned UPS equipment protection device can execute the UPS equipment protection method provided in the embodiments of this application, and has the corresponding functional modules and beneficial effects of the method. Technical details not described in detail in the embodiments of the UPS equipment protection device can be found in the UPS equipment protection method provided in the embodiments of this application.

[0123] See Figure 7 , Figure 7 This is a schematic diagram of a controller provided in an embodiment of this application. The controller 700 includes one or more processors 71 and a memory 72. The memory 72 is connected to one or more processors 71, for example, via a bus.

[0124] Processor 71 is configured to support the controller in performing the corresponding functions in the methods described in the above method embodiments. Processor 71 may be a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof. The aforementioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The aforementioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0125] Memory 72 is used to store program code, etc. Memory 72 may include volatile memory (VM), such as random access memory (RAM); memory may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD); memory may also include combinations of the above types of memory.

[0126] The memory 72 can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the UPS equipment protection method in the embodiments of this application. The processor executes various functional applications and data processing of the UPS equipment protection method and UPS equipment protection device by running the non-volatile software programs, instructions, and modules stored in the memory, thereby realizing the functions of each module or unit of the UPS equipment protection method and UPS equipment protection device provided in the above method embodiments.

[0127] The memory 72 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function. The data storage area may store data created based on the use of the UPS equipment protection device. In some embodiments, the memory may optionally include memory remotely configured relative to the processor, which can be connected to the UPS equipment protection device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0128] The one or more modules are stored in the memory. When executed by the one or more processors, they perform the UPS equipment protection method in any of the above method embodiments. For example, they perform the method steps described in the above method embodiments to realize the functions of the modules described in the above device embodiments.

[0129] This application also provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a controller, cause the controller to perform the method described in the foregoing embodiments.

[0130] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0131] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A UPS equipment protection method, characterized in that, The UPS equipment includes a first switching switch, a power factor correction circuit, a main inverter circuit, a second switching switch, a DC-DC conversion circuit, a battery, a sampling circuit, and a controller. The first switching switch, the power factor correction circuit, and the main inverter circuit are electrically connected in sequence. The second switching switch is electrically connected between the power factor correction circuit and the DC-DC conversion circuit. The DC-DC conversion circuit is electrically connected to the battery. The sampling circuit is electrically connected to the main inverter circuit. The controller is electrically connected to the first switching switch, the power factor correction circuit, the main inverter circuit, the second switching switch, the DC-DC conversion circuit, and the sampling circuit. The protection method includes: Obtain the first bus voltage applied to the main inverter circuit; In response to the first bus voltage being less than or equal to a first voltage threshold, the main inverter circuit is controlled to perform a current limiting operation to reduce the output current of the main inverter circuit; Obtain the second bus voltage applied to the main inverter circuit after the current limiting operation; In response to the second bus voltage being greater than or equal to the second voltage threshold, the main inverter circuit is controlled to perform a current recovery operation to restore the output current of the main inverter circuit to the normal current, wherein the second voltage threshold is greater than the first voltage threshold.

2. The protection method according to claim 1, characterized in that, The step of controlling the main inverter circuit to perform a current limiting operation to reduce the output current of the main inverter circuit in response to the first bus voltage being less than or equal to a first voltage threshold includes: In response to the first bus voltage being less than or equal to a first voltage threshold, a current limiting mode matching the first bus voltage is determined as the target current limiting mode among at least two preset current limiting modes. Based on the target current limiting mode, the main inverter circuit is controlled to perform a current limiting operation to reduce the output current of the main inverter circuit.

3. The protection method according to claim 2, characterized in that, At least two current limiting modes include a first type of current limiting mode and a second type of current limiting mode. The step of determining the current limiting mode matching the first bus voltage as the target current limiting mode among the preset at least two current limiting modes in response to the first bus voltage being less than or equal to a first voltage threshold includes: In response to the first bus voltage being less than or equal to a first voltage threshold, it is detected whether the first bus voltage is less than or equal to a third voltage threshold, wherein the third voltage threshold is less than the first voltage threshold; If the voltage of the first bus is greater than the third voltage threshold and less than or equal to the first voltage threshold, the first type of current limiting mode is determined as the target current limiting mode among at least two preset current limiting modes. The first type of current limiting mode is a mode that limits the output current of the main inverter circuit to a specified current limiting value. If the voltage of the first bus is less than or equal to the third voltage threshold, the second type of current limiting mode is determined as the target current limiting mode among at least two preset current limiting modes. The second type of current limiting mode is the mode that controls the main inverter circuit to stop working.

4. The protection method according to claim 2, characterized in that, At least two current limiting modes include a first type of current limiting mode, and controlling the main inverter circuit to perform a current limiting operation to reduce the output current of the main inverter circuit based on the target current limiting mode includes: If the target rate limiting mode is identified as the first type of rate limiting mode, the rate limiting value is determined. The main inverter circuit is controlled to output a target current that matches the current limiting value.

5. The protection method according to claim 4, characterized in that, The response indicates that the target rate limiting mode is a first-type rate limiting mode, and the rate limiting value is determined by: In response to the target current limiting mode being the first type of current limiting mode, the first bus voltage is used as the input of a preset current limiting model so that the current limiting model outputs a current limiting value.

6. The protection method according to claim 2, characterized in that, At least two current limiting modes include a second type of current limiting mode. The step of controlling the main inverter circuit to perform a current limiting operation to reduce the output current of the main inverter circuit based on the target current limiting mode includes: controlling the main inverter circuit to stop working in response to the target current limiting mode being the second type of current limiting mode.

7. The protection method according to any one of claims 1 to 6, characterized in that, The step of obtaining the first bus voltage applied to the main inverter circuit includes: Determine the target operating mode of the UPS equipment; In response to the target operating mode being battery operating mode, the sampling circuit is controlled to sample the first bus voltage applied to the main inverter circuit.

8. A controller, characterized in that, The device includes a memory and a processor, the memory being connected to the processor, the processor being configured to execute one or more computer programs stored in the memory, and the processor, when executing the one or more computer programs, causing the controller to implement the UPS device protection method as described in any one of claims 1-7.

9. A UPS device, characterized in that, The device includes a first switching switch, a power factor correction circuit, a main inverter circuit, a second switching switch, a DC-DC conversion circuit, a battery, a sampling circuit, and a controller as described in claim 8. The first switching switch, the power factor correction circuit, and the main inverter circuit are electrically connected in sequence. The second switching switch is electrically connected between the power factor correction circuit and the DC-DC conversion circuit. The DC-DC conversion circuit is electrically connected to the battery. The sampling circuit is electrically connected to the main inverter circuit. The controller is electrically connected to the first switching switch, the power factor correction circuit, the main inverter circuit, the second switching switch, the DC-DC conversion circuit, and the sampling circuit.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, cause the processor to perform the UPS equipment protection method as described in any one of claims 1-7.

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