MOS tube driving circuit and power converter

Abstract

The utility model discloses an MOS tube driving circuit and a power converter. The MOS tube driving circuit comprises a voltage division circuit, a pull-down control circuit, a pull-down circuit and a push-pull circuit. The input end of the voltage division circuit is electrically connected with the pulse width modulation end, and the output end of the voltage division circuit and the control end of the push-pull circuit are electrically connected to a first node; the control end of the pull-down control circuit is electrically connected with the pulse width modulation end, the first input end of the pull-down control circuit is electrically connected with the first power supply end, and the second input end of the pull-down control circuit is electrically connected with the second power supply end; the output end of the pull-down control circuit is electrically connected with the control end of the pull-down circuit; the input end of the pull-down circuit is electrically connected with the second power supply end, and the output end of the pull-down circuit is electrically connected to the first node; the first input end of the push-pull circuit is electrically connected with the first power supply end, the second input end of the push-pull circuit is electrically connected with the second power supply end, and the output end of the push-pull circuit and the grid electrode of the MOS tube are coupled at a second node; according to the technical scheme, the MOS tube can be stably driven.

Description

Technical Field

[0001] The utility model relates to the technical field of power electronics, and in particular to a MOS tube driving circuit and a power converter. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a MOS tube. Since the MOS tube includes a gate, a source and a drain, its drain current can be controlled by controlling its gate voltage to achieve switching or amplification functions, making MOS tubes widely used in electronic circuits, such as amplifier circuits, switching circuits and power supply regulation.

[0003] However, when MOS tubes are used as core power devices in electronic circuits, the driving protection of MOS tubes is particularly important. In high-voltage and high-current application scenarios, the instantaneous on- or off-voltage dv / dt and the current di / dt flowing through the MOS tube will produce huge interference spikes. This interference spike will cause the MOS tube to work abnormally, and then cause the circuit to work abnormally, directly damaging the entire circuit system. Utility Model Content

[0004] The embodiment of the utility model provides a MOS tube driving circuit and a power converter, which can provide a stable driving voltage for the MOS tube and improve the working safety and reliability of the MOS tube.

[0005] In a first aspect, an embodiment of the utility model provides a MOS tube driving circuit, the MOS tube driving circuit comprising: a voltage divider circuit, a pull-down control circuit, a pull-down circuit and a push-pull circuit;

[0006] The input end of the voltage divider circuit is electrically connected to the pulse width modulation end, and the output end of the voltage divider circuit is electrically connected to the control end of the push-pull circuit at a first node;

[0007] The control end of the pull-down control circuit is electrically connected to the pulse width modulation end, the first input end of the pull-down control circuit is electrically connected to the first power supply end, and the second input end of the pull-down control circuit is electrically connected to the second power supply end; the output end of the pull-down control circuit is electrically connected to the control end of the pull-down circuit;

[0008] The input end of the pull-down circuit is electrically connected to the second power supply end, and the output end of the pull-down circuit is electrically connected to the first node;

[0009] The first input end of the push-pull circuit is electrically connected to the first power supply end, the second input end of the push-pull circuit is electrically connected to the second power supply end, and the output end of the push-pull circuit is coupled to the gate of the MOS tube at a second node;

[0010] The polarities of the pulse width modulation signal at the pulse width modulation end, the signal at the first node, and the signal at the second node are the same.

[0011] Optionally, the voltage-dividing circuit includes a first voltage-dividing resistor;

[0012] The first end of the first voltage-dividing resistor is electrically connected to the pulse width modulation end, and the second end of the first voltage-dividing resistor is electrically connected to the first node.

[0013] Optionally, the pull-down control circuit includes a first transistor and a second voltage-dividing resistor;

[0014] The first end of the second voltage-dividing resistor is electrically connected to the first power supply end, and the second end of the second voltage-dividing resistor is electrically connected to the first electrode of the first transistor at a third node;

[0015] The gate of the first transistor is electrically connected to the pulse width modulation terminal, and the second electrode of the first transistor is electrically connected to the second power supply terminal;

[0016] Wherein, the control end of the pull-down circuit is electrically connected to the third node.

[0017] Optionally, the pull-down circuit includes a second transistor;

[0018] A gate of the second transistor is electrically connected to the output terminal of the pull-down control circuit, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the second power supply terminal.

[0019] Optionally, the push-pull circuit includes a third transistor and a fourth transistor;

[0020] The gate of the third transistor and the gate of the fourth transistor are both electrically connected to the first node; the first electrode of the third transistor is electrically connected to the first power supply terminal, the second electrode of the third transistor and the second electrode of the fourth transistor are electrically connected to the second node; the first electrode of the fourth transistor is electrically connected to the second power supply terminal;

[0021] The third transistor and the fourth transistor are of different types.

[0022] Optionally, the MOS tube driving circuit further includes: an isolation circuit;

[0023] The isolation circuit is electrically connected between the second node and the gate of the MOS tube.

[0024] Optionally, the isolation circuit includes an optocoupler isolation chip;

[0025] The optocoupler isolation chip includes a first input side pin, a second input side pin, a first output side pin, a second output side pin and a third output side pin; the first input side pin is coupled to the second node, the second input side pin is grounded, the first output side pin is electrically connected to the third power supply terminal, the second output side pin is grounded, and the third output side pin is coupled to the gate of the MOS tube.

[0026] Optionally, the MOS tube driving circuit further includes: a first filtering circuit;

[0027] The first filter circuit is electrically connected to the third power supply end.

[0028] Optionally, the MOS tube driving circuit further includes: a second filtering circuit;

[0029] The second filter circuit is electrically connected to the second node.

[0030] In a second aspect, an embodiment of the utility model further provides a power converter, which includes: a MOS tube and the MOS tube driving circuit described in the first aspect.

[0031] The technical solution of the utility model is to set a voltage divider circuit, a pull-down control circuit, a pull-down circuit and a push-pull circuit in a MOS tube driving circuit, and respectively connect the voltage divider circuit to the pulse width modulation end and the push-pull circuit, so that the voltage divider circuit can divide the pulse width modulation signal of the pulse width modulation end and transmit it to the first node electrically connected to the push-pull circuit; the pull-down control circuit is respectively electrically connected to the pulse width modulation end, the first power supply end, the second power supply end and the pull-down circuit, so that the pull-down control circuit can provide a pull-down control signal to the pull-down circuit according to the pulse width modulation signal of the pulse width modulation end; at the same time, the pull-down circuit is also electrically connected to the second power supply end and the first node, so that the pull-down circuit can control the signal of the first node according to the pull-down control signal provided by the pull-down control circuit; the push-pull circuit can control the signal coupled to the first node under the control of the signal of the first node. The signal at the second node of the gate of the MOS tube makes the signal at the second node consistent with the first power signal of the first power end or the second power signal of the second power end, so as to prevent the signal of the second node from being affected by the interference peak of voltage or current, and then affecting the signal of the first node, resulting in the fluctuation of the pulse width modulation signal at the pulse width modulation end. That is, the utility model can stabilize the signal of the second node through a simple circuit connection method, so as to accurately and stably drive the MOS tube, and improve the working safety and reliability of the MOS tube; in addition, through the above-mentioned circuit structure, the polarity of the pulse width modulation signal at the pulse width modulation end, the signal of the first node, and the signal of the second node can be the same, so as to simplify the driving method of the MOS tube driving circuit and improve the reliability of the MOS tube driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of a MOS tube driving circuit provided by an embodiment of the utility model;

[0033] Figure 2 A specific circuit diagram of a MOS tube driving circuit provided by an embodiment of the utility model;

[0034] Figure 3 A schematic diagram of another MOS tube driving circuit provided by an embodiment of the utility model;

[0035] Figure 4 A specific circuit diagram of another MOS tube driving circuit provided by an embodiment of the utility model. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the utility model clearer, the technical solution of the utility model will be fully described below in combination with the drawings in the embodiments of the utility model through specific implementation methods. Obviously, the described embodiments are part of the embodiments of the utility model, rather than all of the embodiments. Various modifications and changes can be made in the utility model without departing from the spirit or scope of the utility model, which is obvious to those skilled in the art. Therefore, the utility model is intended to cover modifications and changes of the utility model that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents.

[0037] Moreover, the words "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "one" or "the" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. In addition, the descriptions of the same, equal, etc. involved in the embodiments of the present disclosure do not mean that the two objects are completely equal in size and shape, and are allowed to be roughly the same or roughly equal within a certain error range.

[0038] It should be noted that the implementation methods provided in the embodiments of the present utility model can be combined with each other if there is no contradiction.

[0039] MOS tubes can be used in electronic circuits, for example, in power converters to control signal transmission in the power converters and ensure that the power converters can work safely and stably. Figure 1 As shown, the first electrode of the MOS tube Q0 can be electrically connected to the power supply terminal V0 to receive a larger power supply signal, and the second electrode of the MOS tube Q0 can be electrically connected to the charging device or the power-consuming device, so that when the MOS tube Q0 is turned on, the charging device can be controlled to charge the battery, or the power supply signal can be controlled to power the power-consuming device. At this time, the MOS tube Q0 serves as the core switching device of the power converter, and the stability and reliability of its opening or closing are one of the key factors to ensure that the power converter can work safely and reliably.

[0040] In view of this, the present invention provides a MOS tube driving circuit, such as Figure 1 As shown, the MOS transistor driving circuit includes: a voltage divider circuit 10, a pull-down control circuit 20, a pull-down circuit 30 and a push-pull circuit 40; the input terminal I10 of the voltage divider circuit 10 is electrically connected to the pulse width modulation terminal PWM, the output terminal O10 of the voltage divider circuit 10 and the control terminal C40 of the push-pull circuit 40 are electrically connected to the first node N1; the control terminal C20 of the pull-down control circuit 20 is electrically connected to the pulse width modulation terminal PWM, the first input terminal I21 of the pull-down control circuit 20 is electrically connected to the first power supply terminal V1, and the second input terminal I22 of the pull-down control circuit 20 is electrically connected to the second power supply terminal V2; the output terminal I10 of the pull-down control circuit 20 is electrically connected to the pulse width modulation terminal PWM, the output terminal I10 of the voltage divider circuit 10 and the control terminal C40 of the push-pull circuit 40 are electrically connected to the first node N1; the control terminal C20 of the pull-down control circuit 20 is electrically connected to the pulse width modulation terminal PWM, the first input terminal I21 of the pull-down control circuit 20 is electrically connected to the first power supply terminal V1, and the second input terminal I22 of the pull-down control circuit 20 is electrically connected to the second power supply terminal V2; The output terminal O20 is electrically connected to the control terminal C30 of the pull-down circuit 30; the input terminal I30 of the pull-down circuit 30 is electrically connected to the second power supply terminal V2, and the output terminal O30 of the pull-down circuit 30 is electrically connected to the first node N1; the first input terminal I41 of the push-pull circuit 40 is electrically connected to the first power supply terminal V1, the second input terminal I42 of the push-pull circuit 40 is electrically connected to the second power supply terminal V2, and the output terminal O40 of the push-pull circuit 40 is coupled to the gate of the MOS tube Q0 at the second node N2; wherein the pulse width modulation signal of the pulse width modulation terminal PWM, the signal of the first node N1, and the signal of the second node N2 have the same polarity.

[0041] Among them, the first power supply signal of the first power supply terminal V1 can be a positive power supply signal, and the positive power supply signal can include but is not limited to +5V; the second power supply signal of the second power supply terminal V2 can be a negative power supply signal, and the negative power supply signal can be equivalent to a ground signal. Under the premise that the core idea of ​​the embodiment of the utility model can be realized, the embodiment of the utility model does not limit the specific numerical values ​​of the first power supply signal and the second power supply signal. For the convenience of description, under the premise of no special limitation, the embodiment of the utility model takes the first power supply signal as a high-level positive power supply signal and the second power supply signal as a low-level negative power supply signal as an example to exemplarily illustrate the technical solution of the embodiment of the utility model.

[0042] Specifically, the pulse width modulation signal of the pulse width modulation terminal PWM may be provided by a controller or the like, and the pulse width modulation signal may be set to a high level and a low level that change in a specific cycle or a non-specific cycle according to actual needs. The voltage divider circuit 10 can divide the pulse width modulation signal of the pulse width modulation end PWM and provide it to the first node N1; the pull-down control circuit 20 can control the first power signal of the first power end V1 to be provided as a pull-down control signal to the control end C30 of the pull-down circuit 30 according to the pulse width modulation signal of the pulse width modulation end PWM, or control the second power signal of the second power end V2 to be provided as a pull-down control signal to the control end C30 of the pull-down circuit 30; the pull-down circuit 30 can determine whether to pull down the signal of the first node N1 under the control of the pull-down control signal received by its control end C30; the control end C40 of the push-pull circuit 40 is electrically connected to the first node N1, so that the push-pull circuit 40 can control the first power signal of the first power end V1 to be provided as a gate drive signal of the MOS transistor Q0 to the second node N2 according to the signal of the first node N1, or control the second power signal of the second power end V2 to be provided as a gate drive signal of the MOS transistor Q0 to the second node N2, so that the MOS transistor Q0 can be turned on or off according to the gate drive signal.

[0043] In an exemplary embodiment, when the pulse width modulation signal of the pulse width modulation end PWM is at a high level, the high level pulse width modulation signal can be transmitted to the first node N1 after being divided by the voltage divider circuit 10; at the same time, the pull-down control circuit 20 can provide the second power signal of the second power end V2 to the pull-down circuit 30 under the control of the high level pulse width modulation signal, so that the pull-down circuit 30 is in a closed state under the control of the low level second power signal, and the pull-down circuit 30 cannot pull down the signal of the first node N1, and the signal of the first node N1 remains at a high level after the voltage divider circuit 10 divides; the high level signal of the first node N1 can control the push-pull circuit 40 to provide the first power signal of the first power end V1 to the second node N2, so that the signal of the second node N2 can be consistent with the high level first power signal; at this time, the high level signal of the second node N2 can drive the MOS tube Q0 to be in an on state, so that M A path is formed between the power supply terminal V0 electrically connected to the MOS tube and the charging device or the power-consuming device; at the same time, since the signal of the second node N2 is consistent with the first power signal of the first power terminal V1, and the first power signal is usually a signal with a fixed voltage and has a strong ability to resist external interference, even if there is an instantaneous voltage or current interference spike at the MOS tube Q0, the signal of the second node N2 will not change with the interference spike, so that the signal of the second node N2 remains stable; when the signal of the second node N2 remains stable and has sufficient resistance to interference spikes, the signal of the first node N1 indirectly connected to the second node N2 and the pulse width modulation signal of the pulse width modulation terminal PWM will also remain stable and will not be affected by the interference spike, thereby ensuring that the pulse width modulation signal of the pulse width modulation terminal PWM has a high accuracy to prevent the pulse width modulation signal from fluctuating due to the interference spike, resulting in the MOS tube being shut down by mistake.

[0044] When the pulse width modulation signal of the pulse width modulation end PWM is at a low level, the low level pulse width modulation signal can control the pull-down control circuit 20 to provide the first power signal of the first power supply end V1 to the pull-down circuit 30, so that the pull-down circuit 30 is in an open state under the control of the high level first power signal, so that the pull-down circuit 30 can pull down the signal of the first node N1 to be consistent with the second power signal of the second power supply end V2, so that the first node N1 is a low level signal; the low level signal of the first node N1 can control the push-pull circuit 40 to provide the second power signal of the second power supply end V2 to the second node N2, so that the signal of the second node N2 can be consistent with the low level second power signal consistent; at this time, the low-level signal of the second node N2 can drive the MOS tube Q0 to be in a closed state, so that the end between the power supply terminal V0 electrically connected to the MOS tube and the charging device or the power-consuming device is opened; at the same time, since the signal of the second node N2 is consistent with the second power supply signal of the second power supply terminal V2, and the second power supply signal is usually a signal with a fixed voltage, it also has a strong ability to resist external interference. Therefore, based on the same principle as the first power supply signal of the first power supply terminal V1, at this time, it can also ensure that the pulse width modulation signal of the pulse width modulation terminal PWM has a high accuracy, so as to prevent the pulse width modulation signal from fluctuating due to the influence of interference spikes, resulting in the MOS tube being mistakenly turned on.

[0045] In addition, the polarities of the pulse width modulation signal of the pulse width modulation end PWM, the signal of the first node N1, and the signal of the second node N2 are the same, that is, when the pulse width modulation signal of the pulse width modulation end PWM is at a high level, the signal of the first node N1 and the signal of the second node N2 are also at a high level; conversely, when the pulse width modulation signal of the pulse width modulation end PWM is at a low level, the signal of the first node N1 and the signal of the second node N2 are also at a low level, so that when the MOS tube driving circuit provided by the embodiment of the utility model is used to drive the MOS tube, no complicated driving logic is required to ensure that the MOS tube is stably turned on or off.

[0046] In this embodiment, a voltage divider circuit, a pull-down control circuit, a pull-down circuit and a push-pull circuit are arranged in the MOS tube driving circuit, and the voltage divider circuit is electrically connected to the pulse width modulation end and the push-pull circuit respectively, so that the voltage divider circuit can divide the pulse width modulation signal of the pulse width modulation end and transmit it to the first node electrically connected to the push-pull circuit; the pull-down control circuit is electrically connected to the pulse width modulation end, the first power supply end, the second power supply end and the pull-down circuit respectively, so that the pull-down control circuit can provide a pull-down control signal to the pull-down circuit according to the pulse width modulation signal of the pulse width modulation end; at the same time, the pull-down circuit is also electrically connected to the second power supply end and the first node, so that the pull-down circuit can control the signal of the first node according to the pull-down control signal provided by the pull-down control circuit; the push-pull circuit can control the signal coupled to the MOS tube under the control of the signal of the first node. The signal at the second node of the gate is controlled so that the signal at the second node is consistent with the first power signal of the first power supply end or the second power signal of the second power supply end, so as to prevent the signal of the second node from being affected by the interference peak of voltage or current, and then affecting the signal of the first node, resulting in the fluctuation of the pulse width modulation signal at the pulse width modulation end. That is, the utility model can stabilize the signal of the second node through a simple circuit connection method, so as to accurately and stably drive the MOS tube, and improve the working safety and reliability of the MOS tube; in addition, through the above-mentioned circuit structure, the polarity of the pulse width modulation signal at the pulse width modulation end, the signal of the first node, and the signal of the second node can be the same, so as to simplify the driving method of the MOS tube driving circuit and improve the reliability of the MOS tube driving circuit.

[0047] It can be understood that, under the premise that the polarities of the pulse width modulation signal at the pulse width modulation end PWM, the signal at the first node N1, and the signal at the second node N2 are the same, and the MOS tube Q0 can be stably and reliably driven to turn on or off, the embodiment of the utility model does not limit the specific structure of each circuit. The following is an exemplary description of the technical solution of the utility model with reference to a typical circuit example.

[0048] Optional, such as Figure 2 As shown, the voltage dividing circuit 10 may include a first voltage dividing resistor R1; a first end of the first voltage dividing resistor R1 is electrically connected to the pulse width modulation end PWM, and a second end of the first voltage dividing resistor R1 is electrically connected to the first node N1.

[0049] The resistance value of the first voltage-dividing resistor R1 can determine the voltage-dividing capability of the first voltage-dividing resistor R1, thereby being able to control the voltage of the signal at the first node N1. In this embodiment, by making the voltage-dividing circuit 10 include the first voltage-dividing resistor R1, the circuit structure is simple, which is conducive to simplifying the structure of the MOS tube driving circuit.

[0050] Optional, continue to refer to Figure 2The pull-down control circuit 20 may include a first transistor Q1 and a second voltage-dividing resistor R2; the first end of the second voltage-dividing resistor R2 is electrically connected to the first power supply terminal V1, and the second end of the second voltage-dividing resistor R2 is electrically connected to the first electrode of the first transistor Q1 at a third node N3; the gate of the first transistor Q1 is electrically connected to the pulse width modulation terminal PWM, and the second electrode of the first transistor Q1 is electrically connected to the second power supply terminal V2; wherein the control end of the pull-down circuit 30 is electrically connected to the third node N3.

[0051] The first transistor Q1 may be an N-type transistor or a P-type transistor. When the first transistor Q1 is an N-type transistor, a high-level pulse width modulation signal at the pulse width modulation end PWM can control the first transistor Q1 to turn on, and a low-level pulse width modulation signal at the pulse width modulation end PWM can control the first transistor Q1 to turn off; when the first transistor Q1 is a P-type transistor, a high-level pulse width modulation signal at the pulse width modulation end PWM can control the first transistor Q1 to turn off, and a low-level pulse width modulation signal at the pulse width modulation end PWM can control the first transistor Q1 to turn on.

[0052] Specifically, taking the first transistor Q1 as an N-type transistor as an example, when the pulse width modulation signal of the pulse width modulation end PWM is at a high level, the first transistor Q1 is turned on, and the first transistor Q1 can pull down the signal of the third node N3 to be consistent with the second power signal of the second power supply end V2, so that the signal of the third node N3 is at a low level; when the pulse width modulation signal of the pulse width modulation end PWM is at a low level, the first transistor Q1 is turned off, at this time, the first power signal of the first power supply end V1 is divided by the second voltage-dividing resistor R2 and provided to the third node N3, so that the signal of the third node N3 is at a high level after being divided by the second voltage-dividing resistor R2; in this way, by setting the first transistor Q1 and the second voltage-dividing resistor R2 in the pull-down control circuit 20, the signal of the third node N3 can be controlled, and because the control end of the pull-down circuit 30 is electrically connected to the third node N3, the signal of the third node N3 can control the pull-down circuit 30 to be accurately turned on or off.

[0053] Optional, continue to refer to Figure 2 The pull-down circuit 30 includes a second transistor Q2; a gate of the second transistor Q2 is electrically connected to the output end of the pull-down control circuit 20, a first electrode of the second transistor Q2 is electrically connected to the first node N1, and a second electrode of the second transistor Q2 is electrically connected to the second power supply end V2.

[0054] The second transistor Q2 can also be an N-type transistor or a P-type transistor. When the pull-down control circuit 20 includes the first transistor Q1 and the second voltage-dividing resistor R2, and the first transistor Q1 and the second voltage-dividing resistor R2 are electrically connected to the third node N3, the gate of the second transistor Q2 can be electrically connected to the third node N3. At this time, when the second transistor Q2 is an N-type transistor, the high-level signal of the third node N3 can control the second transistor Q2 to turn on, and the low-level signal of the third node N3 can control the second transistor Q2 to turn off; when the second transistor Q2 is a P-type transistor, the high-level signal of the third node N3 can control the second transistor Q2 to turn off, and the low-level signal of the third node N3 can control the second transistor Q2 to turn on.

[0055] Specifically, taking the second transistor Q2 as an N-type transistor as an example, when the signal of the third node N3 is at a high level, the second transistor Q2 is turned on, so that the second transistor Q2 can pull down the signal of the first node N1 to be consistent with the second power signal of the second power terminal V2; when the signal of the third node N3 is at a low level, the second transistor Q2 is turned off, so that the second transistor Q2 cannot pull down the signal of the first node N1, and the signal of the first node N1 is a pulse width modulation signal after voltage division by the first voltage divider circuit 10. In this way, by making the pull-down circuit 30 include the second transistor Q2, the control of the signal of the first node N1 can be achieved through simple control logic and circuit structure.

[0056] Optional, continue to refer to Figure 2 The push-pull circuit 40 includes a third transistor Q3 and a fourth transistor Q4; the gate of the third transistor Q3 and the gate of the fourth transistor Q4 are both electrically connected to the first node N1; the first electrode of the third transistor Q3 is electrically connected to the first power supply terminal V1, and the second electrode of the third transistor Q3 and the second electrode of the fourth transistor Q4 are electrically connected to the second node N2; the first electrode of the fourth transistor Q4 is electrically connected to the second power supply terminal V2.

[0057] The third transistor Q3 and the fourth transistor Q4 are of different types, that is, when the third transistor Q3 is an N-type transistor, the fourth transistor Q4 is a P-type transistor; or when the third transistor Q3 is a P-type transistor, the fourth transistor Q4 is an N-type transistor.

[0058] Specifically, taking the third transistor Q3 as an N-type transistor and the fourth transistor Q4 as a P-type transistor as an example, when the signal of the first node N1 is at a high level, the third transistor Q3 is turned on and the fourth transistor Q4 is turned off. At this time, the first power signal of the first power terminal V1 can be transmitted to the second node N2 through the third transistor Q3, so that the signal of the second node N2 can be consistent with the first power signal; when the signal of the first node N1 is at a low level, the third transistor Q3 is turned off and the fourth transistor Q4 is turned on. At this time, the second power signal of the second power terminal V2 can be transmitted to the second node N2 through the fourth transistor Q4, so that the signal of the second node N2 can be consistent with the second power signal. In this way, by setting different types of third transistors Q3 and fourth transistors Q4 in the push-pull circuit 40, the signal of the second node N2 can be controlled to change between the first power signal and the second power signal based on the signal of the first node N1, thereby ensuring that the signal of the second node N2 has a strong ability to resist interference spikes.

[0059] To better understand Figure 2 The working principle of the MOS tube driving circuit shown in FIG. 1 is as follows, taking the first transistor, the second transistor and the third transistor as N-type transistors and the fourth transistor as a P-type transistor as an example. Figure 2 The working principle of the driving circuit of the MOS tube shown is exemplarily described.

[0060] refer to Figure 2 , when the pulse width modulation signal of the pulse width modulation end PWM is at a high level, the high level pulse width modulation signal is transmitted to the first node N1 after voltage division through the first voltage dividing resistor R1, so that the signal of the first node N1 is a high level pulse width modulation signal after voltage division; at the same time, the high level pulse width modulation signal can control the first transistor Q1 to turn on, and the first transistor Q1 can pull down the signal of the third node N3 to be consistent with the second power signal of the second power end V2, that is, the signal of the third node N3 is at a low level; the low level signal of the third node N3 cannot control the second transistor Q2 to turn on, and the second transistor Q2 is in a closed state, so that the second transistor Q2 will not pull down the signal of the first node N1, and the signal of the first node N1 remains at a high level; the high level signal of the first node N1 can control the third transistor Q3 to be in an on state, so that the first power signal of the first power end V1 is transmitted to the second node N2 through the third transistor Q3, and the second node N2 can be consistent with the high level first power signal; in this way, when the pulse width modulation signal is at a high level, the signal of the first node N1 and the signal of the second node N2 can also be maintained at a high level.

[0061] When the pulse width modulation signal of the pulse width modulation end PWM is at a low level, the first transistor Q1 is turned off, and the first transistor Q1 cannot pull down the signal of the third node N3; the third node N3 is the first power supply signal after voltage division by the second voltage-dividing resistor R2, that is, the signal of the third node N3 is at a high level; the high-level signal of the third node N3 can control the second transistor Q2 to turn on, so that the second transistor Q2 can pull down the signal of the first node N1 to be consistent with the second power supply signal of the second power supply end V2, and the signal of the first node N1 is at a low level; the low-level signal of the first node N1 can control the fourth transistor Q4 to be in an on state, so that the second power supply signal of the second power supply end V2 is transmitted to the second node N2 through the fourth transistor Q4, and the second node N2 can be consistent with the low-level second power supply signal; in this way, when the pulse width modulation signal is at a low level, the signal of the first node N and the signal of the second node N2 can also be kept at a low level.

[0062] Based on the above embodiment, optionally, Figure 3 As shown, the MOS transistor driving circuit provided by the utility model may further include: an isolation circuit 50; the isolation circuit 50 is electrically connected between the second node N2 and the gate of the MOS transistor Q0. The isolation circuit 50 can isolate the gate signal of the MOS transistor Q0 from the second node N2, prevent the signal fluctuation of the second node N2 from affecting the gate signal of the MOS transistor Q0, and prevent the gate signal fluctuation of the MOS transistor Q0 from affecting the signal of the second node N2, so that the signal of the second node N2 and the gate signal of the MOS transistor Q0 can be kept in a relatively stable state, which is conducive to improving the overall stability and reliability of the MOS transistor driving circuit.

[0063] Optional, such as Figure 4 As shown, the isolation circuit 50 may include an optocoupler isolation chip 51; the optocoupler isolation chip 51 includes a first input side pin, a second input side pin, a first output side pin, a second output side pin and a third output side pin; the first input side pin is coupled to the second node N2, the second input side pin is grounded (i.e., electrically connected to the second power supply terminal V2), the first output side pin is electrically connected to the third power supply terminal V3, the second output side pin is grounded GND, and the third output side pin is coupled to the gate of the MOS tube Q0.

[0064] Among them, the optocoupler isolation chip 51 has the functions of signal transmission, isolation and conversion. By coupling the first input side pin of the optocoupler isolation chip 51 to the second node N2, when the signal at the second node N2 is at a high level, the third power supply signal of the third power supply terminal V3 electrically connected to the first output side pin of the optocoupler isolation chip 51 can be controlled to be provided as a gate drive signal to the gate of the MOS tube Q0; and when the signal at the second node N2 is at a low level, the ground signal of the ground terminal GND electrically connected to the second output side pin of the optocoupler isolation chip 51 can be controlled to be provided as a gate drive signal to the gate of the MOS tube Q0; in this way, by controlling the level of the gate drive signal provided to the gate of the MOS tube Q0, the control of turning on or off the MOS tube Q0 can be achieved.

[0065] Based on the above embodiment, optionally, continue to refer to Figure 4 The MOS tube driving circuit provided by the embodiment of the utility model may also include: a first filtering circuit 61; the first filtering circuit 61 is electrically connected to the third power supply terminal V3 to filter and reduce noise of the power supply signal of the third power supply terminal V3 to prevent the third power supply signal of the third power supply terminal V3 from fluctuating and affecting the operating stability of the MOS tube Q0.

[0066] In an exemplary embodiment, the first filter circuit 61 may be composed of components such as capacitors and / or resistors. For example, the first filter circuit 61 may include a first capacitor C1, a first plate of the first capacitor C1 may be electrically connected to the third power supply terminal V3, and a second plate of the first capacitor C1 may be grounded. The capacitance of the first capacitor C1 may be set according to actual needs, and the embodiment of the utility model does not specifically limit this.

[0067] Based on the above embodiment, optionally, continue to refer to Figure 4 The MOS tube driving circuit provided by the embodiment of the utility model may also include: a second filtering circuit 62; the second filtering circuit 62 is electrically connected to the second node N2 to filter and reduce noise on the signal of the second node N2 to prevent the signal fluctuation of the second node N2 from affecting the operating stability of the MOS tube Q0.

[0068] In an exemplary embodiment, the second filter circuit 62 may be composed of components such as capacitors and / or resistors. For example, the second filter circuit 62 may include a second capacitor C2, a first filter resistor R3, and a second filter resistor R4. The first plate of the second capacitor C2 is electrically connected to the second node N2, the second plate of the second capacitor C2 is grounded (i.e., electrically connected to the second power supply terminal V2), the first end of the first filter resistor R3 is electrically connected to the second node N2, the second end of the first filter resistor R3 and the second filter resistor R4 are electrically connected to the first input side pin of the optocoupler isolation chip 51, and the second end of the second filter resistor R4 is grounded (i.e., electrically connected to the second power supply terminal V2). Among them, the capacitance of the second capacitor C2 and the resistance of the first filter resistor R3 and the second filter resistor R4 can be set according to actual needs, and the embodiment of the utility model does not specifically limit this.

[0069] On the basis of the above embodiments, the MOS transistor driving circuit provided by the embodiment of the utility model may further include: a third voltage-dividing resistor R5, the third voltage-dividing resistor R5 is coupled between the second node N2 and the gate of the MOS transistor Q0, or, when an isolation circuit 50 is provided in the MOS transistor driving circuit, the third voltage-dividing resistor R5 is electrically connected to the isolation circuit 50 and the gate of the MOS transistor Q0, so as to divide the gate driving signal provided to the MOS transistor Q0, so that the gate signal of the MOS transistor Q0 can reach the voltage of the normal opening or the voltage of the normal closing of the MOS transistor Q0, so as to prevent the signal provided to the gate of the MOS transistor Q0 from being over-voltage, thereby affecting the working stability of the MOS transistor Q0.

[0070] Based on the same utility model concept, the utility model embodiment also provides a power converter, which can be applied to any device that needs power conversion, such as an inverter, a charger, a charging pile, a server power supply, etc. The power converter includes a MOS tube and any MOS tube drive circuit provided in the above embodiment. Therefore, the power converter also has the beneficial effects of the MOS tube drive circuit in the above embodiment. The similarities can be understood by referring to the above explanation of the display panel, and will not be repeated below.

[0071] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention is described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A MOS tube driving circuit, characterized in that: include: Voltage divider circuit, pull-down control circuit, pull-down circuit and push-pull circuit; The input end of the voltage divider circuit is electrically connected to the pulse width modulation end, and the output end of the voltage divider circuit is electrically connected to the control end of the push-pull circuit at a first node; The control end of the pull-down control circuit is electrically connected to the pulse width modulation end, the first input end of the pull-down control circuit is electrically connected to the first power supply end, and the second input end of the pull-down control circuit is electrically connected to the second power supply end; the output end of the pull-down control circuit is electrically connected to the control end of the pull-down circuit; The input end of the pull-down circuit is electrically connected to the second power supply end, and the output end of the pull-down circuit is electrically connected to the first node; The first input end of the push-pull circuit is electrically connected to the first power supply end, the second input end of the push-pull circuit is electrically connected to the second power supply end, and the output end of the push-pull circuit is coupled to the gate of the MOS tube at a second node; The pulse width modulation signal at the pulse width modulation end, the signal at the first node, and the signal at the second node have the same polarity.

2. The MOS tube driving circuit according to claim 1, characterized in that: The voltage dividing circuit comprises a first voltage dividing resistor; The first end of the first voltage-dividing resistor is electrically connected to the pulse width modulation end, and the second end of the first voltage-dividing resistor is electrically connected to the first node.

3. The MOS tube driving circuit according to claim 1, characterized in that: The pull-down control circuit includes a first transistor and a second voltage-dividing resistor; The first end of the second voltage-dividing resistor is electrically connected to the first power supply end, and the second end of the second voltage-dividing resistor is electrically connected to the first electrode of the first transistor at a third node; The gate of the first transistor is electrically connected to the pulse width modulation terminal, and the second electrode of the first transistor is electrically connected to the second power supply terminal; Wherein, the control end of the pull-down circuit is electrically connected to the third node.

4. The MOS tube driving circuit according to claim 1, characterized in that: The pull-down circuit includes a second transistor; A gate of the second transistor is electrically connected to the output terminal of the pull-down control circuit, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the second power supply terminal.

5. The MOS tube driving circuit according to claim 1, characterized in that: The push-pull circuit includes a third transistor and a fourth transistor; The gate of the third transistor and the gate of the fourth transistor are both electrically connected to the first node; the first electrode of the third transistor is electrically connected to the first power supply terminal, the second electrode of the third transistor and the second electrode of the fourth transistor are electrically connected to the second node; the first electrode of the fourth transistor is electrically connected to the second power supply terminal; The third transistor and the fourth transistor are of different types.

6. The MOS tube driving circuit according to claim 1, characterized in that: Also includes: Isolation circuit; The isolation circuit is electrically connected between the second node and the gate of the MOS tube.

7. The MOS tube driving circuit according to claim 6, characterized in that: The isolation circuit includes an optical coupling isolation chip; The optocoupler isolation chip includes a first input side pin, a second input side pin, a first output side pin, a second output side pin and a third output side pin; the first input side pin is coupled to the second node, the second input side pin is grounded, the first output side pin is electrically connected to the third power supply terminal, the second output side pin is grounded, and the third output side pin is coupled to the gate of the MOS tube.

8. The MOS tube driving circuit according to claim 7, characterized in that: Also includes: a first filtering circuit; The first filter circuit is electrically connected to the third power supply end.

9. The MOS tube driving circuit according to claim 8, characterized in that: Also includes: A second filtering circuit; The second filter circuit is electrically connected to the second node.

10. A power converter, characterized in that: include: A MOS tube and a MOS tube driving circuit as claimed in any one of claims 1 to 9.

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