Integrated chip comprising multi-level semiconductor waveguide and multi-level conductor heater

Abstract

An integrated chip including a multi-level semiconductor waveguide and a multi-level conductor heater includes a base dielectric layer and a multi-level semiconductor waveguide layer on the base dielectric layer. The multi-level semiconductor waveguide layer has a first waveguide layer having a first width at a first height on the base dielectric layer. The multi-level semiconductor waveguide layer has a second waveguide layer having a second width greater than the first width at a second height on the base dielectric layer, the second height being less than the first height. The cladding layer is on the multi-level semiconductor waveguide layer. A multi-level conductor heater layer is on the cladding layer. The multi-level conductor heater layer has a first heater layer on the first waveguide layer. The multi-level conductor heater layer has a pair of second heater layers at the first height above the second waveguide layer and on opposite sides of the first waveguide layer.

Description

Technical Field

[0001] The utility model relates to an integrated chip, which comprises a multi-level conductor heater layer on a multi-level semiconductor waveguide layer. Background Art

[0002] Optical waveguides are commonly used as components in optical integrated devices. Optical waveguides are used to confine and guide light from a first point on an integrated chip (IC) to a second point on the IC with minimal attenuation. Many modern optical waveguides are formed using semiconductors. Semiconductor waveguides may include optical converters or optical couplers for optically coupling optical fibers to semiconductor waveguides. Utility Model Content

[0003] According to an embodiment of the utility model, an integrated chip includes a base dielectric layer, a multi-level semiconductor waveguide layer on the base dielectric layer, a cladding layer, and a multi-level conductor heater layer. The multi-level semiconductor waveguide layer has a first waveguide layer, which has a first width at a first height on the base dielectric layer. The multi-level semiconductor waveguide layer has a second waveguide layer, which has a second width greater than the first width at a second height on the base dielectric layer, and the second height is less than the first height. The cladding layer is located on the multi-level semiconductor waveguide layer. The multi-level conductor heater layer is located on the cladding layer. The multi-level conductor heater layer has a first heater layer on the first waveguide layer. The multi-level conductor heater layer has a pair of second heater layers at the first height, on the second waveguide layer, and on the opposite side of the first waveguide layer.

[0004] According to another embodiment of the utility model, an integrated chip includes a base dielectric layer, a multi-level semiconductor waveguide layer on the base dielectric layer, a cladding layer, a multi-level conductor heater layer, and a plurality of pairs of contacts. The multi-level semiconductor waveguide layer has a first waveguide layer, a second waveguide layer, and a third waveguide layer, wherein the first waveguide layer has a first width at a first height on the base dielectric layer, the second waveguide layer has a second width at a second height on the base dielectric layer, the second width is greater than the first width, and the second height is less than the first height, and the third waveguide layer has a third width at a third height on the base dielectric layer, the third width is greater than the second width, and the third height is less than the second height. The cladding layer conformally covers the multi-level semiconductor waveguide layer. The multi-level conductor heater layer conformally covers the cladding layer. The multi-level conductor heater layer is spaced apart from the multi-level semiconductor waveguide layer by the cladding layer. The multi-level conductor heater layer has a first heater layer on the first waveguide layer. The multi-level conductor heater layer has a pair of second heater layers at the first height, on the second waveguide layer, and on the opposite side of the first waveguide layer. The multi-level conductor heater layer has a pair of third heater layers at a second height, on the third waveguide layer and on the opposite side of the second waveguide layer. A pair of first contacts are located on the multi-level conductor heater layer along the first heater layer and coupled to the multi-level conductor heater layer. A pair of second contacts are located on the multi-level conductor heater layer along one of the pair of second heater layers and coupled to the multi-level conductor heater layer. A pair of third contacts are located on the multi-level conductor heater layer along the other of the pair of second heater layers and coupled to the multi-level conductor heater layer. A pair of fourth contacts are located on the multi-level conductor heater layer along one of the pair of third heater layers and coupled to the multi-level conductor heater layer. A pair of fifth contacts are located on the multi-level conductor heater layer along the other of the pair of third heater layers and coupled to the multi-level conductor heater layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The details of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or decreased for clarity of discussion.

[0006] Figure 1A and Figure 1B Cross-sectional views of some embodiments of an integrated chip including a multi-level conductor heater layer on a multi-level semiconductor waveguide layer are shown.

[0007] Figure 1C Shows Figure 1A and Figure 1B Top view of some embodiments of an integrated chip.

[0008] Figure 2A and Figure 2B Shows Figure 1A Cross-sectional views of some other embodiments of integrated chips.

[0009] Figure 2C Shows Figure 2A and Figure 2B Top view of some embodiments of an integrated chip.

[0010] Figure 3 and Figure 4 Shows Figure 2B Cross-sectional views of some other embodiments of integrated chips.

[0011] Figure 5A Cross-sectional views of some embodiments of integrated chips implementing multi-level semiconductor waveguide layers and multi-level conductor heater layers in a Mach-Zehnder interferometer are shown.

[0012] Figure 5B and Figure 5C Shows Figure 5A Top view of some embodiments of an integrated chip.

[0013] Fig. 6A and Figure 6B Cross-sectional views of some embodiments of integrated chips implementing multi-level semiconductor waveguide layers and multi-level conductor heater layers in a micro-ring modulator are shown.

[0014] Figure 6C and Fig.6D Shows Fig. 6A and Figure 6B Top view of some embodiments of an integrated chip.

[0015] Figures 7 to 18 Cross-sectional views of some embodiments of methods for forming an integrated chip including a multi-level semiconductor waveguide and a multi-level conductor heater on the multi-level semiconductor waveguide are shown.

[0016] Fig.19 A flow chart showing some embodiments of a method of an integrated chip including a multi-level semiconductor waveguide and a multi-level conductor heater on the multi-level semiconductor waveguide. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing the different features of the utility model. Specific examples of components and configurations are described below to simplify the utility model. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the utility model may repeat the figure numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] Additionally, for ease of description, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one device or feature to another device or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0019] The photonic integrated chip includes a semiconductor waveguide layer on a base dielectric layer. The semiconductor waveguide layer has a pair of sidewalls and an upper surface that form an optical waveguide. The upper surface extends between the tops of the sidewalls. The cladding is located on the semiconductor waveguide layer. The difference between the refractive indexes of the semiconductor waveguide layer and the cladding is quite large, so that the optical radiation can be confined within the semiconductor waveguide layer. For example, in some cases, the semiconductor waveguide layer includes silicon and the cladding includes silicon dioxide. However, silicon may be highly sensitive to temperature changes, which may reduce the performance of the semiconductor waveguide layer. For example, temperature changes along the semiconductor waveguide layer may cause phase changes of the optical signal propagating in the optical waveguide. Therefore, some integrated chips include a conductor heater layer on the semiconductor waveguide layer to improve the control of the temperature of the semiconductor waveguide layer. For example, by controlling the amount of current generated in the conductor heater layer, the temperature of the conductor heater layer can be controlled, and thus the temperature of the semiconductor waveguide layer can be controlled. As a result, the performance of the semiconductor waveguide layer can be adjusted. For example, the phase of the optical signal propagating in the optical waveguide can be tuned.

[0020] The conductor heater layer is disposed on the upper surface of the semiconductor waveguide layer and is spaced apart from the upper surface of the semiconductor waveguide layer by the cladding layer. Therefore, the conductor heater layer can control the temperature of the semiconductor waveguide layer along the upper surface of the semiconductor waveguide layer. However, the conductor heater layer does not extend below the upper surface of the semiconductor waveguide layer against the sidewall of the semiconductor waveguide layer. Therefore, the control of the temperature of the semiconductor waveguide layer along the sidewall of the semiconductor waveguide layer can be reduced.

[0021] In various embodiments of the present invention, the conductor heater layer has a multi-tiered structure to increase the control of the temperature of the semiconductor waveguide layer. For example, the multi-tiered conductor heater layer has a first heater layer extending laterally on the upper surface of the semiconductor waveguide layer. Further, the multi-tiered conductor heater layer has a pair of second heater layers below the upper surface of the semiconductor waveguide layer, which are respectively located on opposite sides of the upper surface of the semiconductor waveguide layer and extend laterally away from the sidewall of the semiconductor waveguide layer. The conductor heater layers respectively extend vertically from the first heater layer to the pair of second heater layers located on opposite sides of the upper surface of the semiconductor waveguide layer.

[0022] Because the conductor heater layer has a multi-level structure, the conductor heater layer is on the upper surface of the semiconductor waveguide layer and extends below the upper surface against the sidewall of the semiconductor waveguide layer. Therefore, the control of the temperature of the semiconductor waveguide layer along the sidewall of the semiconductor waveguide layer can be improved. By improving the control of the temperature of the semiconductor waveguide layer, the control of the waveguide performance can be improved. For example, the control of the phase of the optical signal propagating in the optical waveguide can be improved.

[0023] Figure 1A A cross-sectional view 100a of some embodiments of an integrated chip including a multi-level conductor heater layer 108 on a multi-level semiconductor waveguide layer 104 is shown.

[0024] The semiconductor waveguide layer 104 is located on the base dielectric layer 102. The semiconductor waveguide layer 104 has a plurality of waveguide layers having different widths at different heights on the base dielectric layer 102. For example, the semiconductor waveguide layer 104 has a first waveguide layer 112 on a second waveguide layer 114 (e.g., a waveguide base). The first waveguide layer 112 has a first width 124 at a first height 120 on the base dielectric layer 102. The second waveguide layer 114 has a second width (not labeled) greater than the first width 124 at a second height 122 on the base dielectric layer 102, the second height 122 being less than the first height 120.

[0025] The first waveguide layer 112 is formed (e.g., defined) by a first upper surface 104a of the semiconductor waveguide layer 104 and a pair of first sidewalls 104b of the semiconductor waveguide layer 104 located on opposite sides of the first upper surface 104a. The first upper surface 104a extends between the tops of the first sidewalls 104b. The first upper surface 104a and the first sidewalls 104b form (e.g., define) an optical waveguide.

[0026] The second waveguide layer 114 extends laterally beyond the first sidewall 104b of the semiconductor waveguide layer 104. The second waveguide layer 114 is at least partially formed (e.g., defined) by a pair of second upper surfaces 104c of the semiconductor waveguide layer 104. The second upper surfaces 104c are below the first upper surface 104a and on opposite sides of the first upper surface 104a. The second upper surface 104c extends laterally from the first sidewall 104b. In some embodiments, the second upper surface 104c further forms the optical waveguide.

[0027] The cladding layer 106 is located on the semiconductor waveguide layer 104. The cladding layer 106 extends directly between the semiconductor waveguide layer 104 and the conductor heater layer 108. Therefore, the semiconductor waveguide layer 104 is spaced apart from the conductor heater layer 108 by the cladding layer 106. A first upper dielectric layer 110 is located on the conductor heater layer 108 and the cladding layer 106.

[0028] The conductor heater layer 108 is located on the semiconductor waveguide layer 104. The conductor heater layer 108 has a plurality of heater layers at different heights on the base dielectric layer 102. For example, the conductor heater layer 108 has a first heater layer 116 and a pair of second heater layers 118 below the first heater layer 116.

[0029] The first heater layer 116 is located on the first waveguide layer 112. For example, the first heater layer 116 is directly on the first upper surface 104a of the semiconductor waveguide layer 104. The first heater layer 116 extends laterally from the first upper surface 104a to beyond the first sidewall 104b of the semiconductor waveguide layer 104. The first heater layer 116 is at least partially formed (e.g., defined) by the first upper surface 108a and the first lower surface 108b of the conductor heater layer 108.

[0030] The pair of second heater layers 118 are located above the second waveguide layer 114 at a first height 120 and on opposite sides of the first waveguide layer 112. For example, the second heater layers 118 are below and respectively on opposite sides of the first upper surface 104a of the semiconductor waveguide layer 104. The second heater layer 118 extends laterally away from the first sidewall 104b of the semiconductor waveguide layer 104. The second heater layer 118 is at least partially formed (e.g., defined) by a pair of second upper surfaces 108c and a pair of second lower surfaces 108d.

[0031] The conductor heater layer 108 vertically extends from the first heater layer 116 to the pair of second heater layers 118, respectively, against the first sidewall 104b of the semiconductor waveguide layer 104. Specifically, the first pair of inner sidewalls 108e of the conductor heater layer 108 extend from the first lower surface 108b to a pair of second lower surfaces 108d located on opposite sides of the first upper surface 104a of the semiconductor waveguide layer 104. The first pair of outer sidewalls 108f of the conductor heater layer 108 extend from the first upper surface 108a to the pair of second upper surfaces 108c on opposite sides of the first upper surface 104a of the semiconductor waveguide layer 104.

[0032] Because the conductor heater layer 108 has a multi-level structure, the conductor heater layer 108 extends on the first upper surface 104a of the semiconductor waveguide layer 104, against the first side wall 104b of the semiconductor waveguide layer 104, and on the second upper surface 104c of the semiconductor waveguide layer 104. Therefore, the control of the temperature of the semiconductor waveguide layer 104 along the various surfaces of the semiconductor waveguide layer 104 can be improved. As a result, the control of the waveguide performance can be improved. For example, the control of the phase of the optical signal propagating in the optical waveguide can be improved. In addition, because the conductor heater layer 108 is located on the second upper surface 104c of the semiconductor waveguide layer 104 against the first side wall 104b of the semiconductor waveguide layer 104 and extends on the first upper surface 104a of the semiconductor waveguide layer 104, the semiconductor waveguide layer 104 can be heated more quickly and thus more efficiently.

[0033] Figure 1B Shows Figure 1A Another cross-sectional view 100b of some embodiments of an integrated chip. In some embodiments, Figure 1B The cross-sectional view 100b may be along Figure 1C The line B-B' is intercepted. Figure 1C Shows Figure 1A and Figure 1B A top view 100c of some embodiments of an integrated chip. The capping layer 106 and the first upper dielectric layer 110 are not shown. Figure 1C middle.

[0034] The integrated chip includes a plurality of contacts disposed on the conductor heater layer 108. The contacts extend through the first upper dielectric layer 110 to the conductor heater layer 108. For example, in some embodiments, the integrated chip includes a pair of first contacts 126, a pair of second contacts 128, and a pair of third contacts 130.

[0035] The pair of first contacts 126 contact the conductor heater layer 108 along the first heater layer 116 near opposite ends of the conductor heater layer 108. For example, one of the first contacts 126 contacts the conductor heater layer 108 along the first upper surface 108a of the conductor heater layer 108 near the first end 138 of the conductor heater layer 108. The other of the first contacts 126 contacts the conductor heater layer 108 along the first upper surface 108a of the conductor heater layer 108 near the second end 140 of the conductor heater layer 108 (opposite the first end 138).

[0036] The pair of second contacts 128 and the pair of third contacts 130 contact the conductor heater layer 108 near opposite ends of the conductor heater layer along the pair of second heater layers 118. For example, one of the second contacts 128 contacts the conductor heater layer 108 along one of the pair of second upper surfaces 108c of the conductor heater layer 108 near the first end 138 of the conductor heater layer 108. The other of the second contacts 128 contacts the conductor heater layer 108 along one of the pair of second upper surfaces 108c of the conductor heater layer 108 near the second end 140 of the conductor heater layer 108. One of the third contacts 130 contacts the conductor heater layer 108 along another of the pair of second upper surfaces 108c of the conductor heater layer 108 near the first end 138 of the conductor heater layer 108. The other of the third contacts 130 contacts the conductor heater layer 108 along another of the pair of second upper surfaces 108c of the conductor heater layer 108 near the second end 140 of the conductor heater layer 108.

[0037] In some embodiments, the contact pairs are coupled to different voltage inputs disposed on the contacts. For example, in some embodiments, the pair of first contacts 126 are coupled (e.g., as shown by lines 144 representing wiring, such as metal lines, metal vias, etc.) to a pair of first voltage inputs 142. The pair of second contacts 128 are coupled (e.g., as shown by lines 148 representing wiring, such as metal lines, metal vias, etc.) to a pair of second voltage inputs 146. The pair of third contacts 130 are coupled (e.g., as shown by lines 152 representing wiring, such as metal lines, metal vias, etc.) to a pair of third voltage inputs 150. In some embodiments, the voltage inputs 142, 146, 150 may be or include solder bumps, pads, metal lines, metal contacts, or some other suitable conductive features.

[0038] In some embodiments, the voltage inputs are adapted to be coupled to voltage sources. For example, a pair of first voltage inputs 142 are adapted to be coupled to a first voltage source 154 , a pair of second voltage inputs 146 are adapted to be coupled to a second voltage source 156 , and a pair of third voltage inputs 150 are adapted to be coupled to a third voltage source 158 .

[0039] A voltage may be applied across the contact pair via a corresponding voltage input to induce a current in the conductor heater layer 108. For example, the current may flow from the first end 138 of the conductor heater layer 108 to the second end 140 of the conductor heater layer 108. Inducing a current in the conductor heater layer 108 may cause the conductor heater layer 108 to heat up. By controlling the voltage applied across the contacts, the magnitude of the current generated in the conductor heater layer 108 may be controlled, and thus the temperature of the conductor heater layer 108 may be controlled.

[0040] In some embodiments, different voltages may be provided across different pairs of contacts via different voltage inputs. For example, a first voltage may be provided across the pair of first contacts 126 via the pair of first voltage inputs 142. A second voltage different from the first voltage may be provided across the pair of second contacts 128 via the pair of second voltage inputs 146. A third voltage different from the first voltage and the second voltage may be provided across the pair of third contacts 130 via the pair of third voltage inputs 150. The different voltages may be individually controlled to individually adjust the temperature of the conductor heater layer 108 along different layers of the conductor heater layer 108, and thus individually adjust the temperature of the semiconductor waveguide layer 104 along different surfaces of the semiconductor waveguide layer 104. By individually adjusting the temperature of the semiconductor along various surfaces of the conductor heater layer 108, control of the optical waveguide performance may be further improved.

[0041] The top surfaces of the first contact 126, the second contact 128, and the third contact 130 are disposed at a common height (not labeled) on the base dielectric layer 102. The second contact 128 and the third contact 130 extend below the bottom surface of the base dielectric layer 102. For example, the first contact 126 extends to a first depth (not labeled) below the topmost surface (not labeled) of the first upper dielectric layer 110, and the second contact 128 and the third contact 130 extend to a second depth (not labeled) below the topmost surface of the first upper dielectric layer 110, the second depth being greater than the first depth.

[0042] A pair of first metal lines 132 is directly located on the pair of first contacts 126 and coupled to the pair of first contacts 126. A pair of second metal lines 134 is directly located on the pair of second contacts 128 and coupled to the pair of second contacts 128. A pair of third metal lines 136 is directly located on the pair of third contacts 130 and coupled to the pair of third contacts 130. For clarity, Figure 1C The metal lines 132, 134, 136 are not shown.

[0043] In some embodiments, the base dielectric layer 102, the capping layer 106, and / or the first upper dielectric layer 110 may, for example, include silicon dioxide or some other suitable material. In some embodiments, the thickness of the capping layer 106 may be adjusted to adjust the distance between the conductor heater layer 108 and the semiconductor waveguide layer 104. In some embodiments, the semiconductor waveguide layer 104 may, for example, include silicon or some other suitable material. In some embodiments, the conductor heater layer 108 may, for example, include tungsten, titanium nitride, or some other suitable material. In some embodiments, the thickness of the conductor heater layer 108 may be adjusted to adjust the resistance of the conductor heater layer 108. In some embodiments, the contacts 126, 128, 130 may, for example, include tungsten or some other suitable material. In some embodiments, the metal lines 132, 134, 136 may, for example, include copper or some other suitable material. In some embodiments, the base dielectric layer 102 is on a semiconductor substrate (not shown).

[0044] Figure 2A show Figure 1A 200a of some embodiments of an integrated chip, wherein the multi-level semiconductor waveguide layer 104 has a third waveguide layer 202 and the multi-level conductor heater layer 108 has a pair of third heater layers 204. In some embodiments, Figure 2A The cross-sectional view 200a may be along Figure 2C The line C-C' is intercepted.

[0045] The semiconductor waveguide layer 104 has a third waveguide layer 202 below the second waveguide layer 114. The first waveguide layer 112 has a first width 124 at the first height 120. The second waveguide layer 114 has a second width 206 at the second height 122. The third waveguide layer 110 has a third width (not labeled) at a third height 208 above the base dielectric layer 102. The third height 208 is less than the second height 122. The third width is greater than the second width 206.

[0046] The second waveguide layer 114 is formed (e.g., defined) by the pair of second upper surfaces 104c of the semiconductor waveguide layer 104 and the pair of second sidewalls 104d of the semiconductor waveguide layer 104. The third waveguide layer 202 is formed (e.g., defined) by a pair of third upper surfaces 104e of the semiconductor waveguide layer 104. The third upper surfaces 104e are located below the second upper surface 104c and on the opposite side of the second upper surface 104c. The third upper surface 104e extends laterally from the second sidewall 104d.

[0047] The conductor heater layer 108 has a pair of third heater layers 204 below the pair of second heater layers 118. The pair of third heater layers 204 are disposed at the second height 122, on the third waveguide layer 202, and on opposite sides of the second waveguide layer 114. For example, the pair of third heater layers 204 are located below the pair of second upper surfaces 104c of the semiconductor waveguide layer 104 and on opposite sides of the pair of second upper surfaces 104c. The third heater layer 204 extends laterally away from the second sidewall 104d of the semiconductor waveguide layer 104. The third heater layer 204 is at least partially formed (e.g., defined) by the pair of third upper surfaces 108g and the pair of third upper surfaces 108g of the conductor heater layer 108.

[0048] The conductor heater layer 108 vertically extends from the second heater layer 118 to the third heater layer 204 along the second sidewall 104d of the semiconductor waveguide layer 104. Specifically, the second pair of inner sidewalls 108i of the conductor heater layer 108 extend from the second lower surface 108d to the third lower surface 108h. The first pair of outer sidewalls 108j of the conductor heater layer 108 extend from the second upper surface 108c to the third upper surface 108g.

[0049] By having multiple waveguide layers on the waveguide base (e.g., by having the second waveguide layer 114 and the first waveguide layer 112 on the third waveguide layer 202), the performance of the optical waveguide can be improved. For example, when the waveguide has multiple levels on the waveguide base, the optical mode of the optical radiation propagating through the optical waveguide can reduce exposure to the waveguide sidewalls (e.g., the first sidewall 104b and the second sidewall 104d). As a result, the loss of optical radiation along the waveguide can be reduced. In addition, since the conductor heater layer 108 has the third heater layer 204 on the third waveguide layer 202, the control of the temperature of the third waveguide layer 202 can be improved. As a result, the performance of the waveguide can be improved.

[0050] Figure 2B show Figure 2A Another cross-sectional view 200b of some embodiments of an integrated chip. In some embodiments, Figure 2B The cross-sectional view 200b may be along Figure 2C The line D-D' is intercepted. Figure 2C Shows Figure 2A and Figure 2B A top view 200c of some embodiments of an integrated chip. The cap layer 106 and the first upper dielectric layer 110 are not Figure 2C Displayed in.

[0051] A pair of fourth contacts 210 and a pair of fifth contacts 212 contact the conductor heater layer 108 along the pair of third heater layers 204 near opposite ends of the conductor heater layer 108. For example, one of the fourth contacts 210 contacts the conductor heater layer 108 along one of the pair of third upper surfaces 108g of the conductor heater layer 108 near the first end 138 of the conductor heater layer 108. Another of the fourth contacts 210 contacts the conductor heater layer 108 along one of the pair of third upper surfaces 108g of the conductor heater layer 108 near the second end 140 of the conductor heater layer 108. One of the fifth contacts 212 contacts the conductor heater layer 108 along the other of the pair of third upper surfaces 108g of the conductor heater layer 108 near the first end 138 of the conductor heater layer 108. Another of the fifth contacts 212 contacts the conductor heater layer 108 along the other of the pair of third upper surfaces 108g of the conductor heater layer 108 near the second end 140 of the conductor heater layer 108.

[0052] The pair of fourth contacts 210 are coupled to a pair of fourth voltage inputs 222. The pair of fifth contacts 212 are coupled to a pair of fifth voltage inputs 224. The pair of fourth voltage inputs 222 are adapted to be coupled to a fourth voltage source 228 and the pair of fifth voltage inputs 224 are adapted to be coupled to a fifth voltage source 230.

[0053] In some embodiments, a fourth voltage may be provided across the pair of fourth contacts 210 via the pair of fourth voltage inputs 222. Additionally, a fifth voltage may be provided across the pair of fifth contacts 212 via the pair of fifth voltage inputs 224. Thus, individually controllable voltages may be provided on the third heater layer 204 to adjust the temperature of the conductor heater layer 108 along the third heater layer 204, and thus adjust the temperature of the semiconductor waveguide layer 104 along different surfaces of the semiconductor waveguide layer 104 (e.g., the second sidewall 104d and the third upper surface 104e).

[0054] The top surfaces of the fourth contact 210 and the fifth contact 212 are disposed at a common height (not labeled) on the base dielectric layer 102. The fourth contact 210 and the fifth contact 212 extend below the bottom surfaces of the second contact 128 and the third contact 130. For example, the fourth contact 210 and the fifth contact 212 extend to a third depth (not labeled) below the topmost surface (not labeled) of the first upper dielectric layer 110, and the third depth is greater than the second depth.

[0055] In some embodiments, a pair of sixth contacts 214 contact the conductor heater layer 108 along the first heater layer 116 near opposite ends of the conductor heater layer 108. For example, one of the sixth contacts 214 contacts the conductor heater layer 108 along the first upper surface 108a of the conductor heater layer 108 near the first end 138 of the conductor heater layer 108. Another of the sixth contacts 214 contacts the conductor heater layer 108 along the first upper surface 108a of the conductor heater layer 108 near the second end 140 of the conductor heater layer 108. The pair of sixth contacts 214 are laterally spaced apart from the pair of first contacts 126. The pair of sixth contacts 214 are coupled to a pair of sixth voltage inputs 226. The pair of sixth voltage inputs 226 are adapted to be coupled to a sixth voltage source 232. In some embodiments, a sixth voltage may be provided across the pair of sixth contacts 214 via the pair of sixth voltage inputs 226.

[0056] A pair of fourth metal lines 216 is directly located on the pair of fourth contacts 210 and coupled to the pair of fourth contacts 210. A pair of fifth metal lines 218 is directly located on the pair of fifth contacts 212 and coupled to the pair of fifth contacts 212. In some embodiments, a pair of sixth metal lines 220 is directly located on the pair of sixth contacts 214 and coupled to the pair of sixth contacts 214. The metal lines 216, 218, 220 are not connected to the Figure 2C Displayed in.

[0057] Figure 3 Shows Figure 2B A cross-sectional view 300 of some embodiments of an integrated chip of FIG. 1 , wherein a first device contact 302 and a second device contact 304 contact the semiconductor waveguide layer 104 on opposite sides of the conductor heater layer 108 .

[0058] In some embodiments, the semiconductor waveguide layer 104 may be doped to form an active device. For example, in some embodiments, the left side of the semiconductor waveguide layer 104 has a first doping type (e.g., p-type doping) and the right side of the semiconductor waveguide layer 104 has a second doping type (e.g., n-type doping) different from the first doping type. In some embodiments, a region of the semiconductor waveguide layer 104 having the first doping type and a region of the semiconductor waveguide layer 104 having the second doping type intersect along a pn junction in the middle of the semiconductor waveguide layer 104 (e.g., between the first sidewalls 104b), thereby forming a pn device. In some other embodiments, an intrinsic semiconductor region is provided between the regions having doping. For example, the semiconductor waveguide layer 104 has intrinsic doping between a region having the first doping type (e.g., the left side of the semiconductor waveguide layer 104) and a region having the second doping type (e.g., the right side of the semiconductor waveguide layer 104), thereby forming a pin device.

[0059] The first device contact 302 and the second device contact 304 extend through the first upper dielectric layer 110 to the semiconductor waveguide layer 104 on the opposite side of the conductor heater layer 108. In some embodiments, the first device contact 302 and the second device contact 304 contact the semiconductor waveguide layer 104 along the pair of third upper surfaces 104e of the semiconductor waveguide layer 104, respectively. In some embodiments, the doping concentration is increased in the third waveguide layer 202 located on the opposite side of the second waveguide layer 114, where the device contacts 302, 304 contact the third waveguide layer 202, to improve the performance of the active device (e.g., reduce the contact resistance). The first device metal line 312 is located on the first device contact 302 and coupled to the first device contact 302, and the second device metal line 314 is located on the second device contact 304 and coupled to the second device contact 304.

[0060] The first device contact 302 is coupled to a first device voltage input 306 (e.g., a positive voltage input) and the second device contact 304 is coupled to a second device voltage input 308 (e.g., a negative voltage input). In some embodiments, the device voltage inputs 306, 308 may be or include solder bumps, pads, metal wires, metal contacts, or some other suitable conductive features. The device voltage inputs 306, 308 are adapted to be coupled to a device voltage source 310. A voltage may be provided across the device contacts 302, 304 via the device voltage inputs 306, 308. Applying a voltage across the device contacts 302, 304 may change the carrier density in the semiconductor waveguide layer 104. By changing the carrier density in the semiconductor waveguide layer 104, the refractive index of the semiconductor waveguide layer 104 may be changed. This may be referred to as a plasma dispersion effect. By changing the refractive index of the semiconductor waveguide layer 104, the phase of the optical radiation passing through the waveguide may be modulated.

[0061] Figure 4 Shows Figure 3 400 of some embodiments of an integrated chip of the present invention, wherein the semiconductor waveguide layer 104 has protrusions 402 , 404 below the first device contact 302 and the second device contact 304 .

[0062] The protrusions 402, 404 protrude upward from the third waveguide layer 202 (e.g., waveguide base) on opposite sides of the conductor heater layer 108. The protrusions 402, 404 are at least partially formed (e.g., bounded) by a pair of fourth upper surfaces 104f and sidewalls 104g of the semiconductor waveguide layer 104. In some embodiments, the semiconductor waveguide layer 104 is heavily doped (e.g., has an increased dopant concentration) at the protrusions 402, 404. The device contacts 302, 304 contact the semiconductor waveguide layer 104 at the protrusions 402, 404. For example, the device contacts 302, 304 contact the fourth upper surface 104f of the semiconductor waveguide layer 104.

[0063] Figure 5A A cross-sectional view 500a of some embodiments of an integrated chip is shown, wherein the multi-level semiconductor waveguide layer 104 and the multi-level conductor heater layer 108 are implemented in a Mach-Zehnder interferometer. Figure 5B Shows Figure 5A A first top view 500b of some embodiments of an integrated chip. Figure 5C Shows Figure 5A A second top view 500c of some embodiments of the integrated chip. The conductor heater layer 108 is Figure 5B Shown in but not in Figure 5C In some embodiments, Figure 5A The cross-sectional view 500a can be along Figure 5B and Figure 5C The cladding layer 106 and the first upper dielectric layer 110 are not Figure 5B and Figure 5C Displayed in.

[0064] The waveguide splits from the input path 502 into a first branch 504 and a second branch 506. The waveguide then recombine into an output path 508. In some embodiments, the conductor heater layer 108 is on one of the branches 504, 506. In some other embodiments, the conductor heater layer 108 is on both branches 504, 506. For example, in some embodiments, the conductor heater layer 108 forms a first heater 510 on the first branch 504 and forms a second heater 512 on the second branch 506 that is separate from the first heater 510.

[0065] By applying a voltage across the waveguide at the branches 504, 506 (e.g., through the contacts 302, 304 and the contacts 526, 528, respectively), modulation (e.g., phase modulation) can be performed on one or both of the branches 504, 506. In addition, phase shifting can be performed at one or both of the branches by controlling the temperature of the semiconductor waveguide layer 104 using the conductor heater layer 108. For example, the temperature of the waveguide at one or both of the branches 504, 506 can adjust the phase of the modulated optical signal at the branches 504, 506. Because the multi-level conductor heater 108 can improve the temperature control of the semiconductor waveguide layer 104 at the branches 504, 506, the accuracy of the phase shifting performed at the branches 504, 506 using the conductor heater layer 108 can be improved. As a result, higher order modulation (e.g., fourth order pulse amplitude modulation (PAM), eighth order PAM, etc.) can be achieved at the branches 504, 506.

[0066] In some embodiments, the temperature of each heater 510, 512 can be controlled individually. For example, the first heater 510 can be coupled to a first plurality of voltage inputs (e.g., voltage inputs 142, 146, 150, 222, 224, 226) via a first plurality of contacts (e.g., contacts 126, 128, 130, 210, 212, 214), and the second heater 512 can be coupled to a second plurality of voltage inputs (not shown) via a second plurality of contacts (e.g., contacts 514, 516, 518, 520, 522, 524). Thus, the current generated in the heaters 510, 512 can be controlled individually, and thus the temperature of the heaters 510, 512 can be controlled individually. As a result, the temperature of the waveguides at different branches 504, 506 can be controlled individually, and thus the phase of the optical signal propagating within the branches 504, 506 can be tuned individually.

[0067] Fig. 6A A cross-sectional view 600a of some embodiments of an integrated chip is shown, wherein the multi-level semiconductor waveguide layer 104 and the multi-level conductor heater layer 108 are implemented in a micro-ring modulator. Figure 6B Shows Fig. 6A Another cross-sectional view 600b of some embodiments of an integrated chip. Figure 6C Shows Fig. 6A and Figure 6B A first top view 600c of some embodiments of an integrated chip. Fig.6D Shows Fig. 6A and Figure 6B A second top view 600d of some embodiments of the integrated chip. The conductor heater layer 108 is Figure 6C Shown in but not in Fig.6D In some embodiments, Fig. 6A The cross-sectional view 600a can be along Figure 6C and Fig.6D In some embodiments, Figure 6B The cross-sectional view 600b may be along Figure 6C and Fig.6D The capping layer 106 and the first upper dielectric layer 110 are not Figure 6C and Fig.6D Displayed in.

[0068] The waveguide includes a transmission path 602 (e.g., a bus waveguide) and a microring 604 (e.g., a microring waveguide). A conductor heater layer 108 is disposed on the microring 604 to adjust the temperature of the waveguide at the microring 604, thereby controlling the phase of optical radiation propagating within the microring 604. By including multiple layers of conductor heaters 108 on the microring 604, control of the temperature of the waveguide at the microring 604 can be improved. As a result, control of the resonance wavelength of the microring 604 can be improved.

[0069] Figure 7 to Figure 18 Cross-sectional views 700 to 1800 show some embodiments of a method for forming an integrated chip including a multi-level semiconductor waveguide and a multi-level conductor heater on the multi-level semiconductor waveguide. Figure 7 to Figure 18 is a description related to the method, but it should be understood that Figure 7 to Figure 18 The structure disclosed in is not limited to this method, but can stand alone as a structure independent of this method.

[0070] like Figure 7 As shown in the cross-sectional view 700 of FIG. 7 , a semiconductor waveguide layer 104 and a base dielectric layer 102 are provided. The semiconductor waveguide layer 104 is on the base dielectric layer 102. In some embodiments, the base dielectric layer 102 includes silicon dioxide or some other suitable material. In some embodiments, the semiconductor waveguide layer 104 includes silicon or some other suitable material.

[0071] In some embodiments, the base dielectric layer 102 is on a semiconductor substrate (not shown). The semiconductor substrate, the base dielectric layer 102, and the semiconductor waveguide layer 104 are provided as a semiconductor on insulator (SOI) substrate. In some other embodiments, the semiconductor waveguide layer 104 is formed on the base dielectric layer 102 by an epitaxial growth process or some other suitable process.

[0072] like Figure 8 As shown in the cross-sectional view 800 of , a hard mask layer 802 is formed on the semiconductor waveguide layer 104, and the semiconductor waveguide layer 104 is etched according to the hard mask layer 802. The etching forms a pair of recesses 804 in the semiconductor waveguide layer 104, and the etching forms (e.g., defines) the first waveguide layer 112 between the pair of recesses 804.

[0073] In some embodiments, the hard mask layer 802 includes silicon nitride or some other suitable material. In some embodiments, the hard mask layer 802 is formed by depositing the hard mask layer on the semiconductor waveguide layer 104 and patterning the hard mask layer 802 according to a mask (not shown). In some embodiments, the etching includes a dry etching process, such as a plasma etching process, a reactive ion etching process, an ion beam etching process, or some other suitable process.

[0074] like Fig. 9 As shown in the cross-sectional view 900 of FIG. 1 , the semiconductor waveguide layer 104 is etched to form (e.g., define) a second waveguide layer 114 below the first waveguide layer 112 and a third waveguide layer 202 below the second waveguide layer 114. In some embodiments, the etching forms (e.g., defines) protrusions 402, 404 on a peripheral portion of the third waveguide layer 202.

[0075] In some embodiments, the etching is performed based on the photoresist mask 902 and the hard mask layer 802. In some embodiments, the etching includes a dry etching process or some other suitable process. In some embodiments, the photoresist mask 902 and the hard mask layer 802 are removed during and / or after etching.

[0076] like Fig.10 As shown in the cross-sectional view 1000 of , a cladding layer 106 is conformally deposited on the semiconductor waveguide layer 104. In some embodiments, the cladding layer 106 includes silicon dioxide or some other suitable material. In some embodiments, the cladding layer 106 is deposited by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or some other suitable process.

[0077] like Fig.11 As shown in the cross-sectional view 1100 of , a conductor heater layer 108 is conformally deposited on the cap layer 106. In some embodiments, the conductor heater layer 108 includes tungsten, titanium nitride, or some other suitable material. In some embodiments, the conductor heater layer 108 is deposited by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or some other suitable process.

[0078] By conformally depositing the cladding layer 106 and the conductor heater layer 108 on the semiconductor waveguide layer 104 having a multi-level structure (e.g., having a multi-step profile), the cladding layer 106 and the conductor heater layer 108 may have a multi-level structure (e.g., a multi-step profile) similar to the multi-level structure of the underlying waveguide. For example, the conductor heater layer 108 has a first heater layer 116 on the first waveguide layer 112, a pair of second heater layers 118 on the second waveguide layer 114 and on opposite sides of the first waveguide layer 112, and a pair of third heater layers 204 above the third waveguide layer 202 and on opposite sides of the second waveguide layer 114. By forming the conductor heater layer 108 to have the multi-level structure, the temperature control of the semiconductor waveguide layer 104 may be improved, and thus the performance of the waveguide may be improved.

[0079] like Fig.12 1200, the conductor heater layer 108 is etched to further form (e.g., define) the conductor heater layer 108. In some embodiments, the etching of the conductor heater layer 108 removes the conductor heater layer 108 from the protrusions 402, 404. In some embodiments, the etching is performed based on the photoresist mask 1202. In some embodiments, the etching includes a dry etching process or some other suitable process. In some embodiments, the photoresist mask 1202 is removed during and / or after etching.

[0080] like Fig.13 As shown in the cross-sectional view 1300 of , the first upper dielectric layer 110 is deposited on the cap layer 106 and the conductor heater layer 108. In some embodiments, the first upper dielectric layer 110 includes silicon dioxide or some other suitable material. In some embodiments, the first upper dielectric layer 110 is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0081] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 1 , the first upper dielectric layer 110 and the capping layer 106 are etched to form contact openings 1404, 1406, 1408, 1410, 1412, 1416, 1418 in the first upper dielectric layer 110 and the capping layer 106. The etching extends through the first upper dielectric layer 110 and the capping layer 106 to different depths below the topmost surface of the first upper dielectric layer 110, so that the contact openings 1404 expose the upper surface of the conductor heater layer 108 at each layer of the conductor heater layer 108.

[0082] In some embodiments, etching is performed according to the photoresist mask 1402. In some embodiments, the etching comprises a dry etching process or some other suitable process. In some embodiments, the photoresist mask 1402 is removed during and / or after etching.

[0083] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 1 , a contact layer 1502 is deposited on the first upper dielectric layer 110 and in the contact openings 1404, 1406, 1408, 1410, 1412, 1416, 1418. In some embodiments, the contact layer 1502 includes tungsten or some other suitable material. In some embodiments, the contact layer 1502 is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0084] like Fig.16 As shown in the cross-sectional view 1600 of FIG. 1 , a planarization process is performed on the contact layer 1502 to form independent contacts 126, 128, 130, 210, 212, 214, 302, 304 from the contact layer 1502 in the contact openings 1404, 1406, 1408, 1410, 1412, 1416, 1418, respectively. In some embodiments, the planarization process includes chemical mechanical planarization (CMP) or some other suitable process.

[0085] By forming separate (eg, separate) contacts on the various layers of the conductor heater layer 108, control of the temperature of the conductor heater layer 108 may be improved, and thus control of the temperature of the semiconductor waveguide layer 104 may be improved.

[0086] like Fig.17 As shown in the cross-sectional view 1700 of , a second upper dielectric layer 1702 is deposited on the first upper dielectric layer 110 and on the contacts. In addition, metal lines (e.g., metal lines 132, 134, 136, 216, 218, 220, 312, 314) are formed in the second upper dielectric layer 1702 and on the contacts, respectively.

[0087] In some embodiments, the second upper dielectric layer 1702 includes silicon dioxide or some other suitable material. In some embodiments, the second upper dielectric layer 1702 is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0088] In some embodiments, the second upper dielectric layer 1702 is etched (e.g., using a dry etching process or some other suitable process) to form metal line openings (not shown) in the second upper dielectric layer 1702 directly on the contacts. Subsequently, a metal layer (e.g., a layer including copper or some other suitable material) is deposited on the second upper dielectric layer 1702 and in the metal line openings. A planarization process (e.g., CMP or some other suitable process) may then be performed on the metal layer to form (e.g., define) separate metal lines from the metal layer.

[0089] like Fig.18 As shown in the cross-sectional view 1800 of FIG. 1 , voltage inputs (e.g., first pair of voltage inputs 142, second pair of voltage inputs 146, third pair of voltage inputs 150, first device voltage input 306, and second device voltage input 308) are formed on the contacts and coupled to the contacts (e.g., via metal lines). The voltage inputs are suitable for being respectively coupled to separate voltage sources (not shown). The voltage inputs may be or include a plurality of conductive features. For example, in some embodiments, the voltage inputs may be or include solder bumps, pads, metal lines, metal contacts, or some other suitable conductive features.

[0090] Fig.19 A flow chart showing some embodiments of a method 1900 for forming an integrated chip includes a multi-level semiconductor waveguide and a multi-level conductor heater on the multi-level semiconductor waveguide. Although method 1900 is shown and described below as a series of actions or events, it should be understood that the display order of such actions or events should not be interpreted as limiting. For example, some actions may occur in a different order and / or occur simultaneously with other actions or events other than those shown and / or described herein. In addition, all displayed actions may not be required to implement one or more aspects or embodiments described herein. In addition, one or more actions described herein may be performed in one or more individual actions and / or stages.

[0091] At block 1902, a semiconductor waveguide layer is provided. Figure 7 A cross-sectional view 700 corresponding to some embodiments of block 1902 is shown.

[0092] At block 1904, the semiconductor waveguide layer is etched to form a multi-level semiconductor waveguide from the semiconductor waveguide layer. Figure 8 and Fig. 9 Cross-sectional view 800 and cross-sectional view 900 are shown, respectively, corresponding to some embodiments of block 1904 .

[0093] At block 1906, a cladding layer is conformally deposited over the multi-level semiconductor waveguide. Fig.10 A cross-sectional view 1000 corresponding to some embodiments of block 1906 is shown.

[0094] At block 1908, a conductor heater layer is conformally deposited on the cladding layer to form a multi-level conductor heater on the multi-level semiconductor waveguide. Fig.11 A cross-sectional view 1100 corresponding to some embodiments of block 1908 is shown.

[0095] At block 1910, the conductor heater layer is etched to further form a multi-level conductor heater. Fig.12 A cross-sectional view 1200 corresponding to some embodiments of block 1910 is shown.

[0096] At block 1912, an upper dielectric layer is deposited over the multi-level conductor heater. Fig.13 A cross-sectional view 1300 corresponding to some embodiments of block 1912 is shown.

[0097] At block 1914, the upper dielectric layer and the capping layer are etched to form contact openings on different layers of the multi-level conductor heater. Fig.14 A cross-sectional view 1400 corresponding to some embodiments of block 1914 is shown.

[0098] At block 1916, a contact layer is deposited on the upper dielectric layer and in the contact openings to form contacts on different layers of the multi-level conductor heater. Fig.15 and Fig.16 Cross-sectional view 1500 and cross-sectional view 1600 are shown, respectively, corresponding to some embodiments of block 1916 .

[0099] At block 1918, a voltage input is formed on the contact and coupled to the contact. Fig.18 A cross-sectional view 1800 corresponding to some embodiments of block 1918 is shown.

[0100] Therefore, the present invention relates to an integrated chip and a method for forming the integrated chip, which includes a multi-level conductor heater layer on a multi-level semiconductor waveguide layer.

[0101] Therefore, in some embodiments, the utility model relates to an integrated chip, comprising a base dielectric layer and a multi-level semiconductor waveguide layer on the base dielectric layer. The multi-level semiconductor waveguide layer has a first waveguide layer, the first waveguide layer having a first width at a first height on the base dielectric layer. The multi-level semiconductor waveguide layer has a second waveguide layer, the second waveguide layer having a second width greater than the first width at a second height on the base dielectric layer, and the second height is less than the first height. The cladding layer is located on the multi-level semiconductor waveguide layer. The multi-level conductor heater layer is located on the cladding layer. The multi-level conductor heater layer has a first heater layer on the first waveguide layer. The multi-level conductor heater layer has a pair of second heater layers at the first height, on the second waveguide layer and on the opposite side of the first waveguide layer.

[0102] In other embodiments, the utility model relates to an integrated chip, comprising a base dielectric layer and a multi-level semiconductor waveguide layer on the base dielectric layer. The multi-level semiconductor waveguide layer has a first waveguide layer, a second waveguide layer and a third waveguide layer, the first waveguide layer having a first width at a first height on the base dielectric layer, the second waveguide layer having a second width at a second height on the base dielectric layer, the second width being greater than the first width, and the second height being less than the first height, the third waveguide layer having a third width at a third height on the base dielectric layer, the third width being greater than the second width, and the third height being less than the second height. The cladding conformally covers the multi-level semiconductor waveguide layer. The multi-level conductor heater layer conformally covers the cladding. The multi-level conductor heater layer is spaced apart from the multi-level semiconductor waveguide layer by the cladding. The multi-level conductor heater layer has a first heater layer on the first waveguide layer. The multi-level conductor heater layer has a pair of second heater layers at the first height, on the second waveguide layer and on opposite sides of the first waveguide layer. The multi-level conductor heater layer has a pair of third heater layers at a second height, on the third waveguide layer and on the opposite side of the second waveguide layer. A pair of first contacts are located on the multi-level conductor heater layer along the first heater layer and coupled to the multi-level conductor heater layer. A pair of second contacts are located on the multi-level conductor heater layer along one of the pair of second heater layers and coupled to the multi-level conductor heater layer. A pair of third contacts are located on the multi-level conductor heater layer along the other of the pair of second heater layers and coupled to the multi-level conductor heater layer. A pair of fourth contacts are located on the multi-level conductor heater layer along one of the pair of third heater layers and coupled to the multi-level conductor heater layer. A pair of fifth contacts are located on the multi-level conductor heater layer along the other of the pair of third heater layers and coupled to the multi-level conductor heater layer.

[0103] In some other embodiments, the utility model relates to a method for forming an integrated chip. The method includes etching a semiconductor waveguide layer to form a multi-level semiconductor waveguide from the semiconductor waveguide layer. The multi-level semiconductor waveguide has a first waveguide layer, which has a first width at a first height on a base dielectric layer. The multi-level semiconductor waveguide has a second waveguide layer, which has a second width greater than the first width at a second height on the base dielectric layer, and the second height is less than the first height. A cladding layer is conformally deposited on the multi-level semiconductor waveguide. A conductor heater layer is conformally deposited on the cladding layer to form a multi-level conductor heater on the cladding layer and the multi-level semiconductor waveguide. The multi-level conductor heater has a first heater layer on the first waveguide layer. The multi-level conductor heater has a pair of second heater layers at a first height, on the second waveguide layer and on opposite sides of the first waveguide layer. An upper dielectric layer is deposited on the conductor heater layer. The upper dielectric layer is etched to form a first contact opening, a second contact opening, and a third contact opening in the upper dielectric layer. The first contact opening is on the first heater layer. The second contact opening and the third contact opening are respectively on a pair of second heater layers. Metal is deposited on the upper dielectric layer and in the first contact opening, the second contact opening, and the third contact opening to form a first contact in the first contact opening, a second contact in the second contact opening, and a third contact in the third contact opening. The first contact is coupled to the multi-level conductor heater at the first heater layer. The second contact and the third contact are respectively coupled to the multi-level conductor heater at the pair of second heater layers.

[0104] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and those skilled in the art can make various changes, substitutions and modifications to them without departing from the spirit and scope of the present invention.

Claims

1. An integrated chip comprising a multi-level semiconductor waveguide and a multi-level conductor heater, characterized in that: include: a base dielectric layer; a multi-level semiconductor waveguide layer, on the base dielectric layer, the multi-level semiconductor waveguide layer having a first waveguide layer, the first waveguide layer having a first width at a first height above the base dielectric layer, the multi-level semiconductor waveguide layer having a second waveguide layer, the second waveguide layer having a second width at a second height above the base dielectric layer, the second width being greater than the first width, and the second height being less than the first height; a cladding layer on the multi-level semiconductor waveguide layer; as well as a multi-level conductor heater layer on the cladding layer, the multi-level conductor heater layer having a first heater layer on the first waveguide layer, the multi-level conductor heater layer having a pair of second heater layers at the first height, which are above the second waveguide layer and on opposite sides of the first waveguide layer.

2. The integrated chip comprising a multi-level semiconductor waveguide and a multi-level conductor heater according to claim 1, characterized in that: Also includes: a first contact located on the multi-level conductor heater layer and coupled to the multi-level conductor heater layer along the first heater layer; a second contact coupled to the multi-level conductor heater layer along a first of the pair of second heater layers; as well as A third contact is coupled to the multi-level conductor heater layer along a second one of the pair of second heater layers.

3. The integrated chip comprising a multi-level semiconductor waveguide and a multi-level conductor heater according to claim 1, characterized in that: The multi-level semiconductor waveguide layer has a third waveguide layer having a third width greater than the second width and a third height less than the second height on the base dielectric layer.

4. The integrated chip comprising a multi-level semiconductor waveguide and a multi-level conductor heater according to claim 3, characterized in that: The multi-level conductor heater layer has a pair of third heater layers at the second height, above the third waveguide layer and on opposite sides of the second waveguide layer.

5. The integrated chip comprising a multi-level semiconductor waveguide and a multi-level conductor heater according to claim 1, characterized in that: The cladding layer is directly between the first waveguide layer and the first heater layer, and directly between the second waveguide layer and the pair of second heater layers.

6. An integrated chip comprising a multi-level semiconductor waveguide and a multi-level conductor heater, characterized in that: include: a base dielectric layer; a multi-level semiconductor waveguide layer, on the base dielectric layer, the multi-level semiconductor waveguide layer comprising a first waveguide layer having a first width at a first height on the base dielectric layer, a second waveguide layer having a second width at a second height on the base dielectric layer, and a third waveguide layer having a third width at a third height on the base dielectric layer, the second width being greater than the first width, the second height being less than the first height, the third width being greater than the second width, and the third height being less than the second height; a cladding layer conformally covering the multi-level semiconductor waveguide layer; a multi-level conductor heater layer conformally overlying the cladding layer, the multi-level conductor heater layer being spaced apart from the multi-level semiconductor waveguide layer by the cladding layer, the multi-level conductor heater layer having a first heater layer on the first waveguide layer, the multi-level conductor heater layer having a pair of second heater layers at the first height above and on opposite sides of the second waveguide layer, and the multi-level conductor heater layer having a pair of third heater layers at the second height above and on opposite sides of the second waveguide layer; a pair of first contacts along the first heater layer on and coupled to the multi-level conductor heater layer; a pair of second contacts on and coupled to the multi-level conductor heater layer along one of the pair of second heater layers; a pair of third contacts on and coupled to the multi-level conductor heater layer along another one of the pair of second heater layers; a pair of fourth contacts on and coupled to the multi-level conductor heater layer along one of the pair of third heater layers; as well as A pair of fifth contacts are on the multi-level conductor heater layer along another one of the pair of third heater layers and coupled to the multi-level conductor heater layer.

7. The integrated chip comprising a multi-level semiconductor waveguide and a multi-level conductor heater according to claim 6, characterized in that: The first waveguide layer is formed by a first upper surface and a pair of first sidewalls of the multi-level semiconductor waveguide layer, wherein the second waveguide layer is formed by a pair of second upper surfaces and a pair of second sidewalls of the multi-level semiconductor waveguide layer, wherein the pair of second upper surfaces are located on opposite sides of the first upper surface and below the first upper surface, and wherein the third waveguide layer is formed by a pair of third upper surfaces of the multi-level semiconductor waveguide layer, wherein the pair of third upper surfaces are located on opposite sides of the pair of second upper surfaces and below the pair of second upper surfaces.

8. The integrated chip comprising a multi-level semiconductor waveguide and a multi-level conductor heater according to claim 7, characterized in that: The first upper surface extends between the tops of the pair of first side walls, wherein the pair of first side walls extend from the first upper surface to the pair of second upper surfaces, respectively, wherein the pair of second upper surfaces extend from the bottoms of the pair of first side walls to the tops of the pair of second side walls, respectively, wherein the pair of second side walls extend from the pair of second upper surfaces to the pair of third upper surfaces, wherein the pair of third upper surfaces extend laterally from the bottoms of the pair of second side walls, respectively.

9. The integrated chip comprising a multi-level semiconductor waveguide and a multi-level conductor heater according to claim 7, characterized in that: The first heater layer is formed by the first lower surface of the multi-level conductor heater layer, wherein the pair of second heater layers are formed by a pair of second lower surfaces of the multi-level conductor heater layer, wherein the pair of second lower surfaces of the multi-level conductor heater layer are respectively located below the first upper surface of the multi-level semiconductor waveguide layer and directly located on the pair of second upper surfaces of the multi-level semiconductor waveguide layer, wherein the pair of third heater layers are formed by a pair of third lower surfaces of the multi-level conductor heater layer, wherein the pair of third lower surfaces of the multi-level conductor heater layers are respectively located below the pair of second lower surfaces and directly located on the pair of third upper surfaces of the multi-level semiconductor waveguide layer.

10. The integrated chip comprising a multi-level semiconductor waveguide and a multi-level conductor heater according to claim 6, characterized in that: The pair of first contacts are respectively coupled to a pair of first voltage supply inputs, the pair of second contacts are respectively coupled to a pair of second voltage supply inputs, the pair of third contacts are respectively coupled to a pair of third voltage supply inputs, the pair of fourth contacts are respectively coupled to a pair of fourth voltage supply inputs, and the pair of fifth contacts are respectively coupled to a pair of fifth voltage supply inputs.

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