New energy automobile cloud battery management monitoring device

Abstract

The utility model discloses a cloud battery management monitoring device for a new energy automobile. The cloud battery management monitoring device comprises a shell, the main control board comprises a main control chip, an indicating lamp circuit, a crystal oscillator circuit, a plurality of reset circuits, a first filtering voltage stabilizing circuit, a serial port module, a USB module, a CAN conversion module, an SWD burning interface and a charging and discharging circuit. The slave control board comprises a battery pack acquisition module, a slave control chip, a daisy chain circuit, an AFE analog front end, an isoSPI communication interface, a battery equalization circuit, a discharge voltage detection circuit, a digital isolator and an NTC circuit; the slave control chip is connected with the battery pack acquisition module, the discharge voltage detection circuit, the daisy chain circuit, the digital isolator, the AFE analog front end, the isoSPI communication interface, the NTC circuit and the battery equalization circuit through pins. The utility model has the characteristic of improving the energy utilization rate of the battery pack.

Description

Technical Field

[0001] The utility model relates to the technical field of power batteries for new energy vehicles, and more specifically, to a cloud-based battery management and monitoring device for new energy vehicles. Background Art

[0002] With the rapid development of new energy vehicles, power batteries have become one of the most popular energy storage methods in electric vehicles. However, mainstream electric vehicles have experienced serious faults such as battery spontaneous combustion and sudden loss of power, which restricts the development of the new energy vehicle battery field. The reason is that traditional BMS battery management systems have problems such as low efficiency, unreliability, unsafety, and difficult maintenance. Utility Model Content

[0003] The utility model designs and develops a cloud-based battery management and monitoring device for new energy vehicles, which improves the utilization rate of battery pack energy, more accurately manages the health status of the battery pack, and reduces the danger caused by battery aging problems.

[0004] The technical solution provided by the utility model is:

[0005] A cloud-based battery management and monitoring device for new energy vehicles, comprising:

[0006] a housing; and

[0007] A main control board, which includes a main control chip, an indicator light circuit, a crystal oscillator circuit, multiple reset circuits, a first filter voltage stabilization circuit, a serial port module, a USB module, a CAN conversion module, a SWD burning interface and a charge and discharge circuit;

[0008] A slave control board, which includes a battery pack acquisition module, a slave control chip, a daisy chain circuit, an AFE analog front end, an isoSPI communication interface, a battery balancing circuit, a discharge voltage detection circuit, a digital isolator and an NTC circuit;

[0009] The main control chip includes a VBAT pin, a PC13-PC15 pin, a PD0-PD1 pin, a NRST pin, four VSS pins, four VDD pins, a PA0-PA15 pin, a PB0-PB15 pin and a BOOT0 pin. The VBAT pin is connected to the battery voltage, the PC13 pin is connected to the indicator light circuit, the PD0 pin and the PD1 pin are connected to the crystal oscillator circuit, the NRST pin, the PA1 pin, the PA2 pin and the PA3 pin are respectively connected to the first reset circuit, the second reset circuit, the third reset circuit and the fourth reset circuit. The PA5 pin is connected to the first filtering and voltage stabilizing circuit, the PA9 pin and the PA10 pin are connected to the serial port module, the PA11 pin and the PA12 pin are connected to the CAN conversion module, the PA12 pin and the PA13 pin are connected to the SWD burning interface, the PB3 pin and the PB4 pin are connected to the charging and discharging circuit, and the PB10-PB11 pins are connected to the slave control board; the PB12-PB15 pins are connected to the 5-pin connector, the 4 VSS pins are all grounded, the 4 VDD pins all output 3.3V power supply, the BOOT0 pin is connected to the first resistor R101 and then grounded, and the other pins are left floating;

[0010] The slave control chip includes a V+ pin, a C0-C12 pin, a S1-S12 pin, a GPIO1-GPIO5 pin, an NC pin, a VM pin, a VREF1-VREF2 pin, a SWTEN pin, a VREG pin, a DRIVE pin, a WDT pin, an ISOMD pin, an IMA pin, an IPA pin, an SDI pin, an SDO pin, an IBIAS pin, an ICMP pin, an IMB pin and an IPB pin. The V+ pin and the C0-C12 pin are connected to the battery pack acquisition module. The GPIO1 pin is connected to the discharge current. The GPIO2 pin and the GPIO3 pin are connected to the temperature measurement circuit and the AFE analog front end at the same time. The GPIO4 pin and the GPIO5 pin are connected to the I2C circuit. The IMA pin and the IPA pin are connected to the digital isolator and the transformer. The SDI pin and the SDO pin are connected to the digital isolator. The IBIAS pin, the ICMP pin, the IMB pin and the IPB pin are connected to the transformer. The SWTEN pin and the ISOMD pin are connected to the power circuit. The S1-S12 pins are used to connect the battery balancing circuit.

[0011] Preferably, the housing comprises:

[0012] The main body is box-shaped;

[0013] A cover plate, which is arranged on the main body to form a receiving cavity;

[0014] A plurality of connecting rods are symmetrically arranged at two ends of the main body away from the cover plate and used to fix the main body;

[0015] The main control board and the slave control board are spaced apart in the main body, the main body is provided with an SPI communication interface, a CAN receiving circuit and a USB interface, and the cover plate is provided with a battery pack information acquisition device interface and a balancing circuit communication interface.

[0016] Preferably, the indicator light circuit comprises:

[0017] A first indicator light, whose anode is connected to any VDD pin;

[0018] The anode of the second indicator light is connected to any VDD pin;

[0019] A second resistor, one end of which is connected to the cathode of the first indicator light and the other end of which is grounded;

[0020] a third resistor, one end of which is connected to the cathode of the second indicator light, and the other end of which is connected to the PC13 pin;

[0021] The anode of the second indicator light and the anode of the first indicator light are connected to the same VDD pin.

[0022] Preferably, the crystal oscillator circuit comprises:

[0023] a fourth resistor connected between the PD0 pin and the PD1 pin;

[0024] a crystal oscillator connected in parallel to both ends of the fourth resistor;

[0025] A first capacitor, one end of which is connected to one end of the crystal oscillator and the other end of which is grounded;

[0026] A second capacitor has one end connected to the other end of the crystal oscillator and the other end grounded.

[0027] Preferably, the first reset circuit comprises:

[0028] A first self-reset button, comprising pin 1, pin 2, pin 3 and pin 4;

[0029] Among them, pin 1 and pin 2 are connected to each other, pin 1 and pin 2 are connected to the NRST pin, pin 3 and pin 4 are grounded, pin 3 and pin 4 are connected to each other, and there is a self-reset button between pin 1 and pin 3.

[0030] A third capacitor, one end of which is grounded, and the other end is connected to pin 1;

[0031] A fifth resistor has one end connected to any one of the VDD pins, and the other end connected to the other end of the third capacitor.

[0032] Preferably, the slave control chip further includes:

[0033] a twenty-fifth capacitor connected between the VM pin and the VREF2 pin, and one end of the twenty-fifth capacitor connected to the NC pin;

[0034] A twenty-sixth capacitor, one end of which is connected to one end of the twenty-fifth capacitor, and the other end of which is connected to the VREF1 pin;

[0035] A twenty-seventh capacitor, one end of which is connected to one end of the twenty-fifth capacitor, and the other end of which is connected to the VREG pin;

[0036] A twenty-eighth capacitor, one end of which is connected to one end of the twenty-fifth capacitor, and one end of the twenty-eighth capacitor is grounded;

[0037] a 30th resistor, one end of which is connected to the other end of the 28th capacitor, and the other end of which is connected to the C12 pin;

[0038] a thirty-first resistor, one end of which is connected to the WDT pin, and the other end of which is connected between the twenty-seventh capacitor C39 and the VREG pin;

[0039] A bipolar transistor comprising a first C pole, an E pole, a second C pole and a B pole;

[0040] Among them, one end of the 30th resistor is connected to the first C pole, the second C pole is connected between the 28th capacitor and the 30th resistor, the E pole is connected to the other end of the 27th capacitor, and the B pole is connected to the DRIVE pin.

[0041] Preferably, the digital isolator comprises:

[0042] A thirty-first resistor, one end of which is connected to the IMA pin;

[0043] A thirty-second resistor, one end of which is connected to the IMA pin;

[0044] a thirty-third resistor, one end of which is connected to the IPA pin;

[0045] a thirty-fourth resistor, one end of which is connected to the IPA pin;

[0046] a second inductor, one end of which is connected to the other end of the thirty-first resistor, and the other end of which is connected to the conversion chip;

[0047] a third inductor, one end of which is connected to the other end of the thirty-third resistor, and the other end of which is connected to the conversion chip;

[0048] a fourth inductor, one end of which is connected to the SDI pin, and the other end of which is connected to the conversion chip;

[0049] A fifth inductor, one end of which is connected to the SDO pin, and the other end of which is connected to the conversion chip;

[0050] The other end of the thirty-second resistor and the other end of the thirty-fourth resistor are both connected to the transformer.

[0051] Preferably, the battery pack acquisition module includes:

[0052] One end of the first to thirteenth fuses is connected to pins 14 to 2 of the battery pack respectively and one end of the first fuse is connected to pin 15 of the battery pack;

[0053] A thirty-third capacitor, one end of which is connected to pin 16 of the battery pack;

[0054] The 47th to 58th capacitors are connected between the C12 pin to the C0 pin in pairs respectively;

[0055] The 41st to 53rd resistors have one end connected to the other end of the first to 13th fuses respectively, and the other ends connected to the C12 to C0 pins respectively;

[0056] The thirty-fourth to forty-fifth capacitors have one end connected to the other end of the forty-first to fifty-third resistors respectively, and the other ends are grounded;

[0057] a 46th capacitor, one end of which is connected to the other end of the 33rd capacitor, and the other end of which is connected to the C12 pin;

[0058] a sixth inductor, one end of which is connected to one end of the forty-sixth capacitor, and the other end of which is connected to one end of the forty-first resistor;

[0059] a seventh inductor, one end of which is connected to one end of the fifty-third resistor and the other end of which is grounded;

[0060] A first zener diode, a second zener diode and a third zener diode, the cathode of the first zener diode is connected to the other end of the thirty-third capacitor C1, the anode is grounded, the second zener diode and the third zener diode are connected in parallel at both ends of the first zener diode,

[0061] a fifty-fourth resistor, one end of which is connected to the other end of the thirty-third capacitor;

[0062] A fifty-ninth capacitor, one end of which is grounded, and the other end is connected to the C0 pin;

[0063] a sixtieth capacitor, one end of which is connected to the other end of the fifty-fourth resistor;

[0064] Among them, pin 1 of the battery pack is grounded, the fifty-fourth resistor and the sixtieth capacitor are connected in series and in parallel at both ends of the first voltage-stabilizing diode, and the V+ pin is connected between the fifty-fourth resistor and the sixtieth capacitor.

[0065] Preferably, the daisy chain circuit comprises:

[0066] The network port transformer comprises a first pin to a sixteenth pin;

[0067] a sixty-ninth resistor, which is disposed between the first pin and the third pin;

[0068] a seventieth resistor, which is disposed between the sixth pin and the eighth pin,

[0069] a seventy-first capacitor, one end of which is connected to the second pin, and the other end of which is grounded;

[0070] a seventy-second capacitor, one end of which is connected to the seventh pin, and the other end of which is grounded;

[0071] Among them, the first pin is connected to the IPB pin, the third pin is connected to the IMB pin, the sixth pin is connected to the IPA pin, the eighth pin is connected to the IMA pin, the ninth pin and the tenth pin are connected to the first row of pins, the fourteenth pin and the sixteenth pin are connected to the second row of pins, and the remaining pins are left floating.

[0072] Preferably, the transformer includes pin 1 to pin 16, pin 1 is connected to pin IPB, pin 2 is connected to one end of the seventy-third capacitor, the other end of the seventy-third capacitor is grounded, pin 3 is connected to pin IMB, and pins 1 and 3 are connected to the seventy-fifth resistor, pin 6 is connected to the other end of the thirty-fourth resistor, pin 7 is connected to one end of the seventy-fourth capacitor, the other end of the seventy-fourth capacitor is grounded, pin 8 is connected to the other end of the thirty-second resistor, and the seventy-eighth resistor is connected between pins 6 and 8, pins 9, 11, 14, and 16 are connected to interfaces 1 and 2 of the third row of pins for interacting with the main control chip, and the remaining pins are left floating.

[0073] Beneficial effects of the utility model:

[0074] The cloud-based battery management and monitoring device for new energy vehicles provided by the utility model can use the battery more reasonably and avoid overcharging or over-discharging. By using an equalizing circuit to balance the capacity and energy differences of the single cells in the battery pack, the utilization rate of the battery pack energy is improved, the health status of the battery pack is managed more accurately, and the danger caused by battery aging problems is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] Figure 1 It is a structural schematic diagram of the shell of the utility model.

[0076] Figure 2 It is a structural schematic diagram of the main control board of the utility model.

[0077] Figure 3 This is a circuit schematic diagram of the main control chip of the utility model.

[0078] Figure 4 The figure is a circuit schematic diagram of the indicator light circuit of the utility model.

[0079] Figure 5 The schematic diagram of the circuit of the crystal oscillator circuit of the utility model is shown in FIG.

[0080] Figure 6 This is a circuit schematic diagram of the first reset circuit of the utility model.

[0081] Figure 7 This is a circuit schematic diagram of the second reset circuit of the utility model.

[0082] Figure 8 This is a circuit schematic diagram of the third reset circuit of the utility model.

[0083] Fig. 9 This is a circuit schematic diagram of the fourth reset circuit of the utility model.

[0084] Fig.10 This is a circuit schematic diagram of the first filtering and voltage stabilizing circuit of the utility model.

[0085] Fig.11 The schematic diagram of the circuit of the serial port module of the utility model.

[0086] Fig.12 This is a circuit schematic diagram of the USB power supply voltage stabilizing circuit described in the utility model.

[0087] Fig.13 This is a circuit schematic diagram of the USB power supply filter circuit described in the utility model.

[0088] Fig.14 This is a circuit schematic diagram of the second filtering and voltage stabilizing circuit of the utility model.

[0089] Fig.15 This is a circuit schematic diagram of the USB module of the utility model.

[0090] Fig.16 The schematic diagram of the circuit of the CAN conversion module of the utility model.

[0091] Fig.17 This is a circuit schematic diagram of the SWD burning interface described in the utility model.

[0092] Fig.18The figure is a circuit schematic diagram of the charging and discharging circuit of the utility model.

[0093] Fig.19 This is a circuit schematic diagram of the external interrupt interface of the utility model.

[0094] Figure 20a-20d This is the principle diagram of the four power supply filtering and voltage stabilizing circuits described in the utility model.

[0095] Fig.21 This is a circuit schematic diagram of the voltage regulation circuit of the utility model.

[0096] Fig. 22 It is a structural schematic diagram of the slave control board described in the utility model.

[0097] Fig.23 This is a circuit schematic diagram of the slave control chip described in the utility model.

[0098] Fig.24 This is a circuit schematic diagram of the conversion chip described in the utility model.

[0099] Fig.25 This is a circuit schematic diagram of the battery pack acquisition module of the utility model.

[0100] Fig.26 This is a circuit schematic diagram of the discharge voltage detection circuit of the utility model.

[0101] Fig. 27 This is a circuit schematic diagram of the power supply selection circuit of the utility model.

[0102] Fig.28 This is a circuit schematic diagram of the discharge voltage detection circuit of the utility model.

[0103] Fig.29 This is a circuit schematic diagram of the dual-channel computing AFE analog front end of the utility model.

[0104] Fig.30 This is the circuit schematic diagram of the 4-pin thermistor NTC described in the utility model.

[0105] Fig.31 This is a circuit schematic diagram of the I2C circuit described in the utility model.

[0106] Figure 32a-Figure 32l The circuit diagram of the battery equalization circuit of the utility model is shown in FIG.

[0107] Fig.33 This is a circuit schematic diagram of the daisy chain circuit of the utility model.

[0108] Fig.34 This is a circuit schematic diagram of the temperature measurement circuit of the utility model. DETAILED DESCRIPTION

[0109] The present invention will be further described in detail below in conjunction with the accompanying drawings so that those skilled in the art can implement the invention with reference to the description.

[0110] The utility model provides a cloud-based battery management and monitoring device for new energy vehicles, comprising a shell, a main control board and a slave control board. The main control board and the slave control board are both arranged in the shell through copper studs, thereby realizing the collection, uploading, analysis and storage of vehicle power battery data, and being used for monitoring the status of the battery pack.

[0111] Among them, Figure 1 As shown, the shell includes a main body 110, a cover plate 120 and a plurality of connecting rods 130, and the main body 110 is a box-shaped structure; the cover plate 120 is arranged on the main body 110, so that the cover plate 120 and the main body 110 form a accommodating cavity; a plurality of connecting rods 130 are symmetrically spaced at both ends of the main body 110 away from the cover plate 120, for fixing the main body 110; a battery pack information acquisition device interface 101 and a balancing circuit communication interface 102 are arranged on the cover plate 120, the battery pack information acquisition device interface 101 is connected to the battery pack, and the balancing circuit communication interface 102 is connected to the positive and negative poles of the battery pack, and an SPI communication interface 103, a CAN conversion interface 104 and a USB interface 105 are arranged on the main body 110, the SPI communication interface 103 is connected to the slave control board, the CAN conversion interface 104 is a CAN conversion interface P3, and the USB interface 105 is a USB chip U4.

[0112] In this embodiment, the number of the connecting rods 130 is four.

[0113] like Figure 2 As shown, the main control board includes 1. a main control chip U1, 2. an indicator light circuit, 3. a crystal oscillator circuit, 4. multiple reset circuits, 5. a first filtering and voltage stabilizing circuit, 6. a serial port module, 7. a USB module, 8. a CAN conversion module, 9. a SWD burning interface and 10. a charging and discharging circuit.

[0114] like Figure 3As shown, the main control chip U1 includes a VBAT pin, PC13-PC15 pins, PD0-PD1 pins, an NRST pin, 4 VSS pins, 4 VDD pins, PA0-PA15 pins, PB0-PB15 pins and a BOOT0 pin. The VBAT pin is connected to the battery voltage, the PC13 pin is used to connect the indicator light circuit, the PD0 pin and the PD1 pin are used to connect the crystal oscillator circuit, the NRST pin, the PA1 pin, the PA2 pin and the PA3 pin are respectively connected to the first reset circuit, the second reset circuit, the third reset circuit and the fourth reset circuit, and the PA5 pin is used to connect the first filter voltage stabilization circuit. PA9 and PA10 pins are used to connect to the serial port module, PA11 and PA12 pins are used to connect to the CAN conversion module, PA12 and PA13 pins are used to connect to the SWD burning interface, PB3 and PB4 pins are used to connect to the charge and discharge circuit, PB10-PB11 pins are used to connect to the slave control board; PB12-PB15 pins are used to connect to the 5-pin connector, the 4 VSS pins are all grounded, the 4 VDD pins all output 3.3V power supply, the BOOT0 pin is connected to the first 10k resistor R101 and then grounded, and the other pins are left floating and can be used to connect to other slave control boards. Up to 4-5 slave control boards can be connected.

[0115] In this embodiment, the main control chip U1 is STM32F103C8T6. STM32F103C8T6 is a 32-bit microcontroller chip based on the ARM Cortex-M3 core launched by STMicroelectronics. The chip is based on the ARM Cortex-M3 core, with a clock frequency of up to 72MHz, and has high computing performance. It has Flash memory (64KB), SRAM (20KB) and EEPROM, which can be used to store program code and data, and to monitor the status of the battery pack.

[0116] Among them, Figure 4 As shown, the indicator light circuit includes a first indicator light LED3, a second indicator light LED4, a second resistor R91 and a third resistor R92, the anodes of the first indicator light LED3 and the second indicator light LED4 are connected to any one VDD pin (the same one), the cathode of the first indicator light LED3 is connected to one end of the second resistor R91, the other end of the second resistor R91 is grounded, the cathode of the second indicator light LED4 is connected to one end of the third resistor R92, and the other end of the third resistor R92 is connected to the PC13 pin.

[0117] The resistance values ​​of the second resistor R91 and the third resistor R92 are both 510R.

[0118] like Figure 5As shown, the crystal oscillator circuit includes a first capacitor C38, a second capacitor C39, a crystal oscillator X2 and a fourth resistor R89, the two ends of the fourth resistor R89 ​​are respectively connected to the PD0 pin and the PD1 pin, the crystal oscillator X2 is connected in parallel to the two ends of the fourth resistor R89, one end of the first capacitor C38 is connected to one end of the crystal oscillator X2, and the other end is grounded, one end of the second capacitor C39 is connected to the other end of the crystal oscillator X2, and the other end is grounded.

[0119] like Figure 6 As shown, the first reset circuit includes a fifth resistor R93, a third capacitor C41 and a first self-reset button SW1. The first self-reset button SW1 includes 4 pins, wherein pins 1 and 2 are connected to the NRST pin, and pins 3 and 4 are grounded. There is a self-reset button between pins 1 and 2 and pins 3 and 4. When the button is pressed, pins 1 and 2 are connected to pins 3 and 4 to reset the circuit. One end of the third capacitor C41 is connected between pins 3 and 4 and ground, and the other end of the third capacitor C41 is connected between pins 1 and 2 and the NRST pin. At the same time, one end of the fifth resistor R93 is connected to any one of the VDD pins, and the other end is connected to the other end of the third capacitor C41, so that the circuit can be restored to the starting state.

[0120] In this embodiment, the number of reset circuits is 4, as shown in FIG. Figure 6-Figure 9 As shown, the remaining three (second reset circuit, third reset circuit and fourth reset circuit) specifically include a sixth resistor R94, a seventh resistor R95, an eighth resistor R96, a fourth capacitor C42, a fifth capacitor C43, a sixth capacitor C44, a second self-reset button SW2, a third self-reset button SW3 and a fourth self-reset button SW4, and the specific connection method is the same as Figure 6 The same as in the example, they are connected between the remaining three VDD pins and the PA1 pin, PA2 pin and PA3 pin respectively.

[0121] like Fig.10 As shown, the first filtering and voltage stabilizing circuit includes a voltage reference chip U2, a seventh capacitor C25, an eighth capacitor C26 and a ninth resistor R75. The voltage reference chip U2 includes 3 pins, namely an OUT pin, an IN pin and a GND pin. The GND pin is grounded. One end of the seventh capacitor C25 is grounded, and the other end is connected to the OUT pin and the discharge voltage detection circuit at the same time. One end of the ninth resistor R75 is connected between the seventh capacitor C25 and the OUT pin, and the other end is connected to the PA5 pin. One end of the eighth capacitor C26 is grounded, and the other end is connected to the IN pin and the external power supply SUPPLY at the same time.

[0122] In this embodiment, the voltage reference chip U2 is REF3025AIDBZR.

[0123] like Fig.11 As shown, the serial port module includes: a serial port chip U8, a ninth capacitor C50, a tenth resistor R99 and an eleventh resistor R100. The serial port chip U8 includes 10 pins, specifically a UD+ pin, a UD- pin, a GND pin, an RTS# pin, a CTS# pin, a TNOW pin, a VCC pin, a TXD pin, a RXD pin and a V3 pin. The UD+ pin and the UD- pin are used to connect to the USB module as output pins for transmitting forward data and reverse data of USB data packets. The GND pin is grounded. Fig.12 As shown in FIG. 1 , a USB power supply voltage stabilizing circuit is shown, wherein the VCC pin is connected to the anode of the first switch diode D17. Fig.13 As shown in FIG. 1 , a USB power supply filter circuit is shown, wherein the VCC pin is connected to one end of the tenth capacitor C49, and the other end of the tenth capacitor C49 is grounded for filtering. Fig.14 As shown, it is a second filtering and voltage-stabilizing circuit, the cathode of the first switching diode D17 is connected to one end of the eleventh capacitor C40, and the other end of the eleventh capacitor C40 is grounded, the RXD pin is connected to one end of the tenth resistor R99, and the other end of the tenth resistor R99 is connected to the PA9 pin, and the PA9 pin is configured as a sending pin for sending data from the main control chip U1 to the serial port module U8, the TXD pin is connected to one end of the eleventh resistor R100, and the other end of the eleventh resistor R100 is connected to the PA10 pin, and the PA10 pin is configured as a receiving pin for receiving data sent from the serial port module U8 to the main control chip U1, the V3 pin is connected to one end of the ninth capacitor C5, and the other end of the ninth capacitor C5 is grounded, and both the V3 pin and the pin are suspended.

[0124] In this embodiment, the serial port chip U8 is CH340E-C99652, and the resistance of the tenth resistor R99 and the eleventh resistor R100 are both 100R.

[0125] like Fig.15 As shown, the USB module is a USB chip U4, and the USB chip U4 includes 9 pins, specifically a VBUS pin, a D- pin, a D+ pin, an ID pin, a GND pin, and SH1-SH4 pins. The VBUS pin is connected to Fig.13 , Fig.14 , Fig.15 The specific connection method is the same as the VCC pin connection method of the serial port module, the D- pin is connected to the UD- pin, the D+ pin is connected to the UD+ pin, the SH1-SH4 pins are grounded, and the ID pin is left floating.

[0126] The principle of the USB module and the serial port module is to convert the USB signal into a TTL serial communication signal to realize the connection and communication between the computer cloud and the battery monitoring management. The serial port chip U8 integrates a USB controller and a TTL serial port. When the computer is connected to the serial port chip U8 through the USB interface, the chip will convert the USB signal into a TTL serial communication signal and output it through the pin; the serial port chip U8 can accept the 5V power supply of the USB. The VCC of this circuit is connected to the 5V of the USB, and the V3 pin needs to be connected to an external 0.1uF decoupling capacitor to use the serial port chip U8's own step-down to power the chip; the serial port chip U8 supports full-speed USB device interface, is compatible with USB V2.0, has a hardware full-duplex serial port, has a built-in transmit and receive buffer, and supports a communication baud rate of 50bps to 2Mbps.

[0127] In this embodiment, the USB chip U4 is USB-MICRO-B.

[0128] like Fig.16 As shown, the CAN conversion module includes a conversion chip U7 and a twelfth resistor R90. The conversion chip U7 includes 8 pins, specifically a TXD pin, a GND pin, a VCC pin, a RXD pin, a VREF pin, a CANL pin, a CANH pin and an S pin. The TXD pin is connected to the PA12 pin, the GND pin and the S pin are grounded, and the VCC pin is connected to the Fig.15 One end of the eleventh capacitor C40 is connected, the other end of the eleventh capacitor C40 is grounded, the RXD pin is connected to the PA11 pin, the CANH pin and the CANL pin are respectively connected to the 1 and 2 interfaces of the CAN communication interface P3, and the twelfth resistor R90 is connected between the CANH pin and the 1 interface, and the CANL pin and the 2 interface.

[0129] In this embodiment, the conversion chip U7 is TJA1050T / CM,118.

[0130] like Fig.17 As shown, the SWD burning interface includes a 4-pin connector H1, wherein pin 1 is grounded, pin 4 is connected to any VDD pin, and pins 2 and 3 are respectively connected to pins PA12 and PA13, and is used to debug the MCU microcontroller or single-chip microcomputer, and can burn the program code into the flash memory inside the main control chip U1, so that the main control chip U1 can work normally.

[0131] like Fig.18As shown, the charging and discharging circuit includes: a thirteenth resistor R97, a fourteenth resistor R80, a fifteenth resistor R79, a sixteenth resistor R81, a seventeenth resistor R82, an eighteenth resistor R98, a nineteenth resistor R84, a twentieth resistor R83, a twenty-first resistor R85, a twenty-second resistor R86, a twenty-third resistor R87, a twenty-fourth resistor R88, an electric storage chip U4, a current detection amplifier U5, a third indicator light LE, a first voltage regulator diode D1, a fourth indicator light LED2, a third voltage regulator diode D15, a fourth voltage regulator diode D16, a first MOS tube Q14 and a second MOS tube Q15 The electric storage chip U4 includes 4 pins. The first pin of the electric storage chip U4 is connected to any VDD pin through the thirteenth resistor R97. The second pin of the electric storage chip U4 is connected to the PB3 pin. The third pin of the electric storage chip U4 is connected to the cathode of the third voltage zener diode D15. The anode of the third voltage zener diode D15 is connected to the source of the first MOS tube Q14. The drain of the first MOS tube Q14 is connected to the charger. At the same time, the drain is connected to the negative electrode BATC- of the battery. The gate of the first MOS tube Q14 is connected to one end of the sixteenth resistor R81. The sixteenth resistor R The other end of 81 is connected between the third pin and the cathode of the third voltage zener diode D15, the seventeenth resistor R82 is connected in parallel between the anode of the third voltage zener diode D15 and one end of the sixteenth resistor R81, the fourth pin of the electric storage chip U4 is connected to the battery pack power supply through the fourteenth resistor R80, the anode of the first voltage zener diode D1 of the third indicator light LE is connected between the fourteenth resistor R80 and the battery pack power supply, the cathode of the first voltage zener diode D1 of the third indicator light LE is connected to one end of the fifteenth resistor R79, and the other end of the fifteenth resistor R79 is connected between the third pin and the cathode of the third voltage zener diode D15; The current detection amplifier U5 has the same structure as the electrical storage chip U4, and the specific connection relationship is also the same as the connection relationship of the electrical storage chip U4, wherein the second pin of the current detection amplifier U5 is connected to the PB4 pin, the drain of the second MOS tube Q15 is connected to the discharge load and the source of the first MOS tube Q14 at the same time, the source of the second MOS tube Q15 is grounded through the twenty-third resistor R87, and the twenty-fourth resistor R88 and the current acquisition circuit are connected in parallel at both ends of the twenty-third resistor R87, which are used to control the charging and discharging process of the battery pack to prevent the battery pack from being overcharged during the charging process and over-discharged during the discharging process.

[0132] like Fig.19As shown, it is an external interrupt interface circuit, the PB10 pin and the PB11 pin are respectively connected to one end of the twenty-fifth resistor R102 and the twenty-sixth resistor R103, the other ends of the twenty-fifth resistor R102 and the twenty-sixth resistor R103 are respectively connected to the 1 and 2 interfaces of the third row of pins USART3 (J1), the third row of pins USART3 (J1) specifically has 4 interfaces, interface 3 is grounded, and interface 4 is connected to any VDD pin.

[0133] like Figure 20a-20d As shown, the four VDD pins are respectively connected to the twelfth capacitor C45, the thirteenth capacitor C46, ​​the fourteenth capacitor C47 and the fifteenth capacitor C48 of 0.1uF and then grounded as four power supply filtering and voltage stabilizing circuits for filtering.

[0134] like Fig.21As shown, the voltage regulation circuit includes a linear regulator U3, a step-down switch type integrated voltage regulator chip, a sixteenth capacitor C27, a seventeenth capacitor C28, an eighteenth capacitor C29, a nineteenth capacitor C30, a twentieth capacitor C31, a twenty-first capacitor C32, a twenty-second capacitor C33, a twenty-third capacitor C34, a twenty-fourth capacitor C35, a first inductor L2, a twenty-seventh resistor R76, a twenty-eighth resistor R77, a twenty-ninth resistor R78 and a fifth voltage regulator diode SS36, the input is a battery pack power supply and an external 5V voltage, the output is two 3.3V voltages, which are used for power conversion, the The linear regulator U3 includes 4 pins, specifically a VDD pin, 2 VOUT pins and a GND pin. The GND pin is grounded. A VOUT pin outputs VCC3.3, but it cannot be used because it is not filtered. One end of the sixteenth capacitor C27 is connected between the VOUT pin and any VDD pin, and the other end is grounded. The seventeenth capacitor C28 is connected in parallel at both ends of the sixteenth capacitor C27, another VOUT pin is connected to any VDD pin, and the VDD pin is connected to one end of the first inductor L2. The nineteenth capacitor C30, the twentieth capacitor C31, and the twenty-first capacitor C 32. One end of the 22nd capacitor C33 is connected in parallel between the VDD pin and one end of the first inductor L2, and the other end is grounded. At the same time, the anode of the 24th capacitor C35 is connected in parallel between the VDD pin and one end of the first inductor L2, and the other end is grounded. The 27th resistor R76 and the 28th resistor R77 are connected in series between one end of the first inductor L2 and the ground. The buck switch type integrated voltage regulator chip has 6 pins, including VIN pin, VOUT pin, GND pin, FEEDBACK pin, ON / OFF pin and PAD pin. One end of the 29th resistor R78 is connected to V IN pin, and the other end is connected to the battery pack power supply, the positive electrode of the twenty-third capacitor C34 is connected to one end of the twenty-ninth resistor R78, and the negative electrode is grounded. At the same time, the eighteenth capacitor C29 is connected in parallel at both ends of the twenty-third capacitor C34, the VOUT pin is connected to the other end of the first inductor L2, the cathode of the fifth voltage zener diode SS36 is connected between the VOUT pin and the other end of the first inductor L2, the anode is grounded, the GND pin is grounded, the FEEDBACK pin is linked between the twenty-seventh resistor R76 and the twenty-eighth resistor R77, and the ON / OFF pin and the PAD pin are both grounded.

[0135] In this embodiment, the step-down switch integrated voltage regulator chip is LM2576HVR-5.0, and the linear regulator U3 is BL9110-330BPFB.

[0136] like Fig. 22As shown, the slave control board includes 11. a battery pack acquisition module, 12. a slave control chip, 13. a daisy chain circuit, 14. an AFE analog front end, 15. a battery balancing circuit, 16. a discharge voltage detection circuit, 17. a digital isolator, 18. an NTC circuit and 19. an isoSPI communication interface.

[0137] like Fig.23 As shown, the slave control chip includes: V+ pin, C0-C12 pin, S1-S12 pin, GPIO1-GPIO5 pin, NC pin, VM pin, VREF1-VREF2 pin, SWTEN pin, VREG pin, DRIVE pin, WDT pin, ISOMD pin, IMA pin, IPA pin, SDI pin, SDO pin, IBIAS pin, ICMP pin, IMB pin and IPB pin, the V+ pin and C0-C12 pin are connected to the battery pack acquisition module, the GPIO1 pin is connected to the discharge voltage detection circuit, the GPIO2 pin and the GPIO3 pin are simultaneously connected to the temperature measurement circuit and the AFE analog front end, the GPIO4 pin and the GPIO5 pin are connected to the I2C circuit, the IMA pin, the IPA pin, the SDI pin, the SDO pin, the IBIAS pin, the ICMP pin, the IMB pin and the IPB pin are all connected to the digital isolator and the transformer, the twenty-fifth capacitor C34 is connected in series between the VM pin and the VREF2 pin, and the NC pin is connected to the twenty-fifth capacitor C One end of the twenty-sixth capacitor C35 is connected in parallel between the twenty-fifth capacitor C34 and the VM pin, and the other end is connected to the VREF1 pin. One end of the twenty-seventh capacitor C39 is connected in parallel between the twenty-fifth capacitor C34 and the VM pin, and the other end is connected to the VREG pin. One end of the twenty-eighth capacitor C42 is connected in parallel between the twenty-fifth capacitor C34 and the VM pin, and the other end is connected to one end of the thirtieth resistor R32. At the same time, one end of the twenty-eighth capacitor C42 is grounded, and one end of the thirty-first resistor R27 is connected to the WDT pin. , the other end is connected between the twenty-seventh capacitor C39 and the VREG pin, the other end of the thirtieth resistor R32 is connected to the C12 pin, at the same time, one end of the thirtieth resistor R32 is connected to one of the C poles of the bipolar transistor, the other C pole is connected between the twenty-eighth capacitor C42 and the thirtieth resistor R32, the E pole is connected to the other end of the twenty-seventh capacitor C39, the B pole is connected to the DRIVE pin, the SWTEN pin and the ISOMD pin can be optionally connected to REG or ground, and the S1-S12 pins are used to connect the battery balancing circuit.

[0138] In this embodiment, the slave control chip is LTC6804-1. LTC6804 is a slave control chip specially used for multi-cell battery packs. The official error is less than 1.2mv. The fastest sampling speed of 12 channels can reach 290us. The stackable architecture can support hundreds of batteries. It has a built-in isoSPITM interface: 1Mbps isolated serial communication uses a single twisted pair cable, up to 100 meters long, low EMI sensitivity and radiation, and a maximum total measurement error of 1.2mV. The measurement of all batteries in the system can be completed within 290us. 6804-1 adopts a cascade form (cascade control).

[0139] The digital isolator includes: a thirty-first resistor R23, a thirty-second resistor R22, a thirty-third resistor R21, a thirty-fourth resistor R20, a second inductor L6, a third inductor L5, a fourth inductor L4 and a fifth inductor L3, the IMA pin is simultaneously connected to one end of the thirty-first resistor R23 and the thirty-second resistor R22, the other end of the thirty-first resistor R23 is connected to one end of the second inductor L6, the IPA pin is simultaneously connected to one end of the thirty-third resistor R21 and the thirty-fourth resistor R20, the other end of the thirty-third resistor R21 is connected to one end of the third inductor L5, the other end of the thirty-second resistor R22 and the other end of the thirty-fourth resistor R20 are both connected to the transformer, the SDI pin and the SDO pin are respectively connected to one end of the fourth inductor L4 and the fifth inductor L3, the other end of the second inductor L6, the other end of the third inductor L5, the other end of the fourth inductor L4 and the other end of the fifth inductor L3 are all connected to the conversion chip.

[0140] like Fig.24As shown, the conversion chip includes a VDD1 pin, two GN first voltage-stabilizing diode D1 pins, a Vod pin, a Via pin, a Vib pin, a Vic pin, a Vid pin, an RCout pin, two GNDiso pins, a Vsel pin, a Voc pin, a Vob pin, a Voa pin and a Viso pin. The VDD1 pin is simultaneously connected to the 6th and 10th pins of the dual-row 5-pin connector P12. At the same time, the VDD1 pin is connected to a digital voltage DVD D3.3 is used to receive signals. Pins 7, 8 and 9 of the dual-row 5-pin connector P12 are simultaneously connected to the ground pin MCU-GND of the main control chip U1, pin 1 is suspended, pin 2 is connected to the Via pin, pin 3 is connected to the Vib pin, pin 4 is connected to the Vic pin, and pin 5 is connected to the Vod pin. Both GND1 pins are grounded. A twenty-ninth capacitor C47 is connected in series between the VDD1 pin and any one of the GND1 pins. At the same time, a thirtieth capacitor C49 is connected in parallel at both ends of the twenty-ninth capacitor C47. A thirty-fifth resistor R43 is connected in parallel between the Via pin and the VDD1 pin, a thirty-sixth resistor R44 is connected in parallel between the Vib pin and the VDD1 pin, and a thirty-seventh resistor R45 is connected in parallel between the Vic pin and the VDD1 pin. Both GNDiso pins are grounded. The Viso pin It is connected to one end of the thirty-eighth resistor R33, the other end of the thirty-eighth resistor R33 is connected to the other end of the fifth inductor L3, one end of the thirty-first capacitor C43 is connected to one end of the thirty-eighth resistor R33, and the other end is connected to the GNDiso pin, the thirty-second capacitor C44 is connected in parallel to both ends of the thirty-first capacitor C43, one end of the thirty-ninth resistor R36 is connected to one end of the thirty-eighth resistor R33, and the other end is connected to the Vsel pin, one end of the fortieth resistor R37 is connected between the thirty-ninth resistor R36 and the Vsel pin, and the other end is connected to the GNDiso pin, the Vid pin is connected to the other end of the fifth inductor L3, the Voa pin is connected to the other end of the second inductor L6, the Vob pin is connected to the other end of the third inductor L5, and the Voc pin is connected to the other end of the fourth inductor L4.

[0141] In this embodiment, the conversion chip is ADUM5401.

[0142] like Fig.25As shown, in this embodiment, the battery pack is 16 groups of batteries, and correspondingly, the battery pack acquisition module includes the first fuse B1-thirteenth fuse B13, the sixth inductor L1, the seventh inductor L1-1, the thirty-third capacitor C1, the thirty-fourth capacitor C2-forty-fifth capacitor C13, the forty-sixth capacitor C15, the forty-seventh capacitor C16-fifty-eighth capacitor C27, the fifty-ninth capacitor C28, the sixtieth capacitor C29, the forty-first resistor R2-fifty-third resistor R14, the fifty-fourth resistor R15, the first voltage stabilizing diode D 1. The second voltage zener diode D2 and the third voltage zener diode D3, the 1st pin of the battery pack is grounded, the 2nd pin to the 14th pin are respectively connected to one end of the 13th fuse B13-the first fuse B1, the 15th pin is connected to one end of the first fuse B1, the other ends of the first fuse B1-the 13th fuse B13 are respectively connected to one end of the 41st resistor R2-the 53rd resistor R14, the other ends of the 41st resistor R2-the 53rd resistor R14 are respectively connected to the C12-C0 pins, and the C12-C0 pins are connected in pairs. The forty-seventh capacitor C16 to the fifty-eighth capacitor C27 are connected in sequence between the pins, the 16th pin of the battery pack is connected to one end of the thirty-third capacitor C1 as the positive electrode of the battery pack, the other end of the thirty-third capacitor C1 is connected in series with the forty-sixth capacitor C15 and then connected to the C12 pin, the sixth inductor L1 is connected in parallel to both ends of the forty-sixth capacitor C15 and the forty-first resistor R2, the cathode of the first zener diode D1 is connected to the other end of the thirty-third capacitor C1, the anode is grounded, the second zener diode D2 and the third zener diode D3 are both connected in parallel to the first zener diode The fifty-fourth resistor R15 and the sixtieth capacitor C29 are connected in series and then in parallel at both ends of the first voltage zener diode D1, and the V+ pin is connected between the fifty-fourth resistor R15 and the sixtieth capacitor C29, one end of the thirty-fourth capacitor C2-the forty-fifth capacitor C13 is respectively connected to the other end of the forty-first resistor R2-the fifty-third resistor R14, and the other ends are all grounded, the C0 pin is grounded through the fifty-ninth capacitor C28, one end of the seventh inductor L1-1 is connected to one end of the fifty-third resistor R14, and the other end is grounded.

[0143] like Fig.26As shown, the discharge voltage detection circuit includes a current sampling chip, a voltage stabilizing chip, a fifty-fifth resistor R16, a fifty-sixth resistor R17, a fifty-seventh resistor R29, a sixty-first capacitor C31, a sixty-second capacitor C37, a sixty-third capacitor C38 and a sixty-fourth capacitor C46, ​​the current sampling chip includes a -IN pin, a +IN pin, a GND pin, a REF1 pin, a REF2 pin, a V+ pin, an NC pin and an OUT pin, the -IN pin is connected to one end of the fifty-sixth resistor R17, the +IN pin is connected to one end of the fifty-fifth resistor R16, and the sixty-first capacitor C31 is connected between one end of the fifty-sixth resistor R17 and one end of the fifty-fifth resistor R16, the fifty-fifth resistor R16 and the fifty-sixth resistor R17 play a voltage dividing role to protect Circuit, GND pin and NC pin are grounded, REF2 pin is connected to external variable power supply REF, one end of the fifty-seventh resistor R29 is connected to the OUT pin, and the other end is connected to the GPIO1 pin, the other end of the fifty-seventh resistor R29 is grounded through the sixty-second capacitor C37, the V+ pin is connected to the power supply circuit, and at the same time, the V+ pin and the power supply are grounded through the sixty-third capacitor C38, which plays a filtering role and can remove signals in certain frequency bands from the total signal. The voltage stabilizing chip includes 2 GND pins, EN pin, IN pin and 2 OUT pins, the 2 OUT pins are both connected to the REF1 pin, the EN pin and the IN pin are both connected to the power supply circuit, and the EN pin is grounded through the sixty-fourth capacitor C46, ​​which plays a voltage stabilizing role, and the 2 GND pins are both grounded.

[0144] In this embodiment, the current sampling chip is INA282, which is a voltage output current shunt monitor that can sense the voltage drop from -14V to +80V on the common mode voltage, regardless of the power supply voltage. The low offset of the zero-drift architecture reduces the maximum voltage drop of the current sensing across the shunt to 10mV full scale, powered by a +2.7V to +18V power supply, using a maximum power supply current of 900pA, to achieve more accurate current sampling. The voltage regulator chip is REF3225, which is a precision low-dropout linear regulator.

[0145] like Fig. 27 As shown, it is a power supply selection circuit, SUPPLY is the external power supply, REG is the register signal, and by changing the external power supply, the jumper cap can connect the power supply circuit to the 5V power supply or the register signal REG. The REG is connected to the VREG pin of the slave control chip, and can be optionally connected to the SWTEN pin and the ISOMD pin.

[0146] like Fig.28As shown, the discharge voltage detection circuit is connected in parallel to both ends of the twenty-fourth resistor R88 through the other end of the fifty-sixth resistor R17 and the other end of the fifty-fifth resistor R16. At the same time, the discharge voltage detection circuit is connected to pin 1 and pin 2 of the 2-pin connector through the other end of the fifty-sixth resistor R17 and the other end of the fifty-fifth resistor R16, respectively, and the fifty-eighth resistor R1 and the fifty-ninth resistor R1-1 are connected in parallel between pin 1 and pin 2 of the 2-pin connector.

[0147] like Fig.29 As shown, the AFE analog front end includes an amplifier chip, a 60th resistor R18, a 61st resistor R19, a 62nd resistor R34, a 63rd resistor R35, a 65th capacitor C30, a 66th capacitor C33, a 67th capacitor C40, a 68th capacitor C41 and a 69th capacitor C45, the amplifier chip includes an OUTA pin, a -INA pin, a +INA pin, a V- pin, a +INB pin, a -INB pin, an OUTB pin and a V+ pin, the OUTA pin and the -INA pin are both connected to one end of the 61st resistor R19, and the other end of the 61st resistor R19 is connected to the 60th resistor R1 8, the other end of the sixtieth resistor R18 is connected to the GPIO3 pin, one end of the sixty-fifth capacitor C30 is connected to the GPIO3 pin, and the other end is grounded, the +INA pin is grounded through the sixty-sixth capacitor C33, the V- pin is grounded, the +INB pin is grounded through the sixty-seventh capacitor C40, the -INB pin and the OUTB pin are simultaneously connected to one end of the sixty-second resistor R34, the other end of the sixty-second resistor R34 is connected to one end of the sixty-third resistor R35, the other end of the sixty-third resistor R35 is grounded through the sixty-ninth capacitor C45, and at the same time, the other end of the sixty-third resistor R35 is connected to the GPIO2 pin.

[0148] like Fig.30 As shown, pin 1 of the 4-pin thermistor NTC is connected to the other end of the sixty-first resistor R19, pins 2 and 3 are grounded, and pin 4 is connected to the other end of the sixty-second resistor R34.

[0149] like Fig.31As shown, the I2C circuit includes a memory chip, a sixty-fourth resistor R70, a sixty-fifth resistor R71 and a seventy-third capacitor C23, the memory chip includes A0-A2 pins, a VSS pin, an SDA pin, an SCL pin, a WC / pin and a VCC pin, the A0-A2 pins and the VSS pins are grounded, the SDA pin is connected to the GPIO4 pin, the SCL pin is connected to the GPIO5 pin, during the read and write operations, through the signal sent by GPIO, the AT24C02 will send a response signal to confirm that the data has been received, which is an important mechanism to ensure the correctness of data transmission, the WC / pin is connected to one end of the seventy-third capacitor C23, and one end of the seventy-third capacitor C23 is grounded, and the other end of the seventy-third capacitor C23 can be selectively connected to a 5V power supply or a register signal REG under the action of an external power supply SUPPY, the VCC pin can be selectively connected to a 5V power supply or a register signal REG, the sixty-fourth resistor R70 is connected between the SCL pin and the VCC pin, and the sixty-fifth resistor R71 is connected between the SDA pin and the VCC pin.

[0150] In this embodiment, the memory chip is AT 24C02, which is a serial EEPROM memory based on the I2C interface. Under the I2C communication protocol, AT24C02 supports two basic operations: write operation and read operation. The write operation is used to store data in the EEPROM, and the read operation is used to retrieve data from the EEPROM.

[0151] like Figure 32a-Figure 32l As shown in FIG. 1 , a battery balancing circuit (MAX: 100 mA) is connected between the C0-C12 pins in sequence to set the battery balancing circuit between the C0 pin and the C1 pin. Fig.32aFor example, the battery balancing circuit includes an MMOS tube, a sixty-sixth resistor R73, a sixty-seventh resistor R70, a sixty-eighth resistor R76 and a first light-emitting diode D13, one end of the sixty-seventh resistor R70 is connected to the C0 pin, the other end is connected to the source, the gate is connected to the C1 pin, and the current of the output end drain is controlled by the voltage applied to the gate, the anode of the first light-emitting diode D13 is connected to the other end of the sixty-seventh resistor R70, the cathode is connected to one end of the sixty-eighth resistor R76, and the other end of the sixty-eighth resistor R76 is connected to one end of the sixty-seventh resistor R70 The gate is connected to the S1 pin through the sixty-sixth resistor R73, and the other battery balancing circuits are connected in the same manner as above. Specifically, the second light-emitting diode D15, the third light-emitting diode D14, the fourth light-emitting diode D10, the fifth light-emitting diode D12, the sixth light-emitting diode D11, the seventh light-emitting diode D7, the eighth light-emitting diode D9, the ninth light-emitting diode D8, the tenth light-emitting diode D4, the eleventh light-emitting diode D6, the twelfth light-emitting diode D5, the seventy-ninth resistor R72, the eightieth resistor R75, and the eighty-first resistor R78, the eighty-second resistor R71, the eighty-third resistor R74, the eighty-fourth resistor R77, the eighty-fifth resistor R61, the eighty-sixth resistor R64, the eighty-seventh resistor R67, the eighty-eighth resistor R63, the eighty-ninth resistor R66, the ninety-first resistor R69, the ninety-first resistor R62, the ninety-second resistor R65, the ninety-third resistor R68, the ninety-fourth resistor R52, the ninety-fifth resistor R58, the ninety-sixth resistor R55, the ninety-seventh resistor R54, the ninety-eighth resistor R57, the ninety-ninth resistor R60, the one hundredth resistor R5 3. The one-hundred-and-first resistor R56, the one-hundred-and-second resistor R59, the one-hundred-and-third resistor R40, the one-hundred-and-fourth resistor R46, the one-hundred-and-fifth resistor R49, the one-hundred-and-sixth resistor R42, the one-hundred-and-seventh resistor R48, the one-hundred-and-eighth resistor R51, the one-hundred-and-ninth resistor R41, the one-hundred-and-tenth resistor R47 and the one-hundred-and-eleventh resistor R50. Since passive balancing uses resistors to dissipate energy, it will generate heat and the balancing current is small, which will reduce the efficiency of the entire system. The passive balancing designed based on the requirements of thermal management adopts section-by-section balancing.

[0152] like Fig.33As shown, the daisy chain circuit includes a network port transformer L3-3, a sixty-ninth resistor R40, a seventy-first resistor R45, a seventy-first capacitor C19 and a seventy-second capacitor C20, the network port transformer L3-3 includes 16 pins, the first pin is connected to the IPB pin, the second pin is grounded through the seventy-first capacitor C19, and plays a filtering role, the third pin is connected to the IMB pin, the sixty-ninth resistor R40 is set between the first pin and the third pin, and serves as a terminal resistor to reduce signal interference, the sixth pin is connected to the IPA pin, and is used to provide a clock signal to ensure synchronous transmission of data, and the eighth pin is connected to the IMA pin, which can be used to select a specific LTC6804 device for communication. By setting the IMA pin to a low level, the LTC6804 device can be selected. For serial communication with it, the seventieth resistor R45 is set between the sixth pin and the eighth pin, the seventh pin is grounded through the seventy-second capacitor C20, the ninth pin and the tenth pin are connected to the first row of pins A, the fourteenth pin and the sixteenth pin are connected to the second row of pins B, and the remaining pins are left floating, which is used to connect multiple slave control chips in series, so that each battery in a long string of high-voltage batteries can be monitored simultaneously. Each LTC6804 has an isoSPI interface, namely, a serial data input pin SDI, a serial data output pin SDO, a serial clock pin SCK, and a slave chip communication pin CSB for selecting or activating the slave chip, which is used to achieve high-speed, RF-interference-resistant local communication. When using LTC6804-1, multiple devices are connected in daisy chain, and all devices are connected to a main processor.

[0153] In this embodiment, the network port transformer L1 is HX1188NLT.

[0154] like Fig.34 As shown, the temperature measurement circuit includes a second thermistor NTC, a seventy-first resistor R67, a seventy-second resistor R69, a seventy-third resistor R73 and a seventy-fourth resistor R74. The second thermistor NTC is a 4-pin connector, pin 1 is connected to one end of the seventy-first resistor R67, the other end of the seventy-first resistor R67 is connected to the GPIO2 pin, one end of the seventy-second resistor R69 is connected to one end of the seventy-first resistor R67, and the other end is connected to the VREF2 pin, pins 2 and 3 are grounded, pin 4 is connected to the VREF2 pin through the seventy-third resistor R73, one end of the seventy-fourth resistor R74 is connected to pin 4, and the other end is connected to the GPIO3 pin.

[0155] like Fig.23As shown, the transformer has 16 pins, pin 1 is connected to the IPB pin, pin 2 is grounded through the seventy-third capacitor C19, pin 3 is connected to the IMB pin, and the seventy-fifth resistor is connected to pins 1 and 3, pin 6 is connected to the other end of the thirty-fourth resistor R20, pin 7 is grounded through the seventy-fourth capacitor C36, pin 8 is connected to the other end of the thirty-second resistor R22, and the seventy-eighth resistor R28 is connected between pins 6 and 8, pins 9, 11, 14, and 16 are connected to interfaces 1 and 2 of the pin header USART for interacting with the main control chip U1, and the remaining pins are left floating.

[0156] The transformer is TG110.

[0157] Battery interface: Header 16 pins are used to connect the positive and negative poles of the battery pack, and after voltage stabilization, they are connected to the V+ pin of the slave control chip to monitor the voltage and current of the battery. Communication interface: The PA11 and PA12 pins of the master control chip are connected to the TXD and RXD pins of the CAN conversion module U7, and CANL and CANH are connected to the CAN conversion interface P3 for communication with other devices, such as the CAN bus interface. Charge and discharge interface: The PB3 and PB4 pins of the master control chip are connected to the third pin of the electric storage chip U4 and the current detection amplifier U5. The indicator light LED1, the fourth indicator light LED2, the 4 pins of U4 and U5 are connected to R80 and R84, one end of LED1 and LED2 is connected to the battery positive electrode BATVCC and the other end is connected to R79 and R83 respectively, the fourth voltage zener diode D16 and the third voltage zener diode D15 are connected to R81, R82, R85, R86 respectively, the gates of the first MOS tube Q14 and the second MOS tube Q15 are connected to the negative electrode of the battery, thereby changing the current between the drain and the source, which is used to connect the charger and the discharge load to control the charging and discharging process of the battery.

[0158] The working process of the cloud-based battery management and monitoring device for new energy vehicles described in the utility model is as follows:

[0159] The LTC6804 third-generation battery pack monitor is used to measure the voltage of multiple series-connected batteries at the same time, and various sensors are used to collect data on the battery pack. The main control chip U1 is used to manage the battery pack, and then data communication is carried out through the CAN controller local area network communication to realize communication between the main control board and the host computer, complete the setting of various parameters of the main control board and the slave control board, and upload the data to the cloud. The cloud data upload can store the battery pack data throughout the life cycle of the vehicle, so as to grasp the overall situation more accurately.

[0160] The cloud-based battery management and monitoring device for new energy vehicles provided by the utility model can use the battery more reasonably and avoid overcharging or over-discharging. By using an equalizing circuit to balance the capacity and energy differences of the single cells in the battery pack, the utilization rate of the battery pack energy is improved, the health status of the battery pack is managed more accurately, and the danger caused by battery aging problems is reduced.

[0161] Although the implementation scheme of the utility model has been disclosed as above, it is not limited to the applications listed in the specification and implementation modes. It can be fully applied to various fields suitable for the utility model. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the utility model is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A cloud-based battery management and monitoring device for new energy vehicles, characterized in that: include: case; as well as A main control board, which includes a main control chip, an indicator light circuit, a crystal oscillator circuit, multiple reset circuits, a first filter voltage stabilization circuit, a serial port module, a USB module, a CAN conversion module, a SWD burning interface and a charge and discharge circuit; A slave control board, which includes a battery pack acquisition module, a slave control chip, a daisy chain circuit, an AFE analog front end, an isoSPI communication interface, a battery balancing circuit, a discharge voltage detection circuit, a digital isolator and an NTC circuit; The main control chip includes a VBAT pin, a PC13-PC15 pin, a PD0-PD1 pin, a NRST pin, four VSS pins, four VDD pins, a PA0-PA15 pin, a PB0-PB15 pin and a BOOT0 pin. The VBAT pin is connected to the battery voltage, the PC13 pin is connected to the indicator light circuit, the PD0 pin and the PD1 pin are connected to the crystal oscillator circuit, the NRST pin, the PA1 pin, the PA2 pin and the PA3 pin are respectively connected to the first reset circuit, the second reset circuit, the third reset circuit and the fourth reset circuit. The PA5 pin is connected to the first filtering and voltage stabilizing circuit, the PA9 pin and the PA10 pin are connected to the serial port module, the PA11 pin and the PA12 pin are connected to the CAN conversion module, the PA12 pin and the PA13 pin are connected to the SWD burning interface, the PB3 pin and the PB4 pin are connected to the charging and discharging circuit, and the PB10-PB11 pins are connected to the slave control board; the PB12-PB15 pins are connected to the 5-pin connector, the 4 VSS pins are all grounded, the 4 VDD pins all output 3.3V power supply, the BOOT0 pin is connected to the first resistor R101 and then grounded, and the other pins are left floating; The slave control chip includes a V+ pin, a C0-C12 pin, a S1-S12 pin, a GPIO1-GPIO5 pin, an NC pin, a VM pin, a VREF1-VREF2 pin, a SWTEN pin, a VREG pin, a DRIVE pin, a WDT pin, an ISOMD pin, an IMA pin, an IPA pin, an SDI pin, an SDO pin, an IBIAS pin, an ICMP pin, an IMB pin and an IPB pin. The V+ pin and the C0-C12 pin are connected to the battery pack acquisition module. The GPIO1 pin is connected to the discharge current. The GPIO2 pin and the GPIO3 pin are connected to the temperature measurement circuit and the AFE analog front end at the same time. The GPIO4 pin and the GPIO5 pin are connected to the I2C circuit. The IMA pin and the IPA pin are connected to the digital isolator and the transformer. The SDI pin and the SDO pin are connected to the digital isolator. The IBIAS pin, the ICMP pin, the IMB pin and the IPB pin are connected to the transformer. The SWTEN pin and the ISOMD pin are connected to the power circuit. The S1-S12 pins are used to connect the battery balancing circuit.

2. The cloud-based battery management and monitoring device for new energy vehicles according to claim 1, characterized in that: The housing comprises: The main body is box-shaped; A cover plate, which is arranged on the main body to form a receiving cavity; A plurality of connecting rods are symmetrically arranged at two ends of the main body away from the cover plate and used to fix the main body; The main control board and the slave control board are spaced apart in the main body, the main body is provided with an SPI communication interface, a CAN receiving circuit and a USB interface, and the cover plate is provided with a battery pack information acquisition device interface and a balancing circuit communication interface.

3. The cloud-based battery management and monitoring device for new energy vehicles as claimed in claim 2, characterized in that: The indicator light circuit comprises: A first indicator light, whose anode is connected to any VDD pin; The second indicator light has its anode connected to any VDD pin; A second resistor, one end of which is connected to the cathode of the first indicator light and the other end of which is grounded; a third resistor, one end of which is connected to the cathode of the second indicator light, and the other end of which is connected to the PC13 pin; The anode of the second indicator light and the anode of the first indicator light are connected to the same VDD pin.

4. The cloud-based battery management and monitoring device for new energy vehicles as claimed in claim 3, characterized in that: The crystal oscillator circuit comprises: a fourth resistor connected between the PD0 pin and the PD1 pin; a crystal oscillator connected in parallel to both ends of the fourth resistor; A first capacitor, one end of which is connected to one end of the crystal oscillator and the other end of which is grounded; A second capacitor has one end connected to the other end of the crystal oscillator and the other end grounded.

5. The cloud-based battery management and monitoring device for new energy vehicles as claimed in claim 4, characterized in that: The first reset circuit comprises: A first self-reset button, comprising pin 1, pin 2, pin 3 and pin 4; Among them, pin 1 and pin 2 are connected to each other, pin 1 and pin 2 are connected to the NRST pin, pin 3 and pin 4 are grounded, pin 3 and pin 4 are connected to each other, and there is a self-reset button between pin 1 and pin 3. A third capacitor, one end of which is grounded, and the other end is connected to pin 1; A fifth resistor has one end connected to any one of the VDD pins, and the other end connected to the other end of the third capacitor.

6. The cloud-based battery management and monitoring device for new energy vehicles as claimed in claim 5, characterized in that: The slave control chip also includes: a twenty-fifth capacitor connected between the VM pin and the VREF2 pin, and one end of the twenty-fifth capacitor connected to the NC pin; A twenty-sixth capacitor, one end of which is connected to one end of the twenty-fifth capacitor, and the other end of which is connected to the VREF1 pin; A twenty-seventh capacitor, one end of which is connected to one end of the twenty-fifth capacitor, and the other end of which is connected to the VREG pin; A twenty-eighth capacitor, one end of which is connected to one end of the twenty-fifth capacitor, and one end of the twenty-eighth capacitor is grounded; a 30th resistor, one end of which is connected to the other end of the 28th capacitor, and the other end of which is connected to the C12 pin; a thirty-first resistor, one end of which is connected to the WDT pin, and the other end of which is connected between the twenty-seventh capacitor C39 and the VREG pin; A bipolar transistor comprising a first C pole, an E pole, a second C pole and a B pole; Among them, one end of the 30th resistor is connected to the first C pole, the second C pole is connected between the 28th capacitor and the 30th resistor, the E pole is connected to the other end of the 27th capacitor, and the B pole is connected to the DRIVE pin.

7. The cloud-based battery management and monitoring device for new energy vehicles as claimed in claim 6, characterized in that: The digital isolator comprises: A thirty-first resistor, one end of which is connected to the IMA pin; A thirty-second resistor, one end of which is connected to the IMA pin; a thirty-third resistor, one end of which is connected to the IPA pin; A thirty-fourth resistor, one end of which is connected to the IPA pin; a second inductor, one end of which is connected to the other end of the thirty-first resistor, and the other end of which is connected to the conversion chip; a third inductor, one end of which is connected to the other end of the thirty-third resistor, and the other end of which is connected to the conversion chip; a fourth inductor, one end of which is connected to the SDI pin, and the other end of which is connected to the conversion chip; A fifth inductor, one end of which is connected to the SDO pin, and the other end of which is connected to the conversion chip; The other end of the thirty-second resistor and the other end of the thirty-fourth resistor are both connected to the transformer.

8. The cloud-based battery management and monitoring device for new energy vehicles as claimed in claim 7, characterized in that: The battery pack acquisition module comprises: One end of the first to thirteenth fuses is connected to pins 14 to 2 of the battery pack respectively and one end of the first fuse is connected to pin 15 of the battery pack; A thirty-third capacitor, one end of which is connected to pin 16 of the battery pack; The 47th to 58th capacitors are connected between the C12 pin to the C0 pin in pairs respectively; The 41st to 53rd resistors have one end connected to the other end of the first to 13th fuses respectively, and the other ends connected to the C12 to C0 pins respectively; The thirty-fourth to forty-fifth capacitors have one end connected to the other end of the forty-first to fifty-third resistors respectively, and the other ends are grounded; a 46th capacitor, one end of which is connected to the other end of the 33rd capacitor, and the other end of which is connected to the C12 pin; a sixth inductor, one end of which is connected to one end of the forty-sixth capacitor, and the other end of which is connected to one end of the forty-first resistor; a seventh inductor, one end of which is connected to one end of the fifty-third resistor and the other end of which is grounded; A first zener diode, a second zener diode and a third zener diode, the cathode of the first zener diode is connected to the other end of the thirty-third capacitor C1, the anode is grounded, the second zener diode and the third zener diode are connected in parallel at both ends of the first zener diode, a fifty-fourth resistor, one end of which is connected to the other end of the thirty-third capacitor; A fifty-ninth capacitor, one end of which is grounded, and the other end is connected to the C0 pin; a sixtieth capacitor, one end of which is connected to the other end of the fifty-fourth resistor; Among them, pin 1 of the battery pack is grounded, the fifty-fourth resistor and the sixtieth capacitor are connected in series and in parallel at both ends of the first voltage-stabilizing diode, and the V+ pin is connected between the fifty-fourth resistor and the sixtieth capacitor.

9. The cloud-based battery management and monitoring device for new energy vehicles as claimed in claim 8, characterized in that: The daisy chain circuit comprises: The network port transformer comprises a first pin to a sixteenth pin; a sixty-ninth resistor, which is disposed between the first pin and the third pin; a seventieth resistor, which is disposed between the sixth pin and the eighth pin, a seventy-first capacitor, one end of which is connected to the second pin, and the other end of which is grounded; a seventy-second capacitor, one end of which is connected to the seventh pin, and the other end of which is grounded; Among them, the first pin is connected to the IPB pin, the third pin is connected to the IMB pin, the sixth pin is connected to the IPA pin, the eighth pin is connected to the IMA pin, the ninth pin and the tenth pin are connected to the first row of pins, the fourteenth pin and the sixteenth pin are connected to the second row of pins, and the remaining pins are left floating.

10. The cloud-based battery management and monitoring device for new energy vehicles as claimed in claim 9, characterized in that: The transformer includes pins 1 to 16, pin 1 is connected to pin IPB, pin 2 is connected to one end of the seventy-third capacitor, the other end of the seventy-third capacitor is grounded, pin 3 is connected to pin IMB, and pins 1 and 3 are connected to the seventy-fifth resistor, pin 6 is connected to the other end of the thirty-fourth resistor, pin 7 is connected to one end of the seventy-fourth capacitor, the other end of the seventy-fourth capacitor is grounded, pin 8 is connected to the other end of the thirty-second resistor, and the seventy-eighth resistor is connected between pins 6 and 8, pins 9, 11, 14, and 16 are connected to interfaces 1 and 2 of the third row of pins for interacting with the main control chip, and the remaining pins are left floating.

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