Double-SGT MOSFET device with common drain electrode

Abstract

The utility model discloses a drain-shared double-SGT MOSFET device, and relates to the technical field of semiconductors, the drain-shared double-SGT MOSFET device comprises a substrate and an epitaxial layer, the top surface of the epitaxial layer is provided with a plurality of grooves side by side, the bottom side walls and the inner bottoms of the grooves are provided with shield gate oxide layers, and the shield gate oxide layers on the bottom side walls of the grooves are filled with first polycrystalline silicon; a trench middle shielding oxide layer is deposited at the top end of the first polycrystalline silicon, a gate oxide layer is arranged at the top end of the trench middle shielding oxide layer and located on the side wall of the trench, and the gate oxide layer is filled with second polycrystalline silicon; a source region and a base region are formed between every two adjacent grooves from top to bottom, communicated first top layer contact holes are formed in the source regions and the base regions, the first top layer contact holes are filled with conductive materials to form MOS structures, and connecting layers are formed on the surfaces of the MOS structures; and a groove middle insulating column is vertically arranged in the middle in the groove. According to the utility model, the on-resistance is greatly reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and in particular to a double SGT MOSFET device with a shared drain. Background Art

[0002] The SGT MOSFET (Shield Gate Trench MOSFET) structure has a charge coupling effect. It introduces horizontal depletion on the basis of the vertical depletion of the PN junction of the traditional trench MOSFET device, changing the device electric field distribution from a triangular distribution to a nearly rectangular distribution. When using the same epitaxial material specifications with the same doping concentration, the device can achieve a higher breakdown voltage.

[0003] Lithium-ion batteries offer superior performance, making them the preferred choice for consumer electronic devices. However, the materials used in lithium batteries inherently protect them from overcharge, over-discharge, overcurrent, short circuits, and extreme high-temperature charging and discharging. Therefore, lithium battery components are often accompanied by a sophisticated protection board and current fuse. A lithium battery protection board typically includes a control IC, MOS switches, resistors, capacitors, and auxiliary components such as NTCs and ID memory. Under normal conditions, the control IC turns on the MOS switches, allowing the battery cell to communicate with the external circuit. However, if the cell voltage or loop current exceeds specified limits, it immediately (within tens of milliseconds) turns off the MOS switches, protecting the cell.

[0004] In existing protection board circuits, two MOS transistors are connected via external wiring and welding to achieve the protection circuit's switch control function. Taking the charging state as an example, current flows from port P1 into cell B1, from the source of MOS transistor M1, through the MOS structure Q1, drift region, and substrate within MOS transistor M1, out of the drain of MOS transistor M1, then into the drain of MOS transistor M2. Then, it passes through the substrate, drift region, and MOS structure Q2 of MOS transistor M2 and out of the source of MOS transistor M2, thus forming a charging current loop. The discharge process is essentially the same, so the current must pass through the internal and external wiring of the two MOS transistors to achieve loop conduction. As a result, the current path is too long, resulting in excessive on-resistance, which significantly affects the reliability of the device.

[0005] However, an important practical indicator of the protection circuit is the on-resistance. Since communication equipment operates at a high frequency and data transmission requires a low bit error rate, the rising and falling edges of its pulse train are steep, which places high demands on the current output capacity and voltage stability of battery cell B1. Therefore, how to minimize the resistance of the MOS tube when the switch in the protection circuit is turned on is an urgent problem to be solved.

[0006] Currently, no effective solutions have been proposed for the problems in related technologies. Utility Model Content

[0007] In response to the problems in the related art, the present invention proposes a dual SGT MOSFET device with a shared drain to overcome the above technical problems in the existing related art.

[0008] To this end, the specific technical solutions adopted in this utility model are as follows:

[0009] A dual SGT MOSFET device with a shared drain comprises a substrate, an epitaxial layer provided on the top of the substrate, a plurality of trenches arranged side by side on the top surface of the epitaxial layer, shielding gate oxide layers provided on the bottom sidewalls and inner bottom of the trenches, the shielding gate oxide layers on the bottom sidewalls of the trenches being filled with first polysilicon; a middle trench shielding oxide layer deposited on the top of the first polysilicon, a gate oxide layer provided on the top of the middle trench shielding oxide layer and on the sidewalls of the trenches, the gate oxide layer being filled with second polysilicon; a source region and a base region formed between two adjacent trenches from top to bottom, a first top-layer contact hole communicating with the source region and the base region being formed, a MOS structure being formed by filling the first top-layer contact hole with a conductive material, and a connection layer being formed on the surface of the MOS structure; and a middle trench insulating column vertically provided in the middle of the trenches.

[0010] Furthermore, in order to lead out the two sources of the dual SGT MOSFET device, the connection layer includes a first top insulating layer arranged on the surface of the MOS structure, a first top metal is arranged on the surface of the first top insulating layer, a second top insulating layer is arranged between adjacent first top metals and on top of the first top metals, and a second top metal is arranged on the surface of the second top insulating layer; the first top metal includes a first top metal S1 portion, a first top metal S2 portion, a first top metal G1 portion, and a first top metal G2 portion, which correspond to the first top contact holes and are arranged in sequence; the second top metal includes a second top metal S1 portion, a second top metal S2 portion, a second top metal G1 portion, and a second top metal G2 portion, which correspond to the second top contact holes one by one.

[0011] Furthermore, in order to lead out the two gates of the dual SGT device, the insulating column in the middle of the trench isolates the first polysilicon and forms the shielding gate G1 polysilicon and the shielding gate G2 polysilicon; the insulating column in the middle of the trench isolates the second polysilicon and forms the gate G1 polysilicon and the gate G2 polysilicon.

[0012] The beneficial effects of the utility model are:

[0013] 1. The present invention utilizes an integrated drain-sharing design, integrating two SGT MOSFETs in series on a single chip through their source, shield, and gate crossover structures. Therefore, when the drain-sharing dual SGT MOSFET device of the present invention is turned on, a conductive channel is formed around the trench between the two adjacent SGT MOSFET structures. Current flows horizontally through the drift region, eliminating the need to pass through the substrate 1, back metal, or external soldering copper plates or wiring. This significantly reduces on-resistance, lowers power consumption, and improves performance and device reliability.

[0014] 2. The dual SGT MOSFET device with a shared drain provided by the present invention allows current to flow horizontally through the epitaxial layer 2 when on, without passing through the substrate 1 and the back metal. This eliminates the substrate thinning and back metal processes in the traditional MOSFET tube process, simplifies the wafer production process, and saves production costs.

[0015] 3. SGT MOSFET devices have advantages over trench MOSFET devices such as higher breakdown voltage and lower switching loss.

[0016] 4. The dual SGT MOSFET device with a shared drain provided by the present invention has the same function as the two MOSFET tubes connected in series in the existing power protection board circuit, thus greatly facilitating the regional distribution of the device and reducing the cost of the product. In actual use, the connection with the driver chip is the same as the conventional connection method, which has better versatility. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 This is the circuit schematic diagram of the lithium battery protection board.

[0019] Figure 2 Schematic diagram of the existing SGT MOSFET device structure.

[0020] Figure 3 Figure 2. Metal diagram of the front side of a dual SGT MOSFET device with a shared drain.

[0021] Figure 4 This is a cross-sectional view of the structure at the S1 contact hole of a dual SGT MOSFET device with a shared drain.

[0022] Figure 5This is a cross-sectional view of the structure at the S2 contact hole of a dual SGT MOSFET device with a shared drain.

[0023] Figure 6 A perspective view of the structure of a dual SGT MOSFET device with a shared drain and no metal layer.

[0024] Figure 7 This is a cross-sectional view of the shield gate G1 contact hole structure of a dual SGT MOSFET device with a shared drain.

[0025] Figure 8 This is a cross-sectional view of the structure at the shield gate G2 contact hole of a dual SGT MOSFET device with a shared drain.

[0026] Figure 9 This is a cross-sectional view of the structure at the gate G1 of a dual SGT MOSFET device with a shared drain.

[0027] Figure 10 This is a cross-sectional view of the structure of the gate G2 of a dual SGT MOSFET device with a shared drain.

[0028] Figure 11 This is a flow chart of a manufacturing method for the S1 contact hole of a dual SGT MOSFET device with a shared drain.

[0029] Figure 12 The second flowchart of the manufacturing method for the S1 contact hole of the dual SGT MOSFET device with shared drain.

[0030] Figure 13 The third flow chart of the manufacturing method for the S1 contact hole of the dual SGT MOSFET device with shared drain.

[0031] Figure 14 The fourth flowchart of the manufacturing method for the S1 contact hole of the dual SGT MOSFET device with shared drain.

[0032] Figure 15 Flowchart 5 of the manufacturing method for the S1 contact hole of a dual SGT MOSFET device with a shared drain.

[0033] Figure 16 Flowchart 6 of the manufacturing method for the S1 contact hole of a dual SGT MOSFET device with a shared drain.

[0034] Figure 17 Flowchart 7 of the manufacturing method for the S1 contact hole of a dual SGT MOSFET device with a shared drain.

[0035] Figure 18 Flowchart 8 of the manufacturing method for the S1 contact hole of a dual SGT MOSFET device with a shared drain.

[0036] Figure 19 FIG9 is a flowchart of a method for manufacturing the S1 contact hole of a dual SGT MOSFET device with a shared drain.

[0037] Figure 20 The tenth flowchart of the manufacturing method for the S1 contact hole of the dual SGT MOSFET device with a shared drain.

[0038] Figure 21 Flowchart 11 of the manufacturing method for the S1 contact hole of a dual SGT MOSFET device with a shared drain.

[0039] In the picture:

[0040] 1. Substrate; 2. Epitaxial layer; 3. Trench; 4. Shielding gate oxide layer; 5. First polysilicon; 6. Shielding gate G1 polysilicon; 7. Shielding gate G2 polysilicon; 8. Shielding oxide layer in the middle of the trench; 9. Gate oxide layer; 10. Second polysilicon; 11. Gate G1 polysilicon; 12. Gate G2 polysilicon; 13. Narrow trench in the middle of the trench; 14. Insulating pillar in the middle of the trench; 15. Source region; 16. Base region; 17. First top insulating layer; 18. First top contact hole; 19. First top metal; 20. First top metal S1 portion; 21. First top metal S2 portion; 22. First top metal G1 portion; 23. First top metal G2 portion; 24. Second top insulating layer; 25. Second top contact hole; 26. Source S1 contact hole; 27. Source S2 contact hole; 28. Shielding gate G1 contact hole; 29. Shielding gate G2 contact hole; 30. Gate G1 contact hole; 31. Gate G2 contact hole; 32. Second top metal; 33. Second top metal S1 portion; 34. Second top metal S2 portion; 35. Second top metal G1 portion; 36. Second top metal G2 portion. DETAILED DESCRIPTION

[0041] To further illustrate each embodiment, the present invention provides drawings, which are part of the disclosure of the present invention and are mainly used to illustrate the embodiments. They can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. By referring to these contents, ordinary technicians in this field should be able to understand other possible implementation methods and the advantages of the present invention. The components in the figures are not drawn to scale, and similar component symbols are generally used to represent similar components.

[0042] The utility model provides a drain-shared design for two SGT MOSFET tubes. Current flow is achieved through a conductive channel formed by a cross-structure design of the source and gate of the two SGTMOSFET structures. This replaces the dual N-channel common-drain MOSFET tube, not only improving the breakdown voltage but also greatly reducing the on-resistance, lowering power consumption, and improving performance and equipment reliability. The dual SGT MOSFET device with a shared drain and a manufacturing method thereof are provided.

[0043] The present invention will now be further described with reference to the accompanying drawings and specific embodiments. Figures 1-10 As shown, the drain-shared dual SGT MOSFET device according to an embodiment of the present invention includes a substrate 1 of an N+ type semiconductor material, an epitaxial layer 2 of an N-type semiconductor material is provided on the top of the substrate 1, a plurality of trenches 3 are arranged side by side on the top surface of the epitaxial layer 2, the bottom sidewalls and inner bottom of the trench 3 are provided with a shielding gate oxide layer 4, and the shielding gate oxide layer 4 on the bottom sidewall of the trench 3 is filled with a first polysilicon 5; a trench middle shielding oxide layer 8 is deposited on the top of the first polysilicon 5, a gate oxide layer 9 is provided on the top of the trench middle shielding oxide layer 8 and on the sidewall of the trench 3, and a first gate oxide layer 9 is filled in the gate oxide layer 9. Two polysilicon layers 10; a source region 15 and a base region 16 are formed between two adjacent trenches 3 from top to bottom, a first top-level contact hole 18 is formed in the source region 15 and the base region 16, a MOS structure is formed by filling the first top-level contact hole 18 with a conductive material, a connection layer is formed on the surface of the MOS structure, and the two sources and two gates of the dual SGT device are led out through the connection layer, that is, the connection layer is connected to the MOS structure to lead out the two sources of the dual SGT device respectively, which facilitates the implementation of leads in the circuit later; a trench middle insulating column 14 is vertically provided in the middle of the trench 3.

[0044] With the help of the above solution, the present invention adopts an integrated drain-sharing design, integrating two SGT MOSFET tubes in series on a single chip through the source, shield gate, and gate cross structure design of the two SGT MOSFET tubes. Therefore, when the dual SGT MOSFET device with a shared drain of the present invention is turned on, a conductive channel is formed around the trench between the two adjacent SGT MOSFET structures. The current flows horizontally through the drift region without passing through the substrate 1, the back metal, and the external soldering copper plate or wiring. Therefore, the on-resistance is greatly reduced, the power consumption is reduced, and the performance and reliability of the device are improved.

[0045] In one embodiment, the connection layer includes a first top insulating layer 17 disposed on the surface of the MOS structure, a first top metal 19 disposed on the surface of the first top insulating layer 17, a second top insulating layer 24 disposed between adjacent first top metals 19 and on top of the first top metals 19, and a second top metal 32 disposed on the surface of the second top insulating layer 24, thereby enabling the two sources of the dual SGT MOSFET device to be brought out.

[0046] In one embodiment, the first top metal 19 includes a first top metal S1 portion 20 , a first top metal S2 portion 21 , a first top metal G1 portion 22 , and a first top metal G2 portion 23 , which correspond to the first top contact holes 18 and are arranged in sequence.

[0047] In one embodiment, the second top metal 32 includes a second top metal S1 portion 33, a second top metal S2 portion 34, a second top metal G1 portion 35, and a second top metal G2 portion 36, which are sequentially disposed on the surface of the second top insulating layer 24 and correspond one-to-one to the second top contact holes 25. The source S1 contact hole 26 and the shield gate G1 contact hole 28 are connected to the second top metal S1 portion 33, the source S2 contact hole 27 and the shield gate G2 contact hole 29 are connected to the second top metal S2 portion 34, the gate G1 contact hole 30 is connected to the second top metal G1 portion 35, and the gate G2 contact hole 32 is connected to the second top metal G2 portion 36.

[0048] In one embodiment, for the above-mentioned trench middle insulating pillar 14, the trench middle insulating pillar 14 isolates the first polysilicon 5 and forms the shielding gate G1 polysilicon 6 and the shielding gate G2 polysilicon 7; the trench middle insulating pillar 14 isolates the second polysilicon 10 and forms the gate G1 polysilicon 11 and the gate G2 polysilicon 12, thereby being able to lead out the two gates of the dual SGT device.

[0049] The two sources of the dual SGT MOSFET device are spaced apart by the first top metal S1 portion 20 and the first top metal S2 portion 21 on the MOS structure, and the source S1 and source S2 are led out respectively. The source S1 of the dual SGT MOSFET device is led out from the second top metal S1 portion 33 via the first top contact hole 18, the first top metal S1 portion 20, the second top contact hole 25; the source S2 of the dual SGT MOSFET device is led out from the second top metal S2 portion 34 via the first top contact hole 18, the first top metal S2 portion 21, the second top contact hole 25.

[0050] In two adjacent trenches 3, the second polysilicon 10 portion adjacent to the source S1 is the gate G1 polysilicon 11, and the second polysilicon 10 adjacent to the source S2 is the gate G2 polysilicon 12; the first polysilicon 6 adjacent to the source S1 is the shielding gate G1 polysilicon 6, and the first polysilicon 6 adjacent to the source S2 is the shielding gate G2 polysilicon 7.

[0051] In the trench 3 , a trench middle shielding oxide layer 8 is provided between the shielding gate G1 polysilicon 6 and the gate G1 polysilicon 11 ; a trench middle shielding oxide layer 8 is provided between the shielding gate G2 polysilicon 7 and the gate G2 polysilicon 12 .

[0052] In the trench 3, the shielding gate G1 polysilicon 6 is connected to the source S1 through the first top-level contact hole 18, the first top-level metal S1 portion 20, the second top-level contact hole 25, and the second top-level metal S1 portion 33; the shielding gate G2 polysilicon 7 is connected to the source S2 through the first top-level contact hole 18, the first top-level metal S2 portion 21, the second top-level contact hole 25, and the second top-level metal S2 portion 34.

[0053] The two gates of the dual SGT MOSFET device are connected through the first top contact hole 18 opened on the first polysilicon 5 in the trench 3, respectively leading to the gate G1 and the gate G2. The gate G1 of the dual SGT MOSFET device is connected from the gate G1 polysilicon 11 through the first top metal G1 portion 22, through the second top contact hole 25, and from the second top metal G1 portion 35. The gate G2 of the dual SGT MOSFET device is connected from the gate G2 polysilicon 12 through the first top metal G2 portion 23, through the second top contact hole 25, and from the second top metal G2 portion 36.

[0054] In order to facilitate understanding of the above technical solutions of the present invention, the working principle or operation method of the present invention in actual process is described in detail below.

[0055] In actual application, in the charging or discharging state, a driving voltage is applied to the two gates of the dual SGT device through the driver chip U1, so that a corresponding conductive channel is formed in the dual SGT device. The external charging current enters from the second top metal, then passes through the second top contact hole 25 and the first top metal 19 to enter the MOS structure of the corresponding SGT device, and enters the other SGT structure through the conductive channel around the trench 3 between the two adjacent SGT structures. Finally, it passes through the base region 16 and the first top metal 19 again, and then flows out from the second top metal 32, forming a current loop.

[0056] When the charging circuit or the discharging circuit needs to be cut off, one of the SGT structures is turned off by the driver chip, the conductive channel around the groove 3 disappears, and the PN junction (parasitic diode) formed by the base region 16 and the source region 15 in the SGT device is reversely cut off, which has the effect of blocking the current.

[0057] As can be seen from the above, when the dual-SGT device provided by the present invention is turned on, a conductive channel is formed around the trench 3 between the two adjacent SGT structures, and the current flows horizontally through the drift layer, thereby eliminating the need to pass through the substrate, back metal, and external soldering copper plates or wiring. This greatly reduces the on-resistance, reduces power consumption, and improves performance and device reliability.

[0058] The dual SGT device provided by the utility model has the same function as two MOSFET tubes connected in series in the existing power protection board circuit, which greatly facilitates the regional distribution of the device and reduces the cost of the product. In addition, the connection with the driver chip in actual use is the same as the conventional connection method, which has better versatility. Figure 4 、 Figure 5 、 Figure 7 、 Figure 8 As shown, in the front metal diagram of the dual SGT device provided by the utility model, the second top metal S1 portion 33 and the second top metal S2 portion 34 are respectively led out as the source S1 and source S2 of the dual SGT device, and the second top metal G1 portion 35 and the second top metal G2 portion 36 are respectively led out as the gate G1 and gate G2 of the dual SGT device, the gate G1 polysilicon 11 and the gate G2 polysilicon 12 are respectively connected to the second top metal G1 portion 35 and the second top metal G2 portion 35, and the shield gate G1 polysilicon 6 and the shield gate G2 polysilicon 7 are respectively connected to the second top metal S1 portion 33 and the second top metal S2 portion 34, forming an SGT device structure.

[0059] like Figure 11-Figure 21 As shown, used to make Figure 4 The cross-sectional view of the structure at the S1 contact hole of the dual SGT MOSFET device with a shared drain shown includes the following steps:

[0060] Step 1: Form an epitaxial layer 2 on the substrate 1, then perform a first oxidation treatment on the surface of the epitaxial layer 2, and then perform a first photolithography to form a groove 3, as shown in FIG. Figure 11 shown.

[0061] Step 2: Deposit shield gate oxide on the upper surface of the epitaxial layer 2 to form a shield gate oxide layer 4 on the sidewalls and bottom of the trench 3. The thickness of the shield gate oxide layer 4 is set according to the required withstand voltage of the chip and the doping concentration of the epitaxial layer 2.

[0062] Step 3: Fill the shield gate oxide layer 4 with the first polysilicon 5, grind the shield gate oxide layer 4 and the first polysilicon 5 and etch them to the silicon surface, as shown in FIG. Figure 12 shown.

[0063] Step 4: Etch the shield gate oxide layer 4 and the first polysilicon 5 in the trench 3 to the designed position, such as Figure 13 As shown, this step performs the second and third photolithography to form Figure 7 and Figure 8 structure.

[0064] Step 5: Perform oxide deposition (HDP) in the trench 3 to form a trench middle shielding oxide layer 8, and etch the trench middle shielding oxide layer 8 to the designed position, such as Figure 13 shown.

[0065] Step 6: Oxidation is performed in the trench 3 to form a gate oxide layer 9, and the second polysilicon 10 is filled and etched to 0.1 μm below the silicon surface. Figure 14 shown.

[0066] Step 7: Perform the fourth photolithography to form a narrow groove 13 in the middle of the groove 3, as shown in FIG. Figure 16 shown.

[0067] Step 8: Fill the narrow trench 13 in the middle of the trench 3 with insulating material to form an insulating column 14 in the middle of the trench, dividing the SGT structure into two SGT structures, such as Figure 17 shown.

[0068] Step 9: Perform the fifth photolithography to form a base region 16 and a source region 15 on the epitaxial layer 2 to form a MOS structure. Figure 18 shown.

[0069] Step 10: Deposit a first top insulating layer 17 on the chip surface, and then perform a sixth photolithography pass from the surface of the first top insulating layer 17 downward to form a first top contact hole 18. The first top contact hole 18 is opened between two adjacent trenches 3 and passes downward in sequence through the first top insulating layer 17, the source region 15, and into the base region 16. Figure 19 shown.

[0070] Step 11: Deposit metal on the surface of the first top insulating layer 17 and perform the seventh photolithography to form the first top metal 19 arranged at intervals, respectively leading to the source S1 (first top metal S1 portion 20) and the source S2 (first top metal S2 portion 21) of the dual SGT device. Figure 20 shown.

[0071] Step 12: Deposit a second top insulating layer 24 between and above the first top metal 19, and perform an eighth photolithography pass to form second top contact holes 25 that contact the first top metal S1 portion 20 and the first top metal S2 portion 21, respectively. Figure 21 shown.

[0072] Step 13: Perform a second metal deposition on the second top insulating layer 24, and then perform a ninth photolithography to form a second top metal S1 portion 33 and a second top metal S2 portion 34, respectively. Figure 4 The cross-sectional view of the structure at the S1 contact hole of the dual SGTMOSFET tube device with shared drain is shown.

[0073] In the above embodiment, the P-type and N-type material layers are swapped, and the same beneficial effects of the P-channel dual SGT MOSFET device can be achieved based on the same structural manufacturing sequence.

[0074] In summary, the present invention adopts an integrated drain-sharing design, integrating two SGT MOSFET tubes in series on a single chip through the source, shield gate, and gate cross structure design of the two SGT MOSFET tubes. Therefore, when the drain-sharing dual SGT MOSFET device of the present invention is turned on, a conductive channel is formed around the trench between the two adjacent SGT MOSFET structures, and the current flows horizontally through the drift region without passing through the substrate 1, the back metal, and the external soldering copper plate or wiring. This greatly reduces the on-resistance, reduces power consumption, and improves performance and equipment reliability. The drain-sharing dual SGT MOSFET device provided by the present invention, when turned on, the current flows horizontally through the epitaxial layer 2 without passing through the substrate 1 and the back metal, thereby eliminating the substrate thinning and back metal processes in the traditional MOSFET tube process, simplifying the wafer production process and saving production costs. SGT MOSFET devices have advantages over trench MOSFET devices, such as higher breakdown voltage and lower switching loss. The dual SGT MOSFET device with a shared drain provided by the utility model has the same function as the two MOSFET tubes connected in series in the existing power protection board circuit, which greatly facilitates the regional distribution of the device and reduces the cost of the product. In addition, the connection with the driver chip in actual use is the same as the conventional connection method, which has better versatility.

[0075] In the present invention, unless otherwise clearly stipulated and limited, the terms "install", "set", "connect", "fix", "screw" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements. Unless otherwise clearly defined, ordinary technicians in this field can understand the specific meanings of the above terms in the present invention according to the specific circumstances.

[0076] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A dual SGT MOSFET device with a common drain, comprising a substrate (1), an epitaxial layer (2) being provided on the top of the substrate (1), characterized in that: A plurality of trenches (3) are arranged side by side on the top surface of the epitaxial layer (2); shielding gate oxide layers (4) are provided on the bottom sidewalls and inner bottoms of the trenches (3); and first polysilicon (5) is filled in the shielding gate oxide layers (4) on the bottom sidewalls of the trenches (3); A trench middle shielding oxide layer (8) is deposited on the top of the first polysilicon (5), a gate oxide layer (9) is provided on the top of the trench middle shielding oxide layer (8) and on the sidewall of the trench (3), and a second polysilicon (10) is filled in the gate oxide layer (9); A source region (15) and a base region (16) are formed between two adjacent trenches (3) from top to bottom, a first top-level contact hole (18) is formed in the source region (15) and the base region (16), a MOS structure is formed by filling the first top-level contact hole (18) with a conductive material, and a connection layer is formed on the surface of the MOS structure; A groove middle insulating column (14) is vertically arranged in the middle of the groove (3).

2. The dual SGT MOSFET device with a shared drain according to claim 1, wherein: The connection layer comprises a first top insulating layer (17) arranged on the surface of the MOS structure, a first top metal (19) is arranged on the surface of the first top insulating layer (17), a second top insulating layer (24) is arranged between adjacent first top metals (19) and on the top of the first top metal (19), and a second top metal (32) is arranged on the surface of the second top insulating layer (24).

3. The dual SGT MOSFET device with a shared drain according to claim 2, wherein: The first top metal (19) includes a first top metal S1 portion (20), a first top metal S2 portion (21), a first top metal G1 portion (22) and a first top metal G2 portion (23) which correspond to the first top contact hole (18) and are arranged in sequence.

4. The dual SGT MOSFET device with a shared drain according to claim 2, wherein: The second top metal (32) includes a second top metal S1 portion (33), a second top metal S2 portion (34), a second top metal G1 portion (35) and a second top metal G2 portion (36) sequentially arranged on the surface of the second top insulating layer (24).

5. The dual SGT MOSFET device with a shared drain according to claim 1, wherein: The insulating column (14) in the middle of the trench isolates the first polysilicon (5) and forms a shielding gate G1 polysilicon (6) and a shielding gate G2 polysilicon (7).

6. The dual SGT MOSFET device with a shared drain according to claim 1, wherein: The insulating column (14) in the middle of the trench isolates the second polysilicon (10) and forms a gate G1 polysilicon (11) and a gate G2 polysilicon (12).

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