Level conversion circuit, chip and display driving device

Abstract

The utility model discloses a level conversion circuit, a chip and a display driving device. The level conversion circuit comprises an input signal processing unit which is coupled with an enable signal and an input signal, during the effective level period of the enable signal, the input signal processing unit provides a first control signal and a second control signal which are opposite in phase, and the overturning of the first control signal and the second control signal follows the overturning of the input signal; the enabling unit is coupled with the enabling signal and provides the clamping voltage during the invalid level period of the enabling signal; the conversion unit is coupled with the first control signal and the second control signal during the effective level period of the enable signal so as to convert the input signal of the first power domain into the output signal of the second power domain; or a clamp voltage is coupled during the invalid level period of the enable signal to clamp the output signal to the clamp voltage, and the voltage value of the clamp voltage falls into the second power domain. Start-stop control of the level conversion circuit is achieved through the enabling unit, and product use scenes can be expanded.

Description

Technical Field

[0001] The utility model relates to the technical field of level conversion, in particular to a level conversion circuit, a chip and a display driving device. Background Art

[0002] As systems-on-chip (SOCs) evolve toward larger scale and lower power consumption, the modules of circuit systems are becoming more complex. Because different modules may require different power supply voltages, signals must be transferred between low-power and high-power domains to meet performance and power requirements. Therefore, level shifting circuits are required to convert signals from non-target power domains to the target power domains to ensure that the circuits of different modules can operate normally under the power supply voltages to which they are adapted.

[0003] Among existing level converters, low voltage to high voltage conversion is very common. Figure 1 , Figure 1 The conventional low-voltage to high-voltage level conversion circuit 100 has two power domains. The high level of the low power domain is VDDL, and the high level of the high power domain is VDDH (VDDL < VDDH). The low levels of the two power domains are equal to the ground level, which is usually regarded as 0V.

[0004] The level shifter circuit 100 includes an input signal processing unit 110 comprised of inverters INV1 and INV2; a shifter unit 120 comprised of NMOS transistors NM1 and NM2 and PMOS transistors PM1 and PM2; and an output signal processing unit 130 comprised of a PMOS transistor PM3 and an NMOS transistor NM3. PM1 and NM1 are connected in series between VDDH and ground, while PM2 and NM2 are connected in series between VDDH and ground. The gate of PM1 is connected to the drain of PM2, and the gate of PM2 is connected to the drain of PM1, forming a cross-coupling structure. Inverters INV1 and INV2 invert the phases of the signals input to the gates of NM1 and NM2.

[0005] With this circuit configuration, when the input signal Vin is at a high level in the low power domain, NM1 is turned off, NM2 is turned on, and the voltage at point B is pulled down to ground. The output signal processing unit 130 inverts the voltage at point C (i.e., the voltage at point B) to align the output signal Vout with the input signal Vin. The voltage value of the output signal Vout is VDDH, a high level in the high power domain. Simultaneously, because the voltage at point B is pulled down to ground, PM1 turns on, pulling the voltage at point A up to VDDH, while PM2 turns off. This prevents the pull-up current generated by PM2 turning on from affecting the voltage at point B. When the input signal is at a low level, the opposite occurs.

[0006] However, for the level conversion circuit in the prior art, during the conversion process, the output signal changes in real time in response to changes in the input signal, and it is impossible to implement start-stop control according to the application scenario of the product. Utility Model Content

[0007] In view of the above problems, the purpose of this application is to provide a level conversion circuit that can achieve start-stop control.

[0008] According to one aspect of the present application, a level conversion circuit is provided, characterized in that the level conversion circuit includes: an input signal processing unit, coupled to an enable signal and an input signal, during the valid level of the enable signal, the input signal processing unit provides a first control signal and a second control signal, the first control signal and the second control signal have opposite phases, and the flip of the first control signal and the second control signal follows the flip of the input signal; an enable unit, coupled to the enable signal, and providing a clamping voltage during the invalid level of the enable signal; and a conversion unit, coupled to the first control signal and the second control signal during the valid level of the enable signal to convert the input signal of the first power domain into an output signal of the second power domain; or coupled to the clamping voltage during the invalid level of the enable signal to clamp the output signal to the clamping voltage, and the voltage value of the clamping voltage falls into the second power domain.

[0009] Optionally, the voltage value of the enable signal falls within the first power domain, and the enable unit includes: a level shifting module, which receives and converts the enable signal to provide a third control signal, and the voltage value of the third control signal falls within the second power domain; and a clamping module, which provides the clamping voltage during the invalid level of the third control signal.

[0010] Optionally, the input signal processing unit includes: a first inverter, which inverts the input signal to provide the first control signal during the valid level of the enable signal; and a second inverter, which inverts the first control signal to provide the second control signal during the valid level of the enable signal, wherein the high-level power supply terminals of the first inverter and the second inverter are coupled to the first operating voltage, and the low-level power supply terminals are grounded, and the first operating voltage falls into the first power supply domain.

[0011] Optionally, the conversion unit includes: a first PMOS transistor and a first NMOS transistor connected in series between the second operating voltage and ground, the gate of the first NMOS transistor is coupled to the second control signal, and the intermediate node between the first PMOS transistor and the first NMOS transistor is short-circuited with the gate of the first PMOS transistor; and a second PMOS transistor and a second NMOS transistor connected in series between the second operating voltage and ground, the gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, the gate of the second NMOS transistor is coupled to the first control signal, the intermediate node between the second PMOS transistor and the second NMOS transistor provides the output signal, the second operating voltage falls into the second power supply domain, and the voltage value of the second operating voltage is greater than the voltage value of the first operating voltage.

[0012] Optionally, the clamping module includes: a third PMOS transistor, the third PMOS transistor and the first PMOS transistor are connected in parallel; and a fourth PMOS transistor, the fourth PMOS transistor and the second PMOS transistor are connected in parallel, and the gates of the third PMOS transistor and the fourth PMOS transistor are both coupled to the third control signal.

[0013] Optionally, the input signal includes a first input signal and a second input signal, the first input signal and the second input signal are differential signals, the input signal processing unit includes a first processing unit and a second processing unit, the first processing unit is coupled to the first input signal and provides the first control signal, the second processing unit is coupled to the second input signal and provides the second control signal, the conversion unit includes a first subunit and a second subunit, the first subunit is coupled to the first control signal and the second control signal to convert the first input signal into a first output signal of the same phase, the second subunit is coupled to the first control signal and the second control signal to convert the second input signal into a second output signal of the same phase, and during the invalid level of the third control signal, the clamping module clamps the first output signal and the second output signal to the clamping voltage.

[0014] Optionally, the first processing unit includes a third inverter and a fourth inverter connected in series, and the second processing unit includes a fifth inverter and a sixth inverter connected in series. During the active level of the enable signal, the first input signal is sequentially inverted by the third inverter and the fourth inverter to provide the first control signal, and the second input signal is sequentially inverted by the fifth inverter and the sixth inverter to provide the second control signal.

[0015] The high-level power supply terminals of the third inverter, the fourth inverter, the fifth inverter and the sixth inverter are coupled to a first operating voltage, and the low-level power supply terminals are grounded, and the first operating voltage falls within the first power domain.

[0016] Optionally, the first subunit includes: a fifth PMOS transistor and a third NMOS transistor connected in series between the second operating voltage and ground, the gate of the third NMOS transistor is coupled to the first control signal, and the intermediate node between the fifth PMOS transistor and the third NMOS transistor is short-circuited with the gate of the fifth PMOS transistor; and a sixth PMOS transistor and a fourth NMOS transistor connected in series between the second operating voltage and ground, the gate of the sixth PMOS transistor is connected to the gate of the fifth PMOS transistor, the gate of the fourth NMOS transistor is coupled to the second control signal, and the intermediate node between the sixth PMOS transistor and the fourth NMOS transistor provides the first output signal, and the second subunit includes: a fifth PMOS transistor and a third ... a seventh PMOS transistor and a fifth NMOS transistor connected in series between the second operating voltage and ground, the gate of the fifth NMOS transistor being coupled to the second control signal, and the intermediate node between the seventh PMOS transistor and the fifth NMOS transistor being short-circuited with the gate of the seventh PMOS transistor; and an eighth PMOS transistor and a sixth NMOS transistor connected in series between the second operating voltage and ground, the gate of the eighth PMOS transistor being connected to the gate of the seventh PMOS transistor, the gate of the sixth NMOS transistor being coupled to the first control signal, the intermediate node between the eighth PMOS transistor and the sixth NMOS transistor providing the second output signal, the second operating voltage falling into the second power supply domain, and the voltage value of the second operating voltage being greater than the voltage value of the first operating voltage.

[0017] Optionally, the clamping module includes: a ninth PMOS transistor, the ninth PMOS transistor being connected in parallel with the fifth PMOS transistor; and a tenth PMOS transistor, the tenth PMOS transistor being connected in parallel with the sixth PMOS transistor.

[0018] an eleventh PMOS transistor, the eleventh PMOS transistor and the seventh PMOS transistor are connected in parallel; and a twelfth PMOS transistor, the twelfth PMOS transistor and the eighth PMOS transistor are connected in parallel, and the gates of the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor and the twelfth PMOS transistor are all coupled to the third control signal.

[0019] Optionally, the voltage range of the first power domain is from a first voltage to a second voltage, the voltage range of the second power domain is from a first voltage to a third voltage, the clamping voltage is the third voltage, and the second voltage is less than the third voltage.

[0020] Optionally, the transistors in the conversion unit and the clamping module are both high-voltage devices.

[0021] According to another aspect of the present application, a chip is provided, characterized by comprising the level conversion circuit as described in any one of the above items.

[0022] According to a third aspect of the present application, a display driving device is provided, characterized by comprising a level conversion circuit as described in any one of the above items.

[0023] According to the level conversion circuit, chip and display driver provided in the present application, in response to an enable signal that is unrelated to the input signal, during the valid level period of the enable signal, the input signal processing unit and the conversion unit operate normally to provide an output signal; during the invalid level period of the enable signal, the input signal processing unit is not enabled and stops outputting, and the enable unit clamps the output signal, so that the level conversion circuit is not affected by whether the input signal exists, thereby realizing start-stop control, which is conducive to expanding the use scenarios of the level conversion circuit, chip and display driver.

[0024] Furthermore, by setting a level shift module in the enable unit, the level conversion circuit can be controlled by the enable signal of the low power domain to clamp the output signal, lowering the threshold for obtaining the enable signal and facilitating adaptation to more usage scenarios.

[0025] Furthermore, by setting a current mirror-type conversion unit, the waiting time of the circuit is shortened when the input signal is flipped; at the same time, the two-level stacking structure of the transistor makes its equivalent capacitance smaller than the capacitance of a single transistor, the response speed of the circuit is faster, and the conversion rate is increased structurally, so that the maximum operating frequency of the level conversion circuit, chip and display driver provided in this application can reach GHz or above, meeting the demand for high conversion rate.

[0026] Furthermore, the transistors in the conversion unit and the clamping module are both high-voltage devices, which is more conducive to improving the reliability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0028] Figure 1 A schematic circuit topology diagram of a prior art level conversion circuit is shown;

[0029] Figure 2 A schematic structural diagram of a level conversion circuit according to a first embodiment of the present application is shown;

[0030] Figure 3 A schematic circuit topology diagram of a level conversion circuit according to a first embodiment of the present application is shown;

[0031] Figure 4 A schematic structural diagram of a level conversion circuit according to a second embodiment of the present application is shown;

[0032] Figure 5 A schematic circuit topology diagram of a level conversion circuit according to a second embodiment of the present application is shown. DETAILED DESCRIPTION

[0033] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0034] Certain terms are used in this specification and claims to refer to specific components. Those skilled in the art will understand that manufacturers may use different terms to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in their functions.

[0035] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected" between two nodes, it can be directly coupled or connected to the other element or there can be intermediate elements. The connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0036] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0037] The level conversion circuit provided in the present application is used to convert an input signal whose voltage value varies between a low level and a high level in a first power domain into an output signal whose voltage value varies between a low level and a high level in a second power domain. In the following, the level conversion circuit provided in the present application is specifically described by taking the first power domain as a low power domain (the low level of the low power domain is the ground level, and the high level is VDDL) and the second power domain as a high power domain (the low level of the high power domain is the ground level, and the high level is VDDH, VDDH>VDDL) as an example. Among them, the voltage difference between the high level signal and the low level signal in the low power domain is less than or equal to the threshold, and the voltage difference between the high level signal and the low level signal in the high power domain is greater than the threshold, and the threshold is, for example, 5V. Furthermore, devices that work normally in the low power domain are called low-voltage devices, and devices that work normally in the high power domain are called high-voltage devices.

[0038] The level conversion circuit provided by the present application includes an enable unit, an input signal processing unit, and a conversion unit. The level conversion circuit responds to an enable signal that is unrelated to the input signal. During the period when the enable signal is at an effective level, the input signal processing unit and the conversion unit operate normally to provide an output signal. During the period when the enable signal is at an ineffective level, the input signal processing unit is not enabled and stops outputting. The enable unit clamps the output signal, thereby making the level conversion circuit unaffected by the presence or absence of the input signal, realizing start-stop control, and facilitating the expansion of the use scenarios of the level conversion circuit, chip, and display driver device.

[0039] Figure 2 A schematic structural diagram of a level conversion circuit according to the first embodiment of the present application is shown in FIG. Figure 2 As shown:

[0040] The input signal processing unit 220 is coupled to the enable signal PDB and the input signal Vin. During the active period of the enable signal PDB, the first control signal CS1 and the second control signal CS2 are provided with opposite phases based on the input signal Vin. Furthermore, the first control signal CS1 and the second control signal CS2 are configured to transition in accordance with the transitions of the input signal Vin. For example, if the input signal Vin is a periodically transitioning square wave, the first control signal CS1 and the second control signal CS2 are square wave signals with the same period and duty cycle, but opposite phases.

[0041] The enabling unit 210 is coupled to the enabling signal PDB and provides the clamping voltage VC during an inactive level period of the enabling signal PDB.

[0042] The conversion unit 230 couples the first control signal CS1 and the second control signal CS2 to convert the input signal Vin to the output signal Vout when the enable signal PDB is valid, or couples the clamping voltage VC to clamp the output signal Vout to the clamping voltage VC when the enable signal PDB is invalid.

[0043] In the embodiment of the present application, the selected enable signal PDB is independent of the input signal Vin, and thus can achieve start and stop control of the level conversion circuit without being affected by the presence of the input signal Vin.

[0044] In the design of integrated circuits, due to the requirements of low power consumption and circuit safety, signals in the low power domain are more common than signals in the high power domain. In some embodiments, in order to lower the threshold for obtaining the enable signal so as to adapt to more usage scenarios, the signal in the low power domain is selected as the enable signal PDB. Accordingly, in order to realize the start and stop control of the conversion unit, such as Figure 2 As shown, the enabling unit 210 includes a level shifting module 211 and a clamping module 212. The level shifting module 211 receives the enabling signal PDB of the low power domain and converts it into a third control signal CS3 of the high power domain; the clamping module 212 provides a clamping voltage VC to the conversion unit during the inactive level of the third control signal CS3.

[0045] Figure 3 The schematic circuit topology diagram of the level conversion circuit of the first embodiment of the present application is shown. Figure 3 The level conversion circuit of the first embodiment of the present application is further described.

[0046] like Figure 3As shown, the input signal processing unit 220 includes a first inverter INV1 and a second inverter INV2 connected in series. The first inverter INV1 and the second inverter INV2 are low-voltage inverters. Their high-level power supply terminals are both coupled to the high level VDDL (first operating voltage) of the low power domain, their low-level power supply terminals are both coupled to the low level (ground) of the low power domain, and their enable terminals are both coupled to the enable signal PDB. During the active level of the enable signal PDB, the first inverter INV1 inverts the input signal Vin to provide a first control signal CS1, and the second inverter INV2 inverts the first control signal CS1 to provide a second control signal CS2.

[0047] The conversion unit 230 has a high-level power supply terminal coupled to the high-level VDDH (second operating voltage) of the high power domain, and a low-level power supply terminal coupled to the low-level (ground) of the high power domain. Specifically, the conversion unit 230 includes a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM1, and a second NMOS transistor NM2.

[0048] The first PMOS transistor PM1 and the first NMOS transistor NM1 are connected in series between a second operating voltage VDDH and ground. The source of the first PMOS transistor PM1 is coupled to the second operating voltage VDDH. An intermediate node (point A) between the first PMOS transistor PM1 and the first NMOS transistor NM1 is short-circuited with the gate of the first PMOS transistor PM1. The source of the first NMOS transistor NM1 is grounded. The gate of the first NMOS transistor NM1 is coupled to the second control signal CS2.

[0049] The second PMOS transistor PM2 and the second NMOS transistor NM2 are connected in series between the second operating voltage VDDH and ground, the source of the second PMOS transistor PM2 is coupled to the second operating voltage VDDH, the gate of the second PMOS transistor PM2 is coupled to the gate of the first PMOS transistor PM1, the source of the second NMOS transistor NM2 is grounded, the gate of the second NMOS transistor NM2 is coupled to the first control signal CS1, and the middle node (point B) between the second PMOS transistor PM2 and the second NMOS transistor NM2 provides the output signal Vout.

[0050] The enabling unit 210 includes a level shifting module 211 and a clamping module 212 .

[0051] The level shift module 211 has a high-voltage power supply terminal coupled to the second operating voltage VDDH, and a low-voltage power supply terminal coupled to ground, thereby shifting the enable signal PDB from the low-voltage domain to the high-voltage domain. In a preferred embodiment, the level shift module utilizes a low-speed level shifting circuit, for example, to reduce power consumption. Furthermore, a low-speed level shifting circuit occupies less area, facilitating the development of highly integrated circuits.

[0052] The clamping module 212 includes a third PMOS transistor and a fourth PMOS transistor. The third PMOS transistor is connected in parallel with the first PMOS transistor, and the fourth PMOS transistor is connected in parallel with the second PMOS transistor. The gates of the third and fourth PMOS transistors are both coupled to a third control signal CS3. During an inactive state of the third control signal CS3, the clamping module 212 provides a clamping voltage VC that is the second operating voltage VDDH.

[0053] Take the enable signal PDB as an example, where the valid level is high and the invalid level is low:

[0054] When the enable signal PDB is low, the first inverter INV1 and the second inverter INV2 are disabled, and the first and second control signals CS1 and CS2 are stopped from being supplied to the conversion unit 230. The third control signal CS3 output by the level shift module 211 is also low, turning on the third and fourth PMOS transistors PM3 and PM4. The fourth PMOS transistor PM4 clamps the output signal Vout (i.e., the voltage at point B) to the second operating voltage VDDH. The third PMOS transistor pulls up the voltage at point A, keeping the first and second PMOS transistors PM1 and PM2 off, preventing the first and second PMOS transistors PM1 and PM2 from generating pull-up currents that could affect the output signal Vout.

[0055] When the enable signal PDB is high, the third control signal CS3 output by the level shift module 211 is also high, turning off the third PMOS transistor PM3 and the fourth PMOS transistor PM4. The first inverter INV1 and the second inverter INV2 are enabled. If the input signal Vin is high, the first control signal CS1 is at ground voltage, the second control signal CS2 is at the first operating voltage VDDL, the first NMOS transistor NM1 is turned on, and the second NMOS transistor NM2 is turned off. The voltage at point A is pulled down to ground, the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned on, and the voltage at point B (i.e., the output signal Vout) is pulled up to the second operating voltage VDDH. If the input signal Vin is low, the first control signal CS1 is at the first operating voltage VDDL, and the second control signal CS2 is at ground voltage. The first NMOS transistor NM1 is turned off, the second NMOS transistor is turned on, and the voltage at point B (i.e., the output signal Vout) is pulled down to ground.

[0056] When Vin is high, the first NMOS transistor NM1 conducts and acts as a current source. The mirror circuit formed by the first PMOS transistor PM1 and the second PMOS transistor PM2 mirrors the current provided by the first NMOS transistor NM1 to the output port in a 1:1 ratio to charge the output load. When Vin is low, the second NMOS transistor NM2 conducts and acts as a current source, directly discharging the output load. This improves the response speed of the output signal Vout and increases the conversion rate from a structural perspective. Furthermore, because the current values ​​are approximately the same when charging and discharging the output load, the rise and fall times of the output signal Vout are approximately equal. This makes it easier to calculate the required current value for different application rates and load requirements, and the parameter design is simple and reliable.

[0057] Furthermore, in conversion unit 230, the two-stage stacked structure of transistors results in an equivalent capacitance that is smaller than that of a single transistor, resulting in a faster circuit response. Furthermore, because the transistors directly or indirectly bear the second operating voltage VDDH, in some embodiments, the transistors in clamping module 212 and conversion unit 230 are both high-voltage devices to improve circuit reliability. Furthermore, because both transistors are high-voltage devices, the circuit does not require additional isolation components for high- and low-voltage isolation, which further reduces circuit area and increases circuit integration.

[0058] Figure 4 The schematic structural diagram of the level conversion circuit according to the second embodiment of the present application is shown. The level conversion circuit 300 provided in the second embodiment of the present application is used to convert a pair of differential input signals of a low power domain to output a pair of differential output signals of a high power domain.

[0059] like Figure 4 As shown, the input signals of the level conversion circuit 300 include a first input signal Vin1 and a second input signal Vin2, which are a pair of differential signals. The level conversion circuit 300 includes an enabling unit 310, an input signal processing unit 320 and a conversion unit 330.

[0060] The input signal processing unit 320 is coupled to the enable signal PDB and the input signal (the first input signal Vin1 and the second input signal Vin2), and provides the first control signal CS1 and the second control signal CS2 with opposite phases according to the input signal during the active level period of the enable signal PDB. Figure 4 The input signal processing unit 320 includes a first processing unit 321 and a second processing unit 322. The first processing unit 321 is coupled to the first input signal Vin1 and provides a first control signal CS1; the second processing unit 322 is coupled to the second input signal Vin2 and provides a second control signal CS2.

[0061] The enabling unit 310 is coupled to the enabling signal PDB and provides the clamping voltage VC during an inactive level period of the enabling signal PDB.

[0062] The conversion unit 330 couples the first control signal CS1 and the second control signal CS2 during the active level of the enable signal PDB to convert the differential first input signal Vin1 and the second input signal Vin2 into the differential first output signal Vout1 and the second output signal Vout2; or couples the clamping voltage VC during the inactive level of the enable signal PDB to clamp the first output signal Vout1 and the second output signal Vout2 to the clamping voltage VC. For details, see Figure 4 The conversion unit 330 includes a first subunit 331 and a second subunit 332. The first subunit 331 is coupled to the first control signal CS1 and the second control signal CS2 to convert the first input signal Vin1 into a first output signal Vout1 of the same phase; the second subunit 332 is coupled to the first control signal CS1 and the second control signal CS2 to convert the second input signal Vin2 into a second output signal Vout2 of the same phase.

[0063] In the embodiment of the present application, the selected enable signal PDB is independent of the input signal and thus can be unaffected by the presence or absence of the input signal, thereby enabling start and stop control of the level conversion circuit.

[0064] In some embodiments, in order to reduce the acquisition threshold of the enable signal and the circuit power consumption, the signal of the low power domain is selected as the enable signal PDB. Figure 4 As shown, the enabling unit 310 includes a level shifting module 311 and a clamping module 312. The level shifting module 311 receives the enabling signal PDB of the low power domain and converts it into a third control signal CS3 of the high power domain; the clamping module 312 provides a clamping voltage VC to the conversion unit during the inactive level of the third control signal CS3.

[0065] Figure 5 The schematic circuit topology diagram of the level conversion circuit of the second embodiment of the present application is shown. Figure 5 The level conversion circuit of the second embodiment of the present application is further described.

[0066] like Figure 5As shown, the input signal processing unit 320 includes a first processing unit 321 and a second processing unit 322. The first processing unit 321 includes a third inverter INV3 and a fourth inverter INV4 connected in series. The second processing unit 322 includes a fifth inverter INV5 and a sixth inverter INV6 connected in series. The third inverter INV3, the fourth inverter INV4, the fifth inverter INV5, and the sixth inverter INV6 are all low-voltage inverters. Their high-level power supply terminals are coupled to the high level VDDL (first operating voltage) of the low power domain, their low-level power supply terminals are coupled to the low level (ground) of the low power domain, and their enable terminals are coupled to the enable signal PDB. During the active period of the enable signal PDB, the first input signal Vin1 is sequentially inverted by the third inverter INV3 and the fourth inverter INV4 to provide the first control signal CS1. The second input signal Vin2 is sequentially inverted by the fifth inverter INV5 and the sixth inverter INV6 to provide the second control signal CS2.

[0067] The high-level power supply terminal of the conversion unit 330 is coupled to the high-level VDDH (second operating voltage) of the high power domain, and the low-level power supply terminal is coupled to the low-level (ground) of the high power domain. The conversion unit 330 includes a first subunit 331 and a second subunit 332 .

[0068] The first subunit 331 includes a fifth PMOS transistor PM5 , a sixth PMOS transistor PM6 , a third NMOS transistor NM3 , and a fourth NMOS transistor NM4 .

[0069] The fifth PMOS transistor PM5 and the third NMOS transistor NM3 are connected in series between the second operating voltage VDDH and ground. The source of the fifth PMOS transistor PM5 is coupled to the second operating voltage VDDH. An intermediate node (point C) between the fifth PMOS transistor PM5 and the third NMOS transistor NM3 is short-circuited with the gate of the fifth PMOS transistor PM5. The source of the third NMOS transistor NM3 is grounded. The gate of the third NMOS transistor NM3 is coupled to the first control signal CS1.

[0070] The sixth PMOS transistor PM6 and the fourth NMOS transistor NM4 are connected in series between the second operating voltage VDDH and ground, the source of the sixth PMOS transistor PM6 is coupled to the second operating voltage VDDH, the gate of the sixth PMOS transistor PM6 is coupled to the gate of the fifth PMOS transistor PM5, the source of the fourth NMOS transistor NM4 is grounded, the gate of the fourth NMOS transistor NM4 is coupled to the second control signal CS2, and an intermediate node (point D) between the sixth PMOS transistor PM6 and the fourth NMOS transistor NM4 provides a first output signal Vout1 with the same phase as the first input signal Vin1.

[0071] The second subunit 332 includes a seventh PMOS transistor PM7 , an eighth PMOS transistor PM8 , a fifth NMOS transistor NM5 , and a sixth NMOS transistor NM6 .

[0072] The seventh PMOS transistor PM7 and the fifth NMOS transistor NM5 are connected in series between the second operating voltage VDDH and ground. The source of the seventh PMOS transistor PM7 is coupled to the second operating voltage VDDH. An intermediate node (point E) between the seventh PMOS transistor PM7 and the fifth NMOS transistor NM5 is short-circuited with the gate of the seventh PMOS transistor PM7. The source of the fifth NMOS transistor NM5 is grounded. The gate of the fifth NMOS transistor NM5 is coupled to the second control signal CS2.

[0073] The eighth PMOS transistor PM8 and the sixth NMOS transistor NM6 are connected in series between the second operating voltage VDDH and ground, the source of the eighth PMOS transistor PM8 is coupled to the second operating voltage VDDH, the gate of the eighth PMOS transistor PM8 is coupled to the gate of the seventh PMOS transistor PM7, the source of the sixth NMOS transistor NM6 is grounded, the gate of the sixth NMOS transistor NM6 is coupled to the first control signal CS1, and an intermediate node (point F) between the eighth PMOS transistor PM8 and the sixth NMOS transistor NM6 provides a second output signal Vout2 with the same phase as the second input signal Vin2.

[0074] The enabling unit 310 includes a level shifting module 311 and a clamping module 312 .

[0075] The high potential supply terminal of the level shift module 311 is coupled to the second working voltage VDDH, and the low potential supply terminal is grounded to shift the enable signal PDB from the low voltage domain to the high voltage domain. In a preferred embodiment, the level shift module uses a low-speed level conversion circuit to reduce power consumption.

[0076] The clamping module 312 includes a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, an eleventh PMOS transistor PM11, and a twelfth PMOS transistor PM12. The ninth PMOS transistor PM9 is connected in parallel with the fifth PMOS transistor PM5; the tenth PMOS transistor PM10 is connected in parallel with the sixth PMOS transistor PM6; the eleventh PMOS transistor PM11 is connected in parallel with the seventh PMOS transistor PM7; and the twelfth PMOS transistor PM12 is connected in parallel with the eighth PMOS transistor PM8. The gates of the ninth, tenth, eleventh, and twelfth PMOS transistors PM9, PM10, PM11, and PM12 are all coupled to a third control signal CS3. During an inactive period of the third control signal CS3, the clamping module 312 provides a clamping voltage VC equal to the second operating voltage VDDH.

[0077] Take the enable signal PDB as an example, where the valid level is high and the invalid level is low:

[0078] When the enable signal PDB is low, the first and second processing units 321 and 322 are disabled and stop providing the first and second control signals CS1 and CS2 to the conversion unit 330. The third control signal CS3 output by the level shift module 311 is also low, turning on the ninth, tenth, eleventh, and twelfth PMOS transistors PM9, PM10, PM11, and PM12. In the first subunit 331, the tenth PMOS transistor PM10 clamps the first output signal Vout1 (i.e., the voltage at point D) to the second operating voltage VDDH. The ninth PMOS transistor PM9 pulls up the voltage at point C, keeping the fifth and sixth PMOS transistors PM5 and PM6 off, preventing the pull-up current generated in the fifth and sixth PMOS transistors PM5 and PM6 from affecting the first output signal Vout1. Similarly, the second output signal Vout2 provided by the second subunit 332 is also clamped to the second operating voltage VDDH.

[0079] When the enable signal PDB is high, the third control signal CS3 output by the level shift module 311 is also high, turning off the ninth PMOS transistor PM9, the tenth PMOS transistor PM10, the eleventh PMOS transistor PM11, and the twelfth PMOS transistor PM12. This prevents the clamp module 312 from affecting the voltages at points C, D, E, and F. The first processing unit 321 and the second processing unit 322 are enabled. If the first input signal Vin1 is high and the second input signal Vin2 is low, the first control signal CS1 is at the first operating voltage VDDL, and the second control signal CS2 is at ground. In the first subunit 331, the third NMOS transistor NM3 is turned on, and the fourth NMOS transistor NM4 is turned off. The voltage at point C is pulled down to ground, and the fifth and sixth PMOS transistors PM5 and PM6 are turned on, pulling the voltage at point D (the first output signal Vout1) up to the second operating voltage VDDH. In the second sub-unit, the fifth NMOS transistor NM5 is turned off, the sixth NMOS transistor NM6 is turned on, and the voltage at point F (the second output signal Vout2 ) is pulled down to the ground voltage.

[0080] Similarly, when the first input signal Vin1 is at a low level and the second input signal Vin2 is at a high level, the first output signal Vout1 is pulled down to the ground voltage, and the second output signal Vout2 is pulled up to the second operating voltage VDDH.

[0081] Because both first subunit 311 and second subunit 312 utilize current mirror-type conversion circuits, the circuit's response time is shortened when the first input voltage Vin1 and the second input voltage VIn2 reverse, improving the response speed of the first output signal Vout1 and the second output signal Vout2. This increases the circuit's structural conversion rate. Furthermore, because the current values ​​during charge and discharge of the output load are approximately the same, the output signal's rise and fall times are approximately equal. This makes it easier to calculate the required current value for different application rates and load requirements, resulting in simple and reliable parameter design.

[0082] Furthermore, in some embodiments, the transistors in both the clamping module 312 and the conversion unit 330 are high-voltage devices, which can provide a higher current capability and improve circuit efficiency. Furthermore, since both transistors are high-voltage devices, no additional isolation components are required in the circuit to isolate high and low voltages, which helps reduce circuit area and improve circuit integration.

[0083] According to the level conversion circuit, chip and display driver provided in the present application, in response to an enable signal that is unrelated to the input signal, during the valid level period of the enable signal, the input signal processing unit and the conversion unit operate normally to provide an output signal; during the invalid level period of the enable signal, the input signal processing unit is not enabled and stops outputting, and the enable unit clamps the output signal, so that the level conversion circuit is not affected by whether the input signal exists, thereby realizing start-stop control, which is conducive to expanding the use scenarios of the level conversion circuit, chip and display driver.

[0084] Furthermore, by setting a level shift module in the enable unit, the level conversion circuit can be controlled by the enable signal of the low power domain to clamp the output signal, lowering the threshold for obtaining the enable signal and facilitating adaptation to more usage scenarios.

[0085] Furthermore, by setting a current mirror-type conversion unit, the waiting time of the circuit is shortened when the input signal is flipped; at the same time, the two-level stacking structure of the transistor makes its equivalent capacitance smaller than the capacitance of a single transistor, the response speed of the circuit is faster, and the conversion rate is increased structurally, so that the maximum operating frequency of the level conversion circuit, chip and display driver provided in this application can reach GHz or above, meeting the demand for high conversion rate.

[0086] Furthermore, the transistors in the conversion unit and the clamping module are both high-voltage devices, which is more conducive to improving the reliability of the circuit.

[0087] In addition, the present application also provides a chip and a display driving device, both of which adopt the level conversion circuit provided by the present application, and thus also have the above-mentioned beneficial effects, which will not be described in detail here.

[0088] While the embodiments of the present invention are described above, these embodiments do not exhaustively describe all details, nor do they limit the present invention to specific embodiments. Clearly, many modifications and variations are possible based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better utilize the present invention and its modifications. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A level conversion circuit, characterized in that: The level conversion circuit includes: an input signal processing unit coupled to an enable signal and an input signal, wherein during an active level of the enable signal, the input signal processing unit provides a first control signal and a second control signal, wherein the first control signal and the second control signal have opposite phases, and the flipping of the first control signal and the second control signal follows the flipping of the input signal; an enabling unit, coupled to the enabling signal, and providing a clamping voltage during an inactive level of the enabling signal; and A conversion unit is configured to couple the first control signal and the second control signal during an effective level of the enable signal to convert the input signal of the first power domain into an output signal of the second power domain; or to couple the clamping voltage during an ineffective level of the enable signal to clamp the output signal to the clamping voltage, wherein the voltage value of the clamping voltage falls within the second power domain.

2. The level conversion circuit according to claim 1, wherein: The voltage value of the enable signal falls within the first power domain, and the enabling unit includes: a level shift module, receiving and converting the enable signal to provide a third control signal, wherein a voltage value of the third control signal falls within the second power domain; and The clamping module provides the clamping voltage during an inactive level period of the third control signal.

3. The level conversion circuit according to claim 2, wherein: The input signal processing unit includes: a first inverter, configured to invert the input signal to provide the first control signal during a valid level period of the enable signal; and a second inverter, wherein during the active level of the enable signal, the second inverter inverts the first control signal to provide the second control signal; The high-level power supply terminals of the first inverter and the second inverter are coupled to a first operating voltage, and the low-level power supply terminals are grounded. The first operating voltage falls within the first power domain.

4. The level conversion circuit according to claim 3, wherein: The conversion unit includes: a first PMOS transistor and a first NMOS transistor connected in series between a second operating voltage and ground, a gate of the first NMOS transistor coupled to the second control signal, and an intermediate node between the first PMOS transistor and the first NMOS transistor being short-circuited with the gate of the first PMOS transistor; and a second PMOS transistor and a second NMOS transistor connected in series between the second operating voltage and ground, the gate of the second PMOS transistor being connected to the gate of the first PMOS transistor, the gate of the second NMOS transistor being coupled to the first control signal, and an intermediate node between the second PMOS transistor and the second NMOS transistor providing the output signal, The second operating voltage falls within the second power domain, and a voltage value of the second operating voltage is greater than a voltage value of the first operating voltage.

5. The level conversion circuit according to claim 4, wherein: The clamping module includes: a third PMOS transistor, the third PMOS transistor being connected in parallel with the first PMOS transistor; and a fourth PMOS transistor, the fourth PMOS transistor and the second PMOS transistor being connected in parallel, Gates of the third PMOS transistor and the fourth PMOS transistor are both coupled to the third control signal.

6. The level conversion circuit according to claim 2, wherein: The input signal includes a first input signal and a second input signal, wherein the first input signal and the second input signal are differential signals. The input signal processing unit includes a first processing unit and a second processing unit, wherein the first processing unit is coupled to the first input signal and provides the first control signal, and the second processing unit is coupled to the second input signal and provides the second control signal. The conversion unit includes a first subunit and a second subunit, the first subunit is coupled to the first control signal and the second control signal to convert the first input signal into a first output signal of the same phase, and the second subunit is coupled to the first control signal and the second control signal to convert the second input signal into a second output signal of the same phase. During the inactive level of the third control signal, the clamping module clamps the first output signal and the second output signal to the clamping voltage.

7. The level conversion circuit according to claim 6, wherein: The first processing unit includes a third inverter and a fourth inverter connected in series, The second processing unit includes a fifth inverter and a sixth inverter connected in series, During the active level period of the enable signal, the first input signal is sequentially inverted by the third inverter and the fourth inverter to provide the first control signal, and the second input signal is sequentially inverted by the fifth inverter and the sixth inverter to provide the second control signal. The high-level power supply terminals of the third inverter, the fourth inverter, the fifth inverter and the sixth inverter are coupled to a first operating voltage, and the low-level power supply terminals are grounded, and the first operating voltage falls within the first power domain.

8. The level conversion circuit according to claim 7, wherein: The first subunit includes: a fifth PMOS transistor and a third NMOS transistor connected in series between a second operating voltage and ground, a gate of the third NMOS transistor being coupled to the first control signal, and an intermediate node between the fifth PMOS transistor and the third NMOS transistor being short-circuited with the gate of the fifth PMOS transistor; and a sixth PMOS transistor and a fourth NMOS transistor connected in series between the second operating voltage and ground, a gate of the sixth PMOS transistor connected to the gate of the fifth PMOS transistor, a gate of the fourth NMOS transistor coupled to the second control signal, and an intermediate node between the sixth PMOS transistor and the fourth NMOS transistor providing the first output signal, The second subunit includes: a seventh PMOS transistor and a fifth NMOS transistor connected in series between a second operating voltage and ground, a gate of the fifth NMOS transistor coupled to the second control signal, and an intermediate node between the seventh PMOS transistor and the fifth NMOS transistor being short-circuited with the gate of the seventh PMOS transistor; and an eighth PMOS transistor and a sixth NMOS transistor connected in series between the second operating voltage and ground, a gate of the eighth PMOS transistor being connected to a gate of the seventh PMOS transistor, a gate of the sixth NMOS transistor being coupled to the first control signal, and an intermediate node between the eighth PMOS transistor and the sixth NMOS transistor providing the second output signal, The second operating voltage falls within the second power domain, and a voltage value of the second operating voltage is greater than a voltage value of the first operating voltage.

9. The level conversion circuit according to claim 8, wherein: The clamping module comprises: a ninth PMOS transistor, wherein the ninth PMOS transistor is connected in parallel with the fifth PMOS transistor; a tenth PMOS transistor, wherein the tenth PMOS transistor and the sixth PMOS transistor are connected in parallel; an eleventh PMOS transistor, the eleventh PMOS transistor being connected in parallel with the seventh PMOS transistor; and a twelfth PMOS transistor, wherein the twelfth PMOS transistor and the eighth PMOS transistor are connected in parallel, Gates of the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, and the twelfth PMOS transistor are all coupled to the third control signal.

10. The level conversion circuit according to claim 2, wherein: The voltage range of the first power domain is from a first voltage to a second voltage, The voltage range of the second power domain is from the first voltage to the third voltage, The clamping voltage is the third voltage, and the second voltage is lower than the third voltage.

11. The level conversion circuit according to claim 10, wherein: The transistors in the conversion unit and the clamping module are both high-voltage devices.

12. A chip, characterized in that: The method comprises the level conversion circuit according to any one of claims 1 to 11.

13. A display driving device, characterized in that: The method comprises the level conversion circuit according to any one of claims 1 to 11.

Images