Signal generating device, analog-digital hybrid test board card and test machine

Abstract

The utility model relates to a signal generation device, an analog-digital hybrid test board card and a test machine, a read-write control module reads an original waveform from a storage device according to a received read request instruction, and returns the read original waveform to an arbitrary waveform generator; the arbitrary waveform generator receives the original waveform and outputs a reconstructed waveform matched with the frequency of a sampling clock of the digital-to-analog conversion device to the first communication module. And the second communication module is connected with the first communication module, and the reconstructed waveform is received by the second communication module and then is transmitted to the digital-to-analog conversion device. According to the technical scheme, the reconstructed waveform can be generated by resampling the original waveform, the external clock chip outputs the sampling clock with the fixed frequency to the digital-to-analog conversion device, digital-to-analog conversion can be completed, the external clock chip does not need to adjust the frequency of the sampling clock, the hardware requirement for the external clock chip and the digital-to-analog conversion device is low, and the design cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to a signal generating device, an analog-to-digital hybrid testing board, and a testing machine. Background Art

[0002] Semiconductor automated testing refers to the use of automatic test equipment (ATE) to inspect various parameters of devices under test (DUTs), eliminating defective products and ensuring the quality of semiconductor devices before they leave the factory. In analog testing, especially high-speed analog testing, the test signals transmitted to the DUT often have very high requirements for harmonics, signal-to-noise ratio, amplitude, and signal frequency. When implementing IQ functions, the tester must ensure IQ channel synchronization.

[0003] Traditional test signal generation schemes synchronize the IQ channels by varying the frequency of the clock signal output by the clock circuit, thereby adjusting the sampling clock phase of the IQ channel's DAC (digital-to-analog converter). This method of outputting test signals by adjusting the DAC sampling clock phase places very high demands on the clock circuit hardware, resulting in complex and costly designs. Utility Model Content

[0004] Based on this, it is necessary to provide a signal generating device, an analog-to-digital hybrid test board and a test machine that can reduce design costs in order to address the above problems.

[0005] A first aspect of the present application provides a signal generating device, comprising a main test unit and a sub-test unit, wherein:

[0006] The main test unit includes an arbitrary waveform generator, a read-write control module, a storage device and a first communication module;

[0007] The read / write control module is connected to the arbitrary waveform generator and the storage device, reads the original waveform from the storage device according to the received read request instruction, and returns the read original waveform to the arbitrary waveform generator; the arbitrary waveform generator receives the original waveform and outputs a reconstructed waveform matching the frequency of the sampling clock of the digital-to-analog conversion device to the first communication module;

[0008] The sub-test unit includes a second communication module and an external clock chip;

[0009] The external clock chip outputs a sampling clock of a fixed frequency to the digital-to-analog conversion device; the second communication module is connected to the first communication module, receives the reconstructed waveform through the second communication module, and transmits it to the digital-to-analog conversion device; wherein, the reconstructed waveform is used by the digital-to-analog conversion device to perform digital-to-analog conversion according to the sampling clock output by the external clock chip.

[0010] In one embodiment, the arbitrary waveform generator includes:

[0011] a waveform request module connected to the read-write control module and the waveform data processing module, sending a read request instruction to the read-write control module, and sending the original waveform returned by the read-write control module to the waveform data processing module;

[0012] The waveform data processing module is connected to the first communication module, receives the original waveform, and outputs a reconstructed waveform matching the frequency of the sampling clock to the first communication module.

[0013] In one embodiment, the waveform request module includes a waveform request unit, a RAM storage unit and a data selection unit, the waveform request unit is connected to the read-write control module, the RAM storage unit and the data selection unit, and the data selection unit is connected to the RAM storage unit and the waveform data processing module.

[0014] In one embodiment, both the first communication module and the second communication module are gigabit communication modules.

[0015] In one embodiment, the arbitrary waveform generator also includes a first bit width conversion module, and the waveform data processing module is connected to the first communication module through the first bit width conversion module; the sub-test unit also includes a second bit width conversion module, and the second communication module is connected to the second bit width conversion module.

[0016] In one embodiment, the sub-test unit further includes a control module, and the control module is connected to the second bit width conversion module and the digital-to-analog conversion device.

[0017] In one embodiment, the control module includes a sending control module and a synchronization control module, the sending control module is connected to the second bit width conversion module and the synchronization control module, and the synchronization control module is connected to the digital-to-analog conversion device;

[0018] The sending control module receives the reconstructed waveform through the second communication module and sends the reconstructed waveform to the synchronization control module according to a set period; the synchronization control module caches the received reconstructed waveform in an internal cache module, and outputs the reconstructed waveform in the internal cache module after receiving a trigger signal.

[0019] In one embodiment, the main test unit further includes a first service decoding module, which is connected to the arbitrary waveform generator and the read-write control module, configures parameters of the arbitrary waveform generator, and stores the original waveform in the storage device through the read-write control module; and / or

[0020] The sub-test unit further includes a second service decoding module, which is connected to the control module and the external clock chip to perform parameter configuration on the control module and the external clock chip.

[0021] In one embodiment, the sub-test unit further includes a delay module, and the control module is connected to the corresponding digital-to-analog conversion device via the delay module.

[0022] A second aspect of the present application provides an analog-digital hybrid test board, comprising the above-mentioned signal generating device.

[0023] A third aspect of the present application provides a test machine, comprising a communication board, a backplane and the above-mentioned analog-digital hybrid test board.

[0024] The signal generating device, analog-to-digital hybrid test board, and test machine described above include: in a main test unit, a read-write control module reads an original waveform from a storage device according to a received read request instruction, and returns the read original waveform to an arbitrary waveform generator; the arbitrary waveform generator receives the original waveform and outputs a reconstructed waveform that matches the frequency of a sampling clock of a digital-to-analog converter to a first communication module; in a sub-test unit, an external clock chip outputs a fixed-frequency sampling clock to the digital-to-analog converter, and a second communication module is connected to the first communication module, receives the reconstructed waveform, and transmits it to the digital-to-analog converter. The reconstructed waveform can be generated by resampling the original waveform, and the external clock chip outputs a fixed-frequency sampling clock to the digital-to-analog converter to complete digital-to-analog conversion. There is no need for the external clock chip to adjust the frequency of the sampling clock, and the hardware requirements for the external clock chip and the digital-to-analog converter are low, thereby reducing design costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a structural block diagram of a signal generating device in one embodiment;

[0026] Figure 2 is a structural schematic diagram of a main test unit in one embodiment;

[0027] Figure 3 FIG. 4 is a schematic diagram of the structure of a sub-test unit in an embodiment. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0030] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0031] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0032] In one embodiment, Figure 1 As shown, a signal generating device is provided, including a main test unit 100 and a sub-test unit 200, wherein:

[0033] The main test unit 100 includes an arbitrary waveform generator (AWG) 110, a read-write control module 120, a storage device 130 and a first communication module 140; the read-write control module 120 is connected to the arbitrary waveform generator 110 and the storage device 130, reads the original waveform from the storage device 130 according to the received read request instruction, and returns the read original waveform to the arbitrary waveform generator 110; the arbitrary waveform generator 110 receives the original waveform and outputs a reconstructed waveform that matches the frequency of the sampling clock of the digital-to-analog conversion device 230 to the first communication module 140.

[0034] The sub-test unit 200 includes a second communication module 210 and an external clock chip 220, and may further include a digital-to-analog converter 230. The second communication module 210 is connected to the first communication module 140, and the digital-to-analog converter 230 is connected to the second communication module 210 and the external clock chip 220. The external clock chip 220 outputs a fixed-frequency sampling clock to the digital-to-analog converter 230. The reconstructed waveform is received by the second communication module 210 and then transmitted to the digital-to-analog converter 230. The reconstructed waveform is used by the digital-to-analog converter 230 to perform digital-to-analog conversion based on the sampling clock output by the external clock chip 220.

[0035] Among them, the main test unit 100 and the sub-test unit 200 can be the main test board and sub-test board of the test machine respectively. The arbitrary waveform generator 110 outputs a reconstructed waveform that matches the frequency of the sampling clock, which can mean that the sampling rate of the reconstructed waveform is the same as the frequency of the sampling clock, or that the error between the sampling rate of the reconstructed waveform and the frequency of the sampling clock is within an allowable range. The storage device 130 can be a DDR (Double Data Rate) storage device composed of DDR4 particles, and the external clock chip 220 can be a PLL (Phase Locked Loop) clock chip. The first communication module 140 and the second communication module 210 can be gigabit (such as GTX) communication modules, or other types of communication modules.

[0036] In actual applications, the modules within the main test unit 100 and the modules within the sub-test unit 200 can be interchanged as long as their functional relationships are met. For example, the arbitrary waveform generator 110 can be located in the sub-test unit 200. The first communication module 140 is connected to the second communication module 210 via a GTX high-speed communication bus. To meet the requirements of the digital-to-analog converter 230, the frequency of the original waveform arbitrarily set by the user is less than or equal to the frequency of the sampling clock output by the external clock chip 220.

[0037] The number of arbitrary waveform generators 110 can be one or more. For example, one arbitrary waveform generator 110 can be provided for each of the IQ channels of the tester. The number of first communication modules 140, second communication modules 210, and digital-to-analog converters 230 corresponds one-to-one to the number of arbitrary waveform generators 110. After reading the original waveform according to the received read request instruction, the read original waveform is returned to the arbitrary waveform generator 110 of the corresponding channel. After receiving the original waveform, the arbitrary waveform generator 110 performs DC (direct current) calibration, AC (alternating current) calibration, resampling, and other processing, and then generates a reconstructed waveform. The waveform is sent to the digital-to-analog converter 150 through the corresponding first communication module 140 and second communication module 21 for digital-to-analog conversion, resulting in an analog waveform signal output for testing semiconductor chips and other devices under test.

[0038] like Figure 2 As shown, the main test unit 100 also includes a first service decoding module 150. The first service decoding module 150 is connected to the arbitrary waveform generator 110 and the read-write control module 120. The module configures parameters of the arbitrary waveform generator 110 according to instructions issued by the host computer and stores the original waveform in the storage device 130 through the read-write control module 120. The read-write control module 120 and the storage device 130 can be connected via an Avalon interface.

[0039] Specifically, the arbitrary waveform generator 110, read / write control module 120, first communication module 140, and first service decoding module 150 can be disposed within an FPGA (Field-Programmable Gate Array), with the storage device 130 located external to the FPGA. Port DDR_REQ of the first service decoding module 150 is connected to ports DDR_RD and DDR_WR of the read / write control module 120. Port DDR_ARB of the read / write control module 120 is connected to the storage device 130, enabling waveform read and write control of the storage device 130 via the read / write control module 120. Port AWG_CTRL of the first service decoding module 150 is connected to the arbitrary waveform generator 110 to issue control signal parameters to control waveform resampling of the arbitrary waveform generator 110. The arbitrary waveform generator 110 is connected to port DDR_RD of the read / write control module 120 to facilitate waveform reading.

[0040] In one embodiment, the arbitrary waveform generator 110 includes a waveform request module 112 and a waveform data processing module 114. The waveform request module 112 is connected to the read-write control module 120 and the waveform data processing module 114, sends a read request instruction to the read-write control module 120, and sends the original waveform returned by the read-write control module 120 to the waveform data processing module 114; the waveform data processing module 114 is connected to the first communication module 140, receives the original waveform, and outputs a reconstructed waveform matching the frequency of the sampling clock to the first communication module 140.

[0041] The waveform request module 112 includes a waveform request unit 1122, a random access memory (RAM) storage unit 1124, and a data selection unit 1126. The waveform request unit 1122 is connected to the read / write control module 120, the RAM storage unit 1124, and the data selection unit 1126. The data selection unit 1126 is connected to the RAM storage unit 1124 and the waveform data processing module 114. Furthermore, the waveform request unit 1122 and the data selection unit 1126 are also connected to the first service decoding module 150.

[0042] The waveform request unit 1122 initiates a read request instruction to the read / write control module 120 based on the control signal parameters (including the PRE_START instruction, etc.) issued by the first service decoding module 150, requesting to read the corresponding original waveform. The control signal parameters may also include information such as the waveform length, the starting address of the original waveform in the storage device 130, and the number of times the waveform is repeated. When the PRE_START instruction is 1, only the original waveform of the I channel is requested from the read / write control module 120. When the PRE_START instruction is 2, only the original waveform of the Q channel is requested from the read / write control module 120. When the PRE_START instruction is 3, the original waveforms of both the I and Q channels are requested from the read / write control module 120. After the read / write control module 120 responds to the read request instruction, it outputs the original waveforms of both the I and Q channels to the waveform request unit 1122 based on the requested channel data information. After receiving the original waveform, waveform request unit 1122 determines whether to write it to RAM storage unit 1124 based on the waveform length. If the waveform length is less than a preset threshold length (e.g., 1024), it is written to RAM storage unit 1124. Otherwise, waveform request unit 1122 directly outputs the original waveform to data selection unit 1126. Data selection unit 1126 determines the source of the original waveform based on the waveform length parameter (e.g., AWG_Digital_CTRL_SIGNAL instruction) issued by service decoding module 160. If the waveform length is less than the preset threshold length, RAM storage unit 1124 outputs the original waveform. Otherwise, waveform request unit 1122 directly outputs the original waveform. Data selection unit 1126 then sends the original waveform to waveform data processing module 114 for resampling.

[0043] Because the original waveform can be very short, DDR bandwidth utilization is low at very short clock times, insufficient to support continuous waveform output. Therefore, the original waveform needs to be stored in RAM storage unit 1124 and controlled from RAM storage unit 1124 to mitigate the significant DDR bandwidth sacrifice associated with small data. RAM storage unit 1124 supports repeated waveform reads, continuous waveform output, and a stop read operation. When the waveform is relatively short, the original waveform is stored in RAM storage unit 1124, enabling continuous waveform output.

[0044] Furthermore, the arbitrary waveform generator 110 further includes a first bit width conversion module 116. The waveform data processing module 114 is connected to the first communication module 140 via the first bit width conversion module 116. For example, if the first communication module 140 uses a gigabit communication module, the first bit width conversion module 116 can convert a 32-bit reconstructed waveform into a 64-bit width to accommodate transmission using the gigabit communication module.

[0045] In one embodiment, Figure 3 As shown, the sub-test unit 200 also includes a second bit width conversion module 240, the second communication module 210 is connected to the second bit width conversion module 240, and the second bit width conversion module 240 is connected to the digital-to-analog conversion device 230. Again, taking the second communication module 210 as an example of a gigabit communication module, the second bit width conversion module 240 converts the received 64-bit waveform data into 32-bit data before outputting it. Furthermore, the sub-test unit 200 also includes a control module 250, which is connected to the second bit width conversion module 240 and the digital-to-analog conversion device 230. The control module 250 may specifically include a sending control module 252 and a synchronization control module 254, wherein the sending control module 252 is connected to the second bit width conversion module 240 and the synchronization control module 254, and the synchronization control module 254 is connected to the digital-to-analog conversion device 230. The sending control module 252 receives the reconstructed waveform through the second communication module 210 and sends the reconstructed waveform to the synchronization control module 254 according to the set period; the synchronization control module 254 caches the received reconstructed waveform in the internal cache module, and outputs the reconstructed waveform in the internal cache module after receiving the trigger signal.

[0046] In addition, sub-test unit 200 also includes a second service decoding module 260. This second service decoding module 260 is connected to control module 250 and external clock chip 220, and configures parameters for control module 250 and external clock chip 220 according to instructions issued by the host computer. Again, taking the test machine as an example, where the test machine includes IQ channels, the number of second communication modules 210, digital-to-analog converters 230, second bit-width conversion modules 240, and control modules 250 corresponds one-to-one to the number of arbitrary waveform generators 110.

[0047] It should be noted that the first business decoding module 150 and the second business decoding module 260 are both directly controlled by the host computer and sent independently. They do not affect each other and are two independent modules. The host computer configures the parameters of the first business decoding module 150 and the second business decoding module 260 differently.

[0048] Specifically, the second communication module 210, the second bit width conversion module 240, the control module 250, and the second service decoding module 260 can be set within the FPGA, and the external clock chip 220 and the digital-to-analog conversion device 230 are located outside the FPGA. The port PLL_CTRL of the second service decoding module 260 is connected to the external clock chip 220 via an SPI (Serial Peripheral Interface) interface, and the parameters of the external clock chip 220 are configured so that the external clock chip 220 outputs a fixed frequency sampling clock to the digital-to-analog conversion device 230. The external clock chip 220 can be configured to output the sampling clock at the maximum allowed frequency (such as 400MHz) or to output the sampling clock at other frequencies. The port AWG_CTRL of the second service decoding module 260 is connected to the transmission control module 252 and the synchronization control module 254 for parameter configuration.

[0049] The transmission control module 252 first caches the reconstructed waveform in an internal FIFO (First Input First Output) queue. Based on the point count information for a period of time sent by the second service decoding module 260, the transmission control module 252 outputs waveform point count data for a period of time to the synchronization control module 254. Upon receiving a trigger signal TRIG from the second service decoding module 260, the transmission control module 252 determines whether to proceed with subsequent waveform data transmission based on the configured single or repeated transmission parameter instructions. If single transmission is configured, the transmission control module 252 will no longer transmit data to the synchronization control module 254 upon receiving the trigger signal TRIG, waiting for the second service decoding module 260 to issue a stop signal STOP and then returning an idle state signal to the second service decoding module 260. If repeated transmission is configured, the transmission control module 252 will continue to transmit data to the synchronization control module 254 until it receives a stop signal STOP from the second service decoding module 260, then ceases transmitting data to the synchronization control module 254 and returns an idle state signal to the second service decoding module 260. After receiving the data sent by the sending control module 252, the synchronization control module 254 caches the data in the internal FIFO. At this time, the second business decoding module 260 synchronizes the trigger signal TRIG sent to the control module 254 to achieve trigger synchronization of the two channels. When the synchronization control module 254 receives the synchronized trigger signal TRIG, it reads data from the internal FIFO and outputs it to the digital-to-analog conversion device 230 until the data in the FIFO is sent, completing the data sending.

[0050] In addition, the sub-test unit 200 also includes a delay module, and the control module 250 is connected to the corresponding digital-to-analog conversion device 230 through the delay module. Specifically, the synchronization control module 254 in the control module 250 is connected to the corresponding digital-to-analog conversion device 230 through the delay module, and the synchronization control module 254 and the delay module can be connected through an LVDS (Low-Voltage Differential Signaling) interface. The delay module may specifically include an IDELAY unit and an ODELAY unit. The digital-to-analog conversion device 230 outputs the accompanying clock data_clk to the synchronization control module 254, and the synchronization control module 254 outputs the reconstructed waveform according to the accompanying clock data_clk. Since different routing will result in different delays, the IDELAY unit and the ODELAY unit are used to adjust the delay of the reconstructed waveform transmission so that the DAC chip meets the setup and hold time.

[0051] Taking the tester with dual IQ channels as an example, the DAC chips in both channels both send a data_clk clock. Since the sampling clocks input by the two DAC chips share the same source and frequency, only one of the sampling clocks can be used as the shared sampling clock for both DAC chips. The DAC chip outputs the data_clk clock to the synchronization control module 254, which then reconstructs the waveform based on the data_clk clock and sends it to the DAC chip.

[0052] Reference Figure 2 and Figure 3 The IQ DAC chips are identical, and the sampling clock of the DAC chip is set to a fixed maximum sampling clock (400MHz). Since the sampling rate of the original waveform in the storage device 130 can be set arbitrarily, but the DAC chip operates at a fixed maximum sampling clock, the original waveform is resampled by the arbitrary waveform generator 110. While ensuring that the waveform information (amplitude, frequency) remains unchanged, the original waveform of any sampling rate stored in the storage device 130 is resampled to the fixed maximum sampling clock. The sampling rate of the reconstructed waveform obtained is the same as the frequency of the sampling clock of the DAC chip. At the same time, during the resampling process, the initial phase of the reconstructed waveform generated by the resampling can be changed by setting the initial phase. The generated reconstructed waveform is output to the DAC chip, realizing the arbitrary sampling rate and arbitrary phase adjustable functions of the IQ channel. Using two ordinary DAC chips can realize the IQ function and the functions of two non-IQ channels at the same time, reducing the indicator requirements for the external clock chip 220 and the DAC chip, reducing the complexity of the hardware circuit, and reducing the design cost.

[0053] Specifically, the following describes the complete processing of the original waveform: After the signal generating device is powered on, the host computer communicates with the first service decoding module 150 and the second service decoding module 260 to issue instructions. The first service decoding module 150 stores the original waveform in the storage device 130 via the read-write control module 120 and configures parameters for the waveform request unit 1122, data selection unit 1126, and waveform data processing module 114 in the arbitrary waveform generator 110. The second service decoding module 260 configures parameters for the external clock chip 220 so that the external clock chip 220 outputs a fixed-frequency sampling clock to the digital-to-analog conversion device 230, and also configures parameters for the transmission control module 252 and synchronization control module 254.

[0054] The waveform request unit 1122 sends a read request instruction to the read / write control module 120 based on the control signal parameters configured by the first service decoding module 150, requesting to read the original waveform. After receiving the original waveform, the waveform request unit 1122 determines whether to write it to the RAM storage unit 1124 based on the waveform length. If the waveform length is less than a preset threshold length, the waveform request unit 1122 writes it to the RAM storage unit 1124. Otherwise, the waveform request unit 1122 directly outputs the original waveform to the data selection unit 1126. The data selection unit 1126 determines the source of the original waveform based on the waveform length parameter issued by the first service decoding module 150, obtains the original waveform from the RAM storage unit 1124 or the waveform request unit 1122, and sends it to the waveform data processing module 114 for resampling. The reconstructed waveform is then transmitted to the first communication module 140.

[0055] After receiving the reconstructed waveform via the second communication module 210, the transmission control module 252 transmits it to the synchronization control module 254 at a set period. The synchronization control module 254 caches the received reconstructed waveform in an internal buffer module. Upon receiving a trigger signal TRIG, the synchronization control module 254 transmits the cached reconstructed waveform to the DAC chip via a delay module, using the DAC chip's associated clock, data_clk, as the clock. The DAC chip performs digital-to-analog conversion on the received reconstructed waveform based on the sampling clock output by the external clock chip 220, generating an analog waveform signal that is output to the device under test for testing.

[0056] In one embodiment, an analog-digital hybrid test board is further provided, comprising the above-mentioned signal generating device.

[0057] In one embodiment, a test machine is provided, comprising a communication board, a backplane, and the aforementioned analog-digital hybrid test board. The communication board is connected to the analog-digital hybrid test board via the backplane. The test machine also includes a host computer that communicates with the communication board. The host computer can be, but is not limited to, various personal computers, laptops, smartphones, tablet computers, and portable wearable devices. The portable wearable devices can be smart watches, smart bracelets, head-mounted devices, and the like.

[0058] The above-mentioned signal generating device, analog-digital hybrid test board and test machine have the following advantages:

[0059] 1. This application uses a DAC chip to fix the sampling clock frequency. After power-on initialization, there is no need to repeatedly configure the external clock chip, which can simplify the complex procedures of the hardware link, reduce the index requirements for the external clock chip, and save costs.

[0060] 2. This application uses a DAC chip to fix the sampling clock frequency and performs resampling operations through a digital domain algorithm to achieve arbitrary sampling rate design, which can achieve uHZ sampling rate resolution adjustment. This indicator requirement is difficult to achieve by the existing method of adjusting the sampling rate through the clock chip.

[0061] 3. This application can realize both IQ functions and non-IQ functions, making it more flexible and convenient to use and improving the efficiency of equipment use.

[0062] 4. The control method of this application facilitates the expansion, reuse, and transplantation of program channels and can be directly used in other projects. For program updates, only channels need to be added or reduced, which facilitates program code maintenance.

[0063] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0064] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A signal generating device, characterized in that: It includes main test unit and sub-test unit, among which: The main test unit includes an arbitrary waveform generator, a read-write control module, a storage device and a first communication module; The read / write control module is connected to the arbitrary waveform generator and the storage device, reads the original waveform from the storage device according to the received read request instruction, and returns the read original waveform to the arbitrary waveform generator; the arbitrary waveform generator receives the original waveform and outputs a reconstructed waveform matching the frequency of the sampling clock of the digital-to-analog conversion device to the first communication module; The sub-test unit includes a second communication module and an external clock chip; The external clock chip outputs a sampling clock of a fixed frequency to the digital-to-analog conversion device; the second communication module is connected to the first communication module, receives the reconstructed waveform through the second communication module, and transmits it to the digital-to-analog conversion device; wherein, the reconstructed waveform is used by the digital-to-analog conversion device to perform digital-to-analog conversion according to the sampling clock output by the external clock chip.

2. The signal generating device according to claim 1, characterized in that: The arbitrary waveform generator comprises: a waveform request module connected to the read-write control module and the waveform data processing module, sending a read request instruction to the read-write control module, and sending the original waveform returned by the read-write control module to the waveform data processing module; The waveform data processing module is connected to the first communication module, receives the original waveform, and outputs a reconstructed waveform matching the frequency of the sampling clock to the first communication module.

3. The signal generating device according to claim 2, characterized in that: The waveform request module includes a waveform request unit, a RAM storage unit and a data selection unit. The waveform request unit is connected to the read-write control module, the RAM storage unit and the data selection unit. The data selection unit is connected to the RAM storage unit and the waveform data processing module.

4. The signal generating device according to claim 2, characterized in that: The first communication module and the second communication module are both gigabit communication modules.

5. The signal generating device according to claim 4, characterized in that: The arbitrary waveform generator also includes a first bit width conversion module, and the waveform data processing module is connected to the first communication module through the first bit width conversion module; the sub-test unit also includes a second bit width conversion module, and the second communication module is connected to the second bit width conversion module.

6. The signal generating device according to claim 5, characterized in that: The sub-test unit further includes a control module, which is connected to the second bit width conversion module and the digital-to-analog conversion device.

7. The signal generating device according to claim 6, characterized in that: The control module includes a sending control module and a synchronization control module, the sending control module is connected to the second bit width conversion module and the synchronization control module, and the synchronization control module is connected to the digital-to-analog conversion device; The sending control module receives the reconstructed waveform through the second communication module and sends the reconstructed waveform to the synchronization control module according to a set period; the synchronization control module caches the received reconstructed waveform in an internal cache module, and outputs the reconstructed waveform in the internal cache module after receiving a trigger signal.

8. The signal generating device according to claim 6, characterized in that: The main test unit further includes a first service decoding module, the first service decoding module being connected to the arbitrary waveform generator and the read-write control module, performing parameter configuration on the arbitrary waveform generator, and storing the original waveform in the storage device through the read-write control module; and / or The sub-test unit further includes a second service decoding module, which is connected to the control module and the external clock chip to perform parameter configuration on the control module and the external clock chip.

9. The signal generating device according to claim 6, characterized in that: The sub-test unit further includes a delay module, and the control module is connected to the corresponding digital-to-analog conversion device via the delay module.

10. An analog-digital hybrid test board, characterized in that: The invention comprises the signal generating device according to any one of claims 1 to 9.

11. A testing machine, characterized in that: The device comprises a communication board, a backplane and the analog-digital hybrid test board card according to claim 10.

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