Package assembly

Abstract

The embodiment of the utility model relates to a packaging assembly which comprises a semiconductor packaging piece, an optical packaging piece and optical cement. The semiconductor package includes an interposer structure and an overlying photonic structure. The optical package is disposed over the semiconductor package, in which the optical package includes a substrate, a cover, and an optical fiber array unit interposed between the substrate and the cover, and the substrate has at least one light-transmitting region therein. The optical cement is arranged between the photon structure and the at least one light-transmitting area of the substrate and is in contact with the photon structure and the at least one light-transmitting area of the substrate.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a package assembly. BACKGROUND

[0002] In recent years, the semiconductor industry has experienced rapid growth. This growth stems from continuous advances in semiconductor integrated circuitry, which are used in a variety of electronic devices. In order to keep abreast of this growth, there is an ongoing need to design, manufacture, and test integrated circuits more quickly and cost-effectively. One way to achieve these goals is to increase the integration density of the integrated circuits. Increasing integration density, in turn, has placed even more emphasis on reducing the size of the individual components that make up these integrated circuits. Despite the fact that existing integrated circuit packages or package assemblies are generally adequate for their intended purposes, they are not entirely satisfactory in all respects. SUMMARY

[0003] According to some embodiments of the present application, a package assembly includes at least one integrated circuit structure, a photonic structure, a semiconductor substrate, and an optical adhesive. The at least one integrated circuit structure is disposed on an interposer structure. The photonic structure is disposed on the interposer structure, the photonic structure being laterally adjacent to the at least one integrated circuit structure. The semiconductor substrate is disposed on the photonic structure, wherein the semiconductor substrate has at least one recess and at least one transparent region laterally adjacent to the at least one recess. The optical adhesive is disposed in a space between the semiconductor substrate and the photonic structure.

[0004] According to another alternative embodiment of the present application, a package assembly includes a semiconductor package, an optical package, and an optical adhesive. The semiconductor package includes an interposer structure and an overlying photonic structure. The optical package is disposed above the semiconductor package, wherein the optical package includes a substrate, a cap, and an optical fiber array unit between the substrate and the cap, and the substrate has at least one light-transmissive region therein. The optical adhesive is disposed between and in contact with the photonic structure and the at least one light-transmissive region of the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0005] The present application will be best understood by reading the following detailed description together with the accompanying drawings, in which:

[0006] Figures 1-6 is a schematic cross-sectional view of a method of forming a package assembly according to some embodiments.

[0007] Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 7D 、 Figure 7E 、 Figure 7F 、Figure 7G 、 Figure 7H 、 Figure 7I 、 Figure 7J 、 Figure 8 、 Figure 9 、 Figure 10A 、 Figure 10B 、 Figure 11A and Figure 11B shows different views of a flow diagram of a method of forming an optical package according to some embodiments.

[0008] Figures 12-17 is a schematic cross-sectional view of a method of forming a package assembly according to some embodiments.

[0009] Figure 18A 、 Figure 18B 、 Figure 18C 、 Figure 19A and Figure 19B shows different views of a method of forming an optical package according to some embodiments.

[0010] Figure 20 shows a method of forming a package assembly according to some embodiments.

[0011] Figure 21 shows a method of forming a package assembly according to some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. For purposes of summarizing the numerous embodiments of the present disclosure, certain example configurations are described herein. These are presented as examples and do not limit the present disclosure in any way. For example, in the following description, forming a second feature over or on a first feature can include embodiments in which the second feature and the first feature are formed in direct contact, and can also include embodiments in which additional features can be formed between the second feature and the first feature, such that the second feature and the first feature can not be in direct contact. Additionally, in various examples of the present disclosure, the same or similar reference numerals and / or letters can be used to refer to the same or similar components. The use of the same or similar reference numerals and / or letters in various examples is for illustrative purposes, and is not intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, spatially relative terms, such as "under", "below", "lower", "over", "upper", "atop", "on", "down", and "up", can be used herein for ease of reading only. Unless otherwise specified, a spatially relative term refers to at least one of the designated items "disposed", "located", "placed", "attached", or "connected" with respect to each other, with respect to an item, or with respect to an orientation, independent of the particular orientation of the items, the item, or the orientations thereof placed or disposed or attached or connected therein or thereon. The terms "first", "second", "third", etc., can be used herein to describe various elements, but do not imply a particular order or ranking of the elements, unless otherwise specified.

[0014] Embodiments described herein disclose a package assembly such as an opto-electronic integrated circuit (IC) package. In the present embodiments, a substrate with V-grooves for supporting a fiber array unit (FAU) is transparent in at least one portion thereof. Thus, after dispensing ultraviolet (UV) curing optical glue in the space between the substrate and the underlying photonic structure, UV light can pass through the transparent portion of the substrate in the optical glue curing process, thus increasing the adhesion between the substrate and the underlying photonic structure, and thus improving the FAU integration. With the optical interconnection provided by the photonic structure, higher communication performance and more compact packaging can be easily achieved.

[0015] Figures 1-6 is a schematic cross-sectional view of a method of forming a package assembly according to some embodiments. It should be understood that the present embodiments are not limited to the method described below. Additional operations can be provided before, during, and / or after the method, and some operations described below can be replaced or eliminated, in additional embodiments of the method. Although the method is described with reference to the package assembly of Figures 1-6 is described with reference to a method, it should be understood that Figures 1-6 The structure disclosed in

[0016] Referring to Figure 1 At least one semiconductor package PK1 is attached to a wafer tape T. In some embodiments, the semiconductor package PK1 includes the interposer structure 100, and an integrated circuit structure 200 and a photonic structure 300 bonded to the interposer structure 100. The integrated circuit structure 200 can include a system device, and the photonic structure 300 can include a photonic device, as will be described in detail below. However, the present embodiments are not limited thereto. In other embodiments, the semiconductor package PK1 also includes additional integrated circuit structures bonded to the interposer structure 100 in addition to the integrated circuit structure 200. The additional integrated circuit structures can include dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), memory devices such as high bandwidth memory (HBM) cubes, and the like.

[0017] In some embodiments, the interposer structure 100 includes a substrate 102 and a substrate via 104 that extends through the substrate 102. The substrate 102 can include an elemental semiconductor of silicon, germanium, and / or a compound semiconductor of silicon germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide. The substrate via 104 can include a metal such as copper and can be insulated from the substrate 102 by an insulating liner. In some embodiments, the interposer structure 100 further includes a conductive structure disposed between the substrate 102 and the integrated circuit structure 200 or the photonic structure 300 and electrically connected to the substrate via 104. The conductive structure can include a conductive component embedded by a dielectric layer.

[0018] In some embodiments, the interposer structure 100 further includes a metal pad 106 and a metal pad 108 on opposite sides that are configured to be electrically connected to an overlying and underlying electronic device, semiconductor device, or integrated circuit structure, respectively. In some embodiments, bumps B1 and B2 are also formed on and electrically connected to the metal pad 106 and the metal pad 108, respectively. For different overlying electrical structures, the bumps B1 can be divided into bumps B11 and B12. The bumps B1 and B2 can include solder bumps, and / or can include metal pillars (e.g., copper pillars), solder caps formed on the metal pillars, etc. In some examples, the bumps B1 are referred to as“micro bumps.” In some examples, the bumps B2 are referred to as“controlled collapse chip connection (C4) bumps.” The bumps B2 can have a different (e.g., larger) size than the bumps B1.

[0019] In some embodiments, the interposer structure 100 is an active interposer that contains at least one functional device or integrated circuit device included in the conductive structure or the substrate. In some examples, such an active interposer is referred to as a“device- containing interposer.” In some embodiments, the functional device includes an active device, a passive device, or a combination thereof. The functional device includes, for example, but is not limited to, a transistor, a capacitor, a resistor, a diode, a photodiode, a fuse device, and / or other similar devices. In other embodiments, the interposer structure 100 is a passive interposer that does not have a functional device or integrated circuit device. In some examples, such a passive interposer is referred to as a“device-free interposer.”

[0020] Still referring to Figure 1, the integrated circuit structure 200 is bonded to the interposer structure 100. The integrated circuit structure 200 may include a system device, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, a multi-core general-purpose processor (xPU) die, an artificial intelligence (AI) engine die, a transceiver (TRX) die, etc. In some embodiments, the integrated circuit structure 200 (e.g., a system device) includes a substrate 201 and a device layer 203. The substrate 201 may include an elemental semiconductor of silicon or germanium and / or a compound semiconductor of silicon germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide. The substrate 201 may be doped as desired. The device layer 203 may include transistors, such as fin field-effect transistors (FinFETs), nanostructured FETs (nanoFETs) (e.g., nanosheet transistors, nanowire transistors, or gate-all-around transistors), planar FETs, or the like, or a combination thereof. The device layer 203 may also include interconnect structures electrically connected to the transistors.

[0021] In some embodiments, integrated circuit structure 200 (e.g., a system device) further includes a metal pad 204 configured to be electrically connected to an underlying electronic device, semiconductor device, or integrated circuit structure. Specifically, integrated circuit structure 200 (e.g., a system device) is bonded to interposer structure 100 via metal pad 204, bump B11, and metal pad 106. Bump B11 may be formed on metal pad 204, metal pad 106, or both.

[0022] Still refer to Figure 1 , bonding the photonic structure 300 to the interposer structure 100. In some embodiments, the photonic structure 300 includes, from bottom to top, a photonic die 302o, an electronic die 302e, and a support die 310. In some examples, the photonic structure 300 may be referred to as a silicon photonic (SiPh) structure.

[0023] In some embodiments, the photonic die 302o includes a photonic integrated circuit (PIC) 303. The PIC 303 includes optical waveguides (e.g., silicon (Si) waveguides), modulators, detectors, grating couplers, filters, other optical components, or combinations thereof. In some embodiments, the photonic die 302o also includes at least one reflector Rl, at least one optical component 305, and electrically conductive features 307 embedded in at least one dielectric layer 306. The reflector Rl is configured to reflect light beams to a desired direction or a desired optical component. The optical component 305 is optically coupled to the PIC 303. In some embodiments, the optical component 305 includes an edge coupler (EC) and an optical waveguide, and the edge coupler is located between the reflector Rl and the optical waveguide. The optical waveguide included in the optical component 305 includes silicon nitride (SiN) waveguides, silicon carbide (SiC) waveguides, silicon carbon nitride (SiCN) waveguides, etc. The optical waveguide material in the dielectric layer 306 is different from the optical waveguide material inside the PIC 303. The silicon nitride waveguide in the optical component 305 has lower signal propagation loss than the silicon waveguide in the PIC 303, and is used to transmit optical signals over a relatively long distance. The electrically conductive features 307 of the photonic structure 300 are configured to be electrically connected to the underlying interposer structure 100. The reflector Rl and the electrically conductive features 307 can include metal (e.g., copper) and can be formed by an electroplating process or a sputtering process. The dielectric layer 306 can include silicon oxide, silicon nitride, silicon oxynitride, etc., or combinations thereof, and can be formed by a deposition process.

[0024] In some embodiments, a method of forming the photonic die 302o can include providing a silicon-on-insulator (SOI) substrate, forming a PIC 303 substrate on / in an active side (e.g., front side) of a silicon layer of the SOI, removing an oxide layer and a semiconductor layer of the SOI substrate, and forming at least one optical component 305, at least one reflector Rl, and electrically conductive features 307 embedded in at least one dielectric layer 306 on a non-active side (e.g., backside) of the silicon layer.

[0025] In some embodiments, the electronic die 302e includes an electric integrated circuit (EIC). The PIC of the photonic die 302o is integrated with the EIC of the electronic die 302e to achieve higher communication performance and a more compact package. In some embodiments, the electronic die 302e is bonded to the photonic die 302o by hybrid bonding including die-to-die bonding and metal-to-metal bonding.

[0026] In some embodiments, the size (e.g., width) of the electronic die 302e is smaller than the size (e.g., width) of the photonic die 302o, and an insulating material 304 is provided on the sides of the electronic die 302e to fill the space and reinforce the structure. The insulating material 304 can include a dielectric material, a polymer material, or a combination thereof. The dielectric material can include silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination thereof, and can be formed by a deposition process. The polymer material can include polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a molding compound (e.g., an epoxy), and can be formed by a deposition process or a molding process.

[0027] In some embodiments, the support die 310 is a semiconductor die, such as a silicon die. The support die 310 can include an elemental semiconductor of silicon, germanium, and / or a compound semiconductor of silicon germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide.

[0028] In some embodiments, the support die 310 includes at least one optical lens 311 and at least one optical lens 312 on opposite sides thereof. The optical lens 311 and the optical lens 312 can be aligned with each other. The optical lens 311 and the optical lens 312 can be embedded in the support die 310 and face each other. The optical lens 311 and the optical lens 312 are configured to converge a light beam on a desired cross-section, or focus a light beam in a desired direction. In some embodiments, each of the optical lens 311 and the optical lens 312 can have an optical recessed feature. In some embodiments, each of the optical lens 311 and the optical lens 312 has a substantially vertical sidewall and a convex bottom. The shape of the optical lens 311 can be symmetrical to the shape of the optical lens 312, and can be designed to have a desired curvature for focusing a light beam to an underlying optical component.

[0029] In some embodiments, a method of forming each of the optical lens 311 and the optical lens 312 includes performing an etching process or a laser process to form a recessed feature, and filling the recessed feature with an optical material or a transparent material. The optical material has a transmission percentage of about 80-99% (e.g., 85-95% or 88-92%). In some embodiments, the optical material includes an optical liquid silicone rubber, polymethyl methacrylate (PMMA), an optical epoxy, or the like, or a combination thereof. In some embodiments, the optical material includes a high numerical aperture (NA) material with a NA of about 0.2 to 0.5. In some embodiments, a dispensing, injection, and / or spraying process is used, followed by a planarization process to form the optical material.

[0030] In some embodiments, support die 310 is bonded to electronic die 302e via fusion bonding, such as dielectric-to-dielectric bonding or polymer-to-polymer bonding. Specifically, support die 310 is bonded to electronic die 302e via dielectric bonding layer 314 and dielectric bonding layer 309. Dielectric bonding layer 314 and dielectric bonding layer 309 each include a dielectric layer, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or a combination thereof. The dielectric layer may be replaced by a polymer layer or an insulating layer, as desired.

[0031] In some embodiments, the photonic structure 300 (e.g., a photonic device) further includes a metal pad 308 configured to electrically connect to an underlying electronic component, semiconductor device, or integrated circuit structure. Specifically, the photonic structure 300 (e.g., a photonic device) is bonded to the interposer structure 100 via the metal pad 308, the bump B12, and the metal pad 106. The bump B12 may be formed on the metal pad 308, the metal pad 106, or both.

[0032] See also Figure 1 After the integrated circuit structure 200 and the photonic structure 300 are bonded to the interposer structure 100, an underfill layer UF1 is formed to fill the space between the interposer structure 100 and each of the integrated circuit structure 200 and the photonic structure 300, and surround bump B1 including bumps B11 and B12. In some embodiments, underfill layer UF1 includes a molding compound such as epoxy and is formed using a dispensing, injection, and / or spraying process. The underfill layer UF1 between two adjacent structures may have a curved surface and a concave surface. In some examples, underfill layer UF1 may be omitted.

[0033] Thereafter, an encapsulation layer E1 is formed over the interposer structure 100 and laterally surrounds the integrated circuit structure 200 and the photonic structure 300. In some embodiments, the encapsulation layer E1 comprises a molding compound, a molding underfill, a resin, or the like. In some embodiments, the encapsulation layer E1 comprises a polymer material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or a combination thereof. The encapsulation layer E1 can be formed by a molding process followed by a curing process.

[0034] In some embodiments, a wafer dicing process is performed to separate adjacent semiconductor packages PK1 from one another. Each semiconductor package PK1 may have substantially vertical sidewalls. In some embodiments, semiconductor package PK1 includes an interposer structure 100, an integrated circuit structure 200 and a photonic structure 300 bonded to interposer structure 100, and an encapsulation layer E1 that laterally encapsulates the sidewalls of the integrated circuit structure 200 and the photonic structure 300.

[0035] See also Figure 1 andFigure 2 , the wafer tape T is removed, and a board substrate 700 is formed below the interposer structure 100 and electrically connected to the interposer structure 100. In some embodiments, the board substrate 700 is bonded to the interposer structure 100 through bumps B2.

[0036] In some embodiments, the board substrate 700 includes a core layer and two building layers located on opposite sides of the core layer. In some embodiments, the board substrate 700 includes a wiring pattern 702 that penetrates the core layer and the building layers to provide electrical wiring between different devices and electronic devices. The wiring pattern 702 includes lines, through-holes, pads and / or connectors. In some examples, the board substrate 700 is referred to as a "printed circuit board (PCB)". In other embodiments, the core layer of the board substrate 700 can be omitted as needed, and such a board substrate 700 is referred to as a "coreless board substrate".

[0037] Thereafter, an underfill layer UF2 is formed to fill the space between the interposer structure 100 and the board substrate 700 and surround the bumps B2. In some embodiments, the underfill layer UF2 includes a molding compound such as epoxy resin and is formed using a dispensing, injection, and / or spraying process.

[0038] In some embodiments, a support structure 800 is provided and bonded to the side of the photonic structure 300 of the semiconductor package PK1 on the board substrate 700. The support structure 800 is configured to support the optical package PK2 (eg, Figure 2 (as shown), resulting in a very rigid structure. In some embodiments, support structure 800 is a wall structure on one side of photonic structure 300, or a ring structure surrounding photonic structure 300. In this case, support structure 800 comprises a heat dissipation material, such as metal. Support structure 800 is attached to board substrate 700 via adhesive layer 801. However, embodiments of the present invention are not limited thereto. In other embodiments, support structure 800 may be a silicon dummy chip to eliminate coefficient of thermal expansion (CTE) mismatch and thereby reduce package warpage.

[0039] Then, bumps B3 are formed under the board substrate 700 and electrically connected to the board substrate 700. In some embodiments, bumps B3 are electrically connected to the wiring pattern 702 of the board substrate 700. In some embodiments, bumps B3 may include solder bumps and / or may include metal pillars (e.g., copper pillars), solder caps formed on the metal pillars, etc. In some examples, bumps B3 are referred to as "ball grid array (BGA) balls." The size of bumps B3 may be different from (e.g., larger than) the size of bumps B2.

[0040] Referring to Figure 2 An optical package PK2 is disposed over the semiconductor package PK1. In some embodiments, the optical package PK2 includes a fiber array unit (FAU) 500 embedded in a substrate 400 (or referred to as a "carrier" in some examples) and covered by a cap 900 (or referred to as a "cap body" in some examples). In some embodiments, the substrate 400 includes a base substrate 401, a dielectric layer 410, a hard mask layer 414, and all optical components formed in the above layers. In some embodiments, the base substrate 401 is a semiconductor substrate, which includes an elemental semiconductor of silicon or germanium and / or a compound semiconductor of silicon germanium. The base substrate 401 can include a light-blocking material or an opaque material. In some examples, the base substrate 401 can be referred to as a "semiconductor carrier", a "light-blocking substrate", or an "opaque substrate". Figures 7A-7J 、 Figure 8 、 Figure 9 、 Figure 10A 、 Figure 10B 、 Figure 11A and Figure 11B Methods of forming the optical package PK2 are described in different views in Figure 7A Each of FIGS. 1 to 7 shows a simplified top view and a corresponding cross-sectional view taken along line I-I. Figure 8 and Figure 9 show a simplified top view of some components. Figure 10A show a simplified top view of some components, and Figure 10B show a cross-sectional view taken along line II-II of Figure 10A . Figure 11A show a simplified top view of some components, and Figure 11B show a cross-sectional view taken along line II-II of Figure 11A .

[0041] Referring to Figure 7A The base substrate 401 is formed on a carrier C, and a de-bonding layer DL is formed between the carrier C and the base substrate 401. The carrier C can be a glass carrier or any suitable carrier to carry the substrate. The de-bonding layer DL can include a release layer (e.g., a light-to-heat conversion (LTHC) layer) or an adhesive layer (e.g., a UV-cured adhesive or a heat-cured adhesive layer). In some embodiments, the base substrate 401 is a semiconductor substrate, which includes an elemental semiconductor of silicon or germanium and / or a compound semiconductor of silicon germanium. The base substrate 401 can include a light-blocking material or an opaque material. In some examples, the base substrate 401 can be referred to as a "semiconductor carrier", a "light-blocking substrate", or an "opaque substrate".

[0042] Referring to Figure 7BOne or more light-transmitting regions 402 are formed in the base substrate 401. In some embodiments, the method of forming the light-transmitting regions 402 includes forming holes through the base substrate 401 by a lithography and etching process, filling the holes with a light-transmitting material by a deposition process, and removing the excess light-transmitting material outside the holes by a planarization process or a grinding process. The light-transmitting regions 402 can have sloped sidewalls, as shown in Figure 7B However, embodiments of the present disclosure are not limited thereto. In other embodiments, the light-transmitting regions 402 can have substantially vertical sidewalls. In some embodiments, the light-transmitting material includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or a transparent material. For example, the light-transmitting material includes silicon oxide. In some examples, the light-transmitting regions 402 can be referred to as "transparent regions."

[0043] In some embodiments, at least one optical lens 403 is formed between the light-transmitting regions 402. In some embodiments, the optical lens 403 has substantially vertical sidewalls and a convex bottom. The optical lens 403 can be designed to have a desired curvature for focusing a light beam to an underlying optical component. In some embodiments, the method of forming the optical lens 403 includes performing an etching process or a laser process to form a recessed feature, and filling the recessed feature with an optical material or a transparent material. The optical material has a transmission percentage of about 80-99% (e.g., 85-95% or 88-92%). In some embodiments, the optical material includes an optical liquid silicone rubber, polymethyl methacrylate (PMMA), an optical epoxy, etc., or a combination thereof. In some embodiments, the optical material includes a high numerical aperture (NA) material with a NA of about 0.2 to 0.5. In some embodiments, a dispensing, injection, and / or spraying process is used, followed by a planarization process to form the optical material. The optical lens 403 can be optional and can be omitted as needed. In some embodiments, the optical lens 403 can be formed before or after the light-transmitting regions 402 are formed. The shape of the optical lens 403 is different from the shape of the lens region 402 from a top view. The optical lens 403 can be oval or elliptical, and the light-transmitting region 402 can be circular.

[0044] Referring to Figure 7C A first hard mask layer 404 is formed on the base substrate 401. The first hard mask layer 404 is configured to define a groove for supporting a fiber array unit (FAU) 500 later formed, as shown in Figure 10A , Figure 10B , Figure 11A and Figure 11BThe first hard mask layer 404 exposes a region of the base substrate 401 to be etched to define a groove, and exposes another region of the base substrate 401 in which the optical component is formed. In some embodiments, the method of forming the first hard mask layer 404 includes depositing a first hard mask material, followed by a patterning process (e.g., lithography and etching process). The first hard mask material includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, etc. For example, the first hard mask material includes silicon nitride.

[0045] Referring to Figure 7D , at least one reflector R2 and at least one optical component 412 are formed embedded in at least one dielectric layer 410 over the base substrate 401. The dielectric layer 410 can include silicon oxide, silicon nitride, silicon oxynitride, etc. or a combination thereof, and can be formed by a deposition process. The dielectric layer 410 covers the underlying first hard mask layer 404. The reflector R2 and the optical component 412 are configured to reflect and direct the light beams from the optical fiber to the desired optical component (e.g., the underlying optical lens 403, as Figures 3-6 indicated). The reflector R2 can include metal (e.g., copper) and can be formed by an electroplating process or a sputtering process. The optical component 412 is optically coupled to the PIC 303 and the FAU 500 of the photonic structure 300 (as Figure 6 indicated). Specifically, as Figure 8 , Figure 9 , Figure 10A , Figure 10B , Figure 11A and Figure 11B indicated, the plurality of reflectors R2 corresponds to the plurality of optical components 412 (including the plurality of optical waveguides WG and the plurality of edge couplers EC), and thus to the plurality of grooves GR and the overlying optical fibers 506, respectively. In some embodiments, as Figure 8 and Figure 9 indicated, each optical component 412 includes an edge coupler EC and an optical waveguide WG, and the edge coupler EC is located between the reflector R2 and the optical waveguide WG. In some embodiments, the plurality of optical waveguides WG are configured to "direct" the light beams (from the plurality of optical fibers) "straightly" toward the reflector R2, as Figure 8 and Figure 10A indicated. However, the present embodiments are not limited thereto. In other embodiments, the plurality of optical waveguides WG are configured to "direct" the light beams (from the plurality of optical fibers) "narrowly" toward the reflector R2, and thus these optical waveguides WG are referred to as "fan-in waveguides", as Figure 9 and Figure 11AAs shown in FIG. In some embodiments, the optical waveguide WG included in each optical component 412 includes a silicon nitride (SiN) waveguide, a silicon carbide (SiC) waveguide, a silicon nitride carbon (SiCN) waveguide, or the like. The material of the optical waveguide WG in dielectric layer 410 is different from that of the optical waveguide within PIC 303. The silicon nitride waveguide WG in optical component 412 has lower signal propagation loss than the silicon waveguide in PIC 303 and is used to transmit optical signals over relatively long distances.

[0046] refer to Figure 7E , a second hard mask layer 414 is formed on the dielectric layer 410. The second hard mask layer 414 is used to define the grooves (such as Figure 8 、 Figure 9 、 Figure 10A 、 Figure 10B 、 Figure 11A and Figure 11B ). In some embodiments, the second hard mask layer 414 covers a portion of the dielectric layer 410 in which the optical component is formed, while exposing another portion of the dielectric layer 410 without the optical component. In some embodiments, the method of forming the second hard mask material includes depositing the second hard mask material, followed by a patterning process (e.g., a lithography and etching process). The second hard mask material includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, etc. For example, the second hard mask material includes silicon nitride. The second hard mask material can be the same as or different from the first hard mask material. The materials included in the dielectric layer 410 hard mask material and the first hard mask material and the materials included in each hard mask material have different etching selectivities.

[0047] refer to Figure 7F The exposed portion of the dielectric layer 410 is removed by using the second hard mask layer 414 as a mask. The removal process includes an etching process, such as a dry etching process. During the removal process, the underlying first hard mask layer 404 and the area of ​​the base substrate 401 used to define the groove are exposed.

[0048] See also Figure 7G , using the first mask layer 404 and the second mask layer 414 as masks, the exposed portion of the base substrate 401 is removed, thereby forming one or more grooves GR in the base substrate 401. The removal process includes an etching process, such as a wet etching process. In some embodiments, the etching solution etches the silicon of the base substrate 401 along a specific crystal plane, so that the groove GR forms a V-groove, such as Figure 10B and Figure 11B Specifically, the groove GR has a sharp V-shaped bottom. In some embodiments, the angle θ between the top surface and the sidewall of each groove GR is approximately 50 to 70 degrees, for example, approximately 55 to 65 degrees. Due to crystal characteristics, the angle θ is generally a fixed angle.

[0049] Referring Figure 7H , the carrier C is debonded and removed from the base substrate 401. In some embodiments, the debonding layer DL is decomposed under photothermal action, and then the carrier C is peeled off from the backside of the base substrate 401.

[0050] Referring Figure 7I , Figure 10A , Figure 10B , Figure 11A and Figure 11B , the plurality of optical fibers 506 of the FAU 500 are placed on the grooves GR, respectively. Due to the fixed angle of the V-grooves GR, the optical fibers 506 sit on the grooves accurately and stably. The optical fibers 506 are arranged in an array. For example, the optical fibers 506 can be arranged in one row, two rows, or multiple rows as needed. In some embodiments, each optical fiber 506 includes a glass core 502 and a glass cladding 504 surrounding the glass core 502. In some embodiments, as shown in FIG. 5B, a portion of each optical fiber 506 is embedded in a ferrule 508, and the remaining portion of the optical fiber 506 is embedded in a fiber ribbon. Figure 2

[0051] Referring Figure 7J , Figure 10A , Figure 10B , Figure 11A and Figure 11B , the cover 900 is disposed above the base substrate 401, so that the optical fibers 506 of the FAU 500 are interposed between the base substrate 401 and the cover 900. The cover 900 is configured to protect and secure the underlying base substrate 401 and the FAU 500. The cover 900 can be a glass cover or a transparent cover. Thereafter, optical glue GL is dispensed into the space between the FAU 500 and each of the base substrate 401 and the cover 900, followed by a curing process. The optical glue GL contains a curable adhesive material, and has high light transmittance and high adhesion. The optical glue GL can have a convex surface and extend from the sidewall of the cover 900. Thereby, an optical package PK2 including the fiber array unit (FAU) 500 interposed between the base substrate 401 and the cover 900 is completed.

[0052] Referring Figure 3 , the optical package PK2 is placed on the semiconductor package PK1. In some embodiments, the optical lens 403 of the optical package PK2 corresponds to (e.g., is vertically aligned with) the optical lens 312 of the underlying photonic structure 300 of the semiconductor package PK1.

[0053] ​Thereafter, a UV-curable optical glue UGL is dispensed into the space between the optical package PK2 and the semiconductor package PK1. The UV-curable optical glue UGL includes a UV-curable adhesive material with high optical transmittance and high adhesion. The UV-curable optical glue UGL can have a convex shape that extends from the sidewall of the base substrate 401 of the optical package PK2 and from the sidewall of the encapsulation layer E1 of the semiconductor package PK1. The UV-curable optical glue UGL in this stage “uncured” is soft and less sticky, so the optical package PK2 above can be moved and rotated in the horizontal direction (e.g., along the X and / or Y directions) and the vertical direction (e.g., along the Z direction). In some embodiments, before the UV-curing process is performed on the UV-curable optical glue UGL, the position of the optical package PK2 can be adjusted to the proper position to ensure that the optical package PK2 is in place and aligned with the optical package PK1.

[0054] Referring to Figure 4 , a UV curing process P is performed to pass UV light through the light-transmissive region 402 of the optical package PK2 to the UV-curable optical glue to cure and harden the uncured UV-curable optical glue to form a cured optical glue UGL1. Specifically, after the optical package PK2 is adjusted to the proper position, the UV-curable optical glue UGL is cured to fix the position of the optical package PK2.

[0055] Referring to Figure 5 , after the UV curing process P, a buffer layer 802 is provided between the optical package PK2 and the support structure 800 to better support the optical package PK2 to stabilize the entire package assembly. The buffer layer 802 can be an adhesive layer or a thermal interface material (TIM). The back surface of the base substrate 401 is in physical contact with the buffer layer 802 on the support structure 800. In some examples, the buffer layer 802 is considered as part of the support structure 800. The package assembly 10 of the present disclosure is thus completed.

[0056] In some embodiments, as shown in Figure 6 , the light beam L propagates through the optical fiber 506, travels through the edge coupler and the silicon nitride waveguide of the optical assembly 412, is redirected by the reflector R2, and is then optically coupled to the PIC 303 in sequence through the optical lens 312, the optical lens 311, the reflector R1, and the edge coupler and the silicon nitride waveguide of the optical assembly 305.

[0057] In the present invention, the substrate with V-groove for fixing the fiber array unit (FAU) is provided with a transparent region. Therefore, after distributing the ultraviolet (UV) curing optical glue in the space between the substrate and the underlying photonic structure, the ultraviolet light can pass through the transparent region of the substrate in the optical glue curing process, thereby increasing the adhesion between the substrate and the underlying photonic structure, and thus improving the FAU integration.

[0058] In the above embodiment, a transparent region is formed on the semiconductor substrate, so that the ultraviolet light can pass through the transparent region to cure the optical glue. However, the embodiments of the present invention are not limited thereto. In other embodiments, a transparent material substrate such as a glass substrate can be used to replace the semiconductor substrate, so that the ultraviolet light can directly pass through the transparent material substrate to cure the optical glue.

[0059] Figures 12-17 is a schematic cross-sectional view of a method of forming a package assembly according to some embodiments. It should be understood that the embodiments of the present invention are not limited to the method described below. Additional operations can be provided before, during, and / or after the method, and some operations described below can be replaced or eliminated. Although the method is described with reference to the package assembly of Figures 12-17 is described with reference to the method, it should be understood that Figures 12-17 the structure disclosed in is not limited to this method, but can exist independently of the method as a structure.

[0060] Figures 12-17 The method of forming Figures 1-6 is similar to the method of forming Figures 12-12 , the difference being the substrate material of the optical package. In this document, the same or similar reference numerals and / or letters can be used to refer to the same or similar components in various examples of the present invention, and thus Figure 17 the materials, configurations, and / or methods of forming the components in may refer to the descriptions in the above embodiments.

[0061] Figure 12 Referring to Figure 1 , at least one semiconductor package PK1 is attached to the wafer tape T. The semiconductor package PK1 has been described in and will not be described again here.

[0062] Figure 13 Referring to , the wafer tape T is removed, a board substrate 700 is formed under the interposer structure 100 and the board substrate 700 is electrically connected to the interposer structure 100. In some embodiments, the board substrate 700 is bonded to the interposer structure 100 by bumps B2.

[0063] In some embodiments, the board substrate 700 includes a core layer and two building layers located on opposite sides of the core layer. In some embodiments, the board substrate 700 includes a wiring pattern 702 that penetrates the core layer and the building layers to provide electrical wiring between different devices and electronic devices. The wiring pattern 702 includes lines, through-holes, pads and / or connectors. In some examples, the board substrate 700 is referred to as a "printed circuit board (PCB)". In other embodiments, the core layer of the board substrate 700 can be omitted as needed, and such a board substrate 700 is referred to as a "coreless board substrate".

[0064] Thereafter, an underfill layer UF2 is formed to fill the space between the interposer structure 100 and the board substrate 700 and surround the bumps B2. In some embodiments, the underfill layer UF2 includes a molding compound such as epoxy resin and is formed using a dispensing, injection, and / or spraying process.

[0065] In some embodiments, a support structure 800 is provided and bonded to the side of the photonic structure 300 of the semiconductor package PK1 on the board substrate 700. The support structure 800 is configured to support the optical package PK3 (eg, Figure 13 (as shown), resulting in a very strong final structure. In some embodiments, support structure 800 is a wall structure on one side of photonic structure 300, or a ring structure surrounding photonic structure 300. In this case, support structure 800 comprises a heat dissipation material, such as metal. Support structure 800 is attached to board substrate 700 via adhesive layer 801. However, embodiments of the present invention are not limited thereto. In other embodiments, support structure 800 may be a silicon dummy chip to eliminate coefficient of thermal expansion (CTE) mismatch and thereby reduce package warpage.

[0066] Then, bumps B3 are formed under the board substrate 700 and electrically connected to the board substrate 700. In some embodiments, bumps B3 are electrically connected to the wiring pattern 702 of the board substrate 700. In some embodiments, bumps B3 may include solder bumps and / or may include metal pillars (e.g., copper pillars), solder caps formed on the metal pillars, etc. In some examples, bumps B3 are referred to as "ball grid array (BGA) balls." The size of bumps B3 may be different from (e.g., larger than) the size of bumps B2.

[0067] refer to Figure 13 , the optical package PK3 is disposed above the semiconductor package PK1. In some embodiments, the optical package PK3 includes a fiber array unit (FAU) 500 embedded in a substrate 400' (or referred to as a "carrier" in some examples) and covered by a cover 900 (or referred to as a "cover" in some examples).Figures 18A-18C , Figure 19A and Figure 19B The method of forming the optical package PK3 is described in different views in Figure 19A A simplified top view showing some components, and Figure 19B A cross-sectional view taken along line III-III of Figure 19A .

[0068] Referring to Figure 18A , a substrate 400’ is provided. The substrate 400’ can be a glass substrate or a transparent substrate. Then, at least one reflector R2’ is formed on the surface of the substrate 400’. The reflector R2’ is configured to reflect and direct the light beam from the optical fiber 506 to the desired optical component (e.g., the optical lens 403 below, as shown in Figures 14-17 ). Specifically, as shown in Figure 19A and Figure 19B , the plurality of reflectors R2’ respectively correspond to the plurality of grooves GR’ and the optical fiber 506 above. The method of forming the reflector R2’ includes: forming a plurality of grooves on the surface of the substrate 400’ by a glass cutting process, forming a metal (e.g., copper) on the surface of the grooves by an electroplating process or a sputtering process, and then removing the excess metal outside the grooves. The glass cutting process can include a diamond blade cutting process, etc. In some embodiments, the substrate 400’ is patterned by a suitable blade to define the desired shape of the recesses, and those recesses and the reflector R2’ have a rounded top corner and a rounded bottom corner.

[0069] Then, one or more grooves GR’ are formed in the substrate 400’. The method of forming the groove GR’ includes performing a glass cutting process. The glass cutting process can include a diamond blade cutting process, etc. In some embodiments, the substrate 400’ is patterned by a suitable blade to define the desired shape. Specifically, the groove GR’ has a rounded V-shaped bottom. In some embodiments, the substrate 400’ is patterned by a suitable blade to define the desired shape of the groove GR’, and those grooves GR’ have a rounded top corner and a rounded bottom corner. In some embodiments, the included angle θ between the top surface and the sidewall of each groove GR’ is about 50 to 70 degrees, for example, about 55 to 65 degrees.

[0070] Referring to Figure 18CA cover 900 is disposed above the substrate 400', thus the optical fibers 506 of the FAU 500 are inserted between the substrate 400' and the cover 900. The cover 900 is configured to protect and secure the underlying substrate 400' and the FAU 500. The cover 900 can be a glass cover or a transparent cover. Thereafter, an optical glue GL is dispensed into the space between the FAU 500 and each of the substrate 400' and the cover 900, followed by a curing process. The optical glue GL includes a curable adhesive material, and has high light transmittance and high adhesion. The optical glue GL can have a convex surface and extend from the sidewall of the cover 900. Thereby, an optical package PK3 including the fiber array unit (FAU) 500 inserted between the substrate 400' and the cover 900 is completed.

[0071] Referring to Figure 14 The optical package PK3 is placed on the semiconductor package PK1. In some embodiments, the reflector R2' of the optical package PK3 corresponds to (e.g., is aligned vertically with) the optical lens 312 of the underlying semiconductor package PK1.

[0072] Thereafter, an ultraviolet light-cured optical glue UGL is dispensed into the space between the optical package PK3 and the semiconductor package PK1. The ultraviolet light-cured optical glue UGL includes an ultraviolet light-cured adhesive material, and has high light transmittance and high adhesion. The ultraviolet light-cured optical glue UGL can have a convex surface, can extend from the sidewall of the substrate 400' of the optical package PK3, and can extend from the sidewall of the encapsulation layer E1 of the semiconductor package PK1. The "uncured" ultraviolet light-cured optical glue UGL at this stage is soft and less adhesive, thus the optical package PK3 above can be moved and rotated in horizontal directions (e.g., along the X and / or Y directions) and vertical directions (e.g., along the Z direction). In some embodiments, before the ultraviolet light-cured process is performed on the ultraviolet light-cured optical glue UGL, the position of the optical package PK3 can be adjusted to an appropriate position to ensure that the optical package PK3 is in place and aligned with the optical package PK1.

[0073] Referring to Figure 15 An ultraviolet light-cured process P is performed to cure the uncured ultraviolet light-cured optical glue UGL by passing ultraviolet light through the glass substrate 400' of the optical package PK3 to the ultraviolet light-cured optical glue, to harden the uncured ultraviolet light-cured optical glue to form a cured optical glue UGL1. Specifically, after the optical package PK3 is adjusted to an appropriate position, the ultraviolet light-cured optical glue UGL is cured to secure the position of the optical package PK3.

[0074] Referring to Figure 16After the UV curing process P, a buffer layer 802 is disposed between the optical package PK3 and the support structure 800 to better support the optical package PK3 to stabilize the entire package assembly. The buffer layer 802 can be an adhesive layer or a thermal interface material (TIM). The back surface of the substrate 400' is in physical contact with the buffer layer 802 on the support structure 800. In some examples, the buffer layer 802 is considered as part of the support structure 800. The package assembly 20 of the present disclosure is thus completed.

[0075] In some embodiments, as shown in FIG. 5, the light beam L propagates through the optical fiber 506, is redirected by the reflector R2', and is then optically coupled to the PIC 303 in sequence through the optical lens 312, the optical lens 311, the reflector Rl, and the silicon nitride waveguide and edge coupler of the optical assembly 305. Figure 17

[0076] In the present disclosure, the V-grooved substrate used to secure the fiber array unit (FAU) is a transparent substrate. Thus, after dispensing the ultraviolet (UV) curing optical glue in the space between the substrate and the underlying photonic structure, in the optical glue curing process, the ultraviolet light can pass through the transparent substrate, thereby increasing the adhesion between the substrate and the underlying photonic structure, and thus improving the FAU integration.

[0077] Figure 20 A method of forming a package assembly according to some embodiments is shown. Although this method is illustrated and / or described as a series of acts or events, it will be appreciated that the method is not limited by the illustrated ordering of acts or events. Thus, some acts or events can occur in different orders than shown, and / or some acts or events can occur concurrently. In addition, some illustrated acts or events can be omitted, and other unillustrated acts or events can be included. Furthermore, not all illustrated acts or events can be required, and some acts or events can be performed in hardware, software, or a combination thereof.

[0078] At act S200, a semiconductor package is provided, the semiconductor package including an interposer structure and an overlying photonic structure. Figure 1 and Figure 12 A cross-sectional view of some embodiments corresponding to act S200 is shown.

[0079] At act S201, a support structure is provided on a side of the semiconductor package. Figure 2 and Figure 13 A cross-sectional view of some embodiments corresponding to act S201 is shown. Act S201 is optional and can be omitted in some examples.

[0080] ​In step S202, an optical package is placed on a semiconductor package, wherein the optical package includes a substrate, a cap, and a fiber array unit interposed between the substrate and the cap. Figure 2 、 Figures 7A-7J 、 Figure 8 、 Figure 9 、 Figure 10A 、 Figure 10B 、 Figure 11A and Figure 11B 、 Figure 13 、 Figures 18A-18C 、 Figure 19A and Figure 19B show different views of some embodiments of the present application corresponding to act S202.

[0081] In some embodiments, the substrate includes a semiconductor substrate and at least one transparent region through the semiconductor substrate. In some embodiments, the substrate includes two transparent regions and an optical lens, and the optical lens is formed between the two transparent regions. In some embodiments, at least one recess is formed in the substrate, and the fiber array unit is adhered to the at least one recess. In some embodiments, the method of forming the at least one recess includes performing an etching process. See Figure 3 、 Figure 14 、 Figure 3 、 Figure 14 、 Figure 4 、 Figure 15 、 Figure 5 and Figure 16 .

[0082] In some embodiments, the substrate includes a glass substrate. In some embodiments, at least one recess is formed in the substrate, and the fiber array unit is adhered to the at least one recess. In some embodiments, the method of forming the at least one recess includes performing a glass cutting process. See Figure 21 、 Figure 1 、 Figure 1 and Figure 2 .

[0083] In step S204, optical glue is dispensed into a space between the semiconductor package and the optical package. Figure 2 and Figures 7A-7J show cross-sectional views of some embodiments corresponding to act S204. In some embodiments, the optical glue includes ultraviolet-cured optical glue.

[0084] Step S206, after dispensing the optical glue, the position of the optical package is adjusted. Figure 8 and Figure 9 show cross-sectional views of some embodiments corresponding to act S206. Act S206 is performed after act S204 to better optically couple the optical package and the underlying semiconductor package.

[0085] At step S208, the curing light is shone through the optical package to cure the optical glue. Figure 10A and Figure 10B Cross-sectional views are shown corresponding to some embodiments of act S208. Step S208 is performed after step S206 in order to better secure the optical package and the underlying semiconductor package in place.

[0086] At act S209, a buffer layer is provided between the support structure and the optical package. Figure 11A and Figure 11B Cross-sectional views are shown corresponding to some embodiments of act S209. Act S209 is optional and can be omitted in some examples. For example, step S201 and step S209 can be omitted as desired.

[0087] Figure 3 A method of forming a package assembly is shown in accordance with some embodiments. Although this method is illustrated and / or described as a series of acts or events, it will be appreciated that the method is not limited by the illustrated ordering of acts or events. Thus, some acts may, in some embodiments, occur in different orders and / or concurrently with other acts or sub-acts. Also, in some embodiments, not all illustrated acts or events may be required. Additionally, some illustrated acts or events can be omitted in some embodiments.

[0088] At act S300, at least one integrated circuit structure is bonded to the interposer structure. Figure 3 Cross-sectional views are shown corresponding to some embodiments of act S300.

[0089] At act S302, a photonic structure is bonded to the interposer structure, the photonic structure being lateral to the at least one integrated circuit structure. Figure 4 Cross-sectional views are shown corresponding to some embodiments of act S302.

[0090] At act S303, a support structure is provided lateral to the photonic structure. Figure 5 Cross-sectional views are shown corresponding to some embodiments of act S303. Act S303 is optional and can be omitted in some examples.

[0091] At step S304, a semiconductor substrate is provided and placed on the photonic structure, wherein the semiconductor substrate has at least one recess and at least one transparent region at a side of the at least one recess. In some embodiments, the at least one transparent region penetrates the semiconductor substrate. In some embodiments, an optical lens is formed in the semiconductor substrate at a side of the at least one transparent region. In some embodiments, at least one optical component and at least one reflector are formed and embedded in at least one dielectric layer above the semiconductor substrate. In some embodiments, the method of forming the at least one recess comprises performing an etching process. Figures 5-11B 、 Figures 16-19B 、 ​ 、 ​ 、 ​ 、 ​ 、 ​ and ​ show different views corresponding to some embodiments of act S304.

[0092] At act S306, optical glue is dispensed into a space between the semiconductor substrate and the photonic structure. ​ shows cross-sectional views corresponding to some embodiments of act S306. In some embodiments, the optical glue comprises ultraviolet light-cured optical glue.

[0093] At step S308, the position of the semiconductor substrate is adjusted. ​ shows cross-sectional views corresponding to some embodiments of act S308. Act S308 is performed after act S306 to better optically couple the optical package and the underlying semiconductor package.

[0094] At step S310, light is shone through the at least one transparent region of the semiconductor substrate to cure the optical glue. ​ shows cross-sectional views corresponding to some embodiments of act S310. Act S310 is performed after act S308 to better secure the optical package and the underlying semiconductor package in place.

[0095] At step S311, a buffer layer is provided between the support structure and the semiconductor substrate. ​ shows cross-sectional views corresponding to some embodiments of act S311. Act S311 is optional and can be omitted in some examples. For example, step S303 and step S311 can be omitted as desired.

[0096] The following references ​ and ​ show packaged assemblies of the present application.

[0097] In some embodiments, the package assembly 10 includes a semiconductor package PK1, an optical package PK2, and an optical glue UGL1. The semiconductor package PK1 includes the interposer structure 100 and the overlying photonic structure 300. The optical package PK2 is disposed above the semiconductor package PK1. The optical package PK2 includes a substrate 400, a cap 900, and a fiber array unit 500 interposed between the substrate 400 and the cap 900, and has at least one light-transmissive region 402 in the substrate 400. The optical glue UGL1 is disposed between and in contact with the photonic structure 300 and the at least one light-transmissive region 402 of the substrate 400.

[0098] In some embodiments, the substrate 400 has two light-transmissive regions 402 and an optical lens 403 disposed between the two light-transmissive regions 402. In some embodiments, the photonic structure 300 of the semiconductor package PK1 has an optical lens 312 corresponding to the optical lens 403 of the substrate 400 of the optical package PK2. In some embodiments, the package assembly 10 further includes a support structure 800 disposed at a side of the semiconductor package PK1 and configured to support the optical package PK2.

[0099] In some embodiments, the package assembly 20 includes a semiconductor package PK1, an optical package PK3, and an optical glue UGL1. The semiconductor package PK1 includes the interposer structure 100 and the overlying photonic structure 300. The optical package PK3 is disposed above the semiconductor package PK1. The optical package PK3 includes a substrate 400', a cap 900, and a fiber array unit 500 interposed between the substrate 400' and the cap 900, and the substrate 400' is a glass substrate. The optical glue UGL1 is disposed between and in contact with the photonic structure 300 and the substrate 400'.

[0100] In some embodiments, the substrate 400' has at least one reflector R2' at a surface thereof, and the reflector R2' is laterally aligned with the fiber array unit 500. In some embodiments, the photonic structure 300 of the semiconductor package PK1 has an optical lens 312 corresponding to the reflector R' at the substrate 400' of the optical package PK3. In some embodiments, the package assembly 20 further includes a support structure 800 disposed at a side of the semiconductor package PK1 and configured to support the optical package PK3.

[0101] In summary, in the present application, the substrate with V-grooves for fixing the fiber array unit (FAU) is transparent in at least one portion thereof. Thus, after dispensing the ultraviolet (UV) curing optical glue in the space between the substrate and the underlying photonic structure, in the optical glue curing process, the ultraviolet light can pass through the transparent portion of the substrate, thereby increasing the adhesion between the substrate and the underlying photonic structure, and thus improving the FAU integration.

[0102] Many variations of the above examples are contemplated by embodiments of the present application. It should be understood that different embodiments can have different advantages, and that not all embodiments need necessarily exhibit all of the advantages. In some embodiments, the present application provides a method of forming a package assembly. The method includes the following operations. A semiconductor package is provided. The semiconductor package includes an interposer structure and an overlying photonic structure. An optical package is placed on the semiconductor package. The optical package includes a substrate, a cap, and a fiber array unit interposed between the substrate and the cap. Optical glue is dispensed into a space between the semiconductor package and the optical package. After the optical glue is dispensed, a position of the optical package is adjusted. Light is shined through the optical package to cure the optical glue.

[0103] According to some embodiments of the present application, a method of forming a package assembly includes the following operations. A semiconductor package is provided. The semiconductor package includes an interposer structure and an overlying photonic structure. An optical package is placed on the semiconductor package. The optical package includes a substrate, a cap, and a fiber array unit interposed between the substrate and the cap. Optical glue is dispensed into a space between the semiconductor package and the optical package. After the optical glue is dispensed, a position of the optical package is adjusted. Light is shined through the optical package to cure the optical glue.

[0104] According to some embodiments of the present application, a method of forming a package assembly includes the following operations. A semiconductor package is provided. The semiconductor package includes an interposer structure and an overlying photonic structure. An optical package is placed on the semiconductor package. The optical package includes a substrate, a cap, and a fiber array unit interposed between the substrate and the cap. Optical glue is dispensed into a space between the semiconductor package and the optical package. After the optical glue is dispensed, a position of the optical package is adjusted. Light is shined through the optical package to cure the optical glue.

[0105] According to some embodiments of the present application, a method of forming a package assembly includes the following operations. A semiconductor package is provided. The semiconductor package includes an interposer structure and an overlying photonic structure. An optical package is placed on the semiconductor package. The optical package includes a substrate, a cap, and a fiber array unit interposed between the substrate and the cap. Optical glue is dispensed into a space between the semiconductor package and the optical package. After the optical glue is dispensed, a position of the optical package is adjusted. Light is shined through the optical package to cure the optical glue.

[0106] Other features and processes can also be included. For example, test structures can be included to assist in verifying testing of 3D packages or 3DIC devices. Test structures can include, for example, test pads formed in redistribution layers or on substrates that allow for testing of 3D packages or 3DICs, use of probes and / or probe cards, etc. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0107] The foregoing overview of features of several embodiments enables a person of ordinary skill in the art to better understand aspects of the embodiments of the present application. Those skilled in the art should appreciate that they can easily use the embodiments of the present application as a basis for designing or modifying other processes and structures to accomplish the same goals and / or accomplish the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present application, and that they can make various changes, substitutions and alterations without departing from the spirit and scope of the embodiments of the present application.

Claims

1. A packaging assembly, characterized in that: include: at least one integrated circuit structure disposed on the interposer structure; a photonic structure disposed on the interposer structure, the photonic structure being located on a side of the at least one integrated circuit structure; a semiconductor substrate disposed on the photonic structure, wherein the semiconductor substrate has at least one groove and at least one transparent area located on a side of the at least one groove; as well as Optical adhesive is arranged in the space between the semiconductor substrate and the photonic structure.

2. The package assembly according to claim 1, wherein: The at least one transparent region penetrates the semiconductor substrate.

3. The package assembly according to claim 1, wherein: It also includes an optical lens, which is arranged on the side of the at least one transparent area in the semiconductor substrate.

4. The package assembly according to claim 1, wherein: Also included are at least one optical component and at least one reflector disposed in at least one dielectric layer above the semiconductor substrate.

5. The package assembly according to claim 1, wherein: Also included is an optical fiber array unit adhered to the at least one groove.

6. A packaging assembly, characterized in that: include: Semiconductor packages, including interposer structures and overlying photonic structures; an optical package disposed above the semiconductor package, wherein the optical package comprises a substrate, a cover, and an optical fiber array unit interposed between the substrate and the cover, and the substrate has at least one light-transmitting area therein; as well as The optical adhesive is disposed between the photon structure and the at least one light-transmitting region of the substrate and contacts the photon structure and the at least one light-transmitting region of the substrate.

7. The package assembly according to claim 6, wherein: The substrate has two light-transmitting areas and a first optical lens, and the first optical lens is arranged between the two light-transmitting areas.

8. The package assembly according to claim 7, wherein: The photonic structure of the semiconductor package has a second optical lens corresponding to the first optical lens of the substrate of the optical package.

9. The package assembly according to claim 6, wherein: A support structure is also included. The support structure is disposed on a side of the semiconductor package and is configured to support the optical package.

10. The package assembly according to claim 6, wherein: The substrate includes a glass substrate.

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