Test structure and semiconductor structure

Abstract

The utility model relates to a test structure and a semiconductor structure, a test pad and a test lead are connected with a metal layer and a metal plug to form at least one test circuit, and when open circuit defect detection is carried out on the metal layer or the metal plug, the test circuit formed by the metal layer or the metal plug is detected. Whether the open-circuit defect exists in the metal layer or the metal plug can be determined according to the test result, the open-circuit defect of the metal layer or the metal plug can be detected on line in the manufacturing process of the semiconductor chip, and meanwhile the defect position can be located according to the test result. The detection efficiency is improved, the detection cost is reduced, and the detection rate and the detection accuracy are improved.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit technology, and in particular to a test structure and a semiconductor structure. Background Technology

[0002] With the continuous development of integrated circuit technology, more devices will be integrated onto chips, and the geometric dimensions of these devices will continue to shrink. The conductor portion of the multilayer wiring in the back-end of line (BEOL) process of semiconductor chips consists of parallel metal layers and metal plugs connecting these layers. The miniaturization limits of these metal plugs are becoming increasingly apparent, and abnormalities in the metal plugs can lead to a series of electrical problems in the chip, such as open circuits, which can cause semiconductor malfunctions and ultimately result in yield losses. Therefore, inspecting for open circuit defects in the metal plugs is crucial for semiconductor chip development. Utility Model Content

[0003] Therefore, it is necessary to provide a test structure semiconductor structure to address the critical issue of open-circuit defects in metal plugs in existing technologies for semiconductor chips.

[0004] To achieve the above objectives, in a first aspect, the present invention provides a test structure, the test structure comprising:

[0005] The metal layers are stacked at intervals, with adjacent metal layers connected by metal plugs, and each metal layer has at least one corner at the connection point with the metal plug.

[0006] Multiple test pads, each of which is set independently;

[0007] Multiple test leads, wherein the test leads are connected to a metal layer and a test pad, or, the test leads are connected to a metal plug and a test pad;

[0008] Multiple test pads, multiple test leads, the metal layer, and the metal plug are connected together to form multiple test circuits;

[0009] The test circuit includes:

[0010] A first test line is connected to the metal layer and is used to test whether the metal layer has an open circuit defect.

[0011] and / or;

[0012] The second test line is connected to the metal layer and the metal plug connected thereto. The second test line is used to test whether there is an open circuit defect at the corner where the metal layer and the metal plug are connected.

[0013] Optionally, each of the metal layers is connected to two of the test pads via two test leads;

[0014] Each of the metal layers, together with the two test leads and the two test pads, constitutes the first test circuit.

[0015] Optionally, two adjacent metal layers are connected by a metal plug; each metal layer is connected to at least one test pad by at least one test wire;

[0016] The test wire and test pad connected to one of the two adjacent metal layers, the test wire and test pad connected to the other metal layer, the two adjacent metal layers and the metal plug together constitute the second test circuit.

[0017] Optionally, two adjacent metal layers are connected to the metal plug in an I-shaped, Z-shaped, or C-shaped structure.

[0018] Optionally, in the connected metal layer and the metal plug, the metal layer is connected to at least one of the test pads via at least one of the test leads, and the metal plug is connected to at least one of the test pads via at least one of the test leads;

[0019] The test leads and test pads connected by the metal layer and the test leads and test pads connected by the metal plug constitute the second test circuit.

[0020] Optionally, the metal layer and the metal plug are connected in a T-shaped, L-shaped or inverted L-shaped structure.

[0021] Optionally, the test lead includes:

[0022] The first conductive wire is disposed in the same layer as the metal layer.

[0023] A second conductor is connected to the end of the first conductor away from the metal layer. The second conductor is arranged along the direction of the stacking of multiple metal layers. The other end of the second conductor is connected to a test pad.

[0024] Optionally, the projections of each of the test leads on a plane parallel to the metal layer do not overlap.

[0025] Optionally, the test structure is located in the test area or surrounding area of ​​the semiconductor chip.

[0026] In a second aspect, this disclosure provides a semiconductor structure, including the test structure as described in the first aspect.

[0027] The semiconductor test structure of this utility model has the following unexpected technical effects:

[0028] The semiconductor test structure of this invention utilizes test pads and test leads to connect with metal layers and metal plugs to form at least one test line. When detecting open circuit defects in metal layers or metal plugs, the test line composed of metal layers or metal plugs is tested. Based on the test results, it can be determined whether there are open circuit defects in the metal layers or metal plugs. This allows for online detection of open circuit defects in metal layers or metal plugs during the semiconductor chip manufacturing process. At the same time, it can also locate the defect position based on the test results, thereby improving detection efficiency, reducing detection costs, and increasing the detection rate and accuracy. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the test structure provided in one embodiment.

[0031] Figure 2 This is a schematic diagram of the test structure provided in another embodiment.

[0032] Figure 3 This is a schematic diagram of the connection between the metal layer and the metal plug provided in one embodiment.

[0033] Figure 4 This is a schematic diagram of the connection between the metal layer and the metal plug provided in another embodiment.

[0034] Figure 5 This is a schematic diagram of the connection between the metal layer and the metal plug provided in another embodiment.

[0035] Figure 6 This is a schematic diagram of the connection between the metal layer and the metal plug provided in another embodiment.

[0036] Figure 7 This is a schematic diagram of the test structure provided in another embodiment.

[0037] Figure 8 for Figure 7 A top view of the provided test structure.

[0038] Explanation of reference numerals in the attached figures:

[0039] 10. Metal layer; 20. Test pad; 30. Test lead; 31. First lead; 32. Second lead; 321. Lead section; 322. Contact pad; 50. Metal plug;

[0040] 100, First test line; 200, Second test line; 110, First metal layer; 210, Second metal layer; 310, Third metal layer; 120, First test pad; 220, Second test pad; 320, Third test pad; 420, Fourth test pad; 520, Fifth test pad; 620, Sixth test pad; 130, First test lead; 230, Second test lead; 330, Third test lead; 430, Fourth test lead; 530, Fifth test lead; 630, Sixth test lead; 150, First metal plug; 250, Second metal plug. Detailed Implementation

[0041] To facilitate understanding of this utility model, a more complete description will be given below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of this utility model. However, this utility model can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of this utility model more thorough and complete.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0043] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0044] Failure analysis due to open-circuit defects in metal plugs is difficult to pinpoint precisely and suffers from low efficiency. The junction between the metal plug and metal layers is a particularly high-risk location for open-circuit defects. Currently, exploratory factor analysis (EFA) or probability of failure analysis (PFA) is mainly used to identify the high-risk locations of open-circuit defects layer by layer, but this often fails to pinpoint the exact failure location or results in low efficiency. Open-circuit defects in metal plugs are often hidden between multiple metal layers, making them highly concealed and difficult to observe directly. Furthermore, with the continuous development of semiconductor technology, the number of multilayer metal layers is constantly increasing, and the structure is becoming more complex, further increasing the difficulty of detecting and locating open-circuit defects.

[0045] In existing solutions, optical inspection equipment is typically used for online random sampling to detect open-circuit defects in metal plugs. However, this method suffers from low sampling rates, slow inspection speeds, and limited inspection coverage. Furthermore, light cannot penetrate metal, resulting in a low detection rate for open-circuit defects in metal plugs using optical inspection equipment. Other solutions employ the electrical properties of test patterns to monitor the online process; however, existing test patterns cannot accurately reflect even minor open-circuit issues in metal plugs.

[0046] If no open-circuit defects in the metal plugs are detected during online testing, the only way to identify defective chips is after the semiconductor chip fabrication is complete. This is followed by performance testing to screen for defects, then semiconductor failure analysis (FA) to detect process defects, and finally, feedback to the online process for improvement. However, performance testing of semiconductor chips after fabrication is very time-consuming, typically requiring 1.5 months to obtain results. This process is not only costly but also extremely inefficient.

[0047] This invention provides a test structure that forms a test circuit by setting test pads and test leads together with the metal layer and metal plug. This allows for the detection of open circuit defects in the metal layer and / or metal plug during the online manufacturing process of semiconductor chips. This achieves online detection of open circuit defects in the metal layer and / or metal plug, improving detection efficiency and shortening detection time.

[0048] According to an exemplary embodiment, this embodiment provides a test structure, such as... Figure 1 or Figure 2As shown, the test structure includes multiple metal layers 10, multiple test pads 20, and multiple test leads 30; the multiple metal layers 10 are stacked at intervals, and adjacent metal layers 10 are connected by metal plugs 50, with at least one corner at the connection between each metal layer 10 and the metal plug 50; the multiple test pads 20 are set independently; each test lead 30 connects a metal layer 10 to a test pad 20, or each test lead 30 connects a metal plug 50 to a test pad 20; the multiple test pads 20, the multiple test leads 30, the metal layers 10, and the metal plugs 50 are connected together to form multiple test lines. The test circuit includes a first test circuit 100 and / or a second test circuit 200; the first test circuit 100 is connected to the metal layer 10 and is used to test whether the metal layer 10 has an open circuit defect; the second test circuit 200 is connected to the metal layer 10 and the metal plug 50 connected thereto, and is used to test whether the corner at the connection between the metal layer 10 and the metal plug 50 has an open circuit defect.

[0049] The test structure of this utility model utilizes test pads 20 and test leads 30 to connect with the metal layer 10 and metal plug 50 to form at least one test line. When performing open circuit defect detection on the metal layer 10 or metal plug 50, the test line composed of the metal layer 10 or metal plug 50 is tested. Based on the test results, it can be determined whether the metal layer 10 or metal plug 50 has an open circuit defect. This allows for online detection of open circuit defects in the metal layer 10 or metal plug 50 during the semiconductor chip manufacturing process. At the same time, it can also locate the defect position based on the test results, thereby improving detection efficiency, reducing detection costs, and increasing the detection rate and accuracy.

[0050] The test structure of this utility model has a first test line 100 that can directly detect open circuit defects on the metal layer 10, ensuring the integrity of the electrical connection of the layer; the second test line 200 can detect open circuit defects at the vertical connection between the metal layer 10 and the metal plug 50, which can detect potential open circuit defects early in the circuit board manufacturing process, thereby avoiding more serious problems in subsequent production or use, and improving the overall reliability and performance of chip manufacturing.

[0051] In this test structure, a dielectric layer (not shown) is provided between two adjacent metal layers 10. A metal plug 50 penetrates the dielectric layer to connect the upper and lower metal layers 10. Multiple test pads 20 are located on the top layer of the test structure. In some examples, the top layer of the test structure is a metal layer 10, in which case the multiple test pads 20 are disposed on the same layer as the top metal layer 10. In other examples, the top layer of the test structure is a dielectric layer, in which case the multiple test pads 20 are disposed on the surface of the top dielectric layer.

[0052] It should be noted that when the top layer of the test structure is a dielectric layer, a metal plug 50 may be provided in the top dielectric layer, and the top metal layer 10 is connected to the metal plug 50 located thereon. In this example, the test structure may also include test leads 30 and test pads 20 connected to the top metal plug 50, which together form a test circuit, thus enabling the detection of open circuit defects between the top metal plug 50 and the top metal layer 10.

[0053] Multiple metal layers 10 are stacked at intervals and arranged in layers, with each metal layer 10 used for circuit connection or signal transmission. Metal plugs 50 are used to connect adjacent metal layers 10. Metal plugs 50 penetrate the dielectric layer vertically and connect the metal layers 10 to realize circuit interconnection between different metal layers 10.

[0054] Reference Figure 3 , Figure 4 , Figure 5 , Figure 6 There is at least one corner at the connection between each metal layer 10 and the metal plug 50. The corner at the connection between the metal layer 10 and the metal plug 50 is prone to open circuit defects.

[0055] For example, when performing open circuit defect detection, a voltage is applied to one test pad 20 and the test current of the other test pad 20 is detected. This determines the resistance value of the test circuit between the two test pads 20. Based on the resistance value, it can be determined whether there is an open circuit defect at the connection corner between the metal plug 50 and the metal layer 10 between the two test pads 20.

[0056] In some embodiments, refer to Figure 2 , Figure 7 , Figure 8 Each metal layer 10 is connected to two test pads 20 via two test leads 30. Each metal layer 10 and the two test pads 20 together form the first test circuit 100 via the test leads 30.

[0057] For example, the first metal layer 110 is connected to a first test lead 130 and a sixth test lead 630 at its two ends, respectively. The first test lead 130 is connected to a first test pad 120, and the sixth test lead 630 is connected to a sixth test pad 620. The first metal layer 110, the first test lead 130, the first test pad 120, the sixth test lead 630, and the sixth test pad 620 are collectively connected to form a first test circuit 100. By applying voltage or current to the first test pad 120 and measuring the response of the sixth test pad 620, it is possible to detect whether there is a discontinuous electrical path in the first metal layer 110.

[0058] The second metal layer 210 is connected to a second test lead 230 and a fifth test lead 530 at its two ends, respectively. The second test lead 230 is connected to the second test pad 220, and the fifth test lead 530 is connected to the fifth test pad 520. The second metal layer 210, the second test lead 230, the fifth test lead 530, the second test pad 220, and the fifth test pad 520 are connected together to form a first test circuit 100 for detecting whether the second metal layer 210 has an open circuit defect.

[0059] In some embodiments, refer to Figure 2 , Figure 7 , Figure 8 Two adjacent metal layers 10 are connected by a metal plug 50; each metal layer 10 is connected to at least one test pad 20 by at least one test wire 30; the test wire 30 and test pad 20 connected to one metal layer 10, the test wire 30 and test pad 20 connected to the other metal layer 10, the two adjacent metal layers 10 and the metal plug 50 together constitute the second test circuit 200.

[0060] This embodiment applies to structures where two metal layers 10 are connected in an I-shape, Z-shape, or C-shape by a metal plug 50. It is understood that the test structure of this embodiment can be used not only to test structures where the metal layers 10 are connected to the metal plug 50, but also to test other conductor structures connected in an I-shape, Z-shape, or C-shape.

[0061] For example, a first metal layer 110 and a second metal layer 210 are spaced apart and connected by a first metal plug 150. The first metal layer 110 is connected to the first test pad 120 only through a first test lead 130. The second metal layer 210 is connected to the second test pad 220 only through a second test lead 230.

[0062] The first test lead 130, the first test pad 120, the first metal layer 110, the first metal plug 150, the second metal layer 210, the second test lead 230, and the second test pad 220 are connected together to form a second test circuit 200. The second test circuit 200 is used to detect whether there is an open circuit defect at the corner where the first metal layer 110, the second metal layer 210, and the first metal plug 150 are connected. By applying voltage or current to the first test pad 120 and measuring the response of the second test pad 220, it is possible to detect whether there is a discontinuous electrical connection between the first metal layer 110, the second metal layer 210, and the first metal plug 150, and thus determine whether there is an open circuit defect.

[0063] It is understood that in other examples, the first metal layer 110 and the second metal layer 210 may both be connected to the two test pads 20. The first metal layer 110 is also connected to the sixth test pad 620 via the sixth test lead 630, and the second metal layer 210 is also connected to the fifth test pad 520 via the fifth test lead 530.

[0064] Thus, the sixth test lead 630, the sixth test pad 620, the fifth test lead 530, the fifth test pad 520, the first metal layer 110, the first metal plug 150, and the second metal layer 210 are also connected to form a second test line 200.

[0065] The first test lead 130, the first test pad 120, the fifth test lead 530, the fifth test pad 520, the first metal layer 110, the first metal plug 150, and the second metal layer 210 are also connected to form a second test line 200.

[0066] The sixth test lead 630, the sixth test pad 620, the second test lead 230, the second test pad 220, the first metal layer 110, the first metal plug 150, and the second metal layer 210 are also connected to form a second test line 200.

[0067] In some embodiments, in the connected metal layer 10 and metal plug 50, the metal layer 10 is connected to at least one test pad 20 through at least one test lead 30, and the metal plug 50 is connected to at least one test pad 20 through at least one test lead 30; the test lead 30 and test pad 20 connected to the metal layer 10 and the test lead 30 and test pad 20 connected to the metal plug 50 constitute a second test line 200.

[0068] This embodiment applies to a structure in which a metal layer 10 and a metal plug 50 are connected in a T-shape, L-shape, or inverted L-shape.

[0069] For example, metal layer 10 is connected to a test pad 20 via a test lead 30, and the end of metal plug 50 away from the test lead 30 is connected to another test pad 20 via another test lead 30, forming a second test line 200.

[0070] In some embodiments, the test lead 30 may consist only of a first lead 31 disposed in the same layer as the metal layer 10, and the metal layer 10 is directly connected to the test pad 20 through the first lead 31.

[0071] In some embodiments, refer to Figure 1As shown, the test lead 30 includes a first lead 31 and a second lead 32; the first lead 31 is connected to the metal layer 10; the second lead 32 is connected to the end of the first lead 31 away from the metal layer 10, the second lead 32 is arranged along the direction of the stacking of multiple metal layers 10, and the other end of the second lead 32 is connected to a test pad 20.

[0072] Specifically, along the stacking direction of the multilayer metal layers 10, the test leads 30 connected to the top metal layer 10 include only a first lead 31, and the top metal layer 10 is directly connected to the test pad 20 through the first lead 31. The test leads 30 connected to other metal layers 10 below the top metal layer 10 include a first lead 31 and a second lead 32, and the first lead 31 is connected to the test pad 20 through the second lead 32.

[0073] In some embodiments, refer to Figure 7 As shown, the second conductor 32 includes conductor portions 321 spaced apart, and adjacent conductor portions 321 are connected by contact pads 322.

[0074] In some embodiments, refer to Figure 1 or Figure 2 As shown, the first conductors 31 of each test conductor 30 are arranged in parallel, and the second conductors 32 of each test conductor 30 are arranged in parallel. This reduces the wiring difficulty of each test conductor 30, reduces the manufacturing difficulty of the test structure, and also helps to reduce the size occupied by the test structure.

[0075] In some embodiments, refer to Figure 8 The projection of the test wires 30 connected to the top metal layer 10 onto a plane parallel to the metal layer 10 is a straight line; the projections of each test wire 30 onto the plane parallel to the metal layer 10 have no overlapping parts. In this way, the test wires 30 are staggered, which facilitates the setting and layout of the test wires 30 and avoids interference between the test wires 30 when there are a large number of test wires 30.

[0076] In some embodiments, the test structure is located in the test area or surrounding area of ​​the semiconductor chip.

[0077] The test structure of this utility model will now be described with reference to an exemplary embodiment.

[0078] This exemplary embodiment provides a test structure, referring to... Figure 7 , Figure 8As shown, the test structure is located in the test area of ​​the semiconductor chip. The test structure includes a first metal layer 110, a second metal layer 210, and a third metal layer 310 stacked sequentially at intervals. A dielectric layer is provided between the first metal layer 110 and the second metal layer 210, and between the second metal layer 210 and the third metal layer 310. A first metal plug 150 is provided in the dielectric layer between the first metal layer 110 and the second metal layer 210, and the first metal layer 110 and the second metal layer 210 are connected through the first metal plug 150. A second metal plug 250 is provided in the dielectric layer between the second metal layer 210 and the third metal layer 310, and the second metal layer 210 and the third metal layer 310 are connected through the second metal plug 250.

[0079] The test structure includes a first test pad 120 and a first test wire 130, a second test pad 220 and a second test wire 230, a third test pad 320 and a third test wire 330, a fourth test pad 420 and a fourth test wire 430, a fifth test pad 520 and a fifth test wire 530, and a sixth test pad 620 and a sixth test wire 630, all connected in a mating manner.

[0080] The first test pad 120 to the sixth test pad 620 are all disposed on the same layer as the third metal layer 310. The first test lead 130 and the sixth test lead 630 are both connected to the first metal layer 110, and are located on both sides of the first metal layer 110. The second test lead 230 and the fifth test lead 530 are both connected to the second metal layer 210, and are located on both sides of the first metal layer 110. The third test lead 330 and the fourth test lead 430 are both connected to the third metal layer 310, and are located on both sides of the first metal layer 110.

[0081] The first test pad 120 to the sixth test pad 620, the first test lead 130 to the sixth test lead 630, together with the first metal layer 110, the second metal layer 210, the third metal layer 310, the first metal plug 150, and the second metal plug 250, are connected to form a test circuit.

[0082] For example, a voltage U1 is applied to the third test pad 320, and no voltage is applied to the fourth test pad 420. The current I1 of the fourth test pad 420 is detected, and the resistance R1 of the test circuit between the third test pad 320 and the fourth test pad 420 is obtained as U1 / I1. If the resistance R1 < 1E4Ω, it can be considered that the third metal layer 310 has no open circuit defect. If R1 ≥ 1E4Ω, it can be considered that the third metal layer 310 has an open circuit defect.

[0083] Apply voltage U1 to the third test pad 320 and no voltage to the fifth test pad 520. Detect the current I2 of the fifth test pad 520 and obtain the resistance R2 = U1 / I2 of the test circuit between the third test pad 320 and the fifth test pad 520. If the resistance R2 < 1E4Ω, it can be considered that there is no open circuit defect between the third metal layer 310 and the second metal layer 210. If R2 ≥ 1E7Ω, it can be considered that there is an open circuit defect between the third metal layer 310 and the second metal layer 210.

[0084] Furthermore, a voltage U1 is applied to the second test pad 220, while no voltage is applied to the fifth test pad 520. The current I3 of the fifth test pad 520 is detected, and the resistance R3 = U1 / I3 of the test circuit between the second test pad 220 and the fifth test pad 520 is obtained. If the resistance R3 < 1E4Ω, then the second metal layer 210 is not open-circuited, and the open circuit occurs in the second metal plug 250. In this way, electrical failure detection (EFA) can be used to accurately locate the location of the open circuit defect in the second metal plug 250.

[0085] A voltage U1 is applied to the first test pad 120, and no voltage is applied to the fourth test pad 420. The current I4 of the fourth test pad 420 is detected, and the resistance R4 = U1 / I4 of the test circuit between the first test pad 120 and the fourth test pad 420 is obtained. If the resistance R4 > 1E8Ω, then there is an open circuit defect in the circuit between the first metal layer 110 and the third metal layer 310. The previous test action can be repeated to determine the location of the failure caused by the open circuit.

[0086] In other embodiments, the test structure can also be used to test structures with more stacked metal layers 10, such as structures with four or five stacked metal layers 10. This can be achieved by designing the layout of the test leads 30 connecting each metal layer 10 so that the test leads 30 are staggered.

[0087] According to an exemplary embodiment, this embodiment provides a semiconductor structure, including the test structure as described in the above embodiment. The semiconductor structure of this embodiment can be a semiconductor chip.

[0088] The semiconductor structure in this embodiment can incorporate this test structure during the manufacturing design phase. This test structure can be used to monitor defects in the semiconductor structure during the manufacturing process. It can capture and feedback defect information in real time on the production line and make corrections, which can effectively improve product quality and reduce production costs.

[0089] The test structure and semiconductor structure of this utility model have the following unexpected technical effects:

[0090] The test structure and semiconductor structure of this utility model are connected together by multiple test pads, multiple test leads, metal layers, and metal plugs to form a test circuit. When detecting open circuit defects in the metal plug, the test circuit composed of the metal plug is tested. Based on the test results, it can be determined whether there is an open circuit defect in the metal plug. This allows for online detection of open circuit defects in the metal plug during the semiconductor chip manufacturing process. At the same time, it can also locate the defect location based on the test results, thereby improving detection efficiency, reducing detection costs, and increasing the detection rate and accuracy.

[0091] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0092] The embodiments described above are merely illustrative of several implementations of this utility model, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.

Claims

1. A test structure, characterized in that, The test structure includes: Multiple metal layers (10) are stacked at intervals, and adjacent metal layers (10) are connected by metal plugs (50). There is at least one corner at the connection between each metal layer (10) and the metal plug (50). Multiple test pads (20), each of which is set independently; Multiple test leads (30) are connected to a metal layer (10) and a test pad (20), or the test leads (30) are connected to a metal plug (50) and a test pad (20). Multiple test pads (20), multiple test leads (30), the metal layer (10), and the metal plug (50) are connected together to form multiple test lines; The test circuit includes: The first test line (100) is connected to the metal layer (10) and is used to test whether the metal layer (10) has an open circuit defect. and / or; The second test line (200) is connected to the metal layer (10) and the metal plug (50) connected thereto. The second test line (200) is used to test whether there is an open circuit defect at the corner of the connection between the metal layer (10) and the metal plug (50).

2. The test structure according to claim 1, characterized in that, Each of the metal layers (10) is connected to two test pads (20) via two test wires (30); Each of the metal layers (10), together with the two test wires (30) and the two test pads (20), constitutes the first test line (100).

3. The test structure according to claim 1, characterized in that, Two adjacent metal layers (10) are connected by a metal plug (50); each metal layer (10) is connected to at least one test pad (20) by at least one test wire (30). The test wire (30) and the test pad (20) connected by one of the two adjacent metal layers (10), the test wire (30) and the test pad (20) connected by the other metal layer (10), the two adjacent metal layers (10) and the metal plug (50) together constitute the second test circuit (200).

4. The test structure according to claim 3, characterized in that, The two adjacent metal layers (10) are connected to the metal plug (50) in an I-shaped, Z-shaped or C-shaped structure.

5. The test structure according to claim 1, characterized in that, In the connected metal layer (10) and the metal plug (50), the metal layer (10) is connected to at least one of the test pads (20) via at least one of the test leads (30), and the metal plug (50) is connected to at least one of the test pads (20) via at least one of the test leads (30). The test wires (30) and test pads (20) connected by the metal layer (10) and the test wires (30) and test pads (20) connected by the metal plug (50) constitute the second test line (200).

6. The test structure according to claim 5, characterized in that, The metal layer (10) and the metal plug (50) are connected to form a T-shaped, L-shaped or inverted L-shaped structure.

7. The test structure according to claim 1, characterized in that, The test lead (30) includes: The first conductive wire (31) is disposed in the same layer as the metal layer (10). The second conductor (32) is connected to one end of the first conductor (31) away from the metal layer (10), the second conductor (32) is arranged along the direction of the stacking of multiple metal layers (10), and the other end of the second conductor (32) is connected to a test pad (20).

8. The test structure according to any one of claims 1-7, characterized in that, The projections of each of the test leads (30) onto a plane parallel to the metal layer (10) have no overlapping portions.

9. The test structure according to any one of claims 1-7, characterized in that, The test structure is located in the test area or surrounding area of ​​the semiconductor chip.

10. A semiconductor structure, characterized in that, Includes the test structure as described in any one of claims 1-9.

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