Pixel

Abstract

The utility model relates to a pixel. In various embodiments, the pixel includes a substrate configured to generate one or more carriers in response to an incident light beam; a first vertical gate and a second vertical gate disposed inside the substrate; a first vertical gate input electrically coupled to the first vertical gate and configured to receive a first gate control signal; and a second vertical gate input electrically coupled to the second vertical gate and configured to receive a second gate control signal. In various embodiments, the first vertical gate and the second vertical gate are configured to direct the one or more charge carriers to the first sensing node or the second sensing node using a first gate control signal and a second gate control signal.

Description

TECHNICAL FIELD

[0001] Example embodiments of the present disclosure relate generally to light detection, and more specifically to light detection pixels. BACKGROUND

[0002] Light detection pixels are used in a variety of technologies, such as in three-dimensional (3D) and two-dimensional (2D) imaging systems. New developments in technologies that use light detection pixels require the pixels to have improved performance. The Applicant has recognized a number of technical challenges and difficulties associated with light detection pixels. Through the efforts, ingenuity, and innovation applied, the Applicant has solved problems associated with light detection pixels by developing solutions embodied in the present disclosure, which will be described in detail below. SUMMARY

[0003] Various embodiments described herein relate to systems, apparatuses, products, and methods for light detection. In various embodiments, a pixel for detecting light is provided. In various embodiments, the pixel includes a substrate configured to generate one or more carriers in response to an incident light beam; a first vertical gate and a second vertical gate disposed inside the substrate, wherein the first vertical gate and the second vertical gate are configured to direct the one or more carriers to a first sensing node or a second sensing node; a first vertical gate input electrically coupled to the first vertical gate and configured to receive a first gate control signal; and a second vertical gate input electrically coupled to the second vertical gate and configured to receive a second gate control signal, wherein the first vertical gate and the second vertical gate are configured to direct the one or more carriers to the first sensing node or the second sensing node using the first gate control signal and the second gate control signal.

[0004] In various embodiments, the first vertical gate is configured to activate using the first gate control signal and, when activated, direct the one or more carriers to the first sensing node; and the second vertical gate is configured to activate using the second gate control signal and, when activated, direct the one or more carriers to the second sensing node.

[0005] In various embodiments, the first vertical gate is deactivated when the second vertical gate is activated; and the second vertical gate is deactivated when the first vertical gate is activated. In various embodiments, the first gate control signal and the second gate control signal include periodic waveforms and are complementary to each other.

[0006] In various embodiments, the pixel includes: a third vertical gate disposed inside the substrate; a fourth vertical gate disposed inside the substrate, wherein the first vertical gate, the second vertical gate, the third vertical gate, and the fourth vertical gate are configured to direct the one or more carriers to the first sensing node or the second sensing node; a third gate input electrically coupled to the third vertical gate and configured to receive a third gate control signal; and a fourth gate input electrically coupled to the fourth vertical gate and configured to receive a fourth gate control signal, wherein the first vertical gate, the second vertical gate, the third vertical gate, and the fourth vertical gate are configured to direct the one or more carriers to the first sensing node or the second sensing node with the first gate control signal, the second gate control signal, the third gate control signal, and the fourth gate control signal.

[0007] In various embodiments, the pixel further includes: a first deep isolation trench on a first side of the substrate; and a second deep isolation trench on a second side of the substrate, wherein the first deep isolation trench and the second deep isolation trench are configured to create a pinning potential at the substrate to deplete the substrate.

[0008] In various embodiments, the first vertical gate and the second vertical gate are configured to be activated alternately with the first gate control signal and the second gate control signal, wherein at a given time the first gate control signal is the complement of the second gate control signal, and wherein the pixel is configured to determine an indirect time of flight (iToF).

[0009] In various embodiments, the first vertical gate and the second vertical gate are configured to be deactivated simultaneously for a first time period with the first gate control signal and the second gate control signal, and for a second time period the first vertical gate or the second vertical gate is activated, and wherein the pixel is configured to provide two-dimensional imaging.

[0010] In various embodiments, a pixel is provided. The pixel can include: a substrate configured to generate one or more carriers in response to an incident light beam; a first vertical gate and a second vertical gate disposed inside the substrate, wherein the first vertical gate and the second vertical gate are configured to direct the one or more carriers to a first capacitor or a second capacitor; a first vertical gate input electrically coupled to the first vertical gate and configured to receive a first gate control signal; and a second vertical gate input electrically coupled to the second vertical gate and configured to receive a second gate control signal, wherein the first vertical gate and the second vertical gate are configured to direct the one or more carriers to the first capacitor or the second capacitor with the first gate control signal and the second gate control signal.

[0011] In various embodiments, the first vertical gate is configured to be activated with the first gate control signal and, when activated, direct the one or more carriers to the first capacitor; and the second vertical gate is configured to be activated with the second gate control signal and, when activated, direct the one or more carriers to the second capacitor.

[0012] In various embodiments, the first vertical gate is deactivated when the second vertical gate is activated; and the second vertical gate is deactivated when the first vertical gate is activated. In various embodiments, the first gate control signal and the second gate control signal comprise periodic waveforms and are complementary to each other.

[0013] According to various embodiments of the present disclosure, a method is provided. The method can include: deploying a first vertical gate and a second vertical gate inside a substrate, wherein the first vertical gate and the second vertical gate are configured to direct one or more carriers to a first sensing node or a second sensing node, wherein the one or more carriers are generated inside the substrate in response to an incident light beam; configuring a first vertical gate input to receive a first gate control signal, wherein the first vertical gate input is electrically coupled to the first vertical gate; and configuring a second vertical gate input to receive a second gate control signal, wherein the second vertical gate input is electrically coupled to the second vertical gate, wherein the first vertical gate and the second vertical gate are configured to direct the one or more carriers to the first sensing node or the second sensing node with the first gate control signal and the second gate control signal.

[0014] In various embodiments, the method includes: configuring the first vertical gate to be activated with the first gate control signal and, when the first vertical gate is activated, direct the one or more carriers to the first sensing node; and configuring the second vertical gate to be activated with the second gate control signal and, when the second vertical gate is activated, direct the one or more carriers to the second sensing node.

[0015] In various embodiments, the method includes: configuring the first vertical gate to be deactivated when the second vertical gate is activated; and configuring the second vertical gate to be deactivated when the first vertical gate is activated. In various embodiments, the first gate control signal and the second gate control signal comprise periodic waveforms and are complementary to each other.

[0016] In various embodiments, the method includes deploying a third vertical gate inside the substrate; deploying a fourth vertical gate inside the substrate, wherein the first vertical gate, the second vertical gate, and the fourth vertical gate are configured to direct the one or more carriers to the first sensing node or the second sensing node; electrically coupling a third gate input to the third vertical gate to receive a third gate control signal; electrically coupling a fourth gate input to the fourth vertical gate to receive a fourth gate control signal; and directing the one or more carriers to the first sensing node or the second sensing node with the first gate control signal, the second gate control signal, the third gate control signal, or the fourth gate control signal.

[0017] In various embodiments, the method includes deploying a first deep isolation trench on a first side of the substrate; and deploying a second deep isolation trench on a second side of the substrate, wherein the first deep isolation trench and the second deep isolation trench are configured to create a pinning potential at the substrate to deplete the substrate.

[0018] In various embodiments, the method includes alternating activating the first vertical gate and the second vertical gate with the first gate control signal and the second gate control signal, wherein at a given time, the first gate control signal is the complement of the second gate control signal.

[0019] In various embodiments, the method includes electrically coupling the first sensing node with a first supplemental capacitor; electrically coupling the second sensing node with a second supplemental capacitor; and configuring the first supplemental capacitor and the second supplemental capacitor to determine an indirect time-of-flight or a two-dimensional density image with a first charge value of the first supplemental capacitor and a second charge value of the second supplemental capacitor.

[0020] The above summary of the disclosure is only intended to summarize some example embodiments and to provide a basic understanding of some aspects of the disclosure. Thus, it should be appreciated that the above-described embodiments are merely examples and should not be construed as limiting the scope or spirit of the disclosure in any way. It should also be appreciated that the scope of the disclosure encompasses many potential embodiments in addition to those summarized here, some of which will be further described below. BRIEF DESCRIPTION OF DRAWINGS

[0021] Certain example embodiments of the disclosure have been generally described above, reference will now be made to the drawings, which are not necessarily drawn to scale, wherein:

[0022] Figure 1 is a schematic diagram illustrating an iToF determination system.

[0023] Figure 2 is a schematic diagram illustrating a pixel.

[0024] Figure 3is a schematic diagram illustrating a pixel according to various embodiments of the present disclosure.

[0025] Figure 4 is a schematic diagram illustrating operation of a pixel according to various embodiments of the present disclosure.

[0026] Figure 5A is a schematic diagram illustrating a pixel according to various embodiments of the present disclosure.

[0027] Figure 5B is a schematic diagram illustrating a pixel according to various embodiments of the present disclosure.

[0028] Figure 5C is a schematic diagram illustrating a pixel according to various embodiments of the present disclosure.

[0029] Figure 5D is a schematic diagram illustrating a pixel according to various embodiments of the present disclosure.

[0030] Figure 5E is a schematic diagram illustrating a pixel according to various embodiments of the present disclosure.

[0031] Figure 5F is a schematic diagram illustrating a pixel according to various embodiments of the present disclosure.

[0032] Figure 6 is a flowchart illustrating a method according to various embodiments of the present disclosure.

[0033] Figure 7 is a flowchart illustrating a method according to various embodiments of the present disclosure.

[0034] Figure 8 illustrates an example computing device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0035] Embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings, in which some, but not all, embodiments of the present disclosure are shown. Indeed, the present disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like reference numerals refer to like elements throughout.

[0036] The phrases “in one embodiment,” “according to one embodiment,” “in some embodiments,” “in various embodiments,” and the like generally mean the particular feature, structure, or characteristic following the phrase is included in at least one embodiment of the present disclosure, and can include more than one embodiment of the present disclosure, important though such phrases can not necessarily refer to the same embodiment.

[0037] The words “example” or “exemplary” are used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

[0038] If the specification states a component or feature “may,” “could,” “should,” “would,” “can,” “likely,” “possibly,” “normally,” “optionally,” “for example,” “often,” “for instance,” or “maybe” (or other similar language) be included or have a characteristic, that particular component or feature is not required to be included or to have that characteristic. In some embodiments, such a component or feature can be optionally included, or can be excluded.

[0039] The terms “electrically coupled,” “in communication,” “in electronic communication,” or “connected” in the present disclosure refer to two or more elements or components being connected by wired means and / or wireless means such that signals, voltage / current, data, and / or information can be sent to and / or received from the elements or components.

[0040] Various embodiments of the present disclosure are directed to improved systems, apparatuses, products, and methods for light detection, for example, by using an improved light detection system. In various embodiments, the light detection system can be used in 3D imaging, for example, using indirect time-of-flight (iToF) measurements.

[0041] In 3D imaging, distances to objects can be determined. One method of measuring distances to objects is time-of-flight (ToF) measurement. In a ToF system, the time for a light beam to travel from a transmitter to an object and back to a detector is measured. Using the speed of light and the travel time, the distance to the object can be measured.

[0042] In an indirect time-of-flight (iToF) system, the distance to an object is indirectly measured using a phase shift of a received light beam relative to a transmitted light beam.

[0043] Referring now to Figure 1 , a schematic diagram illustrating an indirect time-of-flight (iToF) measurement system 100 is provided. The iToF measurement system 100 includes a transmitter 102 configured to transmit a light beam 104 having, for example, a sinusoidal wave 106. In an example, the transmitted light beam 104 can be an intensity-modulated continuous wave. The transmitted light beam can reflect off an object 108. The reflected light beam 110 will be detected by a pixel 112. In various embodiments, the pixel 112 is a light detection pixel.

[0044] To determine the phase shift between the reflected light beam and the transmitted light beam, the pixel 112 can reconstruct its sinusoidal wave after detecting the reflected light beam 110.

[0045] To reconstruct a sinusoidal wave, the pixel 112 samples the detected light beam. When the light beam is received by the pixel 112, the pixel generates electron carriers (e) and holes (h). The carriers are sampled using switches SI and S2 and directed to the corresponding sense node SNi or SN2 for detection.

[0046] The carriers detected at the sense nodes SNi and SN2 charge the corresponding capacitors. For example, the sense node SNi charges the first capacitor 122 and the sense node SN2 charges the second capacitor 124. The controller 114 can compare the charge stored at the capacitors to reconstruct the phase value of the reflected light beam.

[0047] The sense nodes SNi and SN2 can be floating nodes, and the voltage of the sense nodes can need to be reset after each detection cycle to prepare for another charge acquisition and measurement. The switches 116 and 118 can use a reset signal to reset the voltage to V DC .

[0048] In some examples, the emitted light beam can be in the near-infrared (NIR) wavelength range with a wavelength range of 800 nm - 1100 nm, for example 940 nm. In some examples, the emitted light beam can be in the short-wave infrared (SWIR) wavelength range with a wavelength range of 1100 nm - 3000 nm. Accordingly, suitable materials in the pixel 112 can be used to detect light beams in the corresponding wavelength range. For example, silicon has good absorbance in the NIR wavelength range and can be used in the pixel 112 for iToF and other imaging systems. Other materials such as Ge, InGaAs can be used in the SWIR wavelength range.

[0049] Reference is now made to Figure 2 , providing a schematic diagram illustrating a pixel 200 according to various embodiments that have been used. The pixel 200 can include a substrate 202. In various embodiments, the substrate 202 is a silicon substrate. The pixel 200 includes a P-N junction 208 at the center of the pixel between a first planar gate 204 and a second planar gate 206. The P-N junction 208 can be created, for example, by an N well 210. The N well 210 can be an N implant region approximately at the center of the pixel 200.

[0050] When a light beam is incident on the substrate 202, carriers are generated in the substrate 202. The P-N junction 208 creates an electrostatic potential gradient that transfers the carriers to the top of the pixel. By switching between activation of the first planar gate 204 and the second planar gate 206, the charge is driven to either a first sense node 212 or a second sense node 214. The first and second planar nodes can use an AC signal V AC is activated.

[0051] The first and second sensing nodes can be electrically coupled to an N+ region of the semiconductor. The N+ region can have a high concentration of N-type impurity dopants. In an example, the N+ region can reduce contact resistance with the sensing nodes. For example, the N+ region can be an N fuse diffusion made with arsenic or phosphorous doping.

[0052] Referring now to Figure 3 A schematic diagram of a pixel 300 is provided, which illustrates various embodiments according to the present disclosure. In various embodiments, the pixel 300 includes a substrate 302. The substrate 302 can be configured to generate one or more carriers in response to an incident light beam (e.g., reflected light beam 110). In various embodiments, the pixel 300 includes a transparent layer 322 at a surface of the substrate 302 at which the substrate is configured to absorb the incident light beam. The transparent layer 322 can include any of an anti-reflective layer, a lens, a microlens array, etc.

[0053] In various embodiments, the pixel 300 includes a first vertical gate 304 and a second vertical gate 306 disposed inside the substrate. In various embodiments, the first vertical gate 304 and the second vertical gate 306 are implanted in the substrate 302. The first vertical gate 304 and the second vertical gate 306 can be deep trenches disposed inside the substrate 302.

[0054] In an example embodiment, the height of the substrate can be between 5 microns - 12 microns when operating in the NIR wavelength range. In an example embodiment, the depth of the first vertical gate 304 and the second vertical gate 306 can be between 0.3 microns and 2 microns, e.g., 1 micron. In an example embodiment, the height of the substrate can be smaller if a different material than silicon is used with higher absorption. In various embodiments, the height of a general vertical gate can be between about 5% to 30% of the height of the substrate.

[0055] In various embodiments, the first and second vertical gates are used for efficient transfer of carriers from the substrate 302 to the first sensing node 310 and the second sensing node 312.

[0056] In various embodiments, the first vertical gate 304 and the second vertical gate 306 are activated using a first gate control signal applied to a first vertical gate input 314 and a second gate control signal applied to a second vertical gate input 316. In various embodiments, the first and second vertical gates are configured to direct one or more carriers to the first sensing node 310 or the second sensing node 312 using the first and second gate control signals.

[0057] For example, by alternating activation of the first and second vertical gates, an electric potential is generated in the substrate 302, and one or more carriers are directed from a lower region of the substrate 302 to a higher region, e.g., a region 308 of the substrate closer to the vertical gates. In various embodiments, the electric potential in the region 308 is also generated due to the appropriate doping profile of the substrate 302 and due to the electric potential applied to the deep isolation trenches 324 and 326, as further described below. In various embodiments, when the first vertical gate 304 is activated, carriers are directed in a direction toward the first vertical gate and the first sense node. When the second vertical gate 306 is activated, carriers are directed in a direction toward the second vertical gate and the second sense node.

[0058] In example embodiments, the pixel 300 directs carriers to the corresponding sense node without the need for a P-N junction created by a deep N implant, e.g., as described with respect to the pixel 200. By not requiring an N well, various embodiments provide for a reduction in process variation in manufacturing the pixel, while improving the transfer efficiency of carriers to the sense node. Reducing process variation in manufacturing the pixel can reduce mismatches and / or inconsistencies between individual pixels in a pixel array or matrix.

[0059] In various embodiments, the first vertical gate is deactivated when the second vertical gate is activated, and the second vertical gate is deactivated when the first vertical gate is activated. The vertical gates can be activated using periodic signals generated by a voltage and / or current source 320. The source 320 can generate a first gate control signal and a second gate control signal. The first and second control signals can have periodic waveforms and can be complementary to each other. For example, at a given time, the first gate control signal applied to the first vertical gate input can have a high value, while the second gate control signal applied to the second vertical gate input will have a low value.

[0060] In example embodiments, the pixel 300 provides a more homogenous electrostatic potential in the substrate, with a gradient toward the vertical gates, and then toward the corresponding sense node when each vertical gate is activated, e.g., as compared to the pixel 200.

[0061] In various embodiments, the first and second sense nodes are floating junctions, and the voltage they produce will vary as carriers are directed to each sense node. This can be because each sense node has an intrinsic capacitance, and the charge of the intrinsic capacitance and its corresponding voltage can change when carriers are transferred to the corresponding sense node. In various embodiments, the intrinsic capacitance of each sense node is supplemented using an external capacitance. In various embodiments, when the pixel 300 is used as an iToF pixel, the charge accumulated on each sense node and / or a supplemental capacitor electrically coupled in parallel with the sense node is measured to make iToF determinations, as described, e.g., with reference to Figure 1 the pixel 200.

[0062] In various embodiments, the pixel alternates between charge collection at the first and second sense nodes by switching between activation of the vertical gates. By doing so over a period of time, the controller 114 can integrate the first charge collection on the first sense node and the second charge collection on the second sense node. Using the integrated value, a reconstruction of the phase shift suffered by the light beam when reflected from the object and received by the pixel is determined.

[0063] In various embodiments, by faster alternation between charge collection at different sense nodes, the pixel 300 can provide a more accurate measurement of the phase shift of the reflected signal for iToF determination. In example embodiments, the pixel 300 enables activation and deactivation of the vertical gates at a higher frequency, compared to the pixel 200 for example, thus enabling faster alternation of charge collection at the first and second sense nodes for more accurate iToF measurement.

[0064] In various embodiments, by deep etching the vertical gates in the substrate in the pixel 300, a higher driving potential is created in the substrate volume, thus more efficiently directing the carriers to the sense nodes with lower amplitude requirements for the gate control signals.

[0065] In various embodiments, the pixel 300 includes a first deep isolation trench 324 and a second deep isolation trench 326. The deep isolation trenches can extend as deep as the substrate. In various embodiments, the substrate can be completely surrounded by the plurality of deep isolation trenches.

[0066] In various embodiments, the first deep isolation trench 324 and the second deep isolation trench 326 create a pining potential at the substrate to deplete the substrate. In various embodiments, a DC voltage signal can be applied to the deep isolation trenches to create the pining potential.

[0067] In example embodiments, using the vertical gates and the deep isolation trenches, a uniform electrostatic field can be generated in the substrate from the bottom to the top in order to direct the carriers to the top, and then around the top in the appropriate direction to the proper sense node depending on which vertical gate is activated.

[0068] In various embodiments, a lateral gradient of the electrostatic field is created by the deep isolation trenches to deplete the substrate volume, and a vertical gradient of the electrostatic field is created by the vertical gates to go up and reach the sense node corresponding to the vertical gate activated at a given time.

[0069] In various embodiments, the deep isolation trench and vertical gates are fabricated using a dielectric liner (e.g., SiO2 or HK material, HfO2, AI2O3, etc.) followed by filling with a conductive material (e.g., doped polysilicon or a metal such as Al, W, Ag, etc.). In various embodiments, the substrate is fabricated from silicon, Ge, or InGaAs, etc., as previously described.

[0070] Referring now to Figure 4 , a diagram illustrating an example of operation of a pixel 300 in three-dimensional (3D) imaging or iToF measurement and in two-dimensional (2D) imaging according to various embodiments of the present disclosure is provided. As shown in Figure 4 , a line 402 is a schematic representation of the electrostatic potential level in a pixel 300 according to various embodiments.

[0071] In various embodiments, the pixel 300 can operate in a 3D imaging or iToF mode. When in the iToF mode, the first and second vertical gates of the pixel can be configured to be activated alternately using first and second gate control signals. In various embodiments, at a given time, the first control signal is the complement of the second control signal.

[0072] In various embodiments, when the first vertical gate is deactivated, it creates a low gate that acts as a potential barrier between the carriers in the integration region (e.g., region 308 in Figure 3 ) of the substrate and the first sensing node. When the first vertical gate is deactivated, the second vertical gate can be activated in the iToF mode. When the second vertical gate is activated, it creates a high gate that acts as a potential gradient that directs the carriers to the second sensing node. By alternating the activation and deactivation of the first and / or second gates, the pixel 300 alternately directs the charge to the corresponding first or second sensing node when operating in the iToF mode.

[0073] In example embodiments, by not using a P-N junction or N-well in the integration region, the activation and / or deactivation of the first and second gates in the pixel 300 can be performed at a higher frequency and using a lower amplitude. As a result, the accuracy of the measurement can be increased and the power consumption of the pixel can be reduced.

[0074] In various embodiments, the pixel 300 can operate in 2D imaging, e.g., using light intensity acquisition. When operating in 2D imaging, for a first time period the first and second vertical gates can be configured to be deactivated simultaneously, which can be referred to as an integration time. Then, for a second time period, the first or second vertical gate can be activated, which can be referred to as a readout time. In various embodiments, the vertical gates are activated and deactivated using first and second gate control signals.

[0075] During the integration time, the first and second vertical gates can be deactivated, creating a low gate that acts as a barrier between the carriers in the integration region (e.g., region 308) of the substrate and the first and second sense nodes. Thus, during the integration region, charge is integrated in the integration region. In various embodiments, the barrier created during the integration time can be a stronger barrier than the barrier created during the iToF mode to allow for greater accumulation of charge for 2D imaging. Figure 3

[0076] During the readout time, either the first or second vertical gate can be activated. When the vertical gate is activated, it creates a high gate that acts as a potential gradient that directs the integrated carriers to the corresponding sense node for readout representing the 2D image captured in the pixel.

[0077] In example embodiments, by not using a P-N junction or N-well in the integration region, greater carrier integration in the integration region can be achieved. Using a vertical gate that is deeply implanted in the pixel can allow for providing a gate with very low bias, creating a significantly low gate barrier, allowing for storing a significantly large amount of carriers in the volume of the pixel.

[0078] Thus, in example embodiments, by simply using gate control signals to change the biasing conditions of the vertical gates, the pixel can operate in 3D or 2D imaging mode.

[0079] Reference is now made to Figure 5A , a schematic diagram of a pixel 500 is provided, in accordance with various embodiments of the present disclosure. In various embodiments, the pixel 500 includes a first vertical gate 504, a second vertical gate 506, a third vertical gate 508, and a fourth vertical gate 510 disposed inside a substrate 502. In various embodiments, the vertical gates are implanted in the substrate 502. The vertical gates can be deep trenches disposed inside the substrate 502.

[0080] In various embodiments, the first, second, third, and fourth vertical gates are configured to direct one or more carriers generated inside the substrate 502 in response to an incident light beam to the first sense node 522 or the second sense node 524. In various embodiments, the first and second vertical gates are configured to direct the one or more carriers to the first sense node 522, while the third and fourth vertical gates are configured to direct the one or more carriers to the second sense node 524.

[0081] ​In various embodiments, a first sensing node can be disposed proximate the first and second vertical gates, and a second sensing node can be disposed proximate the third and fourth vertical gates. For example, the first sensing node can be disposed between the first and second vertical gates, and the second sensing node can be disposed between the third and fourth vertical gates.

[0082] In various embodiments, the first vertical gate is electrically coupled to a first vertical gate input 514 and configured to receive a first gate control signal. In various embodiments, the second vertical gate is electrically coupled to a second vertical gate input 516 and configured to receive a second gate control signal. In various embodiments, a third gate input 518 is electrically coupled to the third vertical gate and configured to receive a third gate control signal. In various embodiments, a fourth gate input 520 is electrically coupled to the fourth vertical gate and configured to receive a fourth gate control signal. Figure 5B is a schematic diagram illustrating an arrangement of components from a top view.

[0083] In various embodiments, the first, second, third, and fourth vertical gates are configured to direct one or more carriers to the first sensing node or the second sensing node using the first, second, third, and fourth gate control signals. In example embodiments, carriers are directed to the first sensing node when the first and / or second vertical gates are activated using the first and / or second gate control signals. In example embodiments, carriers are directed to the second sensing node when the third and / or fourth vertical gates are activated using the third and / or fourth gate control signals.

[0084] In various embodiments, the first and second vertical gates can be activated and deactivated similarly and at the same frequency as the third and fourth vertical gates. In various embodiments, each vertical gate can be activated and / or deactivated at various frequencies and / or time shifted relative to one another to provide a higher sampling rate of reflected light beams in an iToF determination.

[0085] In various embodiments, the pixel 500 can include a first deep isolation trench 526 on a first side of the substrate 502 and a second deep isolation trench 528 on a second side of the substrate. The first and second deep isolation trenches can be configured to create a pinning potential at the substrate to deplete the substrate.

[0086] In various embodiments, any number of two or more vertical gates and / or any arrangement of vertical gates relative to the first and second sensing nodes can be used. For example, the vertical gates and sensing nodes and their corresponding N+ regions can be arranged in a single line, as in Figure 5AThe first set of vertical gates can direct carriers from the substrate to a first sensing node, and the second set of vertical gates can direct carriers to a second sensing node. The first sensing node can be disposed proximate the first set of vertical gates, and the second sensing node can be disposed proximate the second set of vertical gates. For example, the first and second vertical gates can be the first set of vertical gates, and the third and fourth vertical gates can be the second set of vertical gates.

[0087] For example, referring to Figure 5C , a schematic diagram 550 is provided that illustrates an arrangement of vertical gates relative to sensing nodes in a pixel according to various embodiments of the disclosure. The schematic diagram 550 illustrates the arrangement of components from a top view.

[0088] In various embodiments, the first vertical gate 504, the second vertical gate 506, the first sensing node 522, and the N+ region corresponding to the first node can be arranged in a first line, and the third vertical gate 508, the fourth vertical gate 510, the second sensing node 524, and the N+ region corresponding to the second sensing node can be arranged in a second line. In various embodiments, the first line can be approximately parallel to the second line.

[0089] In various embodiments, when more than one vertical gate corresponds to each sensing node, as illustrated, for example, in Figure 5A-5C at least one of the vertical gates corresponding to each sensing node can be electrically coupled to and biased with the same DC bias voltage. The other vertical gates corresponding to the sensing nodes can be operated using complementary and variable gate control signals as previously described. For example, the vertical gates 504 and 510 can be electrically coupled to and biased with the same DC bias voltage, while the vertical gates 506 and 508 can be electrically coupled to and biased with complementary AC bias signals. In example embodiments, the DC bias signal applied to at least one of the vertical gates can also facilitate directing one or more carriers from a lower region of the substrate (e.g., region 302) to a higher region of the substrate (e.g., region 308) closer to the vertical gates and the sensing nodes.

[0090] In various embodiments, the vertical gates can have various cross-sectional shapes. For example, at least one or all of the first, second, third, or fourth vertical gates can have various cross-sectional shapes that surround the corresponding sense node, and can completely or partially enclose the corresponding sense node. In various embodiments, at least one or all of the vertical gates can partially enclose the sense node, for example by having a C cross-sectional shape, F cross-sectional shape, or h cross-sectional shape. In various embodiments, at least one or all of the vertical gates can completely enclose the corresponding sense node, for example by having a circular (e.g., O) cross-sectional shape or b cross-sectional shape that surrounds the corresponding sense node. In various embodiments, when more than one vertical gate corresponds to a sense node, the vertical gates that completely or partially enclose the sense node can be concentric or eccentric with respect to each other.

[0091] For example, referring now to Figure 5D , a diagram 555 is provided that illustrates a first vertical gate 556 and a second vertical gate 558 according to various embodiments of the present disclosure. As shown in the example of Figure 5D , the vertical gates can partially enclose the sense nodes 522 and 524. As shown in the example of Figure 5D , the vertical gates have a cross-sectional shape that partially encloses a square shape of the sense nodes, although the vertical gates can have a circular cross-sectional shape, such as a partial circle (e.g., C-shaped) or a partial oval shape.

[0092] For example, referring now to Figure 5E , a diagram 560 is provided that illustrates a first vertical gate 566 and a second vertical gate 568 according to various embodiments of the present disclosure. As shown in the example of Figure 5E , the vertical gates can partially enclose the sense nodes 522 and 524, and have extensions 567 and 569, for example to electrically couple to the first vertical gate input 565 and the second vertical gate input 564, respectively. As shown in the example of Figure 5E , the vertical gates have a cross-sectional shape that partially encloses a square shape of the sense nodes, although the vertical gates can have a circular cross-sectional shape, such as a partial circle or a partial oval shape, that partially encloses the sense nodes.

[0093] For example, referring now to Figure 5F , a diagram 570 is provided that illustrates a first vertical gate 576 and a second vertical gate 578 according to various embodiments of the present disclosure. As shown in the example of Figure 5F , the vertical gates can completely enclose the sense nodes 522 and 524. As shown in the example of Figure 5F , the vertical gates have a cross-sectional shape that completely encloses a square shape of the sense nodes, although the vertical gates can have a circular cross-sectional shape, such as a circular (e.g., ring-shaped) or an oval shape.

[0094] In example embodiments, the vertical gates provided herein can have higher driving capability than planar gates throughout the volume of the pixel substrate. For example, small differences in electrostatic potential between the vertical gates can provide transfer of charge to corresponding sense nodes, thereby improving the efficiency of the pixel by requiring lower amplitudes of gate control signals needed to operate the pixel.

[0095] In example embodiments, using vertical gates and their higher driving capability can enable increasing the volume of the substrate without degrading the frequency performance of the pixel. For example, due to the uniform and strong electrostatic field gradient generated by the vertical gates and the strong driving force of the charge carriers resulting therefrom, using vertical gates increases the quantum efficiency (QE) of the pixel by increasing the thickness of the volume of the substrate silicon without degrading performance. In example embodiments, QE can represent the ratio of total charge carriers measured by the sense node of the pixel to the total incident photons on the pixel. In example embodiments, using vertical gates can also maintain high demodulation contrast (DMC) in the pixel. DMC can indicate an estimate of the rate at which the pixel collects and / or detects photons at the operating frequency.

[0096] Reference is now made to Figure 6 , which illustrates a schematic diagram of a method 600 in accordance with various embodiments of the present disclosure. In various embodiments, the method 600 can be used to fabricate and / or prepare a light detecting pixel, such as the pixel 300 described above. In various embodiments, at step 602, the method 600 arranges a first vertical gate 304 and a second vertical gate 306 inside a substrate 302. In various embodiments, the first and second vertical gates are configured to direct one or more charge carriers to a first sense node 310 or a second sense node 312. In various embodiments, the one or more charge carriers are generated inside the substrate in response to an incident light beam (which can be the reflected light beam 110) on the pixel.

[0097] In various embodiments, at step 604, the method 600 configures a first vertical gate input 314 to receive a first gate control signal. The first vertical gate input can be electrically coupled to the first vertical gate.

[0098] In various embodiments, at step 606, the method 600 configures a second vertical gate input 316 to receive a second gate control signal. The second vertical gate input can be electrically coupled to the second vertical gate. In various embodiments, the first and second vertical gates are configured to direct the one or more charge carriers to the first sense node or the second sense node using the first and second gate control signals. In example embodiments, the first and second sense nodes have intrinsic capacitances and are the first and second sense nodes. In various embodiments, the capacitances of the first and second sense nodes are supplemented by external capacitors, such as shown in Figure 1 and described above.

[0099] Referring now to Figure 7 , a schematic diagram of a method 700 in accordance with various embodiments of the present disclosure is illustrated. In various embodiments, the method 700 can be used to fabricate and / or prepare a photodetection pixel, such as the pixel 300 described above. In various embodiments, at step 702, the method 700 configures a first vertical gate to be activated using a first gate control signal and directs one or more carriers to a first sense node when the first vertical gate is activated.

[0100] In various embodiments, at step 704, the method 700 configures a second vertical gate to be activated using a second gate control signal and directs one or more carriers to a second sense node when the second vertical gate is activated.

[0101] In various embodiments, at step 706, the method 700 configures the first vertical gate to be deactivated when the second vertical gate is activated. In various embodiments, at step 708, the method 700 configures the second vertical gate to be deactivated when the first vertical gate is activated. In various embodiments, the method 700 activates and deactivates the vertical gates using a periodic first gate control signal and a periodic second gate control signal, where the first and second gate control signals are complementary to each other as described above. Thus, in various embodiments, the first and second control signals comprise periodic waveforms and are complementary to each other.

[0102] In various embodiments, the method 700 can include deploying a third vertical gate inside the substrate and deploying a fourth vertical gate inside the substrate, where the first, second, and fourth vertical gates are configured to direct one or more carriers to the first sense node or the second sense node. In various embodiments, the method 700 can include electrically coupling a third gate input to the third vertical gate to receive a third gate control signal and electrically coupling a fourth gate input to the fourth vertical gate to receive a fourth gate control signal. In various embodiments, the method 700 can include directing one or more carriers to the first sense node or the second sense node using the first, second, third, or fourth gate control signals.

[0103] In various embodiments, the method 700 can include deploying a first deep isolation trench on a first side of the substrate and deploying a second deep isolation trench on a second side of the substrate, where the first and second deep isolation trenches are configured to create a pinning potential at the substrate to deplete the substrate.

[0104] In various embodiments, the method 700 can include alternately activating the first and second vertical gates using the first and second gate control signals, where the first control signal is the complement of the second control signal at a given time. In various embodiments, the method 700 can include determining an indirect time-of-flight using a first charge value of a first intrinsic capacitance of the first sense node and a second charge value of an intrinsic capacitance of the second sense node.

[0105] In various embodiments, the method 700 can include electrically coupling the first sense node with a first supplemental capacitor and electrically coupling the second sense node with a second supplemental capacitor, as shown for example with reference to FIG. 6A. In various embodiments, the method 700 can include configuring the first and second supplemental capacitors to determine an indirect time-of-flight or a two-dimensional density image using a first charge value of the first supplemental capacitor and a second charge value of the second supplemental capacitor. Figure 1

[0106] It should be readily appreciated that various additional and alternative ways of configuring embodiments of the systems, apparatuses, and methods described herein can be employed in addition to the ways explicitly described herein.

[0107] Figure 8 FIG. 8 illustrates an example light detection system 800, in accordance with one or more embodiments of the present disclosure.

[0108] ​The light detection system 800 can include a computing device 810 and / or one or more light detection pixels 820 communicatively coupled to the computing device 810 using one or more wired and / or wireless communication techniques. Generally, the terms computing device, computer, system, device, entity, and / or similar words used interchangeably herein can refer to, for example, one or more computers, computing entities, desktops, mobile phones, tablets, notebooks, laptops, distributed systems, kiosks, input terminals, servers or server networks, blade servers, gateways, switches, processing devices, processing entities, controllers, control systems, set-top boxes, relays, routers, network access points, base stations, and / or any combination of devices or entities suitable for performing the functions, operations, and / or processes described herein. Such functions, operations, and / or processes can include, for example, sending, receiving, operating, processing, displaying, storing, determining, creating / generating, monitoring, evaluating, comparing, and / or similar terms used interchangeably herein. In one embodiment, these functions, operations, and / or processes can be performed on data, content, information, and / or similar terms used interchangeably herein. The computing device 810 can include any computing device, including, for example, a light detection processing device configured to perform one or more steps / operations of one or more light detection techniques described herein. In some examples, the computing device 810 can determine indirect time-of-flight (iToF) as described herein. In some examples, the computing device 810 can detect 2D images as described herein. In some embodiments, the computing device 810 can include one or more mobile devices, desktop computer(s), laptop computer(s), server(s), and / or cloud computing platform(s), etc., and / or be associated therewith. In some example embodiments, the computing device 810 can be configured to receive and / or send light detection instructions, data, etc., between one or more light detection pixels 820 to perform one or more steps / operations of one or more light detection techniques described herein.

[0109] The computing device 810 can include one or more processing elements 802 (also referred to as processors, processing circuitry, digital circuitry, and / or similar terms used interchangeably herein) or be in communication with one or more processing elements 802 that communicate with other elements within the computing device 810 via, for example, a bus. As will be appreciated, the processing elements 802 can be implemented in a variety of different manners.

[0110] For example, the processing element 802 can be embodied as one or more complex programmable logic devices (CPLDs), microprocessors, multi-core processors, co-processing entities, application specific instruction set processors (ASIPs), microcontrollers, and / or controllers. Moreover, the processing element 802 can be embodied as one or more other processing devices or circuitry. The term circuitry can refer to an entirely hardware embodiment or a combination of hardware and computer program products. Thus, the processing element 802 can be embodied as integrated circuits, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), hardware accelerators, and / or digital circuitry, etc.

[0111] Thus, as will be appreciated, the processing element 802 can be configured for a particular use or configured to execute instructions stored in volatile or non-volatile media or otherwise accessible to the processing element 802. Whether configured by hardware or computer program products, or by a combination thereof, the processing element 802 can thus be capable of performing steps or operations according to embodiments of the present disclosure while configured accordingly.

[0112] In one embodiment, the computing device 810 can also include or be in communication with one or more memory elements 104. The one or more memory elements 104 can include non-volatile and / or volatile media, for example. The memory element 804 can include non-volatile media (also referred to as non-volatile storage, memory, memory storage, memory circuitry, and / or similar terms used herein interchangeably), for example. In one embodiment, the non-volatile storage or memory can include one or more non-volatile storage or memory media, including but not limited to: hard disks, ROM, PROM, EPROM, EEPROM, flash memory, MMCs, SD memory cards, Memory Sticks, CBRAM, PRAM, FeRAM, NVRAM, MRAM, RRAM, SONOS, FJG RAM, Millipede memory, and / or racetrack memory, etc.

[0113] As will be appreciated, the non-volatile storage or memory media can store databases, database instances, database management systems, data, applications, programs, program modules, scripts, source code, object code, byte code, compiled code, interpreted code, machine code, and / or executable instructions, etc. The terms database, database instance, database management system, and / or similar terms used herein interchangeably can refer to a collection of records or data stored in computer-readable storage media using one or more database models, such as a hierarchical database model, network model, relational model, entity-relationship model, object model, document model, semantic model, and / or graph model, etc.

[0114] Additionally or alternatively, the memory element 804 can include volatile memory. For example, the computing device 810 can also include or be in communication with a volatile medium (also referred to as volatile memory, memory storage, memory circuitry, and / or similar terms used herein interchangeably) or a non-transitory computer-readable medium. In one embodiment, the volatile storage or memory can also include one or more volatile storage or memory media including, but not limited to: RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, TTRAM, T-RAM, Z-RAM, RIMM, DIMM, SIMM, VRAM, cache memory, and / or register memory, etc.

[0115] As will be appreciated, the volatile storage or memory medium can be used to store at least a portion of a database, database instance, database management system, data, application, program, program module, script, source code, object code, byte code, compiled code, interpreted code, machine code, and / or executable instructions, etc. executed by, for example, the processing element 802. Thus, the database, database instance, database management system, data, application, program, program module, script, source code, object code, byte code, compiled code, interpreted code, machine code, and / or executable instructions, etc. can be used to control certain aspects of the operation of the computing device 810 with the help of the processing element 802 and operating system.

[0116] As indicated, in one embodiment, the computing device 810 can also include one or more communication interfaces 808 for communicating with various computing entities, such as by transmitting data, content, information, and / or similar terms used herein interchangeably that can be sent, received, operated on, processed, displayed, and / or stored, etc. Such communication can be performed using wired data transmission protocols, such as fiber-optic distributed data interface (FDDI), digital subscriber line (DSL), Ethernet, asynchronous transfer mode (ATM), frame relay, data over cable service interface specification (DOCSIS), or any other wired transmission protocol. Similarly, the computing device 810 can be configured to communicate via wireless external communication networks using any of a variety of protocols, such as general packet radio service (GPRS), universal mobile telecommunications system (UMTS), code division multiple access 2000 (CDMA2000), CDMA2000 IX (lxRTT), wideband code division multiple access (WCDMA), global system for mobile communications (GSM), enhanced data rates for GSM evolution (EDGE), time division-synchronous code division multiple access (TD-SCDMA), long term evolution (LTE), evolved universal terrestrial radio access network (E-UTRAN), evolution data optimized (EVDO), high-speed packet access (HSPA), high-speed downlink packet access (HSDPA), IEEE 802.9 (Wi-Fi), Wi-Fi Direct, 802.16 (WiMAX), ultra-wideband (UWB), infrared (IR) protocols, near field communication (NFC) protocols, Wibree, Bluetooth protocols, wireless universal serial bus (USB) protocols, and / or any other wireless protocol.

[0117] The light detection system 800 can include input / output circuitry for communicating with one or more users or other systems or devices. For example, the input / output circuitry can include one or more interfaces for providing and / or receiving information with one or more users of the light detection system 800 or other systems or devices, or vice versa. The input / output circuitry can be configured to receive user input or input from various other systems or devices through one or more interfaces of the light detection system 800.

[0118] CONCLUSION

[0119] Those skilled in the art will appreciate, in light of the teachings of the present description and the associated drawings, that many modifications and other embodiments of the disclosed disclosure can occur to them without departing from the scope of the disclosure. While the drawings only illustrate certain components of the devices and systems described herein, it should be understood that various other components can be used in conjunction with the systems. Accordingly, it is to be understood that the present disclosure is not limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. The steps in the above-described methods do not necessarily have to occur in the order depicted in the figures, and in some cases, one or more of the steps depicted can occur substantially concurrently, or with additional steps. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

[0120] While various embodiments in accordance with the principles of the disclosure have been shown and described herein, modifications thereof can be made by those skilled in the art without departing from the spirit and the teachings of the disclosure. The embodiments described herein are representative only and are not intended as limitations on the scope of the disclosure. Many variations, combinations, and modifications are possible and are within the scope of the disclosure. Alternative embodiments resulting from combining, integrating, and / or omitting features of the embodiments are also within the scope of the disclosure. Accordingly, the scope of protection is not limited by the description set forth above, but is given by the appended claims.

[0121] Furthermore, the section headings in this document are provided for consistency with the suggestions of 37 C.F.R. 1.77, and are in no way limiting the subject matter disclosed herein. These headings shall not limit or characterize the disclosure in any way.

[0122] The use of broader terms such as "comprise", "comprises", "comprising", "contain", "contains", and "containing" should be understood not to exclude the narrower terms such as "consisting of", "consists of", and "consists essentially of". The use of the terms "optional", "may", "might", "may not", and other similar forms in connection with an element of an embodiment indicates that the element is not required, or alternatively, that the element is required, both of which are within the scope of the embodiments. Additionally, the use of the term "example" in the description is merely to illustrate an example of the embodiment, and is not intended to be exclusive or exhaustive.

[0123] While the detailed description has set forth some embodiments of the disclosure, the claims appended hereto cover other embodiments of the disclosure that can be different from the foregoing embodiments in various respects, as the skilled artisan will appreciate.

Claims

1. A pixel, characterized by, comprises: a substrate configured to generate one or more carriers in response to an incident light beam; a first vertical gate and a second vertical gate disposed inside the substrate, wherein the first vertical gate and the second vertical gate are configured to direct the one or more carriers to a first sensing node or a second sensing node; a first vertical gate input electrically coupled to the first vertical gate and configured to receive a first gate control signal; and a second vertical gate input electrically coupled to the second vertical gate and configured to receive a second gate control signal, wherein the first vertical gate and the second vertical gate are configured to direct the one or more carriers to the first sensing node or the second sensing node using the first gate control signal and the second gate control signal. wherein:

2. The pixel of claim 1, wherein, the first vertical gate is configured to be activated using the first gate control signal and, when activated, direct the one or more carriers to the first sensing node; and the second vertical gate is configured to be activated using the second gate control signal and, when activated, direct the one or more carriers to the second sensing node. wherein: the first vertical gate is deactivated when the second vertical gate is activated; and 3. The pixel of claim 2, wherein, the second vertical gate is deactivated when the first vertical gate is activated. wherein the first gate control signal and the second gate control signal comprise periodic waveforms and are complementary to each other. further comprising:

4. The pixel of claim 3, wherein, a third vertical gate disposed inside the substrate; 5. The pixel of claim 1, wherein, a fourth vertical gate disposed inside the substrate, wherein the first vertical gate, the second vertical gate, the third vertical gate, and the fourth vertical gate are configured to direct the one or more carriers to the first sensing node or the second sensing node; a third gate input electrically coupled to the third vertical gate and configured to receive a third gate control signal; and a fourth gate input electrically coupled to the fourth vertical gate and configured to receive a fourth gate control signal, wherein the first vertical gate, the second vertical gate, the third vertical gate, and the fourth vertical gate are configured to direct the one or more carriers to the first sensing node or the second sensing node using the first gate control signal, the second gate control signal, the third gate control signal, and the fourth gate control signal. further comprising: a first deep isolation trench on a first side of the substrate; and a second deep isolation trench on a second side of the substrate, wherein the first deep isolation trench and the second deep isolation trench are configured to create a pinning potential at the substrate to deplete the substrate.

6. The pixel of claim 1, wherein, wherein the first vertical gate and the second vertical gate are configured to be activated alternately using the first gate control signal and the second gate control signal, wherein at a given time the first gate control signal is the complement of the second gate control signal, and wherein the pixel is configured to determine an indirect time of flight (iToF). wherein the first vertical gate and the second vertical gate are configured to be deactivated simultaneously for a first time period using the first gate control signal and the second gate control signal, and for a second time period the first vertical gate or the second vertical gate is activated, and wherein the pixel is configured to provide two-dimensional imaging. comprises: a substrate configured to generate one or more carriers in response to an incident light beam; 7. The pixel of claim 1, wherein, ​ 8. The pixel of claim 1, wherein, ​ 9. A pixel, characterized by ​ ​ a first vertical gate and a second vertical gate disposed within the substrate, wherein the first vertical gate and the second vertical gate are configured to direct the one or more charge carriers to the first capacitor or the second capacitor; a first vertical gate input electrically coupled to the first vertical gate and configured to receive a first gate control signal; and a second vertical gate input electrically coupled to the second vertical gate and configured to receive a second gate control signal, wherein the first vertical gate and the second vertical gate are configured to direct the one or more charge carriers to the first capacitor or the second capacitor using the first gate control signal and the second gate control signal.

10. The pixel of claim 9, wherein, wherein: the first vertical gate is configured to be activated using the first gate control signal and, when activated, direct the one or more charge carriers to the first capacitor; and the second vertical gate is configured to be activated using the second gate control signal and, when activated, direct the one or more charge carriers to the second capacitor.

11. The pixel of claim 10, wherein, wherein: the first vertical gate is deactivated when the second vertical gate is activated; and the second vertical gate is deactivated when the first vertical gate is activated.

12. The pixel of claim 11, wherein, wherein the first gate control signal and the second gate control signal comprise periodic waveforms and are complementary to each other.

Images