Power semiconductor device

Abstract

The utility model provides a power semiconductor device, comprising a substrate which comprises a body region and a drift region which are arranged at an interval; the first well region is formed in the body region; the substrate leading-out region is formed in the body region, the first well region and the substrate leading-out region are arranged at intervals, the substrate leading-out region comprises a polycrystalline silicon body, the polycrystalline silicon body extends into the body region from the surface of the body region, and the vertical size of the polycrystalline silicon body is larger than the junction depth of the first well region; the first dielectric layer is arranged on the outer side of the polycrystalline silicon body, and the first well region and the polycrystalline silicon body are separated by the first dielectric layer; the second well region is formed in the drift region; the gate dielectric layer is arranged on the surface of the drift region, the gate dielectric layer is located between the body region and the second well region, and the gate dielectric layer is separated from the second well region; and the polysilicon gate layer is arranged on the surfaces of the gate dielectric layer, the drift region, the substrate and the body region. Without increasing the lateral dimension of the semiconductor device, the withstand voltage between the source electrode and the substrate can be improved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a power semiconductor device. Background Technology

[0002] When designing power management integrated circuits (PMICs), the source and substrate of the semiconductor device need to be separated. In existing PMICs, the small size of the semiconductor device's source leads to a relatively low breakdown voltage between the source and substrate. Ensuring sufficient breakdown voltage between the source and substrate while keeping the source size relatively fixed is a pressing issue that needs to be addressed. Utility Model Content

[0003] This invention provides a power semiconductor device to improve the technical problem in the prior art where the source terminal size of the semiconductor device in the power management chip is small, which leads to a low withstand voltage between the source electrode and the substrate.

[0004] This utility model provides a power semiconductor device, comprising:

[0005] A substrate, wherein the substrate includes a spaced-apart body region and a drift region;

[0006] The first well region is formed within the body region;

[0007] A substrate lead-out region is formed within the body region, and the first well region is spaced apart from the substrate lead-out region. The substrate lead-out region includes:

[0008] A polycrystalline silicon body extending from the surface of the body region into the body region, wherein the vertical dimension of the polycrystalline silicon body is greater than the junction depth of the first well region;

[0009] A first dielectric layer is disposed on the outside of the polysilicon body, and the first dielectric layer separates the first well region and the polysilicon body.

[0010] A second well region is formed within the drift region;

[0011] A gate dielectric layer is disposed on the surface of the drift region, the gate dielectric layer is located between the body region and the second well region, and the gate dielectric layer is separated from the second well region; and

[0012] A polycrystalline silicon gate layer is disposed on the surface of the gate dielectric layer, the drift region, the substrate, and the body region.

[0013] In one embodiment of this invention, the ratio of the vertical dimension of the polycrystalline silicon body to the junction depth of the first well region is greater than 2.

[0014] In one embodiment of this utility model, the vertical dimension of the polycrystalline silicon body is greater than that of the polycrystalline silicon body. The junction depth of the first well region is less than

[0015] In one embodiment of this utility model, in the horizontal direction, the distance between the center of the polycrystalline silicon body and the center of the first well region is... Within the range.

[0016] In one embodiment of this utility model, the substrate is a P-type substrate, the body region is a P-type body region, the drift region is an N-type drift region, the first well region and the second well region are N-type well regions, and the polycrystalline silicon body is a highly doped P-type polycrystalline silicon body.

[0017] In one embodiment of this utility model, the substrate is an N-type substrate, the body region is an N-type body region, the drift region is a P-type drift region, the first well region and the second well region are P-type well regions, and the polycrystalline silicon body is a highly doped N-type polycrystalline silicon body.

[0018] In one embodiment of the present invention, the semiconductor device further includes a shallow trench isolation structure formed in the substrate and the drift region, wherein the shallow trench isolation structure is located on the side of the second well region away from the body region.

[0019] In one embodiment of the present invention, a substrate lead-out region and two first well regions are provided in the body region, and the two first well regions are respectively located on both sides of the substrate lead-out region;

[0020] The drift region, the second well region, the gate dielectric layer, and the polysilicon gate layer are respectively disposed on both sides of the body region.

[0021] In one embodiment of this utility model, the gate dielectric layer is a gate oxide layer, and the first dielectric layer is a linear oxide layer.

[0022] In one embodiment of the present invention, the lateral dimension of the first well region is smaller than the lateral dimension of the second well region.

[0023] The beneficial effects of this invention are as follows: The power semiconductor device proposed in this invention has the unexpected technical effect of introducing voltage breakdown points that are prone to occur in the horizontal direction to the bottom of the polysilicon within the trench, thereby improving the breakdown voltage between the source and the substrate. This application can improve the breakdown voltage between the source and the substrate of the semiconductor device without increasing the lateral dimensions of the semiconductor device. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figure 1 A schematic diagram of the structure of a power semiconductor device provided by the prior art.

[0026] Figure 2 For existing technology Figure 1 The diagram below shows the shallow trench isolation structure.

[0027] Figure 3 For existing technology Figure 2 Simulation diagram of the shallow trench isolation structure.

[0028] Figure 4 This is a schematic diagram of the structure of a power semiconductor device provided in one embodiment of the present invention.

[0029] Figure 5 For the present utility model Figure 4 A schematic diagram of polycrystalline silicon is shown in the figure.

[0030] Figure 6 For the present utility model Figure 5 Simulation diagram of the polycrystalline silicon body.

[0031] Figure 7 This is a comparison graph of the source voltage and source current curves of this utility model and the prior art.

[0032] Figure 8 This is a schematic diagram of a structure in which a substrate lead-out region is formed on a bulk region according to an embodiment of the present invention.

[0033] Explanation of icon numbers

[0034] 10. Substrate; 20. Bulk region; 30. Drift region; 40. First well region; 500. Third well region; 510. Polysilicon bulk; 520. First dielectric layer; 530. Trench; 60. Second well region; 70. Gate dielectric layer; 80. Polysilicon gate layer; 90. Shallow trench isolation structure. Detailed Implementation

[0035] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0036] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0037] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the present invention. However, it will be apparent to those skilled in the art that embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present invention.

[0038] Please see Figures 1 to 8 This invention proposes a power semiconductor structure applicable to the field of power management integrated circuits (PMICs). Figures 1 to 3 In existing technologies, a small source terminal size in semiconductor devices leads to a lower breakdown voltage between the source electrode and the substrate. In this particular device, the source electrode is formed by a first well region 40, and the substrate lead-out region is formed by a third well region 500. In this invention... Figure 4 and Figure 6 In this semiconductor device, voltage breakdown points that are prone to occur in the horizontal direction are introduced to the bottom of the trench 530 through the polysilicon body 510, thereby improving the breakdown voltage between the source and the substrate. The source is formed by the first well region 40, and the substrate lead-out region is formed by the polysilicon body 510. The following is a detailed description through specific embodiments.

[0039] Please see Figure 4 In one embodiment of this utility model, a power semiconductor device may be provided, which may include a substrate 10, a first well region 40, a substrate lead-out region, a second well region 60, a gate dielectric layer 70, and a polysilicon gate layer 80.

[0040] In one embodiment of the present invention, the substrate 10 may include a body region 20 and a drift region 30 disposed at intervals.

[0041] Specifically, the body region 20 refers to the semiconductor material that constitutes the main body of a transistor or other semiconductor device. The body region 20 is the foundation of the entire device, and its doping type and concentration have a significant impact on the device's performance. In this embodiment, the body region 20 is used as the region connecting the substrate voltage.

[0042] Specifically, drift region 30 is a lightly doped semiconductor region whose function is to withstand high voltage and provide a path for current to flow in the on-state. The design of drift region 30 is crucial for controlling the device's on-resistance (Rds(on)) and breakdown voltage. Furthermore, by adjusting the length and doping concentration of drift region 30, device performance can be optimized.

[0043] In one embodiment of the present invention, a first well region 40 and a substrate lead-out region may be formed within the body region 20.

[0044] Specifically, the first well region 40 is spaced apart from the substrate lead-out region, and the first well region 40 can be formed in the top surface of the body region 20 by ion implantation.

[0045] Specifically, the substrate lead-out region includes a polysilicon body 510 and a first dielectric layer 520. The polysilicon body 510 is highly doped and extends from the surface of the body region 20 into the body region 20. The vertical dimension of the polysilicon body 510 is greater than the junction depth of the first well region 40. The first dielectric layer 520 is disposed on the outside of the polysilicon body 510, and the first dielectric layer 520 separates the first well region 40 and the polysilicon body 510.

[0046] In one embodiment of this invention, a second well region 60 is formed within a drift region 30, and can be formed within the top surface of the drift region 30 by ion implantation. A gate dielectric layer 70 is disposed on the surface of the drift region 30, and is located between the body region 20 and the second well region 60, separating the gate dielectric layer 70 from the second well region 60. A polysilicon gate layer 80 is disposed on the surfaces of the gate dielectric layer 70, the drift region 30, the substrate 10, and the body region 20 to form a gate.

[0047] This shows that, Figure 1 In existing technologies, the source electrode and the substrate lead-out region are isolated using a shallow trench isolation structure 90. Figure 4In this application, a highly doped polysilicon body 510 is deposited within a trench 530, and a first dielectric layer 520 is disposed on the outer side of the polysilicon body 510. The first dielectric layer 520 serves to isolate the source electrode from the substrate lead-out region. In this embodiment, the polysilicon body 510 disposed within the trench 530 can introduce voltage breakdown points that are prone to occur in the horizontal direction to the bottom of the polysilicon body 510 within the trench 530, thereby improving the breakdown voltage between the source electrode and the substrate. This embodiment improves the breakdown voltage between the source electrode and the substrate without increasing the lateral dimensions of the semiconductor device.

[0048] Please see Figure 4 In one embodiment of the present invention, the substrate 10 is a P-type substrate, the body region 20 is a P-type body region, the drift region 30 is an N-type drift region, the first well region 40 and the second well region 60 are N-type well regions, and the polysilicon body 510 is a highly doped P-type polysilicon body.

[0049] In other embodiments, not shown in the figures, the substrate 10 is an N-type substrate, the body region 20 is an N-type body region, the drift region 30 is a P-type drift region, the first well region 40 and the second well region 60 are P-type well regions, and the polysilicon body 510 is a highly doped N-type polysilicon body.

[0050] Please see Figure 4 In one embodiment of the present invention, the ratio of the vertical dimension of the polysilicon body 510 to the junction depth of the first well region 40 is greater than 2.

[0051] Specifically, to improve the breakdown voltage between the source and substrate by introducing the voltage breakdown point that is prone to occur in the horizontal direction to the bottom of the polysilicon body 510 within the trench 530, it is necessary to select appropriate sizes for the vertical dimension of the polysilicon body 510 and the junction extension of the first well region 40. For example, the vertical dimension of the polysilicon body 510 is greater than... (Å), the knot depth of the first well region 40 is less than (angstrom), (angstrom).

[0052] Please see Figure 4 , Figure 5 and Figure 6 In one embodiment of this utility model, in the horizontal direction, the distance between the center of the polysilicon body 510 and the center of the first well region 40 is... Within the range.

[0053] For example, please see Figure 2 and Figure 3In the prior art, the lengths of the two shallow trench isolation structures 90 and the third well region 500 are L1 + L1 = 1 μm. A shallow trench isolation structure 90 exists between the source electrode and the substrate at the source end, and the length between the centers of the first well region 40 and the third well region 500 is L1 = 0.5 μm. Please refer to [link / reference]. Figure 5 and Figure 6 In this embodiment, the horizontal width corresponding to the substrate lead-out region is L2 = 0.5 μm, a first dielectric layer 520 exists between the source electrode on the source end and the substrate, and the length between the center of the first well region 40 and the center of the polysilicon body 510 is L2 / 2 = 0.25 μm.

[0054] Specifically, in this embodiment, the distance between the center of the polysilicon body 510 and the center of the first well region 40 in the horizontal direction is... Within this range, the size between the source electrode and the substrate at the source end is reduced. Figure 7 In the diagram, the red curve on the left represents the source voltage and source current curves in the prior art, while the green curve on the right represents the source voltage and source circuit curves in this embodiment. It can be seen that in this embodiment, the isolation dimension between the source and the substrate at the source terminal is smaller, and the withstand voltage between the source and the substrate is higher.

[0055] Please see Figure 4 In one embodiment of this invention, the semiconductor device further includes a shallow trench isolation structure 90, which is formed within the substrate 10 and the drift region 30. The shallow trench isolation structure 90 is located on the side of the second well region 60 away from the body region 20. The shallow trench isolation structure 90 provides electrical isolation to the drain formed in the second well region 60.

[0056] Please see Figure 4 In one embodiment of this invention, a substrate lead-out region and two first well regions 40 are disposed within the body region 20, with the two first well regions 40 located on opposite sides of the substrate lead-out region. A drift region 30, a second well region 60, a gate dielectric layer 70, and a polysilicon gate layer 80 are respectively disposed on opposite sides of the body region 20. The lateral dimension of the first well region 40 is smaller than the lateral dimension of the second well region 60.

[0057] Specifically, such as Figure 4 As shown, in this embodiment, the voltage breakdown point that is prone to occur in the horizontal direction is introduced to the bottom of the polysilicon body 510 in the trench 530, thereby improving the breakdown voltage between the source electrode and the substrate. In order to further save the isolation size between the source electrode and the substrate, in this embodiment, one substrate lead-out region corresponds to two first well regions 40 in the body region 20, thereby making full use of the space size and breakdown voltage function of the polysilicon body 510 in the substrate lead-out region.

[0058] Please see Figure 4 and Figure 5 In one embodiment of this utility model, the gate dielectric layer 70 is a gate oxide layer, and the first dielectric layer 520 is a linear oxide layer.

[0059] Specifically, such as Figure 5 As shown, forming a polycrystalline silicon body 510 within the body region 20 may include the following steps.

[0060] First, a patterned photoresist layer (not shown in the figure) is formed on the surface of the body region 20. Using the patterned photoresist layer as a mask, the exposed body region 20 is etched to form a trench 530. The trench 530 extends from the surface of the body region 20 into the interior of the body region 20.

[0061] Secondly, after forming the trench 530 on the body region 20, a deposition process can be performed in the trench 530 to form a first dielectric layer 520. The first dielectric layer 520 can be a linear oxide layer. The first dielectric layer 520 can be grown along the surface contour of the trench 530. When the first dielectric layer grows uniformly, after a set time, the first dielectric layer 520 has the same surface contour that is proportionally expanded to the surface contour of the trench 530.

[0062] Secondly, after the first dielectric layer 520 is deposited and formed in the trench 530, since the first dielectric layer 520 is insulating, in order to allow the bottom end of the polysilicon body 520 subsequently formed in the trench 530 to extend into the body region 20, the first dielectric layer 520 can be etched. The first dielectric layer 520 is etched so that it is located on the inner wall of the trench 530, and not on the bottom end face of the trench 530.

[0063] Secondly, after etching the first dielectric layer 520 so that the first dielectric layer 520 is located on the inner wall of the trench 530 and not on the bottom end face of the trench 530, a highly doped polycrystalline silicon body 510 is formed in the trench 530 by deposition.

[0064] Specifically, a highly doped polysilicon body 510 fills the trench 530, meaning the polysilicon body 510 extends from the surface of the body region 20 into the interior of the body region 20, and a first dielectric layer 520 is disposed on the outer side of the polysilicon body 510. The highly doped polysilicon body 510 filling the trench 530 introduces voltage breakdown points that are prone to occur in the horizontal direction of the source end to the bottom end of the trench 530 through the polysilicon body 510. By controlling the depth of the trench 530, polysilicon bodies 510 with different vertical dimensions can be designed, thereby achieving devices with different source and substrate breakdown voltage requirements.

[0065] Then, after forming a highly doped polysilicon body 510 in the trench 530, a first well region 40 can be formed on the outside of the first dielectric layer 520 on the surface of the body region 20 by ion implantation. The first well region 40 forms the source, and the polysilicon body 510 forms the substrate lead-out region.

[0066] In summary, this utility model proposes a power semiconductor device with the unexpected technical effect of redirecting the voltage breakdown point, which is prone to occur in the horizontal direction, to the bottom of the polysilicon within the trench, thereby improving the breakdown voltage between the source and the substrate. This application improves the breakdown voltage between the source and the substrate of the semiconductor device without increasing its lateral dimensions.

[0067] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model. As used herein and throughout the claims below, unless otherwise specified, "a" and "the" include plural references. Similarly, as used herein and throughout the claims below, unless otherwise specified, "in" means "in" and "on".

Claims

1. A power semiconductor device, characterized in that, include: A substrate, wherein the substrate includes a spaced-apart body region and a drift region; A first well region is formed within the body region to form a source electrode; A substrate lead-out region is formed within the body region, and the first well region is spaced apart from the substrate lead-out region. The substrate lead-out region includes: A polycrystalline silicon body extending from the surface of the body region into the body region, wherein the vertical dimension of the polycrystalline silicon body is greater than the junction depth of the first well region; A first dielectric layer is disposed on the outside of the polysilicon body, and the first dielectric layer separates the first well region and the polysilicon body. A second well region is formed within the drift region to form a drain. A gate dielectric layer is disposed on the surface of the drift region, the gate dielectric layer is located between the body region and the second well region, and the gate dielectric layer is separated from the second well region; and A polysilicon gate layer is disposed on the surface of the gate dielectric layer, the drift region, the substrate, and the body region to form a gate.

2. The power semiconductor device according to claim 1, characterized in that, The ratio of the vertical dimension of the polycrystalline silicon body to the junction depth of the first well region is greater than 2.

3. The power semiconductor device according to claim 2, characterized in that, The vertical dimension of the polycrystalline silicon body is greater than The junction depth of the first well region is less than 4. The power semiconductor device according to claim 3, characterized in that, In the horizontal direction, the distance between the center of the polycrystalline silicon body and the center of the first well region is... Within the range.

5. The power semiconductor device according to claim 1, characterized in that, The substrate is a P-type substrate, the body region is a P-type body region, the drift region is an N-type drift region, the first well region and the second well region are N-type well regions, and the polycrystalline silicon body is a highly doped P-type polycrystalline silicon body.

6. The power semiconductor device according to claim 1, characterized in that, The substrate is an N-type substrate, the body region is an N-type body region, the drift region is a P-type drift region, the first well region and the second well region are P-type well regions, and the polysilicon body is a highly doped N-type polysilicon body.

7. The power semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a shallow trench isolation structure formed in the substrate and the drift region, the shallow trench isolation structure being located on the side of the second well region away from the body region.

8. The power semiconductor device according to claim 1, characterized in that, The body region is provided with one substrate lead-out region and two first well regions, with the two first well regions located on both sides of the substrate lead-out region; The drift region, the second well region, the gate dielectric layer, and the polysilicon gate layer are respectively disposed on both sides of the body region.

9. The power semiconductor device according to claim 1, characterized in that, The gate dielectric layer is a gate oxide layer, and the first dielectric layer is a linear oxide layer.

10. The power semiconductor device according to claim 1, characterized in that, The lateral dimension of the first well region is smaller than that of the second well region.

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