Semiconductor device structure

Abstract

A semiconductor device structure is provided. The structure includes at least one sloped via formed in a via isolation layer, and at least one anti-reflection element formed on the at least one sloped via.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device structure. Background Technology

[0002] Integrated circuits are formed on semiconductor wafers. The lithography patterning process uses ultraviolet light to transfer the desired photomask pattern onto a photoresist layer on the semiconductor wafer. Then, an etching process can be used to transfer the pattern to a layer beneath the photoresist. This process is repeated multiple times with different patterns to build different layers on the wafer substrate and create a useful device. Thin-film resistors can be used as part of such integrated circuits. Utility Model Content

[0003] In some embodiments, a semiconductor device structure includes a via isolation layer, at least one ramped via, at least one anti-reflective element, a trench isolation layer, at least one trench metal element, and a trench adhesive layer. At least one ramped via is disposed in the via isolation layer. At least one anti-reflective element is formed above the at least one ramped via in the via isolation layer. The trench isolation layer is formed on the at least one anti-reflective element. At least one trench metal element is disposed in the trench isolation layer and on the at least one ramped via. The trench adhesive layer is disposed between the at least one trench metal element and the trench isolation layer.

[0004] In some embodiments, a semiconductor device structure includes a via isolation layer, at least one ramped via, at least one anti-reflective element, a trench isolation layer, and at least one trench metal element. At least one ramped via is disposed in the via isolation layer. At least one anti-reflective element is formed above the at least one ramped via in the via isolation layer. The trench isolation layer is formed on the at least one anti-reflective element. At least one trench metal element is disposed in the trench isolation layer and the at least one anti-reflective element, and contacts the at least one ramped via.

[0005] In some embodiments, a semiconductor device structure includes a via isolation layer, at least one ramped via, at least one anti-reflective element, a trench isolation layer, and at least one trench metal element. At least one ramped via is disposed in the via isolation layer. At least one anti-reflective element is formed above the at least one ramped via on the via isolation layer, and the thickness of the at least one ramped via is [not specified in the original text]. to Within the specified range. A trench isolation layer is formed on at least one anti-reflective element. At least one trench metal element is disposed in the trench isolation layer and contacts at least one ramped through-hole. Attached Figure Description

[0006] The form of this disclosure is similar to that of the accompanying document. Figure 1 The best way to understand this text is by referring to the detailed description below. Please note that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 This is a cross-sectional view of a semiconductor device structure according to some embodiments;

[0008] Figure 2 This is a cross-sectional view of a portion of a semiconductor device structure according to some embodiments;

[0009] Figures 3A to 3S These are cross-sectional views of different manufacturing stages of a semiconductor device structure according to some embodiments;

[0010] Figures 4A to 4D These are cross-sectional views of different manufacturing stages of a comparative example of a semiconductor device structure according to some embodiments;

[0011] Figures 5A to 5C These are cross-sectional views of different manufacturing stages of a comparative example of a semiconductor device structure according to some embodiments;

[0012] Figure 6 This is a flowchart of a method for manufacturing a semiconductor device structure according to some embodiments.

[0013] [Symbol Explanation]

[0014] 100: Semiconductor Device Structure

[0015] 102: Basic structure or layer

[0016] 104: Through-hole isolation layer

[0017] 106: Through-hole adhesive layer

[0018] 108: First slope through hole

[0019] 110: Second slope through hole

[0020] 112: Groove adhesive layer

[0021] 114: Anti-reflective element

[0022] 116: Trench isolation layer

[0023] 118: First groove metal element

[0024] 120: Second groove metal element

[0025] 122: Light-emitting device

[0026] 124: Semiconductor Device Structure

[0027] 126: Grooved metal components

[0028] 128: Sloping through hole

[0029] 130: Depth (D1)

[0030] 132: Depth (D2)

[0031] 134: Depth (D3)

[0032] 136: Length (L1)

[0033] 138: Length (L2)

[0034] 140: Optical Obscuration

[0035] 142: Through hole

[0036] 144: Through-hole metal materials

[0037] 146: First reflective layer

[0038] 148: Optical Obscuration

[0039] 150: Optical Obscuration

[0040] 152: Grooved metal component hole

[0041] 154: Trench Metal Layer

[0042] 156: Optical Obscuration

[0043] 158: Light Source

[0044] 160: Groove cavity

[0045] 162: Grooved metal bridge

[0046] 600: Flowchart

[0047] 602: Steps

[0048] 604: Steps

[0049] 606: Steps

[0050] 608: Steps

[0051] 610: Steps

[0052] 612: Steps

[0053] 614: Steps

[0054] 616: Steps

[0055] 618: Steps

[0056] 620: Steps

[0057] 622: Steps

[0058] 624: Steps

[0059] 626: Steps

[0060] 628: Steps

[0061] 630: Steps

[0062] 632: Steps

[0063] 634: Steps

[0064] 636: Steps Detailed Implementation

[0065] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0066] Additionally, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “top,” and similar terms may be used herein for ease of description to describe the relationship between one or more elements or features illustrated in the figures and another element or feature. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0067] This disclosure relates to structures composed of different layers. When the terms "on," "above," or "over" are used to refer to two different layers (including a substrate), they simply mean that one layer is on top of or on top of another. These terms do not require that the two layers be in direct contact and allow other layers to be located between them. For example, all layers of a structure can be considered to be "on" the substrate, even if they are not all in direct contact with the substrate. The term "direct" can be used to indicate that two layers are in direct contact with each other and there is no layer between them.

[0068] This disclosure relates to various methods for improving via performance, trench metal adhesion, and stress buffering, particularly in back-end-of-line (BEOL) processes. Specifically, this disclosure relates to implementing multiple anti-reflective elements above multiple ramp vias to prevent errors in the patterning of photoresist on multiple trench metal elements. Ramp vias include beveled or angled tops to increase surface adhesion to the trench metal elements. Such angled / beveled surfaces can sometimes reflect light during photoresist patterning, leading to improper photoresist patterning. Anti-reflective elements help absorb or deflect light from the photoresist during the patterning process.

[0069] Next discussion Figure 1 This image shows a cross-sectional view of a semiconductor device structure 100 according to an embodiment of this application. Figure 1 As shown, the semiconductor device structure 100 includes a base structure or layer 102. According to different embodiments, as described above, the base structure or layer 102 may correspond to any layer among back-end processes, back-end process metal wiring, multiple devices, multiple components, etc., and is interconnected using multiple vias. Figure 1 As shown, the semiconductor device structure 100 also includes a via isolation layer 104 located on the base structure or layer 102. The via isolation layer 104 may include, for example, but not limited to, undoped silicate glass (USG), silicon nitride (SiN), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), low-k dielectric material (LK), extremely low-k dielectric material (ELK), and black diamond (BD), etc. It should be understood that other suitable silicate glasses or materials providing similar optical and / or insulating properties may be used in other embodiments. According to some embodiments, the via isolation layer 104 may be implemented with a thickness of approximately 100 angstroms to 500,000 angstroms. to Within the range of ).

[0070] The semiconductor device structure 100 also includes a via adhesive layer 106 located within the via isolation layer 104. The via adhesive layer 106 may include, for example, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), titanium (Ti), molybdenum (Ta), etc. According to some embodiments, the via adhesive layer 106 may have a thickness of approximately [missing information - likely a value]. to Within that range. For example... Figure 1 As shown, the semiconductor device structure 100 includes a first ramp via 108 and a second ramp via 110 formed or located in a via isolation layer 104. It should be understood that the first ramp via 108 and the second ramp via 110 include ramped or inclined side profiles, allowing subsequent components to access a larger surface area. In some embodiments, the larger surface area provides additional adhesion surface after the deposition of the first trench metal element 118 and the second trench metal element 120, improving the interface and reducing stress buffering.

[0071] The first ramp via 108 and / or the second ramp via 110 may comprise, for example, but not limited to, metallic materials, such as tungsten (W), copper (Cu), aluminum (Al), aluminum-copper (AlCu), aluminum-silicon-copper (AlSiCu), aluminum-silicon (AlSi), etc. It should be understood that other suitable metals or metal alloys providing similar conductive properties may be used in other embodiments. According to some embodiments, the thickness of the first ramp via 108 and the second ramp via 110 may be approximately [missing information - likely a measurement range]. to Within that range. It should be understood that... Figure 1 The first ramp via 108 and the second ramp via 110 described herein are for non-limiting purposes only, and the semiconductor device structure 100 may be implemented with any number of ramp vias, such as one, three, four, five, etc.

[0072] Figure 1 The semiconductor device structure 100 also includes one or more anti-reflective elements 114 located on the via isolation layer 104. The anti-reflective element 114 may be implemented as a cone or pyramidal shape, such as... Figure 1As shown in the cross-sectional view, a based pyramid is located on the top surface of the via isolation layer 104 and extends upward therefrom. In some embodiments, an anti-reflective element 114 is used during the formation of the semiconductor device structure 100, which will be discussed in detail below. According to different embodiments, the anti-reflective element 114 may include, for example, but not limited to, silicon oxynitride (SiON), undoped silicate glass (USG), silicon nitride (SiN), phosphosilicate glass (PSG), fluorosilicate glass (FSG), low-k dielectric material (LK), extremely low-k dielectric material (ELK), black diamond (BD), etc. It should be understood that other suitable silicate glasses or materials providing similar optical properties may be used in other embodiments. In some embodiments, the anti-reflective element 114 may comprise one or more layers of the same or different reflective materials. For a further discussion of the anti-reflective element 114, please refer to [link to relevant documentation]. Figures 3A to 3S .

[0073] like Figure 1 As shown, a trench isolation layer 116 is located on the antireflective element 114. The trench isolation layer 116 may include, for example, but not limited to, USG, SiN, PSG, FSG, LK, ELK, BD, etc. It should be understood that other suitable silicate glasses or materials providing similar optical and / or insulating properties may be used in other embodiments. According to some embodiments, the trench isolation layer 116 may be implemented with a thickness of approximately [missing information - likely a value]. to Within the range.

[0074] like Figure 1 As shown, the trench adhesive layer 112 is located on the first ramp via 108, the second ramp via 110, and the trench isolation layer 116. The first trench metal element 118 and the second trench metal element 120 are formed or located on the first ramp via 108 and the second ramp via 110, respectively, and the trench adhesive layer 112 is used as a bonding agent or adhesive. According to some embodiments, the trench adhesive layer 112 includes, for example, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), titanium (Ti), tantalum (Ta), etc. According to some embodiments, the trench adhesive layer 112 can be implemented with a thickness of approximately [missing information]. to Within the range. In different embodiments, the trench adhesive layer 112 and the through-hole adhesive layer 106 may comprise the same or different materials. In other embodiments, the trench adhesive layer 112 and the through-hole adhesive layer 106 may comprise the same or different materials. In other embodiments, such as Figure 1 As shown, the trench adhesive layer 112 can completely encapsulate the aforementioned first trench metal element 118 and second trench metal element 120.

[0075] As mentioned above, Figure 1 The semiconductor device structure 100 also includes a first trench metal element 118 and a second trench metal element 120. For example... Figure 1 As shown, the first trench metal element 118 is located above the first ramp through-hole 108, and the second trench metal element 120 is located above the second ramp through-hole 110. According to some embodiments, the first trench metal element 118 and the second trench metal element 120 may include, for example, but not limited to, metallic materials such as tungsten (W), copper (Cu), aluminum (Al), AlCu, AlSiCu, AlSi, etc. It should be understood that other suitable metals or metal alloys providing similar conductive properties may be used in other embodiments. According to some embodiments, the thickness of the first trench metal element 118 and the second trench metal element 120 may be approximately [missing information - likely a measurement range]. to Within that range. Although Figure 1 The illustration shows two grooved metal elements, but it should be understood that any number of grooved metal elements corresponding to the corresponding number of ramp through-holes can be used, and the illustration of two grooved metal elements is only used as one embodiment.

[0076] Figure 1 A light-emitting device 122 is further depicted, which is operatively coupled to the semiconductor device structure 100. It should be understood that the light-emitting device 122 is only used as a device capable of being attached to the first trench metal element 118, the second trench metal element 120, and the trench isolation layer 116. That is, those skilled in the art should understand that... Figure 1 The semiconductor device structure 100 depicted can be fabricated at any point in the back-end process, that is, it can be inserted between various components on a wafer or piezoelectric chip and / or as shown in the image. Figure 1 The diagram illustrates subsequent bonding, coupling, and attachment of independent devices. Therefore, Figure 1 The light-emitting device 122 mentioned in the application may be an organic light-emitting diode (OLED) array, a light-emitting layer, a transistor layer, a memory layer, a part of random-access memory (RAM) or logic, etc., and this application is not limited to the aforementioned light-emitting device 122.

[0077] Now for reference Figure 2 This shows a cross-sectional view of a semiconductor device structure 124 according to a portion of a second embodiment. Figure 2 As shown, the semiconductor device structure 124 includes a single trench metal element 126 operatively coupled to a ramp via 128. Figure 2 The trench metal element 126 is located within the trench isolation layer 116 and above the through-hole isolation layer 104. For example... Figure 2 As shown, a through-hole adhesive layer 106 is formed around the ramp through-hole 128, and a groove adhesive layer 112 is formed around the groove metal element 126, so that the groove metal element 126 can be bonded to the ramp through-hole 128. Figure 2 In this configuration, one or more anti-reflective elements 114 are located on the through-hole isolation layer 104 and inserted between the through-hole isolation layer 104 and the trench isolation layer 116.

[0078] according to Figure 2 In one embodiment, the via isolation layer 104 can be implemented at a depth (D1) 130 of approximately [missing information]. to Within the range. The trench isolation layer 116 can be implemented at a depth (D2) 132 of approximately... to Within the range. In some embodiments, the depth (D2) 132 of the trench isolation layer 116 is greater than or equal to 1.5 times the depth (D1) 130 of the through-hole isolation layer 104, that is, D2 ≥ 1.5 * D1. Figure 2 As shown, the depth (D3) 134 to which the anti-reflective element 114 can be implemented is approximately [missing information]. to The second figure further shows that the implementable length (L1) 136 of the ramp via 128 is approximately 10 nm to 500 μm. The implementable length (L2) 138 of the trench metal element 126 is approximately in the range of 10 nm to 500 μm.

[0079] Next discussion Figures 3A to 3S The diagram shows cross-sectional views of different manufacturing stages of a semiconductor device structure 100 according to some embodiments. Layer patterning can employ any suitable patterning technique, such as lithography, using the deposition of a photoresist layer and selective exposure to visible light, ultraviolet light, deep ultraviolet light (i.e., deep ultraviolet lithography), extreme ultraviolet light (i.e., extreme ultraviolet lithography), etc., via a photomask, followed by development of the exposed photoresist, and then etching, deposition, or other process steps laterally defined by the developed photoresist. In other embodiments, patterning of the electron-sensitive resist layer can be performed by electron beam exposure (electron beam lithography). Those skilled in the art will understand that the foregoing is merely illustrative.

[0080] like Figure 3AAs shown, a via isolation layer 104 is formed on the underlying base structure or layer 102. As described above, the base structure or layer 102 may correspond to any layer among back-end processes, back-end process metal wiring, multiple devices, multiple components, etc., and are interconnected using vias. As described above, the via isolation layer 104 may include, for example, but not limited to, undoped silicate glass (USG), silicon nitride (SIN), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), low-k dielectric material (LK), extremely low-k dielectric material (ELK), black diamond (BD), or other suitable silicate glass or materials providing similar optical and / or insulating properties, which may be used in other embodiments. According to some embodiments, the via isolation layer 104 can be formed by any suitable deposition or layering process, including, but not limited to, deposition by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, another deposition process, or any suitable combination thereof. In some embodiments, chemical-mechanical polishing (CMP) can be performed after depositing the via isolation layer 104 to produce... Figure 3A The flat surface shown.

[0081] like Figure 3B As shown, photoresist 140 is then deposited and patterned on the via isolation layer 104. In some embodiments, photoresist 140 is applied to the surface of the via isolation layer 104, and then portions of the photoresist 140 are developed by a suitable light source to form a pattern thereon. The unexposed portions are then removed, so that... Figure 3B The patterned photoresist 140 shown is formed. Next, etching is performed to remove those portions of the via isolation layer 104 not protected by the photoresist 140, to form vias 142. Suitable removal processes include, for example, but not limited to, etching processes implemented by dry etching, reactive ion etching, wet etching, some other etching processes, or combinations thereof. Figure 3CIllustrations are provided of the manufacturing stages of the semiconductor device structure 100 after the formation of the via 142.

[0082] exist Figure 3D In this process, a via adhesive layer 106 is deposited on the surface of the via isolation layer 104 and the via 142. The via adhesive layer 106 may include, for example, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), titanium (Ti), tantalum (Ta), etc. According to some embodiments, the via adhesive layer 106 may have a thickness of approximately [missing information - likely a value]. to Within the scope. According to some embodiments, the formation of the via adhesive layer 106 can be accomplished by any suitable deposition or layering process, including, for example but not limited to, deposition by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, another deposition process, or any suitable combination thereof.

[0083] like Figure 3E As shown, a layer of via metal material 144 is then deposited on the semiconductor device structure 100. According to some embodiments, the via metal material 144 may include, for example, but not limited to, tungsten (W), copper (Cu), aluminum (Al), AlCu, AlSiCu, AlSi, etc. It should be understood that other suitable metals or metal alloys providing similar conductive properties may be used in other embodiments. It should be understood that with the deposition of the via metal material 144, the via 142 will be filled. Suitable deposition methods for the via metal material 144 may include, for example, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electrochemical plating (ECP), sputtering, another deposition process, or any suitable combination thereof. Subsequently, as... Figure 3F As shown, chemical mechanical polishing (CMP) is performed on the semiconductor device structure 100 to remove part of the via metal material 144 and via adhesive layer 106, thereby forming a first ramp via 108 and a second ramp via 110.

[0084] like Figure 3GAs shown, a first reflective layer 146 is then formed on the semiconductor device structure 100. The first reflective layer 146 may include, for example, but not limited to, SiON, USG, SiN, PSG, FSG, LK, ELK, BD, etc. It should be understood that other suitable silicate glasses or materials providing similar optical properties may be used in other embodiments. The formation of the first reflective layer 146 can be accomplished by any suitable deposition method, including, for example, but not limited to, CVD, PVD, ALD, sputtering, etc. Figure 3G As shown, the first reflective layer 146 is formed on the top (inclined) portion of the through-hole isolation layer 104, the top (inclined) portion of the first ramp through-hole 108, and the top (inclined) portion of the second ramp through-hole 110.

[0085] like Figure 3H As shown, chemical mechanical polishing (CMP) is performed on the semiconductor device structure 100 to make the first reflective layer 146 substantially flat. Figure 3I As shown, photoresist 148 is then deposited and patterned on the first reflective layer 146. That is, photoresist 148 can be deposited and then selectively exposed to visible light, ultraviolet light, deep ultraviolet light (in other words, deep ultraviolet lithography), extreme ultraviolet light (in other words, extreme ultraviolet lithography), etc., via a photomask, followed by development of the exposed photoresist, resulting in the formation of... Figure 3I The patterned photoresist 148 is shown.

[0086] Figure 3J An illustrative cross-sectional view of a semiconductor device structure 100 is provided after the first reflective layer 146 is covered by etching of an unpatterned photoresist 148. That is, the portions of the first reflective layer 146 not protected by the photoresist 148 are removed by an etching process, such as, but not limited to, dry etching, reactive ion etching, wet etching, some other etching processes, or combinations thereof. Figure 3J As shown, the columnar structures of the first reflective layer 146 are retained after etching. These columnar structures can then form the substrate, around which the antireflective element 114 can be formed. Therefore, the process continues until... Figure 3K The diagram illustrates the formation of an anti-reflective element 114, achieved by adding a second reflective layer (not shown) to the remaining portion of a first reflective layer 146 after etching and removal of photoresist 148. According to one embodiment, the formation of the anti-reflective element 114 is accomplished using a high-density plasma chemical vapor deposition (HDPCVD) deposition process and / or ion bombardment. That is, a second reflective layer material, identical or different from the first reflective layer 146, is deposited on the remaining portion of the first reflective layer 146. Figure 3KAs shown, the deposition process forms a conical or pyramidal antireflective element 114. It should be understood that using the HDPCVD process to form the antireflective coating of the needle-shaped, conical, or pyramidal antireflective element 114 helps to avoid ramp via reflections that would cause the trench isolation portion to be missing (preventing trench bridging), thus improving device performance and thereby increasing device yield by reducing the risk of trench metal short circuits due to trench bridging.

[0087] like Figure 3L As shown, a trench isolation layer 116 is then deposited on the antireflective element 114 of the semiconductor device structure 100. According to some embodiments, the trench isolation layer 116 may include, for example, but not limited to, USG, SiN, PSG, FSG, LK, ELK, BD, or other suitable silicate glasses or materials providing similar optical and / or insulating properties, which may be used in other embodiments. Furthermore, it should be understood that suitable deposition methods for the trench isolation layer 116 may include, for example, but not limited to, CVD, PVD, ALD, sputtering, another deposition process, or any suitable combination thereof. Subsequently, as... Figure 3M As shown, chemical mechanical polishing (CMP) is performed on the semiconductor device structure 100 to remove a portion of the trench isolation layer 116.

[0088] exist Figure 3N In this process, photoresist 150 is deposited and patterned on the trench isolation layer 116 of the semiconductor device structure 100. For example... Figure 3N As shown, photoresist 150 is patterned above the first ramp via 108 and the second ramp via 110. It should be understood that photoresist material is deposited on the trench isolation layer 116, and the photoresist 150 is exposed through a photomask by a suitable light source, forming a photoresist pattern on the protected and unprotected portions of the trench isolation layer 116. In some embodiments, the anti-reflective element 114 prevents accidental patterning by preventing light from being reflected from the angled first ramp via 108 and the angled second ramp via 110 into the photoresist 150. Therefore, after the photoresist 150 is applied to the trench isolation layer 116 and selectively patterned, the unexposed portions are removed, such that... Figure 3N The patterned photoresist 150 shown is formed.

[0089] like Figure 3O As shown, etching is then performed to remove portions of the trench isolation layer 116 that are not protected by the aforementioned photoresist 150, to form trench metal element holes 152. Figure 3OAs shown, the portion of the anti-reflective element 114 located above the first ramp via 108, the second ramp via 110, and the via adhesive layer 106 is removed within the trench metal element via 152. Suitable removal processes include, for example, but not limited to, etching processes implemented using dry etching, reactive ion etching, wet etching, some other etching processes, or combinations thereof. It should be understood that the portion of the trench isolation layer 116 protected by photoresist 150 remains on the semiconductor device structure 100, thereby providing an insulator or separator between the two displayed trench metal element vias 152.

[0090] like Figure 3P As shown, a trench adhesive layer 112 is then formed on the sidewalls and bottom of the trench metal element hole 152, and on the top (angled / sloping) surfaces of the first ramp via 108 and the second ramp via 110. The trench adhesive layer 112 may include, for example, but not limited to, TiN, TaN, W, Ti, Ta, etc. The formation of the trench adhesive layer 112 can be accomplished by any suitable deposition or layering process, including, for example, but not limited to, deposition by, for example, CVD, PVD, ALD, sputtering, another deposition process, or any suitable combination thereof.

[0091] like Figure 3Q As shown, a trench metal layer 154 is then deposited on the semiconductor device structure 100. According to some embodiments, the trench metal layer 154 can be deposited or formed on the semiconductor device structure 100 by suitable deposition or layering processes, including, but not limited to, deposition by, for example, ECP, CVD, PVD, ALD, sputtering, another deposition process, or any suitable combination thereof. As mentioned above, the trench metal layer 154 can be implemented as, for example, but not limited to, metallic materials such as tungsten (W), copper (Cu), aluminum (Al), AlCu, AlSiCu, AlSi, etc. It should be understood that other suitable metals or metal alloys providing similar conductive properties can be used in other embodiments.

[0092] Next, as Figure 3R As shown, chemical mechanical polishing (CMP) is performed on the semiconductor device structure 100 to remove a portion of the trench metal layer 154. Specifically, a first trench metal element 118 and a second trench metal element 120 are formed in trench metal element holes 152, and are bonded to each of the first and second ramp vias 108 and 110 vias 110 through a trench adhesive layer 112 formed at the top (tilted / angled) portions of the first ramp via 108 and the second ramp via 110 and at the bottom of the trench metal element hole 152. Then, as... Figure 3S As shown, the semiconductor device structure 100 can be bonded to and attached to the light-emitting device 122.

[0093] about Figures 4A to 4D and Figures 5A to 5CThis shows a comparative example of patterned photoresist using an anti-reflective element 114 according to some embodiments. For example... Figure 4A As shown, photoresist 156 is formed on the trench isolation layer 116 and patterned by exposure to the light source 158. Figure 4A As shown, the light source 158 is reflected by the top (angled / tilted) surface of the first sloping through-hole 108 towards the center portion of the photoresist 156. Figure 4B As shown, such reflection causes the photoresist 156 to not be cured, and subsequently, the central portion of the photoresist 156 no longer appears on the trench isolation layer 116 after the photoresist 156 has been developed. Then, as... Figure 4C As shown, etching is performed to remove the uncovered portions of the trench isolation layer 116, resulting in a large trench cavity 160. As... Figure 4D As shown, subsequent deposition of the trench metal layer 154 results in the formation of trench metal bridges 162, connecting two (or more) trench metal elements intended to be separated.

[0094] Figures 5A to 5C Illustrative examples of a semiconductor device structure 100 according to the methods and apparatus disclosed herein are provided. For example... Figure 5A As shown, after depositing photoresist 150, exposure is performed through light source 158. Figure 5A As shown, the light source 158 is absorbed by the anti-reflective element 114, which is far from the photoresist 150, resulting in the formation of the photoresist 150. As... Figure 5B As shown, with Figure 4C As shown, the trench metal element hole 152 is separated by the remaining portion of the trench isolation layer 116. Further, as... Figure 5C As shown, the subsequent formation of the first trench metal element 118 and the second trench metal element 120 illustrates the separation of the first trench metal element 118 and the second trench metal element 120 and the absence of... Figure 4D Unwanted grooved metal bridge 162.

[0095] Next discussion Figure 6 The diagram shows a flowchart 600 illustrating a method for manufacturing a semiconductor device structure 100 according to one embodiment. Figure 6As shown, flowchart 600 begins at step 602, followed by deposition of a via isolation layer 104 on the base structure or layer 102. As described above, the via isolation layer 104 may comprise any suitable material providing similar optical and / or insulating properties, including, but not limited to, USG, SIN, PSG, BPSG, FSG, LK, ELK, BD, etc. According to some embodiments, the via isolation layer 104 can be formed by any suitable deposition or layer process, including, but not limited to, deposition via, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, another deposition process, or any suitable combination thereof.

[0096] In step 604, photoresist 140 is deposited and patterned on the via isolation layer 104. Figure 3B An illustrative example of forming photoresist 140 is provided. For example... Figure 3C As shown, in step 606, etching is then performed to form vias 142 through the via isolation layer 104. It should be understood that any suitable etching process can be used to remove the via isolation layer 104 from those portions not protected by the photoresist 140. Figure 3D As shown, after etching, the photoresist 140 is removed, and in step 608, a via adhesive layer 106 is formed on the via isolation layer 104 and the via 142 on the exposed surface. As described above, the via adhesive layer 106 can be implemented with a thickness of approximately [missing information]. to Within the range. In such embodiments, the via adhesive layer 106 may include, for example, but not limited to, TiN, TaN, W, Ti, Ta, etc. The via adhesive layer 106 can be formed by any suitable deposition or layering process, including, for example, but not limited to, deposition by, for example, CVD, PVD, ALD, sputtering, another deposition process, or any suitable combination thereof.

[0097] like Figure 3E As shown, in step 610, a via metal material 144 is deposited on the semiconductor device structure 100. According to one embodiment, the via metal material 144 can be deposited via ECP, ALD, CVD, PVD, etc. Suitable examples of such via metal materials 144 include, but are not limited to, W, Cu, Al, AlCu, AlSiCu, AlSi, etc. It should be understood that other suitable metals or metal alloys providing similar conductive properties can be used in other embodiments. Figure 3EAs shown, the via metal material 144 is adhered or bonded to the via adhesive layer 106. In step 612, chemical mechanical polishing (CMP) is then performed on the semiconductor device structure 100 to form a first ramp via 108 and a second ramp via 110. That is, as Figure 3F As shown, part of the through-hole metal material 144 is removed by CMP, exposing the through-hole isolation layer 104 and forming a first ramp through-hole 108 and a second ramp through-hole 110 with an angled or inclined top.

[0098] like Figure 3G As shown, in step 614, a first reflective layer 146 is deposited on the semiconductor device structure 100. As described above, the first reflective layer 146 may include, for example, but not limited to, SiON, USG, SiN, PSG, FSG, LK, ELK, BD, etc. It should be understood that other suitable silicate glasses or materials providing similar optical properties may be used in other embodiments. Figure 3H As shown, in step 616, chemical mechanical polishing (CMP) is then performed on the first reflective layer 146.

[0099] In step 618, a photoresist 148 is then deposited and patterned on the first reflective layer 146. Figure 3I A patterned photoresist 148 according to one embodiment is described. That is, a layer of photoresist 148 is deposited and then selectively exposed to visible light, ultraviolet light, deep ultraviolet light (in other words, deep ultraviolet lithography), extreme ultraviolet light (in other words, extreme ultraviolet lithography), etc., via a photomask. The exposed photoresist is then developed, resulting in... Figure 3I The patterned photoresist 148 is shown. In step 620, the first reflective layer 146 is then etched, resulting in... Figure 3J This is an intermediate stage in the fabrication of the semiconductor device structure 100 shown. Therefore, in step 620, the portion of the first reflective layer 146 not protected by the photoresist 148 is removed by, for example, but not limited to, etching processes such as dry etching, reactive ion etching, wet etching, some other etching processes, or combinations thereof. According to one embodiment, the pillars of the first reflective layer 146 remaining after etching can then form a substrate, around which an antireflective element 114 can be formed.

[0100] like Figure 3K As shown, in step 622, a second reflective layer is deposited on the remaining portion of the first reflective layer 146 by HDPCVD to form the antireflective element 114. It should be understood that the HDPCVD deposition process used in step 622 can... Figure 3KThe conical or pyramidal antireflective element 114 shown is formed. In step 624, a trench isolation layer 116 is deposited on the semiconductor device structure 100 by, for example but not limited to, CVD, PVD, ALD, sputtering, another deposition process, or any suitable combination thereof. Figure 3L An illustrative example is provided of trench isolation layer 116 deposited on antireflective element 114. As described above, trench isolation layer 116 provides insulation between first trench metal element 118 and second trench metal element 120, and can be implemented as, for example, but not limited to, USG, SiN, PSG, FSG, LK, ELK, BD, or other suitable silicate glasses or materials providing similar optical and / or insulating properties, which may be used in other embodiments. Figure 3M As shown, in step 626, chemical mechanical polishing (CMP) is then performed on the semiconductor device structure 100 to remove a portion of the trench isolation layer 116.

[0101] In step 628, photoresist 150 is then deposited and selectively patterned on the trench isolation layer 116. According to some embodiments, photoresist material is deposited on the trench isolation layer 116 and exposed to the photoresist 150 through a photomask using a suitable light source, forming a photoresist pattern on the protected and unprotected portions of the trench isolation layer 116. In some embodiments, the anti-reflective element 114 prevents accidental patterning by preventing light from being reflected from the angled first ramp via 108 and second ramp via 110 into the photoresist 150. Therefore, after the photoresist 150 is applied and patterned on the trench isolation layer 116, the unexposed portions are then removed, resulting in... Figure 3N The patterned photoresist 150 shown is illustrated.

[0102] In step 630, etching is performed to remove portions of the trench isolation layer 116 and anti-reflective element 114 above the first ramp via 108 and the second ramp via 110. The removed trench isolation layer 116 and anti-reflective element 114 are portions not protected by the patterned photoresist 150, thereby forming the trench metal element hole 152. Figure 3O An illustrative example of the formed trench metal element via 152 is provided. The etching described in step 630 may include, for example, but not limited to, dry etching, reactive ion etching, wet etching, some other etching processes, or combinations thereof. It should be understood that a portion of the trench isolation layer 116 protected by photoresist 150 remains on the semiconductor device structure 100, thereby providing an insulator or separator between the two illustrated trench metal element vias 152.

[0103] In step 632, a trench adhesive layer 112 is formed, for example, deposited on the semiconductor device structure 100. Any suitable deposition or layering process, including, but not limited to, deposition by, for example, CVD, PVD, ALD, sputtering, another deposition process, or any suitable combination thereof, can be used to form the trench adhesive layer 112. Figure 3P As shown, a trench adhesive layer 112 is formed on the sidewalls and bottom of the trench metal element hole 152, and on the top surface (angled / inclined) of the first ramp through-hole 108 and the second ramp through-hole 110. According to some embodiments, the trench adhesive layer 112 may be implemented as, for example, but not limited to, TiN, TaN, W, Ti, Ta, etc. Figure 3Q As shown, in step 634, the trench metal layer 154 is then deposited or formed on the semiconductor device structure 100 and fills the trench metal element holes 152. As described above, the trench metal layer 154 can be implemented as, for example, but not limited to, metallic materials such as W, Cu, Al, AlCu, AlSiCu, AlSi, etc., and can be formed by, for example, ECP, CVD, PVD, ALD, sputtering, another deposition process, or any suitable combination thereof. Subsequently, in step 636, chemical mechanical polishing (CMP) is performed on the semiconductor device structure 100 to remove portions of the trench metal layer 154. Figure 3R A diagram is provided showing a first grooved metal element 118 and a second grooved metal element 120 formed in a grooved metal element hole 152. The first grooved metal element 118 and the second grooved metal element 120 are engaged with the respective first sloped through hole 108 and second sloped through hole 110 through a groove adhesive layer 112 formed at the top (sloping / angled) portion of the first sloped through hole 108 and the second sloped through hole 110 and at the bottom of the grooved metal element hole 152.

[0104] As understood, ramp vias can inadvertently reflect light during exposure, causing portions of the photoresist to form in an unintended manner. For example, while ramp vias improve adhesion to trench metal, the angled top of the ramp via can also reflect light. This reflected light can negatively affect the patterning of the photoresist. After such patterning, a subsequent etching process may remove portions of the trench isolation layer intended to be retained. This can result in the formation of trench metal bridges, i.e., bridges in the trench metal material connecting two or more trench metal elements. However, the addition of anti-reflective elements prevents the photoresist from being improperly patterned, thereby preventing the formation of such bridges. In some embodiments, anti-reflective elements deflect or absorb light, preventing the photoresist from being accidentally patterned and otherwise reflected back to the photoresist through the top of the ramp via.

[0105] According to a first embodiment, a method for manufacturing a semiconductor device structure is provided. This method includes depositing a first reflective layer on a via isolation layer, the via isolation layer including at least one ramped via. The method further includes performing chemical mechanical polishing on the first reflective layer, and depositing photoresist on the first reflective layer after chemical mechanical polishing. The method also includes patterning the photoresist and etching the first reflective layer to form pillars of the first reflective layer. Furthermore, the method includes depositing a second reflective layer on the pillars of the first reflective layer by high-density plasma chemical vapor deposition (HDPCVD) to form pillars corresponding to anti-reflective elements. The method also includes forming a trench isolation layer on the anti-reflective element and selectively patterning the photoresist on the trench isolation layer. This pattern is aligned with at least one ramped via. Furthermore, the method includes etching the trench isolation layer and the anti-reflective element based on the selectively patterned photoresist to form a trench metal element via above the at least one ramped via. Subsequently, the method includes forming a trench metal element in the trench metal element via.

[0106] In some embodiments, selectively patterning photoresist on the trench isolation layer further includes depositing a photoresist layer on the trench isolation layer and exposing the photoresist layer to the light source, wherein at least one anti-reflective element prevents the photoresist from being accidentally exposed from the ramp via.

[0107] In some embodiments, at least one antireflective element is shaped as a cone, pyramid, or needle.

[0108] In some embodiments, forming the trench isolation layer also includes depositing trench isolation material on the through-hole isolation layer and performing chemical mechanical polishing on the trench isolation material.

[0109] In some embodiments, forming a trench metal element further includes forming a trench adhesive layer in the trench metal element orifice, depositing trench metal material in the trench metal element orifice, and performing chemical mechanical polishing on the deposited trench metal material to form the trench metal element.

[0110] In some implementations, the depth of the trench isolation layer is greater than or equal to 1.5 times the depth of the through-hole isolation layer.

[0111] In some embodiments, the first reflective layer and the second reflective layer comprise different materials.

[0112] In some implementations, the first reflective layer and the second reflective layer comprise the same material.

[0113] According to a second embodiment, a method for manufacturing a semiconductor device structure is provided. This method includes forming at least one ramped via in a via isolation layer and forming at least one anti-reflective element on the at least one ramped via. The method further includes forming a trench isolation layer on the at least one anti-reflective element and selectively patterning photoresist on the trench isolation layer based on the at least one anti-reflective element. The method also includes etching the trench isolation layer and the at least one anti-reflective element based on the selectively patterned photoresist to form a trench metal element via above the at least one ramped via. Subsequently, the method includes forming a trench metal element in the trench metal element via.

[0114] In some embodiments, selectively patterning the photoresist further includes depositing a photoresist layer on a trench isolation layer and exposing the photoresist layer to a light source, wherein at least one anti-reflective element prevents the photoresist from being accidentally exposed from a ramp via.

[0115] In some embodiments, forming at least one antireflective element further includes depositing a first reflective layer on a via-insulator layer, patterning the first reflective layer into a plurality of columnar structures, and depositing a second reflective layer on the columnar structures of the first reflective layer by high-density plasma chemical vapor deposition.

[0116] In some embodiments, at least one antireflective element is shaped as a cone, pyramid, or needle.

[0117] In some embodiments, forming at least one ramped via further includes patterning photoresist on a via isolation layer, etching the via isolation layer according to the patterned photoresist to form at least one via, forming a via adhesive layer in at least one via, depositing via material in at least one via, and performing chemical mechanical polishing to form at least one ramped via.

[0118] In some implementations, the depth of the trench isolation layer is greater than or equal to 1.5 times the depth of the through-hole isolation layer.

[0119] In some embodiments, forming at least one trench metal element further includes forming a trench adhesive layer in the trench metal element orifice, depositing trench metal material in the trench metal element orifice, and performing chemical mechanical polishing on the deposited trench metal material to form the trench metal element.

[0120] According to a third embodiment, a semiconductor device structure is provided. This semiconductor device structure includes a via isolation layer and at least one ramped via located within the via isolation layer. The thickness of the at least one ramped via is... to Within the range. This semiconductor device structure also includes at least one anti-reflective element located above at least one ramp via on the via isolation layer, and a trench isolation layer formed on the at least one anti-reflective element. This semiconductor device also includes at least one trench metal element located in the trench isolation layer and contacting at least one ramp via.

[0121] In some embodiments, at least one antireflective element includes a first reflective layer and a second reflective layer, the second reflective layer being formed by high-density plasma chemical vapor deposition.

[0122] In some embodiments, at least one antireflective element is shaped as a cone, pyramid, or needle.

[0123] In some embodiments, the semiconductor device structure further includes a via adhesive layer and a trench adhesive layer. The via adhesive layer is disposed between at least one ramped via and a via isolation layer. The trench adhesive layer is disposed between at least one trench metal element and a trench isolation layer.

[0124] In some implementations, the depth of the trench isolation layer is greater than or equal to 1.5 times the depth of the through-hole isolation layer.

[0125] A semiconductor device structure includes a through-hole isolation layer, at least one ramped through-hole, at least one anti-reflective element, a trench isolation layer, at least one trench metal element, and a trench adhesive layer. At least one ramped through-hole is disposed in the through-hole isolation layer. At least one anti-reflective element is formed above the at least one ramped through-hole in the through-hole isolation layer. The trench isolation layer is formed on the at least one anti-reflective element. At least one trench metal element is disposed in the trench isolation layer and on the at least one ramped through-hole. The trench adhesive layer is disposed between the at least one trench metal element and the trench isolation layer.

[0126] In some embodiments, at least one antireflective element is shaped as a cone, pyramid, or needle.

[0127] In some embodiments, the thickness of at least one beveled through-hole is... to Within the range.

[0128] The semiconductor device structure also includes a via adhesive layer. The via adhesive layer is disposed between at least one ramped via and a via isolation layer.

[0129] A semiconductor device structure includes a via isolation layer, at least one ramped via, at least one anti-reflective element, a trench isolation layer, and at least one trench metal element. At least one ramped via is disposed in the via isolation layer. At least one anti-reflective element is formed above the at least one ramped via in the via isolation layer. The trench isolation layer is formed on the at least one anti-reflective element. At least one trench metal element is disposed in the trench isolation layer and the at least one anti-reflective element, and contacts the at least one ramped via.

[0130] In some embodiments, at least one antireflective element is shaped as a cone, pyramid, or needle.

[0131] In some implementations, the depth of the trench isolation layer is greater than or equal to 1.5 times the depth of the through-hole isolation layer.

[0132] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same benefits. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device structure, characterized in that, include: One through-hole isolation layer; At least one sloping through-hole is provided in the through-hole isolation layer; At least one anti-reflective element is formed above the at least one ramped through-hole on the through-hole isolation layer; A trench isolation layer is formed on the at least one antireflective element; At least one grooved metal element is disposed in the grooved isolation layer and on the at least one ramped through-hole; and A grooved adhesive layer is disposed between the at least one grooved metal element and the grooved isolation layer.

2. The semiconductor device structure as described in claim 1, characterized in that, One of the shapes of the at least one antireflective element is conical, pyramidal, or needle-shaped.

3. The semiconductor device structure as described in claim 1, characterized in that, Wherein the thickness of at least one inclined through-hole is to Within the range.

4. The semiconductor device structure according to any one of claims 1 to 3, characterized in that, Also includes: A through-hole adhesive layer is disposed between the at least one sloping through-hole and the through-hole isolation layer.

5. A semiconductor device structure, characterized in that, include: One through-hole isolation layer; At least one sloping through-hole is provided in the through-hole isolation layer; At least one anti-reflective element is formed above the at least one ramped through-hole on the through-hole isolation layer; A trench isolation layer is formed on the at least one antireflective element; and At least one grooved metal element is disposed in the grooved isolation layer and the at least one anti-reflective element, and contacts the at least one ramp through hole.

6. The semiconductor device structure as described in claim 5, characterized in that, One of the shapes of the at least one antireflective element is conical, pyramidal, or needle-shaped.

7. The semiconductor device structure as described in claim 5 or 6, characterized in that, The depth of the trench isolation layer is greater than or equal to 1.5 times the depth of the through-hole isolation layer.

8. A semiconductor device structure, characterized in that, include: One through-hole isolation layer; At least one beveled through-hole is disposed in the through-hole isolation layer, wherein the thickness of the at least one beveled through-hole is... to Within the range; At least one anti-reflective element is formed above the at least one ramped through-hole on the through-hole isolation layer; A trench isolation layer is formed on the at least one antireflective element; and At least one grooved metal element is disposed in the grooved isolation layer and contacts the at least one ramp through hole.

9. The semiconductor device structure as described in claim 8, characterized in that, One of the shapes of the at least one antireflective element is conical, pyramidal, or needle-shaped.

10. The semiconductor device structure as described in claim 8 or 9, characterized in that, Also includes: A through-hole adhesive layer is disposed between the at least one sloping through-hole and the through-hole isolation layer; as well as A grooved adhesive layer is disposed between the at least one grooved metal element and the grooved isolation layer.

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