Power MOSFET layout and MOSFET
By optimizing the trench layout of the shielded gate power MOSFET, eliminating the source contact holes in the trench region, and adding source contact holes in the third trench region, the problem of low breakdown voltage of the shielded gate power MOSFET was solved, and the breakdown withstand performance of the device was improved.
Patent Information
- Application Number
- CN202520632927.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-03
- Publication Date
- 2026-03-17
- Estimated Expiration
- 2035-04-03
AI Technical Summary
In existing shielded gate power MOSFET layout designs, the isolation design of the source polysilicon electrode, gate, and source contact hole leads to a reduction in the breakdown voltage of the shielded gate power MOSFET, making it more susceptible to breakdown.
In the layout of the shielded gate power MOSFET, the source contact hole between the first trench region and the second trench region is removed, a third trench region is added and a source contact hole is set in between, the trench layout of the cell region is optimized to improve the breakdown voltage and reduce the electric field strength and collision ionization rate at the bottom of the trench.
By optimizing the trench layout, the breakdown voltage of the shielded gate power MOSFET was improved, the electric field strength and impact ionization rate at the bottom of the trench were reduced, and the breakdown resistance of the device was enhanced.
Smart Images
Figure CN224007006U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor technology, and in particular relates to a shielded gate power MOSFET layout and MOSFET. Background Technology
[0002] Current shielded-gate power MOSFET layout designs require the source polysilicon electrode, gate, and source to be connected separately, and the source polysilicon electrode to be isolated from the gate. Before design optimization, such as... Figure 1 As shown, a source contact hole 8 is provided between the terminal region of the shielded gate power MOSFET and the first trench and the second trench near the cell region. This can reduce the breakdown voltage of the shielded gate power MOSFET, making the shielded gate power MOSFET device easier to break down. Summary of the Invention
[0003] To solve or alleviate the above-mentioned technical problems, in a first aspect, embodiments of this application provide a shielded gate power MOSFET layout, including: a cell region and a termination region;
[0004] The terminal area is disposed around the cell area;
[0005] The terminal area is provided with a first groove area and a second groove area at an adjacent interval near the cell area.
[0006] Source electrode contact hole areas are respectively provided in the first trench area and the second trench area;
[0007] No contact hole area is provided between the first trench area and the second trench area.
[0008] In a preferred embodiment of this application, the cell region includes a plurality of spaced third trench regions, a source contact hole region is provided between the third trench regions, and a gate contact hole region is provided in the third trench region.
[0009] Secondly, this application also provides a shielded gate power MOSFET, characterized in that it is fabricated using the layout described in the first aspect.
[0010] Compared with the prior art, the shielded gate power MOSFET layout and MOSFET provided in this application embodiment do not have a contact hole region between the first trench region and the second trench region. This can improve the breakdown voltage of the shielded gate power MOSFET, and the electric field strength / impact ionization rate at the bottom of the trench in the MOSFET terminal region provided in this application embodiment is reduced. Attached Figure Description
[0011] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:
[0012] Figure 1 This is a layout of a shielded gate power MOSFET in the prior art;
[0013] Figure 2 This is a shielded gate power MOSFET layout provided in an embodiment of this application. Detailed Implementation
[0014] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.
[0015] like Figure 2 As shown, this application embodiment provides a shielded gate power MOSFET layout, including: cell region 2 and terminal region 1;
[0016] The terminal region 1 is disposed around the cell region 2;
[0017] The terminal region 1 is provided with a first groove region 3 and a second groove region 4 at an adjacent interval near the cell region 2.
[0018] Gate contact hole regions 6 are respectively provided in the first trench region 3 and the second trench region 4;
[0019] No source contact area is provided between the first trench area 3 and the second trench area 4.
[0020] In a preferred embodiment of this application, the cell region 2 includes a plurality of spaced third trench regions 7, with source contact hole regions 5 disposed between the third trench regions 7, and gate contact hole regions disposed in the third trench regions 7.
[0021] Secondly, this application also provides a shielded gate power MOSFET, characterized in that it is fabricated using the layout described in the first aspect.
[0022] Compared with the prior art, the shielded gate power MOSFET layout and MOSFET provided in this application embodiment do not have a contact hole region between the first trench region and the second trench region. This can improve the breakdown voltage of the shielded gate power MOSFET, and the electric field strength / collision ionization rate at the bottom of the trench in the MOSFET terminal region provided in this application embodiment is reduced. In this application, when a contact hole is provided between the first trench region 3 and the second trench region 4 near the cell region 2, current tends to accumulate at this contact hole, and the electric field strength is highest at this point, which can easily cause terminal breakdown. If this contact hole is removed, the current does not flow through this point, the highest point of the surface electric field will shift towards the cell region 2, and the collision ionization rate will also decrease, thus significantly improving the terminal breakdown voltage.
[0023] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A power MOSFET layout, characterized by, Comprising: a cell region and a terminal region; the terminal region is arranged around the cell region; a first trench region and a second trench region are adjacently arranged at positions close to the cell region; a source contact hole region is arranged in the first trench region and the second trench region respectively; no contact hole region is arranged between the first trench region and the second trench region.
2. A power MOSFET layout as defined in claim 1, wherein, the cell region comprises a plurality of adjacently arranged third trench regions, a source contact hole region is arranged between the third trench regions, and a gate contact hole region is arranged in the third trench region.
3. A MOSFET, characterized by, Preparation by the layout as claimed in claim 1 or 2.