RS485 anti-leakage current circuit
By dynamically controlling the PMOS transistor and grounding control unit in the RS485 circuit, the leakage current problem caused by wiring errors in the traditional RS485 circuit is solved, thereby improving the flexibility and reliability of the circuit and preventing chip damage.
Patent Information
- Application Number
- CN202521206911.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-12
- Publication Date
- 2026-06-12
- Estimated Expiration
- 2035-06-12
AI Technical Summary
In traditional RS485 circuit design, due to non-standard construction and wiring, the pins of RS485 communication chips are prone to incorrect wiring, which can lead to leakage current, chip burnout, and system instability.
The controller outputs PWM signals to control the signal and grounding control unit, dynamically manages the power management unit and interface communication unit, prevents leakage current by switching PMOS transistors on and off, and combines diodes and TVS diodes to prevent reverse power connection and surge voltage, thereby improving circuit flexibility and reliability.
It effectively prevents leakage current, avoids chip overheating or burnout, and ensures that the circuit can still operate safely and reliably under abnormal power supply conditions, thus improving the long-term reliability and safety of the circuit.
Smart Images
Figure CN224355820U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of RS485 communication circuits, and in particular to an RS485 leakage current protection circuit. Background Technology
[0002] RS485 communication technology, as an important component of industrial communication, is widely used in scenarios such as data acquisition, remote monitoring, and automation control. Its stability and reliability are crucial for ensuring the normal operation of industrial equipment. Due to its differential signal transmission characteristics, the RS485 communication interface can effectively resist noise interference and achieve long-distance, high-speed data transmission.
[0003] However, in practical engineering applications, traditional RS485 circuit designs are prone to wiring errors in the bus communication stage due to non-standard construction wiring. This can lead to overcurrent and chip burnout of the RS485 communication chip, resulting in abnormal product communication and even compromising system stability. Utility Model Content
[0004] In order to achieve the best possible leakage current prevention effect, this application provides an RS485 leakage current prevention circuit.
[0005] The RS485 leakage current protection circuit provided in this application adopts the following technical solution:
[0006] An RS485 leakage current protection circuit includes a controller, a power management unit, a signal control unit, an interface communication unit, and a grounding control unit. The power management unit provides operating voltage to subsequent circuits, and its control terminal is electrically connected to the output terminal of the signal control unit. The interface communication unit implements RS485 communication functionality, and its control terminal is electrically connected to the input terminal of the grounding control unit. The control terminals of both the signal control unit and the grounding control unit are controlled and connected to the input / output terminals of the controller, and the controller's input / output terminals are used to output PWM signals.
[0007] By adopting the above technical solution, the controller can flexibly control the state of the signal control unit and the grounding control unit by outputting PWM signals, thereby realizing dynamic management of the power management unit and the interface communication unit, improving the flexibility and adaptability of the circuit, and effectively preventing leakage current.
[0008] Preferably, the power management unit includes a power supply V1, a PMOS transistor Q1, and an electrolytic capacitor EC1. The voltage output terminal of the power supply V1 is electrically connected to the positive terminal of the electrolytic capacitor EC1, and the negative terminal of the electrolytic capacitor EC1 is grounded to GND. The drain of the PMOS transistor Q1 is electrically connected to the negative terminal of the electrolytic capacitor EC1, and the source of the PMOS transistor Q1 is grounded to GND2. The gate of the PMOS transistor Q1 is set as the control terminal of the power management unit, and the gate of the PMOS transistor Q1 is electrically connected to the output terminal of the signal control unit.
[0009] By adopting the above technical solution, the second unit is controlled by the PWM signal to control the switching of the PMOS transistor Q1, which can realize the dynamic cutting off of the power supply and prevent power leakage in the non-working state, thereby effectively avoiding the generation of leakage current.
[0010] Preferably, the power management unit further includes a diode D1, with the voltage output terminal of the power supply V1 electrically connected to the positive terminal of the diode D1, and the negative terminal of the diode D1 electrically connected to the positive terminal of the electrolytic capacitor EC1.
[0011] By adopting the above technical solution, the addition of diode D1 can effectively prevent reverse power connection. When the polarity of the power supply V1 is reversed, diode D1 will prevent current from flowing in the opposite direction, thereby protecting other components in the circuit from damage and improving the reliability and safety of the circuit.
[0012] Preferably, the power management unit further includes a TVS diode D2, the positive terminal of the electrolytic capacitor EC1 is electrically connected to one end of the TVS diode D2, and the other end of the TVS diode D2 is grounded to GND2.
[0013] By adopting the above technical solution, the TVS diode D2 can effectively prevent surge voltage in the power supply from damaging the circuit. When a power surge occurs, the TVS diode D2 will quickly conduct, clamping the surge voltage within a safe range and protecting sensitive components in the subsequent circuit.
[0014] Preferably, the power management unit further includes a freewheeling diode D3, the positive terminal of which is electrically connected to the drain of the PMOS transistor Q1, and the negative terminal of which is electrically connected to the source of the PMOS transistor Q1.
[0015] By adopting the above technical solution, when the PMOS transistor Q1 is suddenly turned off, the current in the electrolytic capacitor EC1 can continue to flow through the freewheeling diode D3, which avoids the reverse electromotive force generated by the sudden current change from damaging the PMOS transistor Q1 and other components, and improves the reliability of the circuit.
[0016] Preferably, the signal control unit includes a Schottky diode D4, a capacitor C3, and a capacitor C4. The input / output terminal IO_PWM of the controller is electrically connected to pin 1 of the Schottky diode D4 through capacitor C4. Pin 2 of the Schottky diode D4 is grounded to GND2 through resistor R3 and capacitor C4 in sequence. Pin 3 of the Schottky diode D4 is grounded to GND2. The control terminal of the power management unit is electrically connected to the connection point between resistor R3 and capacitor C4.
[0017] By adopting the above technical solution, when the PWM signal is high, the signal control unit can output a high level to turn off the PMOS transistor Q1; when the PWM signal is low, by utilizing the characteristic that the capacitor voltage cannot change abruptly, the signal control unit can output a low level to turn on the PMOS transistor Q1, thereby ensuring that the PMOS transistor Q1 switches synchronously with the PWM signal.
[0018] Preferably, the interface communication unit includes an interface transceiver chip U1 and peripheral components. Pin 5 of the interface transceiver chip U1 is grounded to GND1, and pin 5 of the interface transceiver chip U1 is electrically connected to the input terminal of the grounding control unit.
[0019] By adopting the above technical solution, dynamic management of the power supply to the interface communication unit is achieved by electrically connecting pin 5 of the transceiver chip to the grounding control unit.
[0020] Preferably, the grounding control unit includes a PMOS transistor Q2, a Schottky diode D4, a capacitor C6, and a capacitor C7. The input / output terminal IO_PWM of the controller is electrically connected to pin 1 of the Schottky diode D4 through capacitor C7. Pin 3 of the Schottky diode D4 is grounded to GND, and pin 2 of the Schottky diode D4 is electrically connected to the gate of the PMOS transistor Q2 through resistor R11. The gate of the PMOS transistor Q2 is also grounded to GND2 through capacitor C6. The source of the PMOS transistor Q2 is grounded to GND, and the gate of the PMOS transistor Q2 is electrically connected to the source of the PMOS transistor Q2 through resistor R10. The drain of the PMOS transistor Q2 is set as the input terminal of the grounding control unit.
[0021] By adopting the above technical solution, when the PWM signal is high, capacitor C7 charges, causing the gate voltage of PMOS transistor Q2 to rise and turn off, thereby completely disconnecting the electrical connection between GND1 and GND, and making the interface communication unit not work; when the PWM signal is low, capacitor C7 discharges, causing PMOS transistor Q2 to turn on, restoring the power supply to the interface communication unit to ensure normal communication.
[0022] In summary, this application includes at least one of the following beneficial technical effects:
[0023] 1. By dynamically controlling the synchronous cut-off of power supply (PMOS transistor Q1) and grounding circuit (PMOS transistor Q2) through PWM, the interface transceiver chip U1 is completely de-energized in case of abnormal wiring, avoiding leakage current circuits caused by parasitic capacitance or poor insulation of RS485A / B lines, thereby eliminating chip overheating or burnout caused by standby current and significantly improving long-term reliability.
[0024] 2. The power management unit provides dual protection through the reverse connection protection diode D1 and TVS diode D2: when the power supply V1 is reversed, diode D1 can reverse cut off, blocking the current loop and preventing high voltage from directly impacting the subsequent circuit; at the same time, TVS diode D2 can absorb instantaneous surge voltage, preventing chip damage caused by reverse connection or power fluctuations, and ensuring that the RS485 interface remains safe and reliable under abnormal power supply conditions. Attached Figure Description
[0025] Figure 1 This is a schematic block diagram of an embodiment of this application;
[0026] Figure 2 This is a circuit diagram of the power management unit and the signal control unit in the embodiments of this application;
[0027] Figure 3 This is a circuit diagram of the interface communication unit and the grounding control unit in the embodiments of this application.
[0028] Reference numerals: 1. Power management unit; 2. Signal control unit; 3. Interface communication unit; 4. Grounding control unit. Detailed Implementation
[0029] The following is in conjunction with the appendix Figure 1-3 This application will be described in further detail.
[0030] This application discloses an RS485 leakage current protection circuit.
[0031] Reference Figure 1 An RS485 leakage current prevention circuit includes a controller, a power management unit 1, a signal control unit 2, an interface communication unit 3, and a grounding control unit 4. The power management unit 1 provides operating voltage to subsequent circuits, and its control terminal is electrically connected to the output terminal of the signal control unit 2. The interface communication unit 3 implements RS485 communication, and its control terminal is electrically connected to the input terminal of the grounding control unit 4. The control terminals of both the signal control unit 2 and the grounding control unit 4 are controlled and connected to the input and output terminals of the controller, which outputs PWM signals to dynamically control the operation and shutdown of the power management unit 1 and the interface communication unit 3, thus achieving leakage current prevention.
[0032] Reference Figure 2 The power management unit 1 includes a power supply V1, a diode D1, a TVS diode D2, a PMOS transistor Q1, and an electrolytic capacitor EC1. In this embodiment, the output voltage of the power supply V1 is 24V. The voltage output terminal of the power supply V1 is electrically connected to the positive terminal of the diode D1. The negative terminal of the diode D1 is electrically connected to one end of the TVS diode D2 through a resistor R1. The other end of the TVS diode D2 is grounded to GND2. By setting the diode D1, reverse connection protection is provided, and the TVS diode D2 provides surge protection. The gate of the PMOS transistor Q1 is electrically connected to the source of the PMOS transistor Q1 through a resistor R7, and the source of the PMOS transistor Q1 is grounded to GND2. The drain of the PMOS transistor Q1 is electrically connected to the negative terminal of the electrolytic capacitor EC1. The positive terminal of the electrolytic capacitor EC1 is electrically connected to the junction between the resistor R1 and the TVS diode D2, and the negative terminal of the electrolytic capacitor EC1 is grounded to GND. The gate of PMOS transistor Q1 is set as the control terminal of power management unit 1, and the gate of PMOS transistor Q1 is electrically connected to the output terminal of signal control unit 2.
[0033] When the signal control unit 2 outputs a high level, the PMOS transistor Q1 is turned off, and the output voltage of the power supply V1 can charge the electrolytic capacitor EC1 through the resistor R1; when the signal control unit 2 outputs a low level, the PMOS transistor Q2 is turned on, and the electrolytic capacitor EC1 is discharged.
[0034] Preferably, the power management unit 1 further includes a freewheeling diode D3, capacitor C1, and capacitor C2. The anode of the freewheeling diode D3 is electrically connected to the drain of the PMOS transistor Q1, and the cathode of the freewheeling diode D3 is electrically connected to the source of the PMOS transistor Q1, thereby providing a discharge path after the PMOS transistor Q1 is suddenly turned off, effectively functioning as a PMOS transistor Q1. One end of each capacitor C1 and capacitor C2 is electrically connected to the junction between resistor R1 and TVS diode D2, and the other end of each capacitor C1 and capacitor C2 is grounded (GND). Capacitors C1 and C2 can filter out noise and improve the stability of the voltage output.
[0035] The signal control unit 2 includes a Schottky diode D4, capacitor C3, and capacitor C4. The controller's input / output terminal IO_PWM is electrically connected to pin 1 of the Schottky diode D4 through capacitor C4. Pin 2 of the Schottky diode D4 is grounded to GND2 via resistor R3 and capacitor C4, and pin 3 of the Schottky diode D4 is also grounded to GND2. The control terminal of the power management unit 1 is electrically connected to the connection point between resistor R3 and capacitor C4. In this embodiment, the duty cycle of the PWM signal is 50%, and the frequency is 1000Hz.
[0036] When the PWM signal is high, the output current of the input / output terminal IO_PWM flows sequentially through capacitor C3, pins 1 and 4 of Schottky diode D4, and grounds to GND2. This charges capacitor C3 and discharges capacitor C4, enabling signal control unit 2 to output a high level, thus turning off PMOS transistor Q1. When the PWM signal is low, since the voltage across capacitor C3 cannot change abruptly, the voltage on the left side of capacitor C3 is pulled down to negative. This negative output voltage of capacitor C3 charges capacitor C4 through diode D4, with the charging speed limited by resistor R3. The voltage then returns to the right side of capacitor C3 through D4. At this time, signal control unit 2 outputs a low level, turning on PMOS transistor Q1.
[0037] Reference Figure 3 The interface communication unit 3 includes an interface transceiver chip U1 and a power supply V2. In this embodiment, the output voltage of the power supply V2 is 3.3V. Pins 1, 2, 3, and 4 of the interface transceiver chip U1 are electrically connected to the port of the controller, and pin 3 of the interface transceiver chip U1 is grounded through resistor R4. Pin 7 of the interface transceiver chip U1 is grounded through resistor R5, and pin 7 of the interface transceiver chip U1 is also electrically connected to the communication transceiver terminal RS485B2 through resistor R6. Pin 6 of the interface transceiver chip U1 is electrically connected to the voltage output terminal of the power supply V2 through resistor R7, and pin 6 of the interface transceiver chip U1 is also electrically connected to the communication transceiver terminal RS485A2 through resistor R8. Preferably, pin 6 of the interface transceiver chip U1 is grounded to GND1 through TVS diode D5, and pin 7 of the interface transceiver chip U1 is grounded to GND1 through TVS diode D6 to achieve the purpose of surge voltage discharge.
[0038] Pin 8 of the interface transceiver chip U1 is electrically connected to the voltage output terminal of the power supply V2 through resistor R9, and pin 5 of the interface transceiver chip U1 is grounded to GND1. Pin 8 of the interface transceiver chip U1 is electrically connected to pin 5 of the interface transceiver chip U1 through capacitor C5, and pin 5 of the interface transceiver chip U1 is electrically connected to the input terminal of the grounded control unit 4.
[0039] When the ground control unit 4 is disconnected, GND1 and GND are disconnected. At this time, the interface transceiver chip U1 is completely de-energized or enters a high-impedance state, and there is no current in the bus. When the ground control unit 4 is turned on, GND1 and GND are connected. At this time, the interface transceiver chip U1 is powered normally, allowing normal data transmission.
[0040] The grounding control unit 4 includes a PMOS transistor Q2, a Schottky diode D4, capacitors C6 and C7. The controller's input / output terminal IO_PWM is electrically connected to pin 1 of the Schottky diode D4 through capacitor C7. Pin 3 of the Schottky diode D4 is grounded to GND, and pin 2 of the Schottky diode D4 is electrically connected to the gate of the PMOS transistor Q2 through resistor R11. The gate of the PMOS transistor Q2 is also grounded to GND2 through capacitor C6. The source of the PMOS transistor Q2 is grounded to GND, and the gate of the PMOS transistor Q2 is electrically connected to the source of the PMOS transistor Q2 through resistor R10. The drain of the PMOS transistor Q2 is set as the input terminal of the grounding control unit 4.
[0041] When the PWM signal is at a high level, capacitor C7 begins to charge, and PMOS transistor Q2 is turned off, disconnecting GND and GND1. When the PWM signal is at a low level, since the voltage across capacitor C7 cannot change abruptly, the voltage on the right side of capacitor C7 is pulled down to negative. At this time, PMOS transistor Q2 turns on, connecting GND and GND1.
[0042] The implementation principle of the RS485 leakage current prevention circuit in this application embodiment is as follows: When the PWM signal is low, the signal control unit 2 controls the PMOS transistor Q1 in the power management unit 1 to conduct; at the same time, the ground control unit 4 controls the interface communication unit 3 to supply power normally, allowing normal data transmission. When the PWM signal is high, the signal control unit 2 controls the PMOS transistor Q1 in the power management unit 1 to turn off, and the capacitor EC1 charges; at the same time, the ground control unit 4 controls the interface communication unit 3 to turn off power, interrupting data transmission. This solves the leakage current problem caused by bus parasitic capacitance or poor insulation in traditional RS485 circuits, avoids leakage current paths formed by parasitic parameters on the RS485A / B line, and achieves the effect of preventing leakage current.
[0043] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.
Claims
1. An RS485 leakage current protection circuit, characterized in that: The system includes a controller, a power management unit (1), a signal control unit (2), an interface communication unit (3), and a ground control unit (4). The power management unit (1) is used to provide operating voltage for the subsequent circuits, and the control terminal of the power management unit (1) is electrically connected to the output terminal of the signal control unit (2). The interface communication unit (3) is used to implement RS485 communication function, and the control terminal of the interface communication unit (3) is electrically connected to the input terminal of the ground control unit (4). The control terminals of the signal control unit (2) and the ground control unit (4) are both controlled to be connected to the input and output terminals of the controller, and the input and output terminals of the controller are used to output PWM signals.
2. The RS485 leakage current protection circuit according to claim 1, characterized in that: The power management unit (1) includes a power supply V1, a PMOS transistor Q1, and an electrolytic capacitor EC1. The voltage output terminal of the power supply V1 is electrically connected to the positive terminal of the electrolytic capacitor EC1, and the negative terminal of the electrolytic capacitor EC1 is grounded to GND. The drain of the PMOS transistor Q1 is electrically connected to the negative terminal of the electrolytic capacitor EC1, and the source of the PMOS transistor Q1 is grounded to GND2. The gate of the PMOS transistor Q1 is set as the control terminal of the power management unit (1), and the gate of the PMOS transistor Q1 is electrically connected to the output terminal of the signal control unit (2).
3. The RS485 leakage current protection circuit according to claim 2, characterized in that: The power management unit (1) further includes a diode D1, the voltage output terminal of the power supply V1 is electrically connected to the positive terminal of the diode D1, and the negative terminal of the diode D1 is electrically connected to the positive terminal of the electrolytic capacitor EC1.
4. The RS485 leakage current protection circuit according to claim 2, characterized in that: The power management unit (1) also includes a TVS diode D2. The positive terminal of the electrolytic capacitor EC1 is electrically connected to one end of the TVS diode D2, and the other end of the TVS diode D2 is grounded to GND2.
5. The RS485 leakage current protection circuit according to claim 2, characterized in that: The power management unit (1) further includes a freewheeling diode D3, the positive terminal of which is electrically connected to the drain of the PMOS transistor Q1, and the negative terminal of which is electrically connected to the source of the PMOS transistor Q1.
6. The RS485 leakage current protection circuit according to claim 1, characterized in that: The signal control unit (2) includes a Schottky diode D4, a capacitor C3 and a capacitor C4. The input / output terminal IO_PWM of the controller is electrically connected to pin 1 of the Schottky diode D4 through the capacitor C4. Pin 2 of the Schottky diode D4 is grounded to GND2 through the resistor R3 and the capacitor C4 in sequence. Pin 3 of the Schottky diode D4 is grounded to GND2. The control terminal of the power management unit (1) is electrically connected to the connection point between the resistor R3 and the capacitor C4.
7. The RS485 leakage current protection circuit according to claim 1, characterized in that: The interface communication unit (3) includes an interface transceiver chip U1 and peripheral components. Pin 5 of the interface transceiver chip U1 is grounded to GND1, and pin 5 of the interface transceiver chip U1 is electrically connected to the input terminal of the ground control unit (4).
8. The RS485 leakage current protection circuit according to claim 7, characterized in that: The grounding control unit (4) includes a PMOS transistor Q2, a Schottky diode D4, a capacitor C6, and a capacitor C7. The input / output terminal IO_PWM of the controller is electrically connected to pin 1 of the Schottky diode D4 through capacitor C7. Pin 3 of the Schottky diode D4 is grounded to GND, and pin 2 of the Schottky diode D4 is electrically connected to the gate of the PMOS transistor Q2 through resistor R11. The gate of the PMOS transistor Q2 is also grounded to GND2 through capacitor C6. The source of the PMOS transistor Q2 is grounded to GND. The gate of the PMOS transistor Q2 is electrically connected to the source of the PMOS transistor Q2 through resistor R10, and the drain of the PMOS transistor Q2 is set as the input terminal of the grounding control unit (4).