A current detection circuit

Abstract

The utility model discloses a current detection circuit, and the current mirror circuit is connected through the output side switch tube mirror image in the measured circuit, thereby the power supply current of measured circuit is imaged as mirror current, and the operational amplifier circuit, current mirror circuit and current detection switch tube constitute the feedback path, because the operational amplifier circuit gain is greater than the preset gain, then the operational amplifier circuit is high gain operational amplifier, utilizes the virtual breakage virtual short feature of high gain operational amplifier, makes the voltage of two input ends of operational amplifier circuit consistent, namely makes the voltage of the output end of current mirror circuit and the voltage of the second end of output side switch tube same, thereby ensures the proportion between mirror current and power supply current is current mirror ratio, and further ensures that current detection module can accurately determine the power supply current of measured circuit according to the mirror current of the second end of current detection switch tube and current mirror ratio, and determines whether power supply current is greater than the preset overcurrent threshold, to realize the accurate current detection of measured circuit.

Description

Technical Field

[0001] This utility model relates to the field of power electronics technology, and in particular to a current detection circuit. Background Technology

[0002] Power transmission circuits typically convert electrical energy from the power supply to power the load. When the load malfunctions, the current in the power transmission circuit will fluctuate. A large current can cause the voltage-resistant components in the power transmission circuit to burn out. Therefore, it is usually necessary to detect the current in the power transmission circuit in order to protect the power transmission circuit based on the current.

[0003] However, the existing current detection circuits have low detection accuracy and cannot detect large currents in the power transmission circuit in time when the load malfunctions or there are abnormal conditions such as overvoltage or short circuit, which can lead to damage to the components in the power transmission circuit. Utility Model Content

[0004] The purpose of this invention is to provide a current detection circuit. The current mirror circuit is connected to the output-side switch in the circuit under test to mirror the supply current of the circuit under test. The operational amplifier circuit, the current mirror circuit, and the current detection switch form a feedback path. Since the gain of the operational amplifier circuit is greater than the preset gain, the operational amplifier circuit is a high-gain operational amplifier. Utilizing the virtual open and virtual short characteristics of the high-gain operational amplifier, the voltages at the two input terminals of the operational amplifier circuit are made consistent. This means that the voltage at the output terminal of the current mirror circuit is the same as the voltage at the second terminal of the output-side switch, thereby ensuring that the ratio between the mirror current and the supply current is the current mirror ratio. This ensures that the current detection module can accurately determine the supply current of the circuit under test based on the mirror current at the second terminal of the current detection switch and the current mirror ratio, and determine whether the supply current is greater than the preset overcurrent threshold, so as to achieve accurate current detection of the circuit under test.

[0005] To solve the above-mentioned technical problems, this utility model provides a current detection circuit.

[0006] The circuit under test includes an output-side switching transistor. The first terminal of the output-side switching transistor is connected to a power supply, and the second terminal of the output-side switching transistor is connected to a load when the current detection circuit is operating. The current detection circuit includes:

[0007] A current mirror circuit is connected in mirror to the output-side switching transistor to mirror the power supply current of the circuit under test into a mirror current.

[0008] An operational amplifier circuit is included, wherein its first input terminal is connected to the output terminal of the current mirror circuit, its second input terminal is connected to the second terminal of the output-side switching transistor, and its output terminal is connected to the control terminal of the current-sensing switching transistor. This control circuit controls the current-sensing switching transistor to conduct and adjusts the voltage at its control terminal to make the voltage between its first and second input terminals the same. The gain of the operational amplifier circuit is greater than a preset gain to ensure that the mirrored current matches the supply current.

[0009] The ratio between them is the current mirror ratio;

[0010] The current sensing switch has its first terminal connected to the output terminal of the current mirror circuit and its second terminal connected to the input terminal of the current sensing module, and is used to output the mirror current when it is turned on.

[0011] The current detection module is used to determine the supply current based on the mirror current and the current mirror ratio, and to determine whether the supply current is greater than a preset overcurrent threshold.

[0012] This application provides a current detection circuit. The current mirror circuit is connected to the output-side switch of the circuit under test to mirror the supply current of the circuit under test. The operational amplifier circuit, the current mirror circuit, and the current detection switch form a feedback path. Since the gain of the operational amplifier circuit is greater than the preset gain, the operational amplifier circuit is a high-gain operational amplifier. Utilizing the virtual open and virtual short characteristics of the high-gain operational amplifier, the voltages at the two input terminals of the operational amplifier circuit are made consistent. This also ensures that the voltage at the output terminal of the current mirror circuit is the same as the voltage at the second terminal of the output-side switch, thereby ensuring that the ratio between the mirror current and the supply current is the current mirror ratio. This ensures that the current detection module can accurately determine the supply current of the circuit under test based on the mirror current at the second terminal of the current detection switch and the current mirror ratio, and determine whether the supply current is greater than the preset overcurrent threshold, so as to achieve accurate current detection of the circuit under test. Attached Figure Description

[0013] To more clearly illustrate the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This application provides a schematic diagram of the structure of a current detection circuit;

[0015] Figure 2 A schematic diagram showing the connection between a current mirror circuit and an output-side switching transistor provided in this application;

[0016] Figure 3 A schematic diagram of a current mirror circuit provided in this application;

[0017] Figure 4 A schematic diagram of a specific structure of a current detection circuit provided in this application;

[0018] Figure 5 This application provides a schematic diagram of the structure of a diagnostic trigger circuit;

[0019] Figure 6 A schematic diagram of a diagnostic voltage divider circuit and a first diagnostic shutdown switch provided in this application;

[0020] Figure 7 This application provides a schematic diagram of the structure of a first bias circuit;

[0021] Figure 8 This application provides a connection diagram of a shutdown switch tube;

[0022] Figure 9 This application provides a schematic diagram of the structure of a second bias circuit;

[0023] Figure 10 This is a schematic diagram of a clamping circuit provided in this application. Detailed Implementation

[0024] The core of this invention is to provide a current detection circuit. The current mirror circuit is connected to the output-side switch in the circuit under test, thereby mirroring the supply current of the circuit under test into a mirror current. The operational amplifier circuit, the current mirror circuit, and the current detection switch form a feedback path. Since the gain of the operational amplifier circuit is greater than the preset gain, the operational amplifier circuit is a high-gain operational amplifier. Utilizing the virtual open and virtual short characteristics of the high-gain operational amplifier, the voltages at the two input terminals of the operational amplifier circuit are made consistent, which means that the voltage at the output terminal of the current mirror circuit is the same as the voltage at the second terminal of the output-side switch. This ensures that the ratio between the mirror current and the supply current is the current mirror ratio. In turn, it ensures that the current detection module can accurately determine the supply current of the circuit under test based on the mirror current at the second terminal of the current detection switch and the current mirror ratio, and determine whether the supply current is greater than the preset overcurrent threshold, so as to achieve accurate current detection of the circuit under test.

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0026] Please refer to Figure 1 , Figure 1 This application provides a schematic diagram of a current detection circuit. The circuit under test includes an output-side switch transistor ON. The first terminal of the ON output-side switch transistor is connected to a power supply, and the second terminal of the ON output-side switch transistor is connected to a load when the current detection circuit is working. The current detection circuit includes:

[0027] Current mirror circuit 1 is connected to the ON-side switch on the output side to mirror the power supply current of the circuit under test into a mirror current.

[0028] Operational amplifier circuit 2 has its first input terminal connected to the output terminal of current mirror circuit 1, its second input terminal connected to the second terminal of the output-side switch transistor ON, and its output terminal connected to the control terminal of the current detection switch transistor. This circuit controls the current detection switch transistor to conduct and adjusts the voltage at the control terminal of the current detection switch transistor so that the voltage between its first and second input terminals is the same. The gain of operational amplifier circuit 2 is greater than a preset gain so that the ratio between the mirrored current and the supply current is the current mirror ratio.

[0029] The current sensing switch 3 has its first terminal connected to the output terminal of the current mirror circuit 1 and its second terminal connected to the input terminal of the current sensing module, and is used to output mirror current when it is turned on.

[0030] The current detection module 4 is used to determine the supply current based on the mirror current and the current mirror ratio, and to determine whether the supply current is greater than the preset overcurrent threshold.

[0031] When the circuit under test supplies power to the load, the supply current may fluctuate due to abnormal load conditions. If the supply current is too large, it may cause the components in the circuit under test to burn out. Therefore, it is necessary to detect the supply current of the circuit under test so as to maintain the circuit under test in time when abnormal current occurs. However, the detection accuracy of the supply current in the existing technology is low, and it is impossible to detect abnormal supply current in time, which may lead to damage to the components.

[0032] The output-side switch ON in the circuit under test is connected between the power supply and the load when the current detection circuit is working, or when the load needs power. That is, the conduction and cutoff of the output-side switch ON are related to the power supply to the load. Therefore, the current on the output-side switch ON is the supply current. The current detection circuit in this application includes a current mirror circuit 1, an operational amplifier circuit 2, a current detection switch 3, and a current detection module 4. The current mirror circuit 1 is connected to the output-side switch ON in the circuit under test to mirror the supply current on the output-side switch ON into a mirror current for measurement or monitoring. This avoids the losses, interference, and complexity caused by directly connecting the measuring instrument to the high-current main circuit.

[0033] The current mirror circuit 1 includes a mirror transistor. The output-side switch ON and the mirror transistor in the current mirror circuit 1 are strictly matched in physical structure. They are usually manufactured on the same chip using the same process, or in discrete designs, devices of the same model and batch are selected. They have the same channel length, and their channel widths W are usually in a specific ratio (such as 1:1, 1:N, N:1). The most common 1:1 ratio means that the two are exactly the same size, and the mirrored current is equal to the supply current. If the ratio between the channel width of the output-side switch ON and the channel width of the mirror transistor in the current mirror circuit 1 is N:1, then the current mirror ratio is N:1, and the mirrored current is 1 / N of the supply current, so as to reduce the power consumption and measurement difficulty of the current mirror circuit 1. Furthermore, if both the mirror transistor and the output-side switch ON in current mirror circuit 1 are NMOS transistors, then the gates of the mirror transistor and the output-side switch ON are connected together, receiving the same gate control voltage. This ensures that the conduction state (channel formation) of both devices is controlled by the same signal. The drains of the output-side switch ON and the mirror transistor are connected together and share a power supply, ensuring that both devices have the same drain potential. The source of the output-side switch ON is connected in the main power circuit, such as when connected to a high-voltage, high-current load. The source of the mirror transistor is connected to a precise current source formed by the operational amplifier circuit 2 and the current-sensing switch 3, and a mirrored current is drawn for current detection. The operational amplifier circuit 2 is responsible for establishing a suitable source operating point for the mirror transistor and forcing the mirrored current flowing through the mirror transistor to accurately mirror the supply current flowing through the output-side switch ON. Please refer to [reference needed]. Figure 2 , Figure 2 This is a schematic diagram showing the connection between a current mirror circuit and an output-side switching transistor, as provided in this application. Figure 2In the diagram, ON represents the output-side switch ON, CM_ON is the mirror transistor in current mirror circuit 1, OUT is the second terminal of the output-side switch ON, and FB is the output terminal of current mirror circuit 1. The gate voltage of the mirror transistor CM_ON in current mirror circuit 1 is equal to that of the output-side switch ON, and their drain voltages are connected to the power supply voltage VS. The source of the output-side switch ON is the output terminal OUT of the circuit under test. The source voltage of the mirror transistor CM_ON in current mirror circuit 1 is... .

[0034] Since the gain of operational amplifier circuit 2 is greater than the preset gain, operational amplifier circuit 2 is a high-gain operational amplifier. Furthermore, since the first input terminal of operational amplifier circuit 2 is connected to the output terminal of current mirror circuit 1, the second input terminal is connected to the second terminal of the output-side switch transistor ON, and the output terminal is connected to the control terminal of current detection switch transistor 3, and the first terminal of current detection switch transistor 3 is connected to the output terminal of current mirror circuit 1, when operational amplifier circuit 2 controls current detection switch transistor 3 to conduct, the entire circuit constitutes a feedback circuit. Utilizing the virtual open / virtual short characteristics of the high-gain operational amplifier, the voltages at the two input terminals of operational amplifier circuit 2 are forced to be the same. Therefore, the ratio of the mirror current to the supply current in current mirror circuit 1 is precisely determined as the current mirror ratio. The mirror current flows from current detection switch transistor 3 to current detection module 4. Current detection module 4 uses the detected mirror current and current mirror ratio to infer the supply current in the circuit under test, thereby determining whether an overcurrent has occurred in the circuit under test, i.e., whether the load is abnormal, thus achieving accurate detection of the supply current of the circuit under test.

[0035] Because of the virtual short and virtual open characteristics of operational amplifier circuit 2, the voltage at the second terminal of the ON-side switch transistor on the output side is the same as the voltage at the output terminal of current mirror circuit 1. Therefore, we can obtain... ,in, The voltage at the second terminal of the ON switch on the output side. Let be the voltage at the output of the mirror transistor in current mirror circuit 1, and also the feedback voltage of operational amplifier circuit 2. Based on this, the current mirror ratio can be obtained:

[0036] ;

[0037] ;

[0038] ;

[0039] in, For mirror current, For supply current, The electron mobility of the NMOS transistor. Where W is the gate oxide capacitance per unit area, W is the physical width of the conductive channel below the MOSFET gate, L is the physical length of the conductive channel below the MOSFET gate, and W / L is the width-to-length ratio. The aspect ratio of the mirror transistor in current mirror circuit 1 is given. The aspect ratio of the ON switch on the output side. For the output-side switch ON and the gate-source voltage of the mirror transistor, This refers to the ON threshold voltage of the output-side switch and the mirror transistor. The current mirror ratio between the mirror current and the supply current is (i.e., ) In other words, the ratio between the width-to-length ratio of the mirror transistor and the width-to-length ratio of the output-side switch ON is equivalent to determining the current mirror ratio once the structure of the mirror transistor and the output-side switch ON is determined. This ensures that the ratio between the mirror current and the supply current is the current mirror ratio, so that the current detection module 4 can accurately deduce the magnitude of the supply current based on the mirror current, thereby improving the accuracy of current detection.

[0040] like Figure 3 As shown, Figure 3 This application provides a schematic diagram of a current mirror circuit 1. Considering the parasitic parameters in the mirror transistor or output-side switch ON caused by layout design, as well as the changes in the actual current mirror ratio due to manufacturing and packaging stress, a trimming circuit can be used to fine-tune the size of the mirror transistor to maintain the actual current mirror ratio after manufacturing as the same as the current mirror ratio during design. Each PMOS transistor in the trimming circuit is a trimming switch, and the NMOS transistor is a scaled-down version of the mirror transistor CM_ON. During normal operation, the trimming value of the trimming circuit is at an intermediate value, thus ensuring that the actual current mirror ratio is the desired current mirror ratio. When the above-mentioned changes cause a change in the current mirror ratio due to mirror error, the mirror accuracy can be improved by adjusting the trimming value. Specifically… Figure 3 VG in the diagram represents the control signal for the ON of the output-side switch transistor and the ON of the mirror transistor CM_ON. TRIM represents the trimming circuit, and TRIM_0, TRIM_1, TRIM_2, and TRIM_3 are control signals for adjusting the trimming value of the trimming circuit. When TRIM_0, TRIM_1, TRIM_2, and TRIM_3 are 0000, all NMOS transistors in the trimming circuit are turned on. When TRIM_0, TRIM_1, TRIM_2, and TRIM_3 are 1111, all NMOS transistors in the trimming circuit are turned off. Based on this, by adjusting TRIM_0, TRIM_1, TRIM_2, and TRIM_3, the control of the turned-on NMOS transistors is achieved, thereby adjusting the trimming value.

[0041] It should be noted that the preset gain can be, but is not limited to, a value between 90-100dB.

[0042] In summary, the current mirror circuit 1 mirrors the power supply current of the circuit under test by connecting to the ON-side switch in the circuit under test. The operational amplifier circuit 2, the current mirror circuit 1, and the current detection switch 3 form a feedback path. Since the gain of the operational amplifier circuit 2 is greater than the preset gain, the operational amplifier circuit 2 is a high-gain operational amplifier. Utilizing the virtual open and virtual short characteristics of the high-gain operational amplifier, the voltages at the two input terminals of the operational amplifier circuit 2 are made consistent. This also ensures that the voltage at the output terminal of the current mirror circuit 1 is the same as the voltage at the second terminal of the ON-side switch, thus ensuring that the ratio between the mirrored current and the power supply current is the current mirror ratio. This, in turn, ensures that the current detection module 4 can accurately determine the power supply current of the circuit under test based on the mirrored current at the second terminal of the current detection switch 3 and the current mirror ratio, and determine whether the power supply current is greater than the preset overcurrent threshold, thereby achieving accurate current detection of the circuit under test.

[0043] Based on the above embodiments:

[0044] Please refer to Figure 4 , Figure 4 This is a schematic diagram of a current detection circuit provided in this application. INN is the first input terminal of operational amplifier circuit 2, and INP is the second input terminal of operational amplifier circuit 2. Back-to-back clamping of diodes between the first and second input terminals of operational amplifier circuit 2 can help accelerate loop establishment and limit the difference between the first and second input terminals. Figure 4 The PMOS transistor MP14 mentioned below is the current sensing switch 3.

[0045] In a preferred embodiment, the current detection circuit further includes:

[0046] The diagnostic trigger circuit is used to control the diagnostic control switch MP10 to turn off when a current detection command is received, and otherwise control the diagnostic control switch MP10 to turn on.

[0047] The diagnostic control switch MP10 has its control terminal connected to the output terminal of the diagnostic trigger circuit. The first terminal of the diagnostic control switch MP10 is connected to the power supply, and the second terminal of the diagnostic control switch MP10 is connected to the control terminal of the current detection switch 3 and the output terminal of the operational amplifier circuit 2. It is used to turn off the current detection switch 3 when it is turned on, and to turn on the current detection switch 3 when it is turned off.

[0048] In this embodiment, a diagnostic trigger circuit and a diagnostic control switch MP10 are also provided. That is, when the diagnostic trigger circuit receives a current detection command, it turns off the diagnostic control switch MP10, thereby turning on the current detection switch 3 under the control of the operational amplifier circuit 2, thus starting the current detection circuit to perform current detection.

[0049] For example, when the current sensing switch 3 is a PMOS transistor, the gate of the PMOS transistor is the control terminal of the current sensing switch 3, the source of the PMOS transistor is the first terminal of the current sensing switch 3, and the drain of the PMOS transistor is the second terminal of the current sensing switch 3, when the diagnostic trigger circuit does not receive a current sensing command, it controls the diagnostic switch to turn on, and the gate voltage of the current sensing switch 3 is pulled up to the power supply voltage and turned off. Conversely, when the diagnostic trigger circuit receives a current sensing command, it controls the diagnostic switch to turn off, and the gate voltage of the current sensing switch is controlled by the operational amplifier circuit 2.

[0050] Based on this, the current sensing switch 3 can be turned off when current sensing is not required, thereby reducing losses.

[0051] In a preferred embodiment, the diagnostic control switch MP10 is a PMOS transistor, the gate of the PMOS transistor is the control terminal of the diagnostic control switch MP10, the source of the PMOS transistor is the first terminal of the diagnostic control switch MP10, the drain of the PMOS transistor is the second terminal of the diagnostic control switch MP10, and the diagnostic trigger circuit includes a first pull-up resistor R3 and a diagnostic trigger switch MN10.

[0052] The first end of the first pull-up resistor R3 is connected to the power supply, and the second end of the first pull-up resistor R3 is connected to the control terminal of the diagnostic control switch MP10.

[0053] The first terminal of the diagnostic trigger switch MN10 is connected to the second terminal of the first pull-up resistor R3. The second terminal of the diagnostic trigger switch MN10 is grounded. The second terminal of the first pull-up resistor R3 and the first terminal of the diagnostic trigger switch MN10 are the output terminals of the diagnostic trigger circuit. The diagnostic trigger switch MN10 is used to turn off when it receives a current detection command at its control terminal, so that the output terminal of the diagnostic trigger circuit outputs a high level, and to turn on when it does not receive a current detection command, so that the output terminal of the diagnostic trigger circuit outputs a low level.

[0054] When the diagnostic control switch MP10 is a PMOS transistor, it turns on when the gate-source voltage VGS is less than the turn-on threshold VTH, and turns off otherwise. Therefore, when the diagnostic trigger switch MN10 of the diagnostic trigger circuit does not receive a current detection command, it turns on, thereby pulling the gate voltage of the diagnostic control switch MP10 low to a low level. This causes the gate-source voltage VGS to be less than the turn-on threshold VTH, at which point the diagnostic control switch MP10 turns on, the current detection switch 3 is turned off, and the current detection circuit is in a power-off state. When the diagnostic trigger switch MN10 of the diagnostic trigger circuit receives a current detection command, it turns off, and the gate voltage of the diagnostic control switch MP10 is pulled up to the power supply voltage. This causes the gate-source voltage VGS to be not less than the turn-on threshold VTH, at which point the diagnostic control switch MP10 turns off, the current detection switch 3 is controlled by the operational amplifier circuit 2, and the current detection circuit is in a power-on state.

[0055] Please refer to Figure 5 , Figure 5 This is a schematic diagram of a diagnostic trigger circuit provided in this application. The diagnostic trigger switch MN10 is an NMOS transistor. An inverter can be connected to the gate of MN10 to make the current detection command high. When the current detection command received at the input of the inverter is high, the output is low, thereby pulling down the gate voltage of MN10 and turning it off. The first pull-up resistor R3 pulls up the voltage at the first terminal of MN10. The diagnostic control switch MP10 is a PMOS transistor, thus turning it off. When the current detection switch 3 is a PMOS transistor, the current detection... The source of switch transistor 3 is connected to the power supply, and its drain is grounded. Therefore, the gate voltage of the current detection switch transistor 3 is controlled by the operational amplifier circuit 2. When the input of the inverter does not receive a current detection command, it outputs a high level, thereby pulling up the gate voltage of the diagnostic trigger switch transistor MN10, which in turn turns on the diagnostic trigger switch transistor MN10, pulls down the voltage at the first terminal of the diagnostic trigger switch transistor MN10, pulls down the gate voltage of the diagnostic control switch transistor MP10, and turns on the diagnostic control switch transistor MP10, which in turn pulls up the gate voltage of the current detection switch transistor 3, which in turn turns off the current detection switch transistor 3, thus stopping the current detection circuit.

[0056] In a preferred embodiment, the current detection switch 3 is a PMOS transistor, the gate of the PMOS transistor is the control terminal of the current detection switch 3, the source of the PMOS transistor is the first terminal of the current detection switch 3, and the drain of the PMOS transistor is the second terminal of the current detection switch 3. The current detection circuit also includes a diagnostic shutdown voltage divider circuit, a first diagnostic shutdown switch MP9, and a second diagnostic shutdown switch MP12.

[0057] The first terminal of the diagnostic shutdown voltage divider circuit is connected to the power supply, and the second terminal is connected to the first terminal of the first diagnostic shutdown switch MP9. The control terminal of the first diagnostic shutdown switch MP9 is connected between the output terminal of the output-side switch ON and the second input terminal INP of the operational amplifier circuit 2. The second terminal of the first diagnostic shutdown switch MP9 serves as the ground terminal. The first terminal of the first diagnostic shutdown switch MP9 is connected to the control terminal of the second diagnostic shutdown switch MP12. The first terminal of the second diagnostic shutdown switch MP12 is connected to the power supply, and the second terminal of the second diagnostic shutdown switch MP12 is connected to the control terminal of the current detection switch 3.

[0058] The first diagnostic shutdown switch MP9 is used to turn on when the current detection circuit is in an overload operating state, so as to turn on the second diagnostic shutdown switch MP12, thereby turning off the current detection switch MP14.

[0059] When the voltage at the output terminal of the ON-side switch drops to a preset voltage threshold, it indicates that the current detection circuit is in an overloaded operating state.

[0060] The preset voltage threshold is negatively correlated with the preset overcurrent threshold.

[0061] In this embodiment, considering that the voltage at the second terminal of the output-side switch ON decreases as the supply current increases, the voltage at the second terminal of the output-side switch ON can reflect the change in the supply current. When the voltage at the second terminal of the output-side switch ON decreases to a preset voltage threshold, it reflects that the supply current has risen to a preset overcurrent threshold. At this time, not only can the current detection module 4 detect the abnormal supply current, but in order to protect the current detection circuit, the second diagnostic shutdown switch MP12 will also be turned on, thereby turning off the current detection switch 3 to shut down the current detection circuit.

[0062] Please refer to Figure 6 , Figure 6This application provides a schematic diagram of a diagnostic voltage divider circuit and a first diagnostic shutdown switch MP9. The diagnostic voltage divider circuit includes diagnostic voltage divider switches. The first terminal of the diagnostic voltage divider switch is connected to the power supply, and the second terminal is connected to the first terminal of the first diagnostic shutdown switch MP9. The diagnostic voltage divider switch, the first diagnostic shutdown switch MP9, and the second diagnostic shutdown switch MP12 are all PMOS transistors. When the gate of the diagnostic voltage divider switch is at a low level, i.e., no circuit fault signal is received, it is turned on. If the power supply current is normal, the voltage at the output terminal of the ON switch on the output side is greater than a preset voltage threshold, and the first diagnostic shutdown switch MP9 remains in the off state. When the first terminal of the switching transistor MP9 is high, the second diagnostic shutdown switching transistor MP12 is turned off, and the gate voltage of the current detection switching transistor 3 is controlled by the operational amplifier circuit 2. If the load increases and the supply current is abnormal, the voltage at the output terminal of the ON-side switching transistor gradually decreases until it drops to a preset voltage threshold. The first diagnostic shutdown switching transistor MP9 is turned on, and the difference between the gate voltage and the source voltage of the first diagnostic shutdown switching transistor MP9 turns on the second diagnostic shutdown switching transistor MP12. The gate voltage of the current detection switching transistor 3 is pulled high and turned off. At this time, the preset voltage threshold can be, but is not limited to, the sum of the turn-on thresholds of the two PMOS transistors, the first diagnostic shutdown switching transistor MP9 and the second diagnostic shutdown switching transistor MP12. Figure 6 In this circuit, FAULT is the circuit fault signal, INP is the second input terminal of the operational amplifier circuit 2, which is the port connected to the output terminal of the output-side switch transistor ON, and FGND is the output terminal of the first bias circuit.

[0063] In a preferred embodiment, the power supply terminal of the operational amplifier circuit 2 is connected to a power supply, and the current detection circuit also includes a first bias circuit.

[0064] The power supply terminal of the first bias circuit is connected to the power supply, the second terminal is grounded, and the output terminal is connected to the ground terminal of the operational amplifier circuit 2. It is used to output a preset floating ground voltage when no circuit fault signal is received. The voltage difference between the preset floating ground voltage and the power supply voltage is the preset voltage difference. When a circuit fault signal is received, the power supply voltage is output.

[0065] The ground terminal of the first diagnostic switch MP9 is connected to the output terminal of the first bias circuit.

[0066] In this embodiment, considering that when the output voltage of the power supply, i.e. the power supply voltage, is large, it may cause overvoltage damage to the components in the current detection circuit, a first bias circuit is also provided. The first bias circuit provides a preset floating ground voltage for the operational amplifier circuit 2. Since the voltage difference between the preset floating ground voltage and the power supply voltage is a preset voltage difference, the current detection circuit can be applied to circuits with a wider range of power supply voltages, thereby expanding the application scenario range of the current detection circuit and improving the utilization rate of the current detection circuit.

[0067] In a preferred embodiment, the first bias circuit includes a first current source Ig1, a first current mirror circuit, a second current mirror circuit, a third current mirror circuit, a first bias drive switch MN701, a first circuit fault control switch MN9, and a first circuit fault control resistor R2.

[0068] The input-side switch MN5 of the first current mirror circuit is connected between the output terminal of the first current source Ig1 and the ground terminal; the input-side switch MP5 of the second current mirror circuit is connected in series between the power supply and the output-side switch MN6 of the first current mirror circuit; the input-side switch MN7 of the third current mirror circuit is connected in series between the output-side switch MP6 of the second current mirror circuit and the ground terminal; the first circuit fault control resistor R2 and the first circuit fault control switch MN9 are connected in series between the power supply and the output-side switch MN8 of the third current mirror circuit; the connection point between the first circuit fault control resistor R2 and the first circuit fault control switch MN9 serves as the output terminal of the first bias circuit and is connected to the ground terminal of the operational amplifier circuit 2; the first terminal of the first bias drive switch MN701 is connected to the control terminal of the input-side switch MN5 and the control terminal of the output-side switch MN6 in the first current mirror circuit, and is used to control the input-side switch MN5 and the output-side switch MN6 in the first current mirror circuit to conduct when the first bias enable signal is received;

[0069] The first current mirror circuit receives the output current of the first current source Ig1 through its own input-side switch MN5 and mirrors it to its own output-side switch MN6; the second current mirror circuit receives the current on the output-side switch MN6 of the first current mirror circuit through its own input-side switch MP5 and mirrors it to its own output-side switch MP6; the third current mirror circuit receives the current on the output-side switch MP6 of the second current mirror circuit through its own input-side switch MN7 and mirrors it to its own output-side switch MN8 when the first circuit fault control switch MN9 is turned on.

[0070] The first circuit fault control switch MN9 is used to turn on when no circuit fault signal is received, so that the output terminal of the first bias circuit outputs a preset floating ground voltage; and to turn off when a circuit fault signal is received, so that the output terminal of the first bias circuit outputs a power supply voltage.

[0071] Please refer to Figure 7 , Figure 7This application provides a schematic diagram of a first bias circuit, wherein the gates of the input-side switch MN5 and the output-side switch MN6 of the first current mirror circuit are connected to a first bias drive switch MN701. The first bias drive switch MN701 is an NMOS transistor. When the gate of the first bias drive switch MN701 receives a first bias enable signal, the first bias drive switch MN701 is turned off, thereby causing the gate voltages of the input-side switch MN5 and the output-side switch MN6 of the first current mirror circuit to be high and thus turned on. The input-side switch MN5 of the first current mirror circuit is connected to a first current source. Between Ig1 and the ground terminal, the current on the input-side switch MN5 of the first current mirror circuit is the output current of the first current source Ig1. The output-side switch MN6 of the first current mirror circuit mirrors the current on the input-side switch MN5. Since the output-side switch MN6 of the first current mirror circuit is connected in series with the input-side switch MP5 of the second current mirror circuit, the current on the input-side switch MP5 of the second current mirror circuit is the same as the current on the output-side switch MN6 of the first current mirror circuit. The output-side switch MP6 of the second current mirror circuit mirrors the current on the input-side switch MP5. Since the output-side switch MP6 of the second current mirror circuit is connected in series with the input-side switch MN7 of the third current mirror circuit, the current on the input-side switch MN7 of the third current mirror circuit is the same as the current on the output-side switch MP6 of the second current mirror circuit. The first terminal of the first circuit fault control resistor R2 is connected to the power supply, the second terminal of the first circuit fault control resistor R2 is connected to the first terminal of the first circuit fault control switch MN9, and the second terminal of the first circuit fault control switch MN9 is connected to the first terminal of the output-side switch MN8 of the third current mirror circuit. When the first circuit fault control switch MN9... When the signal received by the gate is the opposite of the circuit fault signal, that is, when FAULT is low and FAULT is high, it means that no circuit fault signal has been received. The first circuit fault control switch MN9 is an NMOS transistor, so the first circuit fault control switch MN9 is turned on, which causes the output switch MN8 of the third current mirror circuit to mirror the current on the input switch MN7. That is, the current on the output switch MN8 can be determined based on the output current of the first current source Ig1, combined with the current mirror ratio in the first current mirror circuit, the second current mirror circuit and the third current mirror circuit.Since the first circuit fault control switch MN9 is connected in series with the output switch MN8 of the third current mirror circuit, the current on the first circuit fault control switch MN9 is the same as the current on the output switch MN8 of the third current mirror circuit. Since the output terminal of the first bias circuit is connected to the ground terminal of the operational amplifier circuit 2, the current between the ground terminal of the operational amplifier circuit 2 and the output terminal of the first bias circuit has no static power consumption in the digital module and is a proportional mirror current in the high-gain operational amplifier. Therefore, the current from the ground terminal of the operational amplifier circuit 2 to the output terminal of the first bias circuit is constant, which in turn makes the current on the first circuit fault control resistor R2 constant. Thus, the preset floating ground voltage is independent of the current and only changes with the power supply voltage, ensuring the wide operating voltage range of the current detection circuit and the operating voltage range of the fault signal transmission circuit.

[0072] Wherein, EN_N is the first bias enable signal when it is low.

[0073] It should be noted that the current mirror circuits in the first and second bias circuits and the current mirror circuit connected to the ON-side switch on the output side are not the same circuit.

[0074] The relationship between the current at the ground terminal of operational amplifier circuit 2 and the connection point between the first circuit fault control resistor R2 and the first circuit fault control switch MN9, the current on the first circuit fault control resistor R2, and the current on the first circuit fault control switch MN9 is as follows:

[0075] ;

[0076] ;

[0077] in, The magnitude of the current through the fault control resistor R2 in the first circuit. The magnitude of the current between the ground terminal of operational amplifier circuit 2 and the output terminal of the first bias circuit. The magnitude of the current on the control switch MN9 is determined by the fault in the first circuit. To preset the floating ground voltage, This is the power supply voltage. Let R2 be the resistance value of the fault control resistor in the first circuit. It can be seen that, due to... and If it remains unchanged, then the voltage difference between the preset floating ground voltage and the power supply voltage is the preset voltage difference, and the preset voltage difference is... .

[0078] As a preferred embodiment, it also includes a second bias circuit, a first stop switch transistor MP7, a second stop switch transistor MN11, a third stop switch transistor MP11, a fourth stop switch transistor MN12, a fifth stop switch transistor MP13, and a clamping circuit.

[0079] The power supply terminal of the second bias circuit is connected to a power source, the second terminal is grounded, and the output terminal is connected to the control terminal of the first stop switch transistor MP7 and the control terminal of the fifth stop switch transistor MP13. The first terminal of the first stop switch transistor MP7 is connected to a power source, the second terminal of the first stop switch transistor MP7 is connected to the first terminal of the second stop switch transistor MN11, and the second terminal of the second stop switch transistor MN11 is connected to the output terminal of the first bias circuit. The control terminal of the third stop switch transistor MP11 is connected to the first terminal of the second stop switch transistor MN11, the first terminal of the third stop switch transistor MP11 is connected to a power source, and the third stop switch... The second terminal of the shut-off transistor MP11 is connected to the first terminal of the second diagnostic shut-off switch transistor MP12; the control terminal of the fourth stop switch transistor MN12 is connected to the first terminal of the second stop switch transistor MN11, the first terminal of the fourth stop switch transistor MN12 is connected to the control terminal of the current detection switch transistor 3, and the second terminal of the fourth stop switch transistor MN12 is grounded; the first terminal of the fifth stop switch transistor MP13 is connected to the power supply, and the second terminal of the fifth stop switch transistor MP13 is connected to the first terminal of the current detection switch transistor 3; the first terminal of the clamping circuit is connected to the second terminal of the current detection switch transistor 3, and the second terminal of the clamping circuit is grounded.

[0080] The second bias circuit is used to output a fault indication signal when a circuit fault signal is received, so as to turn on the first stop switch transistor MP7 and the fifth stop switch transistor MP13.

[0081] The second stop switch transistor MN11 is used to turn off when it receives a circuit fault signal at its own control terminal, so that the third stop switch transistor MP11 is turned off and the fourth stop switch transistor MN12 is turned on.

[0082] The fourth stop switch transistor MN12 is used to turn on the current detection switch transistor 3 after it turns on, and to make the current detection switch transistor 3 output the fault indication current of itself and the circuit in series with the fifth stop switch transistor MP13.

[0083] The clamping circuit is used to clamp the voltage at the second terminal of the current detection switch 3 to a preset clamping voltage when the current detection switch 3 outputs a fault indication current.

[0084] This embodiment introduces the processing of circuit fault signals. The system is usually equipped with a temperature detection device or other safety monitoring device. When an abnormality is detected, a circuit fault signal will be output. In order to avoid the current detection circuit from being affected by the abnormality in the system, a second bias circuit is also set. When a circuit fault signal is received, the second bias circuit outputs a fault indication signal. The first stop switch transistor MP7, the second stop switch transistor MN11, the third stop switch transistor MP11, the fourth stop switch transistor MN12, and the fifth stop switch transistor MP13 work together to control the current detection circuit to stop current detection, and control the current detection switch transistor 3 to output a large fault indication current, thereby prompting the staff to troubleshoot the system and maintain the circuit.

[0085] For example, please refer to Figure 8 , Figure 8 This application provides a schematic diagram of the connection of a stop switch transistor. When the current detection switch transistor 3 is a PMOS transistor, the first stop switch transistor MP7 is a PMOS transistor, the second stop switch transistor MN11 is an NMOS transistor, the third stop switch transistor MP11 is a PMOS transistor, the fourth stop switch transistor MN12 is an NMOS transistor, and the fifth stop switch transistor MP13 is a PMOS transistor, the second bias circuit outputs a fault indication signal when it receives a circuit fault signal. The circuit fault signal is high level, and the fault indication signal is low level. The first stop switch transistor MP7 is turned on, the second stop switch transistor MN11 is turned off, the first terminal of the second stop switch transistor MN11, which is also the second terminal of the first stop switch transistor MP7, is high level, the third stop switch transistor MP11 (the PMOS transistor) is turned off, and the fourth stop switch transistor MP13 is turned off. When switch MN12 is turned on, the gate voltage of the current detection circuit is low, and current detection switch 3 remains on. However, since the first bias circuit outputs the power supply voltage at this time, the operational amplifier circuit 2 stops working, and the current detection circuit stops. In order to indicate the presence of a fault in the circuit, the fifth stop switch MP13 is turned on due to the low output of the second bias circuit. The large fault indication current flowing through the fifth stop switch MP13 is output through the current detection switch 3 to prevent the current detection module 4 from being damaged by overvoltage. The clamping circuit clamps the voltage at the second terminal of the current detection switch 3 to a preset clamping voltage, ensuring that the current detection module 4 can detect the fault indication current while protecting the current detection module 4.

[0086] Furthermore, the second terminal of the second stop switch transistor MN11 is connected to the output terminal of the first bias circuit. When the second bias circuit does not receive a circuit fault signal, it outputs a high level. A level converter can also be set at the gate of the second stop switch transistor MN11. When no circuit fault signal is received, that is, when the circuit fault signal is low, FAULTB is high. The first bias circuit outputs a preset floating ground voltage. The level converter converts FAULTB into a voltage between the power supply voltage and the preset floating ground voltage. The first stop switch transistor MP7 is turned off, the second stop switch transistor MN11 is turned on, the first terminal of the second stop switch transistor MN11, that is, the second terminal of the first stop switch transistor MP7, is low. The third stop switch transistor MP11 is turned on, the fourth stop switch transistor MN12 is turned off, and the gate voltage of the current detection circuit is controlled by the operational amplifier circuit 2.

[0087] Figure 4 The CLAMP in this context is the clamping circuit.

[0088] In a preferred embodiment, the second bias circuit includes a second current source Ig2, a fourth current mirror circuit, a fifth current mirror circuit, a sixth current mirror circuit, a second bias drive switch MN901, a second circuit fault control switch MP3, a third circuit fault control switch MP4, and a second circuit fault control resistor R1.

[0089] The input-side switch MN1 of the fourth current mirror circuit is connected between the output terminal of the second current source Ig2 and the ground terminal; the input-side switch MP1 of the fifth current mirror circuit is connected in series between the power supply and the output-side switch MN2 of the fourth current mirror circuit; the input-side switch MN3 of the sixth current mirror circuit and the second circuit fault control switch MP3 are connected in series between the output-side switch MP2 of the fifth current mirror circuit and the ground terminal; the third circuit fault control switch MP4 and the second circuit fault control resistor R1 are connected in parallel between the power supply and the output-side switch MN4 of the sixth current mirror circuit; the connection point between the second circuit fault control resistor R1 and the output-side switch MN4 of the sixth current mirror circuit serves as the output terminal of the second bias circuit and is connected to the control terminal of the first stop switch MP7 and the control terminal of the fifth stop switch MP13; the first terminal of the second bias drive switch MN901 is connected to the control terminal of the input-side switch MN1 and the control terminal of the output-side switch MN2 in the fourth current mirror circuit, and is used to control the input-side switch MN1 and the output-side switch MN2 in the fourth current mirror circuit to conduct when the first bias enable signal is received;

[0090] The fourth current mirror circuit receives the output current of the second current source Ig2 through its own input-side switch MN1 and mirrors it to its own output-side switch MN2; the fifth current mirror circuit receives the current on the output-side switch MN2 of the fourth current mirror circuit through its own input-side switch MP1 and mirrors it to its own output-side switch MP2; the sixth current mirror circuit receives the current on the output-side switch MP2 of the fifth current mirror circuit through its own input-side switch MN3 when the second circuit fault control switch MP3 is turned on, and mirrors it to its own output-side switch MN4.

[0091] The second circuit fault control switch MP3 is used to turn off when no circuit fault signal is received, so that the circuit containing the input-side switch MN3 of the sixth current mirror circuit is disconnected, and the voltage at the output terminal of the second bias circuit is pulled up to the power supply voltage by the second circuit fault control resistor R1; and when a circuit fault signal is received, it is turned on, so that the third circuit fault control switch MP4 and the fifth stop switch MP13 are mirrored, so that the third circuit fault control switch MP4 receives most of the current on the output-side switch MN4 of the sixth current mirror circuit and mirrors it to the fifth stop switch MP13. The fifth stop switch MP13 will receive the current as the fault indication current. It should be noted that the current received by the third circuit fault control switch MP4 is greater than the current on the second circuit fault control resistor R1.

[0092] Please refer to Figure 9 , Figure 9This application provides a schematic diagram of a second bias circuit, wherein the gates of the input-side switch MN1 and the output-side switch MN2 of the fourth current mirror circuit are connected to the second bias drive switch MN901, which is an NMOS transistor. When the gate of the second bias drive switch MN901 receives the first bias enable signal EN_N, i.e., when the first bias enable signal EN_N is low, the second bias drive switch MN901 is turned off, thereby turning on the gate voltages of the input-side switch MN1 and the output-side switch MN2 of the fourth current mirror circuit, which are high. The input-side switch MN1 of the fourth current mirror circuit is connected between the second current source Ig2 and the ground terminal. The current is the output current of the second current source Ig2. The output switch MN2 of the fourth current mirror circuit mirrors the current on the input switch MN1. Since the output switch MN2 of the fourth current mirror circuit is connected in series with the input switch MP1 of the fifth current mirror circuit, the current on the input switch MP1 of the fifth current mirror circuit is the same as the current on the output switch MN2 of the fourth current mirror circuit. When the gate of the second circuit fault control switch MP3 receives a high level FAULTB, that is, when the circuit fault signal is low, the second circuit fault control switch MP3 is turned off. The first end of the second circuit fault control resistor R1 is connected to the power supply, and the second end of the second circuit fault control resistor R1 is the output end of the second bias circuit, which outputs a high level.When the gate of the second circuit fault control switch MP3 receives a low level FAULTB (i.e., FAULT is high), the second circuit fault control switch MP3 is turned on. The output switch MP2 of the fifth current mirror circuit mirrors the current on the input switch MP1. Since the output switch MP2 of the fifth current mirror circuit is connected in series with the input switch MN3 of the sixth current mirror circuit, the current on the input switch MN3 of the sixth current mirror circuit is the same as the current on the output switch MP2 of the fifth current mirror circuit. The first terminal of the second circuit fault control resistor R1 is connected to the power supply, and the second terminal of the second circuit fault control resistor R1 is connected to the first terminal of the output switch MN4 of the sixth current mirror circuit. The first terminal of the third circuit fault control switch MP4 is connected to the power supply, and the second terminal of the third circuit fault control switch MP4 is connected to the first terminal of the output switch MN4 of the sixth current mirror circuit. This causes the output switch MN4 of the sixth current mirror circuit to mirror the current on the input switch MN3. In other words, based on the output current of the second current source Ig2, combined with the fourth current mirror circuit and the fifth current mirror circuit... The current mirror ratio in the current mirror circuit and the sixth current mirror circuit determines the current on the output-side switch MN4. Since the fault control switch MP4 of the third circuit is connected in parallel with the fault control resistor R1 of the second circuit, and then in series with the output-side switch MN4 of the sixth current mirror circuit, the sum of the currents in the third circuit fault control switch MP4 and the second circuit fault control resistor R1 is the current on the output-side switch MN4 of the sixth current mirror circuit. The impedance of the third circuit fault control switch MP4 is relatively low, so it can be approximated that the current on the third circuit fault control switch MP4 is the same as the current on the output-side switch MN4 of the sixth current mirror circuit. Since the gate and source of the third circuit fault control switch MP4 are connected, and also connected to the gate of the fifth stop switch MP13, and the sources of both the third circuit fault control switch MP4 and the fifth stop switch MP13 are connected to the power supply, the third circuit fault control switch MP4 and the fifth stop switch MP13 form current mirror circuit 1. The fifth stop switch MP13 mirrors the current on the third circuit fault control switch MP4 and outputs it as the fault indication current through the current detection switch 3.

[0093] In a preferred embodiment, the clamping circuit includes a first clamping switch MP102, a first voltage divider resistor R102, a second clamping switch MN101, and a second voltage divider resistor R103.

[0094] The first terminal of the first clamping switch transistor MP102 is connected to the second terminal of the current detection switch transistor 3, the second terminal of the first clamping switch transistor MP102 is connected to the first terminal of the second clamping switch transistor MN101, and the second terminal of the second clamping switch transistor MN101 is grounded.

[0095] The control terminal of the first clamping switch MP102 is connected to the first terminal of the first voltage divider resistor R102, and the control terminal of the second clamping switch MN101 is connected to the first terminal of the second voltage divider resistor R103. The first terminals of the first voltage divider resistor R102 and the first terminals of the second voltage divider resistor R103 are connected and connected to a second bias enable signal. The level of the second bias enable signal is opposite to that of the first bias enable signal.

[0096] The first clamping switch MP102 and the second clamping switch MN101 are used to turn on when the current detection switch 3 outputs a fault indication current and the voltage at the second terminal of the current detection switch 3 is greater than the voltage value of the second bias enable signal, so as to clamp the voltage at the second terminal of the current detection switch 3 to a preset clamping voltage.

[0097] Specifically, please refer to Figure 10 , Figure 10 This is a schematic diagram of a clamping circuit provided in this application. It also includes a continuously active switch MP101 to raise the preset clamping voltage. The continuously active switch MP101 and the first clamping switch MP102 are PMOS transistors, and the second clamping switch MN101 is an NMOS transistor. The source of the continuously active switch MP101 is connected to the second terminal of the current detection switch 3, i.e., to the drain of the current detection switch 3. The gate of the continuously active switch MP101 is grounded through a grounding resistor R101, thus maintaining the continuously active switch MP101. When EN is high, it represents the second bias enable signal. EN and EN_N have opposite levels. When EN_N is high, the first and second bias circuits are not working. When the current detection circuit is in a shutdown state, EN is low, and the second clamping switch MN101 in the clamping circuit cannot be turned on. Therefore, the clamping circuit is in a non-operating state. However, when EN_N is low and EN is high, the second clamping switch MN101 is turned on, and the gate of the first clamping switch MP102 is at a digital high level. When the source voltage of the first clamping switch MP102 is higher than the EN voltage by a turn-on threshold voltage, the clamping circuit operates, clamping the voltage at the second terminal of the current detection switch MP14 to a preset clamping voltage. The preset clamping voltage is shown in the following formula:

[0098] ;

[0099]

[0100] The voltage at the second terminal of the current sensing switch MP14 is used. For the voltage divider of the always-on switching transistor MP101, This is the absolute value of the gate-source voltage of the first clamping switch MP102. This refers to the voltage value of the second bias enable signal, that is, the voltage value of EN when EN_N is low and EN is high. This refers to the current on the first clamping switch, MP102. The electron mobility of the PMOS transistor. Where W is the gate oxide capacitance per unit area, W is the physical width of the conductive channel below the MOSFET gate, L is the physical length of the conductive channel below the MOSFET gate, and W / L is the width-to-length ratio. This is the gate-source voltage of the first clamping switch MP102. This is the turn-on threshold voltage of the PMOS transistor, which is also the turn-on threshold voltage of the always-on switch MP101 and the first clamping switch MP102.

[0101] Combining the two equations above, we can obtain the voltage at the second terminal of the current sensing switch MP14. The current on the first clamping switch MP102 Relationship:

[0102] ;

[0103] It can be seen that the voltage at the second terminal of the current sensing switch MP14 is... The current on the first clamping switch MP102 As a non-linear relationship, with The increase, Increase slowly to achieve clamping.

[0104] In a preferred embodiment, the circuit under test includes multiple sub-channels under test, each sub-channel under test includes an output-side switch ON, and each sub-channel under test corresponds to a current mirror circuit 1.

[0105] The current detection circuit includes multiple current mirror circuits 1 and multiple switching modules, each of which corresponds to the sub-channel under test.

[0106] The first input terminal of each switch module is connected to the second terminal of the corresponding output-side switch transistor ON. The first output terminal of each switch module is connected to the second input terminal of the operational amplifier circuit 2. The second input terminal of each switch module is connected to the output terminal of the corresponding current mirror circuit 1. The second output terminal of each switch module is connected to the first input terminal of the corresponding operational amplifier circuit 2. The third input terminal of each switch module is connected to the output terminal of the corresponding current mirror circuit 1. The third output terminal of each switch module is connected to the first terminal of the current detection switch transistor 3.

[0107] Each switch module is used to turn on when a channel current detection command is received.

[0108] When multiple power supply circuits are considered in a conductive circuit, a switching module is also set up to detect the current of each power supply circuit. Users can send channel current detection commands to the switching module as needed, thereby connecting the corresponding sub-channel under test to the current detection circuit for current detection, thus improving the efficiency of multi-channel current detection. Note that the channel current detection command and the current detection command are different commands.

[0109] Specifically, such as Figure 4 As shown in the diagram, taking the current detection circuit capable of detecting the current on four tested sub-channels as an example, CH1, CH2, CH3, and CH4 are the structures of the output-side switching transistors of the four tested sub-channels and the corresponding current mirror circuits, respectively. That is, the circuit structures of CH1, CH2, CH3, and CH4 are all as shown in the diagram. Figure 2 As shown, and Figure 2 In this context, ON stands for ON_CHX, which is the output-side switch of the Xth sub-channel under test; CM_ON stands for CM_ON_CHX, which is the mirror transistor in the current mirror circuit of the Xth sub-channel under test; OUT stands for OUTX, which is the second terminal of the output-side switch of the Xth sub-channel under test; and FB_CHX is the output terminal of the current mirror circuit corresponding to the Xth sub-channel under test. In these contexts, X can be any number from 1, 2, 3, to 4. Figure 4 In this diagram, SW1 is the switch module corresponding to the first sub-channel under test, SW2 is the switch module corresponding to the second sub-channel under test, SW3 is the switch module corresponding to the third sub-channel under test, and SW4 is the switch module corresponding to the fourth sub-channel under test. When the channel current detection command is the channel current detection command for the first sub-channel under test, SW1 closes, and so on. When a specific sub-channel under test needs to be detected, the channel current detection command is the corresponding channel current detection command for that sub-channel, and the corresponding switch module closes. It should be noted that only one sub-channel under test can be detected at a time, meaning that only one switch channel is conducting at any given time.

[0110] The following explanation is based on the images above:

[0111] In each diagram, VS represents the power supply, DIAG_EN represents the current detection command when it is high, FAULT represents the circuit fault signal of other chip protection modules (such as temperature protection, overvoltage protection, undervoltage protection, etc.), FAULT and FAULTB have opposite voltages, OUTX represents the second terminal of the output-side switch in the Xth sub-channel under test, and SWX represents the switch module corresponding to the Xth sub-channel under test.

[0112] When DIAG_EN is high, MN10 is off, point B has a high voltage VS, MP10 is off, and the current detection circuit works normally. When DIAG_EN is low, MN10 is on, point B is at a low level, MP10 is on, pulling the gate voltage of MP14 high, turning off MP14, cutting off the feedback path of the current detection circuit, and shutting down the current detection circuit. When EN_N is 0, the first and second bias circuits work normally; when EN_N is 1, the first and second bias circuits are off, and the current detection circuit does not work.

[0113] When the current detection circuit is working normally, DIAG_EN is high, EN_N is low, FAULTB is high (the chip is not in fault mode), and FAULT is low. In the second bias circuit, the second circuit fault control switch MP3 is turned off, so the output switch MN4 of the sixth current mirror circuit is not turned on, and point A outputs a high voltage VS. The diagnostic trigger switch MN10 is turned off, and point B outputs a high voltage VS. The first stop switch MP7 is turned off, and the second stop switch MN11 is turned on, pulling point C to the preset floating ground voltage. In the diagnostic voltage divider circuit, the diagnostic voltage divider switch MP8 is turned on. When no overcurrent abnormality occurs in the tested sub-channel, the first diagnostic shutdown switch MP9 is turned off, and a high voltage VS is output at point D. In the first bias circuit, the first circuit fault control switch MN9 is turned on, and the output terminal FGND of the first bias circuit generates a voltage that varies with VS, that is, the voltage difference between the preset floating ground voltage and the power supply voltage VS is the preset voltage difference.

[0114] exist Figure 4 In this circuit, the diagnostic control switch MP10, the second diagnostic shutdown switch MP12, the fifth shutdown switch MP13, and the fourth shutdown switch MN12 are turned off. OUTX is connected to the positive input terminal of operational amplifier circuit 2, i.e., the second input terminal, after passing through SWX. The feedback signal VFB_CHX from the output terminal of the current mirror circuit of the Xth tested sub-channel is connected to the negative input terminal of operational amplifier circuit 2, i.e., the first input terminal, after passing through the switch module SWX. The output terminal of operational amplifier circuit 2 is connected to the gate of current detection switch MP14, and after passing through the source output of current detection switch MP14, it reaches VFB_CHX after passing through switch SWX. The negative feedback loop of the current detection circuit is turned on.

[0115] The second terminal of the current-sensing switch MP14, i.e., the drain port, is connected to an external current-sensing module. This current-sensing module can include a current-sensing resistor and a voltage-sensing module. The voltage-sensing module is based on the second terminal of the current-sensing switch MP14, i.e. Figure 4The voltage across the current sensing resistor at the CS terminal and the resistance value of the current sensing resistor are used to calculate the mirror current of the current sensing switch MP14 using Ohm's law. Then, the supply current of the circuit under test is inferred from the current mirror ratio. When the current sensing circuit is working normally and the supply current is normal, the current sensing circuit outputs the mirror current according to the set current mirror ratio, and the clamping circuit does not work at this time.

[0116] During normal operation, the third shutdown switch MP11 is turned on, FAULT is low, and the diagnostic voltage divider switch MP8 is turned on. The voltage at point D is affected by the voltage at the INP terminal. INP is connected to OUTX via the switch module SWX, meaning the voltage at INP is equal to the voltage at OUTX. When the load increases, the supply current rises, and the voltage at OUTX (INP) gradually decreases. When the voltage at OUTX falls below the turn-on threshold voltage of one PMOS transistor in VS, the voltage at point D changes with the voltage at OUTX. When the voltage at OUTX falls below the turn-on threshold voltage of both PMOS transistors in VS, the voltage difference between point D and VS causes the second diagnostic shutdown switch MP12 to turn on, the gate voltage of the current detection switch MP14 to rise, and the current detection switch MP14 to turn off, shutting down the current detection circuit. At this time, the current detection circuit is in overload operating mode.

[0117] When a fault occurs in the circuit under test, such as an overtemperature or overvoltage fault, DIAG_EN is high, EN_N is low, FAULT is high, and FAULTB is low. In the first bias circuit, the first circuit fault control switch MN9 is turned off, and a high voltage VS is output at the FGND terminal, preventing the operational amplifier circuit 2 from operating. In the second bias circuit, the second circuit fault control switch MP3 is turned on, increasing the gate voltage of the output switch MN4 of the sixth current mirror circuit. The output switch MP4 of the sixth current mirror circuit is turned on, pulling down the voltage at point A. The output at point A becomes a bias voltage, turning on the first stop switch MP7 and the fifth stop switch MP13. The output switch MP4 of the sixth current mirror circuit and the fifth stop switch MP13 form a current mirror circuit with a mirror ratio of [missing value]. The fifth stop switch transistor MP13 outputs a large current in fault mode, which is also the fault indication current. Since FAULTB is low, the second stop switch transistor MN11 is turned off, point A is the bias voltage, the first stop switch transistor MP7 is turned on, point C outputs a high voltage VS, the fourth stop switch transistor MN12 is turned on, pulling down the gate voltage of the current detection switch transistor MP14. The current detection switch transistor MP14 is turned on, so the fault indication current on the fifth stop switch transistor MP13 will flow to the CS port through the current detection switch transistor MP14. The CS terminal is clamped by the clamping circuit and outputs the preset clamping voltage.

[0118] In summary, this application uses high-gain operational amplifier negative feedback to reduce the errors of virtual short and virtual open circuits, and reduces the error of current mirror ratio caused by the voltage difference between the mirror transistor and the output-side switch. At the same time, a trimming circuit is added to further reduce the errors generated by production stress and further improve the detection accuracy.

[0119] To address the issue of a small operating voltage range in existing current detection circuits, the first bias circuit in this application can output a preset floating ground voltage, ensuring that the current detection circuit still operates normally under a wide power supply voltage.

[0120] To address the issue that existing current detection circuits cannot report fault signals, this application employs a signal transmission module that integrates with external circuit fault signals. When the chip is detected to be in fault mode, i.e., when a circuit fault signal is received, the current detection circuit will be shut down promptly, and the CS output port will output a high level. It can also detect whether the circuit is in an overload state under normal operation. If it is in an overload state, the current detection circuit will also be shut down promptly, and the CS output port will output a high level, thereby achieving rapid indication of circuit fault signals and overcurrent signals.

[0121] To address the complexity of designing multi-path current detection circuits in existing current detection circuits, this application employs a multi-path mirror current circuit. Corresponding mirror transistors and adjustment circuits are added to each path, and the signal to be fed back is connected to a high-gain negative feedback loop. This ensures that the voltage at the port of the mirror transistor is equal to that of the corresponding output-side switch, reducing mirror error. In other words, only an additional mirror transistor is added to each channel before connecting to the current detection circuit. By using different switching modules, the output current of the corresponding path can be detected, thus reducing the design complexity of multi-path current detection.

[0122] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, article, or apparatus that includes the element.

[0123] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A current detection circuit, characterized in that, The circuit under test includes an output-side switching transistor. The first terminal of the output-side switching transistor is connected to a power supply, and the second terminal of the output-side switching transistor is connected to a load when the current detection circuit is operating. The current detection circuit includes: A current mirror circuit is connected in mirror to the output-side switching transistor to mirror the power supply current of the circuit under test into a mirror current. An operational amplifier circuit is provided, wherein its first input terminal is connected to the output terminal of the current mirror circuit, its second input terminal is connected to the second terminal of the output-side switching transistor, and its output terminal is connected to the control terminal of the current-sensing switching transistor. This circuit controls the current-sensing switching transistor to conduct and adjusts the voltage at the control terminal of the current-sensing switching transistor so that the voltage between its first and second input terminals is the same. The gain of the operational amplifier circuit is greater than a preset gain, so that the ratio between the mirrored current and the supply current is the current mirror ratio. The current sensing switch has its first terminal connected to the output terminal of the current mirror circuit and its second terminal connected to the input terminal of the current sensing module, and is used to output the mirror current when it is turned on. The current detection module is used to determine the supply current based on the mirror current and the current mirror ratio, and to determine whether the supply current is greater than a preset overcurrent threshold.

2. The current detection circuit as described in claim 1, characterized in that, The current detection circuit also includes: A diagnostic trigger circuit is provided, which controls the diagnostic control switch to turn off when a current detection command is received, and otherwise controls the diagnostic control switch to turn on. The diagnostic control switch has its control terminal connected to the output terminal of the diagnostic trigger circuit. The first terminal of the diagnostic control switch is connected to the power supply, and the second terminal of the diagnostic control switch is connected to the control terminal of the current detection switch and the output terminal of the operational amplifier circuit. It is used to turn off the current detection switch when it is turned on, and to turn on the current detection switch when it is turned off.

3. The current detection circuit as described in claim 2, characterized in that, The diagnostic control switch is a PMOS transistor, the gate of the PMOS transistor is the control terminal of the diagnostic control switch, the source of the PMOS transistor is the first terminal of the diagnostic control switch, and the drain of the PMOS transistor is the second terminal of the diagnostic control switch. The diagnostic trigger circuit includes a first pull-up resistor and a diagnostic trigger switch. The first end of the first pull-up resistor is connected to the power supply, and the second end of the first pull-up resistor is connected to the control terminal of the diagnostic control switch. The first terminal of the diagnostic trigger switch is connected to the second terminal of the first pull-up resistor. The second terminal of the diagnostic trigger switch is grounded. The second terminal of the first pull-up resistor and the first terminal of the diagnostic trigger switch are the output terminals of the diagnostic trigger circuit. The diagnostic trigger switch is used to turn off when it receives the current detection command at its control terminal, so that the output terminal of the diagnostic trigger circuit outputs a high level, and to turn on when it does not receive the current detection command, so that the output terminal of the diagnostic trigger circuit outputs a low level.

4. The current detection circuit as described in claim 1, characterized in that, The current detection switch is a PMOS transistor, the gate of the PMOS transistor is the control terminal of the current detection switch, the source of the PMOS transistor is the first terminal of the current detection switch, and the drain of the PMOS transistor is the second terminal of the current detection switch. The current detection circuit also includes a diagnostic shutdown voltage divider circuit, a first diagnostic shutdown switch, and a second diagnostic shutdown switch. The first terminal of the diagnostic shutdown voltage divider circuit is connected to the power supply, and the second terminal is connected to the first terminal of the first diagnostic shutdown switch. The control terminal of the first diagnostic shutdown switch is connected between the output terminal of the output-side switch and the second input terminal of the operational amplifier circuit. The second terminal of the first diagnostic shutdown switch serves as a ground terminal. The first terminal of the first diagnostic shutdown switch is connected to the control terminal of the second diagnostic shutdown switch. The first terminal of the second diagnostic shutdown switch is connected to the power supply, and the second terminal of the second diagnostic shutdown switch is connected to the control terminal of the current detection switch. The first diagnostic shutdown switch is used to turn on when the current detection circuit is in an overload operating state, so as to turn on the second diagnostic shutdown switch and thereby turn off the current detection switch. When the voltage at the output terminal of the output-side switch drops to a preset voltage threshold, it indicates that the current detection circuit is in an overload operating state. The preset voltage threshold is negatively correlated with the preset overcurrent threshold.

5. The current detection circuit as described in claim 4, characterized in that, The power supply terminal of the operational amplifier circuit is connected to the power supply, and the current detection circuit further includes a first bias circuit. The power supply terminal of the first bias circuit is connected to the power supply, the second terminal is grounded, and the output terminal is connected to the ground terminal of the operational amplifier circuit. It is used to output a preset floating ground voltage when no circuit fault signal is received. The voltage difference between the preset floating ground voltage and the power supply voltage is a preset voltage difference. When a circuit fault signal is received, the power supply voltage is output. The ground terminal of the first diagnostic shut-off switch is connected to the output terminal of the first bias circuit.

6. The current detection circuit as described in claim 5, characterized in that, The first bias circuit includes a first current source, a first current mirror circuit, a second current mirror circuit, a third current mirror circuit, a first bias drive switch, a first circuit fault control switch, and a first circuit fault control resistor. The input-side switch of the first current mirror circuit is connected between the output terminal of the first current source and the ground terminal; the input-side switch of the second current mirror circuit is connected in series between the power supply and the output-side switch of the first current mirror circuit; the input-side switch of the third current mirror circuit is connected in series between the output-side switch of the second current mirror circuit and the ground terminal; the first circuit fault control resistor and the first circuit fault control switch are connected in series between the power supply and the output-side switch of the third current mirror circuit; the connection point between the first circuit fault control resistor and the first circuit fault control switch serves as the output terminal of the first bias circuit and is connected to the ground terminal of the operational amplifier circuit; the first terminal of the first bias drive switch is connected to the control terminal of the input-side switch and the control terminal of the output-side switch in the first current mirror circuit, and is used to control the input-side switch and the output-side switch in the first current mirror circuit to conduct when a first bias enable signal is received; The first current mirror circuit is used to receive the output current of the first current source through its own input-side switch and mirror it to its own output-side switch; the second current mirror circuit is used to receive the current on the output-side switch of the first current mirror circuit through its own input-side switch and mirror it to its own output-side switch; the third current mirror circuit is used to receive the current on the output-side switch of the second current mirror circuit through its own input-side switch and mirror it to its own output-side switch when the first circuit fault control switch is turned on. The first circuit fault control switch is used to turn on when no circuit fault signal is received, so that the output terminal of the first bias circuit outputs the preset floating ground voltage; And when the circuit fault signal is received, it is turned off so that the output terminal of the first bias circuit outputs the power supply voltage.

7. The current detection circuit as described in claim 5, characterized in that, It also includes a second bias circuit, a first stop switch transistor, a second stop switch transistor, a third stop switch transistor, a fourth stop switch transistor, a fifth stop switch transistor, and a clamping circuit; The power supply terminal of the second bias circuit is connected to the power supply, the second terminal is grounded, and the output terminal is connected to the control terminals of the first stop switch transistor and the fifth stop switch transistor. The first terminal of the first stop switch transistor is connected to the power supply, the second terminal of the first stop switch transistor is connected to the first terminal of the second stop switch transistor, and the second terminal of the second stop switch transistor is connected to the output terminal of the first bias circuit. The control terminal of the third stop switch transistor is connected to the first terminal of the second stop switch transistor, the first terminal of the third stop switch transistor is connected to the power supply, and the second terminal of the third stop switch transistor is connected to the first terminal of the second diagnostic shutdown switch transistor. The control terminal of the fourth stop switch transistor is connected to the first terminal of the second stop switch transistor, the first terminal of the fourth stop switch transistor is connected to the control terminal of the current detection switch transistor, and the second terminal of the fourth stop switch transistor is grounded. The first terminal of the fifth stop switch transistor is connected to the power supply, and the second terminal of the fifth stop switch transistor is connected to the first terminal of the current detection switch transistor. The first terminal of the clamping circuit is connected to the second terminal of the current detection switch transistor, and the second terminal of the clamping circuit is grounded. The second bias circuit is used to output a fault indication signal when the circuit fault signal is received, so as to turn on the first stop switch transistor and the fifth stop switch transistor. The second stop switch is used to turn off when it receives a circuit fault signal at its control terminal, so that the third stop switch is turned off and the fourth stop switch is turned on. The fourth shutdown switch is used to turn on the current detection switch after it turns on, and to make the current detection switch output the fault indication current of itself and the series circuit in which the fifth shutdown switch is located. The clamping circuit is used to clamp the voltage at the second terminal of the current detection switch to a preset clamping voltage when the current detection switch outputs the fault indication current.

8. The current detection circuit as described in claim 7, characterized in that, The second bias circuit includes a second current source, a fourth current mirror circuit, a fifth current mirror circuit, a sixth current mirror circuit, a second bias drive switch, a second circuit fault control switch, a third circuit fault control switch, and a second circuit fault control resistor. The input-side switch of the fourth current mirror circuit is connected between the output terminal of the second current source and the ground terminal; the input-side switch of the fifth current mirror circuit is connected in series between the power supply and the output-side switch of the fourth current mirror circuit; the input-side switch of the sixth current mirror circuit and the second circuit fault control switch are connected in series between the output-side switch of the fifth current mirror circuit and the ground terminal; the third circuit fault control switch and the second circuit fault control resistor are connected in parallel between the power supply and the output-side switch of the sixth current mirror circuit; the connection point between the second circuit fault control resistor and the output-side switch of the sixth current mirror circuit serves as the output terminal of the second bias circuit and is connected to the control terminal of the first stop switch and the control terminal of the fifth stop switch; the first terminal of the second bias drive switch is connected to the control terminal of the input-side switch and the control terminal of the output-side switch in the fourth current mirror circuit, and is used to control the input-side switch and the output-side switch in the fourth current mirror circuit to conduct when a first bias enable signal is received; The fourth current mirror circuit is used to receive the output current of the second current source through its own input-side switch and mirror it to its own output-side switch; the fifth current mirror circuit is used to receive the current on the output-side switch of the fourth current mirror circuit through its own input-side switch and mirror it to its own output-side switch; the sixth current mirror circuit is used to receive the current on the output-side switch of the fifth current mirror circuit through its own input-side switch and mirror it to its own output-side switch when the second circuit fault control switch is turned on. The second circuit fault control switch is used to turn off when no circuit fault signal is received, so that the circuit where the input-side switch of the sixth current mirror circuit is located is disconnected, and the voltage at the output terminal of the second bias circuit is pulled up to the power supply voltage by the second circuit fault control resistor; and when the circuit fault signal is received, it is turned on, so that the third circuit fault control switch and the fifth stop switch are mirrored, so that the third circuit fault control switch receives the current on the output-side switch of the sixth current mirror circuit and mirrors it to the fifth stop switch, and the fifth stop switch receives the current as the fault indication current.

9. The current detection circuit as described in claim 8, characterized in that, The clamping circuit includes a first clamping switch, a first voltage divider resistor, a second clamping switch, and a second voltage divider resistor; The first end of the first clamping switch is connected to the second end of the current detection switch, the second end of the first clamping switch is connected to the first end of the second clamping switch, and the second end of the second clamping switch is grounded. The control terminal of the first clamping switch is connected to the first terminal of the first voltage divider resistor, and the control terminal of the second clamping switch is connected to the first terminal of the second voltage divider resistor. The first terminals of the first and second voltage dividers are connected and connected to a second bias enable signal. The level of the second bias enable signal is opposite to that of the first bias enable signal. The first clamping switch and the second clamping switch are used to turn on when the current detection switch outputs the fault indication current and the voltage at the second terminal of the current detection switch is greater than the voltage value of the second bias enable signal, so as to clamp the voltage at the second terminal of the current detection switch at a preset clamping voltage.

10. The current detection circuit according to any one of claims 1-9, characterized in that, The circuit under test includes multiple sub-channels under test, each sub-channel under test includes an output-side switching transistor, and each sub-channel under test corresponds to a current mirror circuit. The current detection circuit includes multiple current mirror circuits and multiple switching modules, each of which corresponds to one of the tested sub-channels. The first input terminal of each of the switch modules is connected to the second terminal of the corresponding output-side switch transistor. The first output terminal of each of the switch modules is connected to the second input terminal of the operational amplifier circuit. The second input terminal of each of the switch modules is connected to the output terminal of the corresponding current mirror circuit. The second output terminal of each of the switch modules is connected to the first input terminal of the corresponding operational amplifier circuit. The third input terminal of each of the switch modules is connected to the output terminal of the corresponding current mirror circuit. The third output terminal of each of the switch modules is connected to the first terminal of the current detection switch transistor. Each of the aforementioned switch modules is configured to turn on upon receiving a channel current detection command.

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