Driving backplane, light-emitting substrate and display device thereof

Abstract

Embodiments of the present disclosure provide a driving backboard, a light-emitting substrate and a display device thereof, and relate to the technical field of display, which is used to reduce development cost and improve production yield. The driving backboard comprises a substrate, a driving circuit layer and a second conductive layer. The driving circuit layer is arranged on one side of the substrate. The driving circuit layer comprises a transistor, and the transistor comprises a channel portion, a first electrode, a second electrode and a control electrode. The driving circuit layer further comprises a first conductive layer, and the first electrode and the second electrode are located on the first conductive layer. The second conductive layer is arranged on the side of the driving circuit layer away from the substrate. The second conductive layer comprises a positive power line and a negative power line arranged at intervals, the positive power line is configured to be electrically connected to the positive electrode of a power supply, and the negative power line is configured to be electrically connected to the negative electrode of the power supply. The thickness of the second conductive layer is greater than the thickness of the first conductive layer. The driving backboard is used to drive a light-emitting device.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a driving backplane, a light-emitting substrate, and a display device thereof. Background Technology

[0002] With the development of light-emitting diode (LED) technology, display devices using LEDs at the sub-millimeter (Mini) or even micrometer (Micro) scale have been widely used. Among them, Micro / Mini LED display devices are widely used in various display products such as mobile phones, televisions, and laptops due to their advantages such as high brightness, high contrast, long lifespan, low power consumption, and high resolution.

[0003] In related technologies, in order to reduce the voltage drop of the positive and negative power lines, the positive and negative power lines are set on different conductive layers, which increases the number of conductive and insulating layers on the drive backplane, greatly increasing the development cost. In addition, the overlapping position of the positive and negative power lines is prone to short circuit, resulting in low production yield. Utility Model Content

[0004] The purpose of this disclosure is to provide a driving backplane, a light-emitting substrate, and a display device thereof, so as to reduce development costs and improve production yield.

[0005] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0006] On one hand, a driving backplane is provided. The driving backplane is used to connect a light-emitting chip. The driving backplane includes a substrate, a driving circuit layer, and a second conductive layer. The driving circuit layer is disposed on one side of the substrate. The driving circuit layer includes a transistor, the transistor including a channel, a first electrode, a second electrode, and a control electrode. The driving circuit layer further includes a first conductive layer, with the first electrode and the second electrode located on the first conductive layer. The second conductive layer is disposed on the side of the driving circuit layer away from the substrate. The second conductive layer includes a positive power line and a negative power line spaced apart, the positive power line being configured to be electrically connected to the positive terminal of a power supply, and the negative power line being configured to be electrically connected to the negative terminal of a power supply. The thickness of the second conductive layer is greater than the thickness of the first conductive layer.

[0007] In the aforementioned drive backplane, the positive and negative power lines are located on the same conductive layer (the second conductive layer), reducing the number of conductive layers in the drive backplane and thus lowering development costs. Furthermore, the positive and negative power lines are spaced apart to prevent short circuits at overlapping layers, improving production yield. Additionally, the thickness of the second conductive layer is greater than that of the first conductive layer, resulting in a larger thickness for both the positive and negative power lines. This allows for a larger cross-sectional area of ​​the positive and negative power lines, reducing their impedance, improving drive current uniformity, and lowering power consumption. In summary, the drive backplane of this embodiment reduces the impedance of the positive and negative power lines, decreases the number of conductive layers, lowers development costs, and prevents short circuits at overlapping layers, thus improving production yield.

[0008] In some embodiments, the difference between the thickness of the second conductive layer and the thickness of the first conductive layer is greater than or equal to 1 μm.

[0009] In some embodiments, the thickness of the second conductive layer is greater than or equal to 2 μm; and / or, the thickness of the first conductive layer is 0.5 μm to 1 μm.

[0010] In some embodiments, the driving backplane further includes a third conductive layer disposed on the side of the second conductive layer away from the substrate. The third conductive layer includes a plurality of chip pads electrically connected to at least one of the transistors, and the chip pads are configured to connect to the light-emitting chip; the thickness of the third conductive layer is less than the thickness of the second conductive layer.

[0011] In some embodiments, the thickness of the third conductive layer is less than or equal to 2 μm.

[0012] In some embodiments, the second conductive layer further includes chip pads electrically connected to at least one of the transistors, and the chip pads are configured to connect to the light-emitting chip. The distance between the chip pads and the substrate is greater than the distance between the positive power line and the negative power line and the substrate.

[0013] In some embodiments, the driving backplane further includes a first planarization layer and a second planarization layer, the first planarization layer being disposed between the driving circuit layer and the second conductive layer. The second planarization layer includes a plurality of spaced-apart planar portions. Each planar portion is disposed between the chip pad and the first planarization layer, and is offset from the positive power line and the negative power line.

[0014] In some embodiments, the driving circuit layer includes a pixel circuit, at least one pulse amplitude modulation sub-circuit, and one pulse width modulation sub-circuit. The pixel circuit is electrically connected to a plurality of chip pads. The pixel circuit includes a plurality of sub-pixel circuits. Each sub-pixel circuit includes at least one pulse amplitude modulation sub-circuit and one pulse width modulation sub-circuit. The at least one pulse amplitude modulation sub-circuit is coupled to a first data signal terminal, a first power signal terminal, and a first node. The first power signal terminal is electrically connected to the positive power line or the negative power line. The first data signal terminal is configured to receive a first data signal. The pulse amplitude modulation sub-circuit is configured to control the magnitude of the driving current flowing through the first node according to the first data signal from the first data signal terminal. A pulse width modulation sub-circuit is coupled to the first node and the chip pads. The pulse width modulation sub-circuit is configured to control the first node and the chip pads to be continuously on, and / or to control the first node and the chip pads to be intermittently on.

[0015] In some embodiments, at least one pixel circuit is electrically connected to N positive power lines and N negative power lines, wherein the N positive power lines include a first positive power line, a second positive power line, ..., an Nth positive power line. The N negative power lines include a first negative power line, a second negative power line, ..., an Nth negative power line; N is greater than or equal to 2 and is an integer. In at least one pixel circuit, the plurality of sub-pixel circuits include one first sub-pixel circuit and (N-1) second sub-pixel circuits. The first sub-pixel circuit includes a pulse amplitude modulation sub-circuit and a pulse width modulation sub-circuit, and the first power signal terminal of the first sub-pixel circuit is electrically connected to the first positive power line. The second sub-pixel circuit includes two pulse amplitude modulation sub-circuits and one pulse width modulation sub-circuit. In the Mth second sub-pixel circuit, the first power signal terminal of one pulse amplitude modulation sub-circuit is electrically connected to the (M+1)th positive power line, and the first power signal terminal of the other pulse amplitude modulation sub-circuit is electrically connected to the (M+1)th negative power line. Where 1 ≤ M ≤ (N-1), and is an integer. The first sub-pixel circuit and the second sub-pixel circuit are electrically connected to different chip pads, and different second sub-pixel circuits are electrically connected to different chip pads.

[0016] In some embodiments, at least one pixel circuit is electrically connected to N positive power lines and N negative power lines, wherein the N positive power lines include a first positive power line, a second positive power line, ..., an Nth positive power line. The N negative power lines include a first negative power line, a second negative power line, ..., an Nth negative power line; N is greater than or equal to 2 and is an integer. In at least one pixel circuit, the plurality of sub-pixel circuits include a third sub-pixel circuit, (N-1) fourth sub-pixel circuits, and (N-1) fifth sub-pixel circuits. The third sub-pixel circuit includes a pulse amplitude modulation sub-circuit and a pulse width modulation sub-circuit, and the first power signal terminal of the third sub-pixel circuit is electrically connected to the first positive power line. The fourth sub-pixel circuit includes a pulse amplitude modulation sub-circuit and a pulse width modulation sub-circuit, and the first power signal terminal of the Mth fourth sub-pixel circuit is electrically connected to the (M+1)th positive power line. The third sub-pixel circuit and the fourth sub-pixel circuit are electrically connected to different chip pads, and different fourth sub-pixel circuits are electrically connected to different chip pads. The fifth sub-pixel circuit includes a pulse amplitude modulation sub-circuit and a pulse width modulation sub-circuit, and the first power supply signal terminal of the Mth fifth sub-pixel circuit is electrically connected to the (M+1)th negative power supply line. Wherein, 1≤M≤(N-1), and are integers. The third sub-pixel circuit and the fifth sub-pixel circuit are electrically connected to different chip pads, different fifth sub-pixel circuits are electrically connected to different chip pads, and one fourth sub-pixel circuit and one fifth sub-pixel circuit are electrically connected to the same chip pad.

[0017] In some embodiments, the width of the positive power line is greater than the width of the negative power line.

[0018] In some embodiments, the pixel circuit is electrically connected to N chip pads, N positive power lines, and N negative power lines, where N is greater than or equal to 2 and is an integer. The N positive power lines include a first positive power line, a second positive power line, ..., an Nth positive power line. The N negative power lines include a first negative power line, a second negative power line, ..., an Nth negative power line. The positive and negative power lines extend along a second direction, and along a first direction, they are arranged cyclically in the order of first positive power line, first negative power line, second positive power line, second negative power line, ..., Nth positive power line, Nth negative power line. The first and second directions intersect.

[0019] In some embodiments, the driving backplane includes a display area and a peripheral area located on at least one side of the display area. The driving backplane also includes a spacer disposed on the side of the second conductive layer away from the substrate and located in the peripheral area. The distance between the surface of the spacer away from the substrate and the substrate is equal to the distance between the surface of the chip pad away from the substrate and the substrate.

[0020] In some embodiments, the positive power line and the negative power line are arranged along a first direction and extend along a second direction. The first direction and the second direction intersect. Along the first direction, a portion of the positive power line and the negative power line are disposed in the display area, and another portion of the positive power line and the negative power line are disposed in the peripheral area. Furthermore, in the display area, the positive power line and the negative power line extend along the second direction to the peripheral area. In the peripheral area, the positive power line and the negative power line have perforated openings, and the spacer is located within the perforated openings.

[0021] On the other hand, a light-emitting substrate is provided. The light-emitting substrate includes a driving backplane and a light-emitting chip, wherein the driving backplane is the driving backplane as described in any of the above embodiments, and the light-emitting chip is connected to the driving backplane.

[0022] In some embodiments, the driving backplane includes pixel circuits, chip pads, and power pads. The power pads and chip pads are made of the same material and are disposed on the same layer. One pixel circuit is electrically connected to multiple chip pads, and the light-emitting chip is connected to the chip pads. The light-emitting substrate further includes a fourth conductive layer, a first adapter line, and a second adapter line. The fourth conductive layer is disposed on the side of the light-emitting chip away from the driving backplane. The fourth conductive layer includes the first adapter line and the second adapter line. Multiple light-emitting chips electrically connected to the same pixel circuit are connected in series through the first adapter line. Among the multiple light-emitting chips connected in series, along the current direction, the first light-emitting chip is electrically connected to the chip pad through the second adapter line. Alternatively, the last light-emitting chip is electrically connected to the power pad through the second adapter line, and the power pad is electrically connected to the negative power line.

[0023] In some embodiments, the driving backplane includes a third conductive layer disposed on the side of the second conductive layer away from the substrate. The third conductive layer includes a plurality of chip pads electrically connected to at least one of the transistors. The thickness of the third conductive layer is less than the thickness of the second conductive layer; the light-emitting chip is connected to the chip pads, and the light-emitting chip is located near the surface of the substrate, within the area of ​​the chip pads away from the substrate.

[0024] In some embodiments, the second conductive layer further includes chip pads electrically connected to at least one of the transistors. The distance between the chip pads and the substrate is greater than the distance between the positive power line and the negative power line and the substrate. The light-emitting chip is connected to the chip pads, and the surface of the chip pads away from the substrate is located within the range of the surface of the light-emitting chip close to the substrate.

[0025] In another aspect, a display device is provided. The display device includes a light-emitting substrate and a circuit board, wherein the light-emitting substrate is the light-emitting substrate as described in any of the above embodiments, and the circuit board is connected to the light-emitting substrate.

[0026] The above-described display device and light-emitting substrate have the same structure and beneficial technical effects as the driving backplane provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0028] Figure 1 This is a structural diagram of a display device according to some embodiments;

[0029] Figure 2 This is a structural diagram of another display device according to some embodiments;

[0030] Figure 3 for Figure 2 A sectional view along section line AA';

[0031] Figure 4 This is a film layer structure diagram of a light-emitting substrate according to some embodiments;

[0032] Figure 5 This is a diagram of the film structure of a drive backplate according to some embodiments;

[0033] Figure 6 A block diagram of a pixel circuit according to some embodiments;

[0034] Figure 7 A block diagram of another pixel circuit according to some embodiments;

[0035] Figure 8This is a circuit diagram of a sub-pixel circuit according to some embodiments;

[0036] Figure 9 This is a circuit diagram of another sub-pixel circuit according to some embodiments;

[0037] Figure 10 This is a film structure diagram of another light-emitting substrate according to some embodiments;

[0038] Figure 11 This is a film structure diagram of another light-emitting substrate according to some embodiments;

[0039] Figure 12 This is a film structure diagram of another light-emitting substrate according to some embodiments;

[0040] Figure 13 This is a top view of a drive backplate in the display area according to some embodiments;

[0041] Figure 14 This is a top view of a light-emitting substrate according to some embodiments;

[0042] Figure 15 This is a top view of a drive backplate in the peripheral area according to some embodiments. Detailed Implementation

[0043] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0044] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0045] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0046] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0047] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0048] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0049] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0050] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0051] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.

[0052] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.

[0053] In the circuits provided in the embodiments of this disclosure, the transistors used can be thin film transistors (TFTs), metal oxide semiconductors (MOSs), or other switching devices with the same characteristics. In the embodiments of this disclosure, thin film transistors are used as an example for illustration.

[0054] In the circuits provided by the embodiments of this disclosure, the control electrode of each transistor is the gate of the transistor, the first electrode is one of the source and drain of the thin-film transistor, and the second electrode is the other of the source and drain of the thin-film transistor. Since the source and drain of the thin-film transistor can be structurally symmetrical, their source and drain can be structurally indistinguishable. That is, the first electrode and the second electrode of the thin-film transistor in the embodiments of this disclosure can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first electrode is the source and the second electrode is the drain; for example, when the transistor is an N-type transistor, the first electrode is the drain and the second electrode is the source.

[0055] In addition, one or more transistors in the circuit provided in the embodiments of this disclosure can be N-type transistors or P-type transistors. It is only necessary to connect the terminals of the selected type of transistors in accordance with the terminals of the corresponding transistors in the embodiments of this disclosure, and to provide the corresponding high voltage or low voltage at the corresponding voltage terminals.

[0056] In embodiments of this disclosure, the capacitor can be a capacitor device fabricated separately through a process, such as by fabricating dedicated capacitor electrodes. Each capacitor electrode can be implemented using a metal layer, a semiconductor layer (e.g., doped polysilicon), etc. The capacitor can also be the parasitic capacitance between transistors, or it can be implemented through the transistor itself and other devices or circuits, or it can utilize the parasitic capacitance between the circuit's own lines.

[0057] In the embodiments of this disclosure, nodes such as the first node, the second node, and the third node do not represent actual existing components, but rather represent the junction points of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junction points of related electrical connections in the circuit diagram.

[0058] like Figure 1 As shown, some embodiments of this disclosure provide a display device 1000, which can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images) and whether it is text or images.

[0059] For example, the display device 1000 can be any product or component with display functionality, such as a television, laptop computer, tablet computer, mobile phone, personal digital assistant (PDA), navigator, in-vehicle display, flight display, wearable device, augmented reality (AR) device, virtual reality (VR) device, extended reality (XR) device, or mixed reality (MR) device. For instance, the display device 1000 can be... Figure 1 The laptop shown. For example, the display device 1000 can be... Figure 2 The phone shown.

[0060] Depending on the form of the display device 1000, the display device 1000 can be a flat display device, a curved display device, or a foldable display device, and the shape of the display surface of the display device 1000 can be any of the following: circle, ellipse, polygon, or irregular shape.

[0061] In some embodiments, see Figure 3 The display device 1000 includes a light-emitting substrate 100, which has opposing light-emitting and non-light-emitting sides. The light-emitting side refers to the side of the light-emitting substrate 100 that can emit light. Figure 3 The upper side of the light-emitting substrate 100), the non-light-emitting side refers to the side opposite to the light-emitting side ( Figure 3 (Lower side of the light-emitting substrate 100).

[0062] Please continue reading. Figure 3 The display device 1000 also includes a circuit board 200, which is connected to the light-emitting substrate 100 to provide light-emitting signals to the light-emitting substrate 100. The circuit board 200 may include, for example, a timing controller (TCON), a power management chip (DC / DC), and a variable resistor voltage divider circuit (generating Vcom), etc. Of course, the circuit board 200 may also include other circuit structures, which will not be listed here.

[0063] Please continue reading. Figure 3 The display device 1000 also includes a housing 300 and a cover plate 400. The cover plate 400 is disposed on the light-emitting side of the light-emitting substrate 100 to protect the light-emitting substrate 100. Exemplarily, the housing 300 can be a box-shaped structure with an opening. The light-emitting substrate 100 and the circuit board 200 can be disposed inside the housing 300, and the cover plate 400 is disposed on the light-emitting side of the light-emitting substrate 100 and located at the opening of the housing 300. Of course, the display device 1000 may also omit the cover plate 400; this embodiment does not specifically limit this. In addition, the display device 1000 may also include a touch structure, an under-display camera, and an under-display fingerprint recognition sensor, enabling the display device 1000 to realize various functions such as touch control, photography, video recording, or fingerprint recognition, which will not be listed here.

[0064] In some embodiments, such as Figure 3 As shown, the light-emitting substrate 100 includes a driving backplate 10 and a plurality of light-emitting chips 20. The plurality of light-emitting chips 20 are disposed on one side of the driving backplate 10 and connected to the driving backplate 10 to receive driving current and drive the light-emitting chips 20 to emit light. The plurality of light-emitting chips 20 on the driving backplate 10 can emit light of a single color, such as white or blue. Alternatively, the plurality of light-emitting chips 20 on the driving backplate 10 can emit light of multiple colors, such as red, green, and blue, as detailed below.

[0065] The aforementioned light-emitting chip 20 includes Micro LEDs and / or Mini LEDs. The radial length of the orthographic projection of the Micro LED onto the driving backplane 10 can be less than or equal to 50 μm, for example, 10 μm to 50 μm. The radial length of the orthographic projection of the Mini LED onto the driving backplane 10 can be greater than or equal to 50 μm, for example, 50 μm to 150 μm, such as 80 μm to 120 μm. Furthermore, the orthographic projection of the light-emitting chip 20 onto the driving backplane 10 can be any of a circle, an ellipse, and a polygon, and the embodiments disclosed herein are not limited to these.

[0066] It should be noted that the radial length of the orthographic projection of the light-emitting chip 20 on the driving backplane 10 refers to the length of the line segment connecting two points on the orthographic projection boundary, with the connecting line segment passing through the geometric center of the orthographic projection. For example, when the orthographic projection is a quadrilateral, the radial length includes the side length and the length of the diagonal. For example, when the orthographic projection is a circle, the radial length is the diameter.

[0067] Furthermore, the structure of the aforementioned light-emitting chip 20 can be any of a regular mounting structure, a flip-chip structure, or a vertical mounting structure. The following description uses a vertically mounted structure of the light-emitting chip 20 as an example to illustrate some embodiments of this disclosure, but the embodiments of this disclosure are not limited thereto.

[0068] In some embodiments, see Figure 4 The driving backplane 10 includes a substrate 11 and a driving circuit layer 12, which is disposed on one side of the substrate 11. The driving circuit layer 12 includes pixel circuits 30, each pixel circuit 30 being electrically connected to at least one light-emitting chip 20 to provide driving current to the light-emitting chip 20.

[0069] The substrate 11 can be a rigid substrate or a flexible substrate. The rigid substrate is made of at least one of glass, quartz, sapphire, ceramic, and polymethyl methacrylate (PMMA). The flexible substrate is made of at least one of epoxy resin, triazine, silicone resin, and polyimide.

[0070] It should be understood that the driving backplane 10 also includes a power line 40, through which a power source (such as a power management chip) is connected to the pixel circuit 30 and the light-emitting chip 20 to form a current loop. The power line 40 includes a positive power line 41 and a negative power line 42. The positive power line 41 is configured to be electrically connected to the positive terminal of the power source; that is, the positive power line 41 is directly electrically connected to the positive terminal of the power source. The negative power line 42 is configured to be electrically connected to the negative terminal of the power source; that is, one end of the negative power line 42 is directly electrically connected to the negative terminal of the power source.

[0071] Micro / Mini LEDs exhibit high luminous efficiency at high current densities and low luminous efficiency with a shifted main peak at low current densities. Specifically, the luminous efficiency of a Micro / Mini LED reaches its peak when the input driving current reaches a certain value. Below this value, the luminous efficiency gradually increases with increasing driving current, meaning that both the luminous intensity and efficiency gradually increase. Therefore, to improve the luminous efficiency of Micro / Mini LEDs, a relatively large driving current, exceeding milliamperes, is required.

[0072] Since Micro / Mini LEDs require a large driving current, the positive power line 41 and negative power line 42 in the driving backplate 10 are required to have low impedance and high tolerance, which increases the area required to lay the positive power line 41 and negative power line 42.

[0073] In related technologies, to reduce the voltage drop of the positive and negative power lines, they are placed on different conductive layers to increase their width. In this case, the positive and negative power lines can intersect in the direction perpendicular to the substrate, allowing for a larger trace width and thus reducing the voltage drop. However, placing the positive and negative power lines on different conductive layers increases the number of conductive and insulating layers on the driver backplane, significantly increasing development costs. Furthermore, the overlapping areas of the positive and negative power lines are prone to short circuits, resulting in low production yield.

[0074] Based on this, such as Figure 4 and Figure 5 As shown, in some embodiments of the present disclosure, the driving backplane 10 includes a pixel circuit 30 comprising a transistor 31, which includes a channel portion 311, a first electrode 312, a second electrode 313, and a control electrode 314. The driving circuit layer 12 includes a first conductive layer 121, and the first electrode 312 and the second electrode 313 of the transistor 31 are located on the first conductive layer 121.

[0075] Building upon this, the drive backplane 10 further includes a second conductive layer 13, which is disposed on the side of the drive circuit layer 12 away from the substrate 11. This second conductive layer 13 includes a positive power line 41 and a negative power line 42; that is, the positive power line 41 and the negative power line 42 are located on the same conductive layer (second conductive layer 13), reducing the number of conductive layers in the drive backplane 10 and thus lowering development costs. Furthermore, the positive power line 41 and the negative power line 42 are spaced apart to avoid short circuits at overlapping locations across layers, improving production yield.

[0076] Furthermore, the thickness of the second conductive layer 13 is greater than the thickness of the first conductive layer 121. This results in a larger thickness of the second conductive layer 13, which in turn increases the thickness of the positive power line 41 and the negative power line 42. This allows for an increase in the cross-sectional area of ​​the positive power line 41 and the negative power line 42, thereby reducing their impedance, improving the uniformity of the drive current, and reducing power consumption.

[0077] In summary, in the driving backplane 10 of this embodiment, the number of conductive layers of the driving backplane 10 can be reduced by lowering the impedance of the positive power line 41 and the negative power line 42, thereby reducing development costs and avoiding short circuits between the positive power line 41 and the negative power line 42 at the overlapping position, thus improving production yield.

[0078] For example, the difference between the thickness of the second conductive layer 13 and the thickness of the first conductive layer 121 is greater than or equal to 1 μm, so that the impedance of the positive power line 41 and the negative power line 42 in the second conductive layer 13 can be significantly reduced. For example, the thickness of the second conductive layer 13 can be greater than or equal to 2 μm, such as 2 μm, 2.5 μm, 2.7 μm, 2.8 μm, 3 μm, 3.2 μm, 3.5 μm, 4 μm or thicker. This embodiment of the present disclosure does not specifically limit this. In this way, the second conductive layer 13 can be prepared by electroplating process, which has high production efficiency and low preparation cost. And / or, the thickness of the first conductive layer 121 can be 0.5μm to 1μm. For example, the thickness of the second conductive layer 13 can be any one of 0.5μm, 0.53μm, 0.55μm, 0.58μm, 0.6μm, 0.62μm, 0.65μm, 0.7μm, 0.75μm, 0.8μm, 0.85μm, 0.9μm, 0.95μm and 1μm. This embodiment does not specifically limit this. In this way, the first conductive layer 121 can be prepared by sputtering process. The preparation process does not require a seed layer. The film structure is more compact, the purity is higher, and the corrosion resistance and conductivity are better.

[0079] In some embodiments, such as Figure 4As shown, the driving backplane 10 also includes a third conductive layer 14, which is disposed on the side of the second conductive layer 13 away from the substrate 11. The third conductive layer 14 includes a plurality of chip pads 51, each electrically connected to at least one transistor 31, and configured to connect to a light-emitting chip 20. Specifically, the light-emitting chip 20 is connected to the chip pads 51, for example, by bonding. In this case, the light-emitting chip 20 is close to the surface of the substrate 11, for example, within the area of ​​the chip pads 51 away from the substrate 11. This facilitates the bonding of the light-emitting chip 20 to the chip pads 51, and ensures that the light-emitting chip 20 can be completely positioned on the chip pads 51, minimizing the risk of tilting and resulting in high brightness uniformity. Of course, the chip pad 51 can be located away from the surface of the substrate 11, for example, within the range of the surface of the light-emitting chip 20 near the substrate 11. That is, the boundary of the surface of the light-emitting chip 20 near the substrate 11 extends beyond the surface of the chip pad 51 away from the substrate 11. This facilitates achieving higher pixel density and improving resolution. This embodiment of the present disclosure does not impose specific limitations here. Here, the longitudinal section (the plane perpendicular to the lower surface of the substrate 11) of the light-emitting chip 20 can be... Figure 4 The regular trapezoid shown is, or is Figure 5 The inverted trapezoid shown is not specifically limited in this embodiment.

[0080] It should be noted that the distance between the boundary of the chip pad 51 away from the surface of the substrate 11 and the boundary of the light-emitting chip 20 near the surface of the substrate 11 is greater than or equal to the bonding deviation distance. The bonding deviation distance can be set according to the actual transfer equipment capability and transfer process. This embodiment does not limit it in this respect.

[0081] The thickness of the third conductive layer 14 can be, for example, less than the thickness of the second conductive layer 13. In this case, the thicker second conductive layer 13 can be prepared by electroplating, which is efficient and low-cost. The thinner third conductive layer 14 can be prepared by sputtering, resulting in good film thickness uniformity. The maximum percentage deviation of the chip pad 51 from the surface of the substrate 11 is less than the maximum percentage deviation of the third conductive layer 14 from the surface of the substrate 11. This results in better flatness of the surface of the chip pad 51 away from the substrate 11, which is beneficial to improving the bonding yield between the chip pad 51 and the light-emitting chip 20.

[0082] The thickness of the third conductive layer 14 is less than or equal to 2 μm. For example, the thickness of the third conductive layer 14 can be any of 0.5 μm, 0.55 μm, 0.6 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 1.7 μm, 1.8 μm, and 2 μm, and this embodiment does not specifically limit this. In this way, the thickness of the third conductive layer 14 is relatively thin, which is beneficial for forming using a sputtering process.

[0083] In other embodiments, such as Figure 5 As shown, the second conductive layer 13 also includes a chip pad 51. That is, the chip pad 51, the positive power line 41, and the negative power line 42 are fabricated in the same layer and made of the same material, which can reduce the number of conductive layers in the driving backplane 10 and reduce development costs. Furthermore, the chip pad 51 is electrically connected to at least one transistor 31. The chip pad 51 is configured to connect to the light-emitting chip 20, that is, the light-emitting chip 20 is connected to the chip pad 51, such as by bonding it to the chip pad 51. In this case, the chip pad 51 is located away from the surface of the substrate 11, for example, within the area of ​​the surface of the light-emitting chip 20 near the substrate 11. That is, the boundary of the surface of the light-emitting chip 20 near the substrate 11 extends beyond the surface of the chip pad 51 away from the substrate 11, which facilitates higher pixel density and improved resolution. Of course, the light-emitting chip 20 can be located near the surface of the substrate 11, for example, within the range of the chip pad 51 away from the surface of the substrate 11. This facilitates the fixing of the light-emitting chip 20 to the chip pad 51 by bonding, and the light-emitting chip 20 can be completely located on the chip pad 51. The risk of tilting the light-emitting chip 20 is small, and the brightness uniformity is high. This embodiment of the present disclosure does not impose specific limitations here. Here, the longitudinal section (the plane perpendicular to the lower surface of the substrate 11) of the light-emitting chip 20 can be... Figure 4 The regular trapezoid shown is, or is Figure 5 The inverted trapezoid shown is not specifically limited in this embodiment.

[0084] It should be noted that the distance between the boundary of the chip pad 51 away from the surface of the substrate 11 and the boundary of the light-emitting chip 20 near the surface of the substrate 11 is greater than or equal to the bonding deviation distance. The bonding deviation distance can be set according to the actual transfer equipment capability and transfer process. This embodiment does not limit it in this respect.

[0085] The distance between the chip pad 51 and the substrate 11 can be, for example, greater than the distance between the positive power line 41 and the negative power line 42 and the substrate 11. This ensures that the surface of the chip pad 51 away from the substrate 11 is higher than the surfaces of the positive power line 41 and the negative power line 42 away from the substrate 11, facilitating the bonding of the light-emitting chip 20 to the chip pad 51. For example, the driving backplane 10 also includes a first planarization layer 61 and a second planarization layer 62. The first planarization layer 61 is disposed between the driving circuit layer 12 and the second conductive layer 13. The second planarization layer 62 includes a plurality of spaced-apart planar portions 621, which are disposed between the chip pad 51 and the first planarization layer 61 and offset from the positive power line 41 and the negative power line 42. That is, the positive power line 41 and the negative power line 42 are not raised by the planar portions 621 on their undersides, but the chip pad 51 is raised by the planar portions 621, facilitating the bonding of the light-emitting chip 20 to the chip pad 51. In addition, the drive backplate 10 may also include a first passivation layer 71, which is disposed between the second planarization layer 62 and the second conductive layer 13 to improve corrosion resistance.

[0086] The following describes some embodiments of the present disclosure by taking the example that the drive backplane 10 also includes a third conductive layer 14, which is disposed on the side of the second conductive layer 13 away from the substrate 11 and includes a plurality of chip pads 51. However, the embodiments of the present disclosure are not limited thereto, and the second conductive layer 13 may also include chip pads 51.

[0087] In some embodiments, see Figure 4 , Figure 6 and Figure 7 The pixel circuit 30 is electrically connected to multiple chip pads 51, and the chip pads 51 are electrically connected to the light-emitting chips 20. That is, the pixel circuit 30 can be electrically connected to multiple light-emitting chips 20. Of course, a pixel circuit 30 can also be electrically connected to only one chip pad 51, that is, one pixel circuit 30 drives only one light-emitting chip 20, and multiple light-emitting chips 20 emit light independently. This embodiment does not specifically limit this.

[0088] For example, see Figure 6 , Figure 7 , Figure 8 and Figure 9 The pixel circuit 30 includes a plurality of sub-pixel circuits 80, each sub-pixel circuit 80 including at least one pulse amplitude modulation sub-circuit 81 and a pulse width modulation sub-circuit 82.

[0089] See Figure 8 and Figure 9The pulse amplitude modulation sub-circuit 81 is coupled to the first data signal terminal D1, the first power signal terminal DC1, and the first node N1. The first power signal terminal DC1 is electrically connected to either the positive power line 41 or the negative power line 42. The first data signal terminal D1 is configured to receive a first data signal. The pulse amplitude modulation sub-circuit 81 is configured to control the magnitude of the drive current flowing through the first node N1 based on the first data signal from the first data signal terminal D1.

[0090] For example, such as Figure 8 As shown, the pulse amplitude modulation sub-circuit 81 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a first capacitor C1. The first terminal of the first transistor T1 is connected to the second node N2, the second terminal is connected to the first node N1, and the control terminal is connected to the third node N3. The first terminal of the second transistor T2 is connected to the first data signal terminal D1, the second terminal is connected to the second node N2, and the control terminal is connected to the first scan signal terminal G1. The first terminal of the third transistor T3 is connected to the first node N1, the second terminal is connected to the third node N3, and the control terminal is connected to the second scan signal terminal G2. The first terminal of the fourth transistor T4 is connected to the first initialization signal terminal VN1, the second terminal is connected to the third node N3, and the control terminal is connected to the first reset signal terminal R1. The first terminal of the fifth transistor T5 is connected to the first initialization signal terminal VN1, the second terminal is connected to the fourth node N4, and the control terminal is connected to the second reset signal terminal R2. The fourth node N4 can be connected to the chip pad 51 (see...). Figure 4 Electrical connection, that is, electrical connection with the anode of a light-emitting chip 20, the cathode of the light-emitting chip 20 can be electrically connected to the second power supply signal terminal DC2, and the second power supply signal terminal DC2 can be electrically connected to the negative power supply line 42 (see...). Figure 4 The first terminal of the sixth transistor T6 is connected to the first power supply signal terminal DC1, the second terminal is connected to the second node N2, and the control terminal is connected to the light emission control signal EM.

[0091] The first plate of the first capacitor C1 is connected to the first power signal terminal DC1, and the second plate is connected to the third node N3.

[0092] The first transistor T1, the second transistor T2, and the sixth transistor T6 mentioned above can be, for example, P-type transistors, and the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can be, for example, N-type transistors. Furthermore, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be single-gate or dual-gate transistors; this disclosure does not specifically limit their application.

[0093] It should be noted that the pulse amplitude modulation sub-circuit 81 may also exclude at least one of the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the first capacitor C1, and this disclosure does not specifically limit this.

[0094] For example, such as Figure 9 As shown, the pulse amplitude modulation sub-circuit 81 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1, and a second capacitor C2. The first terminal of the first transistor T1 is connected to the second node N2, the second terminal is connected to the first node N1, and the control terminal is connected to the third node N3. The first terminal of the second transistor T2 is connected to the first data signal terminal D1, the second terminal is connected to the third node N3, and the control terminal is connected to the first scan signal terminal G1. The first terminal of the third transistor T3 is connected to the first node N1, the second terminal is connected to the third node N3, and the control terminal is connected to the second scan signal terminal G2. The first terminal of the fourth transistor T4 is connected to the first power supply signal terminal DC1, the second terminal is connected to the second node N2, and the control terminal is connected to the light emission control signal EM. The first plate of the first capacitor C1 is connected to the fourth node N4, the second plate is connected to the third node N3, and the fourth node N4 is connected to the first power supply signal terminal DC1. The first plate of the second capacitor C2 is connected to the first power supply signal terminal DC1, and the second plate is connected to the fourth node N4.

[0095] The first transistor T1, the second transistor T2, and the third transistor T3 mentioned above can be, for example, N-type transistors, and the fourth transistor T4 can be, for example, a P-type transistor. Furthermore, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be single-gate or dual-gate transistors; this disclosure does not specifically limit their application.

[0096] Please continue reading. Figure 8 and Figure 9 A pulse width modulation sub-circuit 82 is coupled to the first node N1 and the chip pad 51; the pulse width modulation sub-circuit 82 is configured to control the first node N1 and the chip pad 51 to be continuously turned on so as to drive the light-emitting chip 20 to emit light continuously; and / or to control the first node N1 and the chip pad 51 to be intermittently turned on so as to drive the light-emitting chip 20 to emit light intermittently.

[0097] For example, such as Figure 8As shown, the pulse width modulation sub-circuit 82 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The first terminal of the seventh transistor T7 is connected to the first node N1, the second terminal to the fourth node N4, and the control terminal to the fifth node N5. The first terminal of the eighth transistor T8 is connected to the first voltage signal terminal V1, the second terminal to the fifth node N5, and the control terminal to the sixth node N6. The first terminal of the ninth transistor T9 is connected to the second voltage signal terminal V2, the second terminal to the fifth node N5, and the control terminal to the sixth node N6. The first terminal of the tenth transistor T10 is connected to the second data signal terminal D2, the second terminal to the sixth node N6, and the control terminal to the first control signal terminal K1. The first plate of the second capacitor C2 is connected to the reference voltage signal terminal VC, and the second plate is connected to the sixth node N6. At this time, one fourth node N4 can be connected to a chip pad 51 (see...). Figure 4 The connection is as follows: It is electrically connected to the anode of a light-emitting chip 20. The cathode of the light-emitting chip 20 can be electrically connected to the second power signal terminal DC2, and the second power signal terminal DC2 can be electrically connected to the negative power line 42 (see...). Figure 4 ).

[0098] Of the aforementioned eighth transistor T8 and ninth transistor T9, one is a P-type transistor and the other is an N-type transistor. For example, the seventh transistor T7 and the eighth transistor T8 are P-type transistors, and the ninth transistor T9 and the tenth transistor T10 are N-type transistors. Furthermore, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 can be single-gate or dual-gate transistors, and this disclosure does not specifically limit them.

[0099] Of the aforementioned first voltage signal terminal V1 and second voltage signal terminal V2, one is configured to transmit a constant operating level during the light-emitting phase to control the seventh transistor T7 to be continuously turned on; the other is configured to alternately transmit operating and non-operating levels during the light-emitting phase to control the seventh transistor T7 to be intermittently turned on. Furthermore, during the light-emitting phase, the voltage signal terminal transmitting a constant operating level can have the same signal transmitted as the light-emitting control signal terminal EM.

[0100] For example, such as Figure 9 As shown, the pulse amplitude modulation sub-circuit 81 includes a fifth transistor T5. The first terminal of the fifth transistor T5 is connected to the first node N1, the second terminal is connected to the fifth node N5, and the control terminal is connected to the light emission control signal terminal EM. At this time, one fifth node N5 can be connected to one chip pad 51. The fifth node N5 can be connected to the chip pad 51 (see...). Figure 4Electrical connection, that is, electrical connection with the anode of a light-emitting chip 20, the cathode of the light-emitting chip 20 can be electrically connected to the second power supply signal terminal DC2, and the second power supply signal terminal DC2 can be electrically connected to the negative power supply line 42 (see...). Figure 4 The fifth transistor T5 can be, for example, a P-type transistor, and can be a single-gate or dual-gate transistor; this disclosure does not specifically limit this.

[0101] In some embodiments, see Figure 6 In at least one pixel circuit 30, multiple sub-pixel circuits 80 include a first sub-pixel circuit 810 and at least one second sub-pixel circuit 820. For example, multiple sub-pixel circuits 80 include a first sub-pixel circuit 810 and two second sub-pixel circuits 820. In this case, one pixel circuit 30 is electrically connected to three chip pads 51, that is, electrically connected to three light-emitting chips 20.

[0102] See Figure 6 , Figure 8 and Figure 9 The first sub-pixel circuit 810 includes a pulse amplitude modulation sub-circuit 81 and a pulse width modulation sub-circuit 82, and the first power supply signal terminal DC1 of the first sub-pixel circuit 810 is electrically connected to the positive power supply line 41. The first sub-pixel circuit 810 can be used to generate a drive current.

[0103] See Figure 6 , Figure 8 and Figure 9 The second sub-pixel circuit 820 may include two pulse amplitude modulation sub-circuits 81 and one pulse width modulation sub-circuit 82. In the second sub-pixel circuit 820, the first power supply signal terminal DC1 of one pulse amplitude modulation sub-circuit 81 is electrically connected to the positive power supply line 41, and the first power supply signal terminal DC1 of the other pulse amplitude modulation sub-circuit 81 is electrically connected to the negative power supply line 42. At this time, one pulse amplitude modulation sub-circuit 81 in the second sub-pixel circuit 820 can be used to help increase the current flowing through the next light-emitting chip 20, and the other can be used to help decrease the current flowing through the next light-emitting chip 20. For example, in the two pulse amplitude modulation sub-circuits 81, the driving transistor (first transistor T1) of one is a P-type transistor, and the driving transistor (first transistor T1) of the other is an N-type transistor. In this case, the pulse amplitude modulation sub-circuit 81, which includes a P-type transistor, can be used to help increase the current flowing through the next light-emitting chip 20, and the pulse amplitude modulation sub-circuit 81, which includes an N-type transistor, can be used to help reduce the current flowing through the next light-emitting chip 20, which is beneficial for precise control of the current magnitude.

[0104] In this circuit, the first sub-pixel circuit 810 and the second sub-pixel circuit 820 are electrically connected to different chip pads 51, and different second sub-pixel circuits 820 are electrically connected to different chip pads 51. At this time, multiple light-emitting chips 20 connected to a pixel circuit 30 can be connected in series, and the current flowing through each light-emitting chip 20 can be increased or decreased individually.

[0105] It should be noted that, within the same pixel circuit 30, the voltage transmitted by the positive power line 41 connected to the first power signal terminal DC1 of the first sub-pixel circuit 810 is different from the voltage transmitted by the positive power line 41 connected to the first power signal terminal DC1 of the second sub-pixel circuit 820. Furthermore, the voltage transmitted by the positive power line 41 connected to the first power signal terminal DC1 of different second sub-pixel circuits 820 is different, as is the voltage transmitted by the negative power line 42 connected to the first power signal terminal DC1 of different second sub-pixel circuits 820. The specific settings can be made according to the actual situation.

[0106] For example, the pixel circuit 30 is electrically connected to N positive power lines 41 and N negative power lines 42, where N is greater than or equal to 2 and is an integer. The N positive power lines 41 include a first positive power line, a second positive power line, ..., an Nth positive power line. The voltages of the signals transmitted by the first positive power line, the second positive power line, ..., the Nth positive power line are not equal, and can be set according to actual conditions. The N negative power lines 42 also include a first negative power line, a second negative power line, ..., an Nth negative power line. The voltages of the signals transmitted by the first negative power line, the second negative power line, ..., the Nth negative power line are not equal, and can be set according to actual conditions.

[0107] At this time, the pixel circuit 30 includes a first sub-pixel circuit 810 and (N-1) second sub-pixel circuits 820. The first power supply signal terminal DC1 of the first sub-pixel circuit 810 can be electrically connected to, for example, the first positive power supply line. In the Mth second sub-pixel circuit 820, the first power supply signal terminal DC1 of one pulse amplitude modulation sub-circuit 81 can be electrically connected to, for example, the (M+1)th positive power supply line, and the first power supply signal terminal DC1 of the other pulse amplitude modulation sub-circuit 81 can be electrically connected to, for example, the (M+1)th negative power supply line. Furthermore, the first negative power supply line can be electrically connected to the cathode 22 of the last light-emitting chip 20. Where 1 ≤ M ≤ (N-1), and the numbers are integers.

[0108] In some embodiments, see Figure 7In at least one pixel circuit 30, multiple sub-pixel circuits 80 include a third sub-pixel circuit 830, at least one fourth sub-pixel circuit 840, and at least one fifth sub-pixel circuit 850. For example, the multiple sub-pixel circuits 80 include a third sub-pixel circuit 830, a fourth sub-pixel circuit 840, and a fifth sub-pixel circuit 850. In this case, one pixel circuit 30 is electrically connected to two chip pads 51.

[0109] See Figure 7 , Figure 8 and Figure 9 The third sub-pixel circuit 830 includes a pulse amplitude modulation sub-circuit 81 and a pulse width modulation sub-circuit 82, and the first power supply signal terminal DC1 of the third sub-pixel circuit 830 is electrically connected to the positive power supply line 41. This third sub-pixel circuit 830 can be used to generate a drive current.

[0110] See Figure 7 , Figure 8 and Figure 9 The fourth sub-pixel circuit 840 includes a pulse amplitude modulation sub-circuit 81 and a pulse width modulation sub-circuit 82, and the first power supply signal terminal DC1 of the fourth sub-pixel circuit 840 is electrically connected to the positive power supply line 41. In this case, the fourth sub-pixel circuit 840 can be used to assist in increasing the current flowing through the next light-emitting chip 20. In this fourth sub-pixel circuit 840, the driving transistor (first transistor T1) of the pulse amplitude modulation sub-circuit 81 is a P-type transistor, which is beneficial for precise control of the current magnitude.

[0111] See Figure 7 , Figure 8 and Figure 9 The fifth sub-pixel circuit 850 includes a pulse amplitude modulation sub-circuit 81 and a pulse width modulation sub-circuit 82, and the first power supply signal terminal DC1 of the fifth sub-pixel circuit 850 is electrically connected to the negative power supply line 42. In this case, the fifth sub-pixel circuit 850 can be used to help reduce the current flowing through the next light-emitting chip 20. In this fifth sub-pixel circuit 850, the driving transistor (first transistor T1) of the pulse amplitude modulation sub-circuit 81 is an N-type transistor, which is beneficial for precise control of the current magnitude.

[0112] In this configuration, the third sub-pixel circuit 830 and the fourth sub-pixel circuit 840 are electrically connected to different chip pads 51, and different fourth sub-pixel circuits 840 are electrically connected to different chip pads 51. Similarly, the third sub-pixel circuit 830 and the fifth sub-pixel circuit 850 are electrically connected to different chip pads 51, and different fifth sub-pixel circuits 850 are electrically connected to different chip pads 51. Furthermore, one fourth sub-pixel circuit 840 and one fifth sub-pixel circuit 850 are electrically connected to the same chip pad 51. In this case, multiple light-emitting chips 20 connected to one pixel circuit 30 can be connected in series, and the current flowing through each light-emitting chip 20 can be increased or decreased individually.

[0113] It should be noted that, within the same pixel circuit 30, the voltage transmitted by the positive power line 41 connected to the first power signal terminal DC1 of the third sub-pixel circuit 830 is different from the voltage transmitted by the positive power line 41 connected to the first power signal terminal DC1 of the fourth sub-pixel circuit 840. Furthermore, the voltage transmitted by the positive power line 41 connected to the first power signal terminal DC1 of different fourth sub-pixel circuits 840 is different, and the voltage transmitted by the negative power line 42 connected to the first power signal terminal DC1 of different fifth sub-pixel circuits 850 is different. The specific settings can be made according to the actual situation.

[0114] For example, the pixel circuit 30 is electrically connected to N positive power lines 41 and N negative power lines 42, where N is greater than or equal to 2 and is an integer. The N positive power lines 41 include a first positive power line, a second positive power line, ..., an Nth positive power line. The voltages of the signals transmitted by the first positive power line, the second positive power line, ..., the Nth positive power line are not equal, and can be set according to actual conditions. The N negative power lines 42 also include a first negative power line, a second negative power line, ..., an Nth negative power line. The voltages of the signals transmitted by the first negative power line, the second negative power line, ..., the Nth negative power line are not equal, and can be set according to actual conditions.

[0115] At this time, the pixel circuit 30 includes a third sub-pixel circuit 830, (N-1) fourth sub-pixel circuits 840, and (N-1) fifth sub-pixel circuits 850. The first power signal terminal DC1 of the third sub-pixel circuit 830 can, for example, be electrically connected to the first positive power line. The first power signal terminal DC1 of the Mth fourth sub-pixel circuit 840 can, for example, be electrically connected to the (M+1)th positive power line. The first power signal terminal DC1 of the Mth fifth sub-pixel circuit 850 can, for example, be electrically connected to the (M+1)th negative power line. Furthermore, the first negative power line can be electrically connected to the cathode 22 of the last light-emitting chip 20. Where 1 ≤ M ≤ (N-1), and these are integers.

[0116] The various sub-pixel circuits 80 with different structures described above can be combined in any suitable manner in one or more embodiments or examples. For example, when the pixel circuit 30 includes a first sub-pixel circuit 810 and at least one second sub-pixel circuit 820, it may also include at least one fourth sub-pixel circuit 840 and at least one fifth sub-pixel circuit 850. The embodiments disclosed herein will not be exemplified one by one.

[0117] In some embodiments, such as Figure 4 and Figures 10-12 As shown, the driving backplane 10 includes power pads 52, which are made of the same material as the chip pads 51 and are disposed on the same layer. At this time, the light-emitting substrate 100 includes a fourth conductive layer 15, which is disposed on the side of the light-emitting chip 20 away from the driving backplane 10. The fourth conductive layer 15 includes a first adapter line 151 and a second adapter line 152. Multiple light-emitting chips 20 electrically connected to the same pixel circuit 30 are connected in series via the first adapter line 151.

[0118] like Figure 10 and Figure 11 As shown, in the light-emitting chip 20, the cathode 22 is located on the side of the anode 21 closest to the chip pad 51, i.e., the cathode 22 faces downwards. In this case, among the multiple light-emitting chips 20 connected in series, the first light-emitting chip 20 is electrically connected to the chip pad 51 via the second adapter wire 152 along the current direction. It should be noted that a quantum well light-emitting layer is also disposed between the anode 21 and the cathode 22; however, this embodiment does not specifically limit its application.

[0119] Or, such as Figure 4 and Figure 12 As shown, in the light-emitting chip 20, the anode 21 is located on the side of the cathode 22 closer to the chip pad 51, i.e., the anode 21 faces downwards. In this case, among the multiple light-emitting chips 20 connected in series, along the current direction, the last light-emitting chip 20 is electrically connected to the power pad 52 via the second adapter cable 152, and the power pad 52 is electrically connected to the negative power line 42. It should be noted that a quantum well light-emitting layer is also disposed between the anode 21 and the cathode 22; however, this embodiment is not specifically limited to this.

[0120] As can be seen from the pixel circuit 30 described above, the width of the positive power line 41 directly affects the potential difference between the gate and source of the driving transistor (first transistor T1). Therefore, the width of the positive power line 41 is greater than the width of the negative power line 42, so that the impedance of the positive power line 41 is smaller, which is more conducive to improving the accuracy of the driving current.

[0121] In some embodiments, see Figure 4 and Figure 13The pixel circuit 30 is electrically connected to N chip pads 51, N positive power lines 41, and N negative power lines 42, where N is greater than or equal to 2 and is an integer. The N positive power lines 41 include a first positive power line, a second positive power line, and so on up to the Nth positive power line. The voltages of the signals transmitted by the first positive power line, the second positive power line, and so on up to the Nth positive power line are not equal and can be set according to actual conditions. The N negative power lines 42 also include a first negative power line, a second negative power line, and so on up to the Nth negative power line. The voltages of the signals transmitted by the first negative power line, the second negative power line, and so on up to the Nth negative power line are not equal and can be set according to actual conditions.

[0122] Please continue reading. Figure 13 The positive power line 41 and the negative power line 42 extend along the second direction Y and along the first direction X. The positive power line 41 and the negative power line 42 are arranged in a cyclical pattern according to the order of first positive power line, first negative power line, second positive power line, second negative power line... Nth positive power line, Nth negative power line. The circuit layout is neat, and the cross-sectional area of ​​the positive power line 41 and the negative power line 42 can be set to be larger, resulting in lower impedance. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular.

[0123] The distance between adjacent positive power lines 41 and negative power lines 42 should be sufficient to ensure that there is no short circuit between them. For example, the distance between adjacent positive power lines 41 and negative power lines 42 should be greater than the limit value of the process preparation, such as greater than or equal to 3μm.

[0124] Furthermore, the driving backplane 10 may also include positive and negative connection lines, which can be located in any conductive layer of the driving circuit layer 12, such as the sixth conductive layer 17, but this embodiment is not limited thereto. The positive connection line can extend along the first direction X and be electrically connected to multiple positive power lines 41 with voltages equal to those of the transmitted signal to form a mesh structure, and the pixel circuit 30 can be electrically connected to the positive power lines 41 via the positive connection line. Similarly, the negative connection line can extend along the first direction X and be electrically connected to multiple negative power lines 41 with voltages equal to those of the transmitted signal to form a mesh structure, and the pixel circuit 30 can be electrically connected to the negative power lines 42 via the negative connection line.

[0125] In some embodiments, see Figure 14 The driving backplane 10 includes a display area AA and a peripheral area BB located on at least one side of the display area AA. The display area AA is configured to house the light-emitting chip 20, and the peripheral area is configured to house the source driving circuit 102, the gate driving circuit 101, the fan-out trace 103, etc. Figure 14The diagram uses the surrounding area BB and the surrounding display area AA as an example.

[0126] Based on this, combined Figure 4 , Figure 14 and Figure 15 The driving backplane 10 also includes a spacer PS, which is disposed on the side of the second conductive layer 13 away from the substrate 11 and located in the peripheral region BB. The distance between the surface of the spacer PS away from the substrate 11 and the substrate 11 is equal to the distance between the surface of the chip pad 51 away from the substrate 11 and the substrate 11. In this case, during the bonding process between the light-emitting chip 20 and the chip pad 51, the spacer PS in the peripheral region BB can provide support, thereby improving the bonding yield between the light-emitting chip 20 and the chip pad 51.

[0127] Furthermore, along the first direction X, a portion of the positive power lines 41 and negative power lines 42 are disposed in the display area AA, while another portion of the positive power lines 41 and negative power lines 42 can be disposed, for example, in the peripheral area BB. In the display area AA, the positive power lines 41 and negative power lines 42 extend along the second direction Y to the peripheral area BB to improve the uniformity of the second conductive layer 13 formed by the electroplating process. Here, the arrangement and shape of the positive power lines 41 and negative power lines 42 in the peripheral area BB are the same as those in the display area AA to improve the uniformity of the second conductive layer 13 formed by the electroplating process. For example, a virtual pad 511 is provided in the peripheral area BB, and the arrangement of this virtual pad 511 is consistent with that of the chip pad 51 and power pad 52 in the display area AA to improve the uniformity of the second conductive layer 13 formed by the electroplating process.

[0128] Based on this, in the peripheral area BB, the positive power line 41 and the negative power line 42 are provided with hollow openings, and the spacer PS is located within the hollow openings to reduce the conductive pattern layer under the spacer PS and reduce the risk of inconsistent support heights of multiple spacer PS. Here, along the first direction X, the spacer PS located on opposite sides of the display area AA can overlap with the clock signal line below and be staggered from other circuit structures (such as the gate drive circuit). Along the second direction Y, the spacer PS located on opposite sides of the display area AA can also overlap with the fan-out trace 103 below, so that there is a conductive layer supporting the spacer PS in the peripheral area BB, resulting in good height uniformity. Of course, depending on the actual circuit setup, the spacer PS can also be completely staggered from the conductive pattern below, and this embodiment does not specifically limit this.

[0129] The aforementioned spacers PS are evenly arranged in the peripheral area BB. For example, the spacers PS are arranged in multiple rows and columns, with one row including multiple spacers PS arranged along the first direction X and one column including multiple spacers PS arranged along the second direction Y. The distance between two adjacent spacers PS along the first direction X can, for example, be equal to the distance between two adjacent light-emitting chips 20, and the distance between two adjacent spacers PS along the second direction Y can, for example, be equal to the distance between two adjacent light-emitting chips 20. Of course, the distance between two adjacent spacers PS along the first direction X can also be greater than or less than the distance between two adjacent light-emitting chips 20, and the distance between two adjacent spacers PS along the second direction Y can also be greater than or less than the distance between two adjacent light-emitting chips 20. As long as there is a predetermined proportional relationship between the distance between the spacers PS and the distance between the light-emitting chips 20, this embodiment of the disclosure does not impose specific limitations.

[0130] The following describes the film structure of the driving circuit layer 12 in some embodiments of this disclosure in conjunction with specific film layers, but the embodiments of this disclosure are not limited thereto.

[0131] In some embodiments, see Figure 4 and Figure 10 The driving circuit layer 12 also includes a first semiconductor layer 131, a fifth conductive layer 16 and a sixth conductive layer 17. The fifth conductive layer 16 is disposed on the side of the first semiconductor layer 131 away from the substrate 11, the sixth conductive layer 17 is disposed on the side of the fifth conductive layer 16 away from the substrate 11, and the first conductive layer 121 is located on the side of the sixth conductive layer 17 away from the substrate 11.

[0132] At this time, the channel portion of transistor 31 is located in the first semiconductor layer 131. That is, when the pixel circuit 30 includes P-type transistors and N-type transistors, the channels of both P-type and N-type transistors are located in the first semiconductor layer 131. The control electrode of transistor 31 is located in the fifth conductive layer 16. The conductive pattern included in the sixth conductive layer 17 can be opposite to a portion of the conductive pattern in the fifth conductive layer 16 to form a capacitor.

[0133] In some examples, see Figure 11 and Figure 12 The driving circuit layer 12 may also include a second semiconductor layer 132 and a seventh conductive layer 18. The second semiconductor layer 132 is disposed on the side of the sixth conductive layer 17 away from the substrate 11, and the seventh conductive layer 18 is disposed on the side of the second semiconductor layer 132 away from the substrate 11. The first conductive layer 121 is located on the side of the seventh conductive layer 18 away from the substrate 11.

[0134] In this case, in the pixel circuit 30, the channel portions of some transistors 31 can be located in the first semiconductor layer 131, and the channel portions of other transistors 31 can be located in the second semiconductor layer 132. For example, if the pixel circuit 30 includes P-type transistors and N-type transistors, all P-type transistors are located in the first semiconductor layer 131, and all N-type transistors have their channels located in the second semiconductor layer 132. In this case, the control electrode of the P-type transistor 31 can be located in the fifth conductive layer 16, and the N-type transistor can be a dual-gate structure, with the bottom gate located in the sixth conductive layer 17 and the top gate located in the seventh conductive layer 18.

[0135] It should be noted that the driving circuit layer 12 may also include more or fewer conductive layers, which will not be exemplified one by one in this embodiment. Furthermore, one or more insulating layers may be disposed between adjacent semiconductor layers and conductive layers, as well as between adjacent conductive layers. These insulating layers may be organic or inorganic insulating layers, which are not specifically limited in this embodiment.

[0136] In addition, please continue to refer to Figure 4 and Figures 10-12 The driving backplate 10 may also include a light-shielding layer 19, which is disposed between the driving circuit layer 12 and the substrate 11. The light-shielding layer 19 is used to block the channel portion 311 of the transistor 31 to reduce the risk of the threshold voltage of the transistor 31 shifting due to light.

[0137] It is understandable that, depending on the application scenario, the wavelength of the light emitted from the light-emitting substrate 100 can be modulated (e.g., filtering and / or color conversion) and / or the propagation direction can be modulated (e.g., uniform light processing) to achieve full-color display.

[0138] The light-emitting substrate 100 can directly emit a single color of light, which, after color conversion and / or filtering, achieves full-color display. Alternatively, the light-emitting substrate 100 can also emit multiple colors of light (e.g., red, blue, and green) to achieve full-color display.

[0139] For example, see Figure 4 and Figures 10-12 The light-emitting substrate 100 emits monochromatic (e.g., white or blue) light. At this time, the light-emitting substrate 100 also includes a color conversion layer 91, which is disposed on the side of the light-emitting chip 20 away from the driving backplate 10. The color conversion layer 91 includes a plurality of quantum dot films 910, which at least partially overlap with the light-emitting chip 20 to convert the monochromatic light emitted by the light-emitting chip 20 into a color, thereby achieving full-color display.

[0140] For example, see Figure 4 and Figures 10-12The light emitted by the light-emitting chip 20 is blue. At this time, the multiple quantum dot films 910 include a first quantum dot film 911, a second quantum dot film 912, and a third quantum dot film 913. The first quantum dot film 911 is configured to emit red light when illuminated by the light emitted from the light-emitting chip 20. The second quantum dot film 912 is configured to emit green light when illuminated by the light emitted from the light-emitting chip 20. The third quantum dot film 913 is configured to transmit the light emitted from the light-emitting chip 20.

[0141] Based on this, refer to Figure 4 and Figures 10-12 The light-emitting substrate 100 also includes a light filter layer 92, which is disposed on the side of the color conversion layer 91 away from the driving backplate 10. The light filter layer 92 includes a plurality of light filter sections 920, which cover the side of the quantum dot film 910 away from the driving backplate 10 to transmit light of one color and reflect light of other colors, thereby improving the light extraction efficiency of the light-emitting substrate 100 and reducing power consumption.

[0142] For example, such as Figure 4 and Figures 10-12 As shown, the plurality of filter sections 920 include a first filter section 920, a second filter section 922, and a third filter section 923. The first filter section 920 covers a first quantum dot film 911 to transmit red light and reflect blue and green light. The second filter section 922 covers a second quantum dot film 912 to transmit green light and reflect red and blue light. The third filter section 923 covers a third quantum dot film 913 to transmit blue light and reflect red and green light.

[0143] Furthermore, the light-emitting substrate 100 may also include a black matrix 930, which is used to separate the light emitted by each light-emitting chip 20 and reduce the reflection of ambient light. For example, the black matrix 930 has multiple openings, and the aforementioned quantum dot film 910 and filter 920 are stacked within these openings. In addition, the light-emitting substrate 100 may also include reflector cups, focusing lenses, and other various functional structures that can improve the light extraction efficiency or adjust the viewing angle of the light-emitting substrate 100, which will not be listed here.

[0144] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0145] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A drive backplane, characterized in that, For connecting the light-emitting chip; the driving backplate includes; Substrate; A driving circuit layer is disposed on one side of the substrate; the driving circuit layer includes a transistor, the transistor including a channel portion, a first electrode, a second electrode and a control electrode; the driving circuit layer further includes a first conductive layer, the first electrode and the second electrode being located in the first conductive layer; A second conductive layer is disposed on the side of the driving circuit layer away from the substrate; the second conductive layer includes a positive power line and a negative power line disposed at intervals, the positive power line being configured to be electrically connected to the positive terminal of the power supply, and the negative power line being configured to be electrically connected to the negative terminal of the power supply; wherein, the thickness of the second conductive layer is greater than the thickness of the first conductive layer.

2. The drive backplane according to claim 1, characterized in that, The difference between the thickness of the second conductive layer and the thickness of the first conductive layer is greater than or equal to 1 μm.

3. The drive backplane according to claim 1 or 2, characterized in that, The thickness of the second conductive layer is greater than or equal to 2 μm; and / or the thickness of the first conductive layer is 0.5 μm to 1 μm.

4. The drive backplane according to claim 1, characterized in that, Also includes: A third conductive layer is disposed on the side of the second conductive layer away from the substrate; the third conductive layer includes a plurality of chip pads, the chip pads being electrically connected to at least one of the transistors, and the chip pads being configured to connect to the light-emitting chip; the thickness of the third conductive layer is less than the thickness of the second conductive layer.

5. The drive backplane according to claim 4, characterized in that, The thickness of the third conductive layer is less than or equal to 2 μm.

6. The drive backplane according to claim 1, characterized in that, The second conductive layer further includes chip pads, which are electrically connected to at least one of the transistors and are configured to connect to the light-emitting chip; the distance between the chip pads and the substrate is greater than the distance between the positive power line and the negative power line and the substrate.

7. The drive backplane according to claim 6, characterized in that, Also includes: A first planarization layer is disposed between the driving circuit layer and the second conductive layer; The second planarization layer includes a plurality of planar portions spaced apart; the planar portions are disposed between the chip pads and the first planarization layer, and are offset from the positive power line and the negative power line.

8. The drive backplate according to any one of claims 4 to 7, characterized in that, The driving circuit layer includes: Pixel circuitry, electrically connected to multiple chip pads; the pixel circuitry includes multiple sub-pixel circuits, each sub-pixel circuit comprising: At least one pulse amplitude modulation sub-circuit is coupled to a first data signal terminal, a first power signal terminal, and a first node; the first power signal terminal is electrically connected to the positive power line or the negative power line; the first data signal terminal is configured to receive a first data signal; the pulse amplitude modulation sub-circuit is configured to control the magnitude of the drive current flowing through the first node according to the first data signal from the first data signal terminal. A pulse width modulation sub-circuit is coupled to the first node and the chip pad; the pulse width modulation sub-circuit is configured to control the first node and the chip pad to be continuously on; and / or to control the first node and the chip pad to be intermittently on.

9. The drive backplane according to claim 8, characterized in that, At least one of the pixel circuits is electrically connected to N positive power lines and N negative power lines, wherein the N positive power lines include a first positive power line, a second positive power line, ..., an Nth positive power line; and the N negative power lines include a first negative power line, a second negative power line, ..., an Nth negative power line; N is greater than or equal to 2 and is an integer. In at least one of the pixel circuits, the plurality of sub-pixel circuits include: A first sub-pixel circuit includes a pulse amplitude modulation sub-circuit and a pulse width modulation sub-circuit, and the first power supply signal terminal of the first sub-pixel circuit is electrically connected to the first positive power supply line. There are (N-1) second sub-pixel circuits, each second sub-pixel circuit including two pulse amplitude modulation sub-circuits and one pulse width modulation sub-circuit; in the Mth second sub-pixel circuit, the first power supply signal terminal of one pulse amplitude modulation sub-circuit is electrically connected to the (M+1)th positive power supply line, and the first power supply signal terminal of the other pulse amplitude modulation sub-circuit is electrically connected to the (M+1)th negative power supply line; wherein, 1≤M≤(N-1), and is an integer; the first sub-pixel circuit and the second sub-pixel circuit are electrically connected to different chip pads, and different second sub-pixel circuits are electrically connected to different chip pads.

10. The drive backplane according to claim 8, characterized in that, At least one of the pixel circuits is electrically connected to N positive power lines and N negative power lines, wherein the N positive power lines include a first positive power line, a second positive power line, ..., an Nth positive power line; and the N negative power lines include a first negative power line, a second negative power line, ..., an Nth negative power line; N is greater than or equal to 2 and is an integer. In at least one of the pixel circuits, the plurality of sub-pixel circuits include: A third sub-pixel circuit includes a pulse amplitude modulation sub-circuit and a pulse width modulation sub-circuit, and the first power supply signal terminal of the third sub-pixel circuit is electrically connected to the first positive power supply line. (N-1) fourth sub-pixel circuits, each fourth sub-pixel circuit including a pulse amplitude modulation sub-circuit and a pulse width modulation sub-circuit; the first power supply signal terminal of the Mth fourth sub-pixel circuit is electrically connected to the (M+1)th positive power supply line; the third sub-pixel circuit and the fourth sub-pixel circuit are electrically connected to different chip pads, and different fourth sub-pixel circuits are electrically connected to different chip pads; (N-1) fifth sub-pixel circuits, each fifth sub-pixel circuit including a pulse amplitude modulation sub-circuit and a pulse width modulation sub-circuit; the first power supply signal terminal of the Mth fifth sub-pixel circuit is electrically connected to the (M+1)th negative power supply line; where 1≤M≤(N-1) and is an integer; the third sub-pixel circuit and the fifth sub-pixel circuit are electrically connected to different chip pads, different fifth sub-pixel circuits are electrically connected to different chip pads, and a fourth sub-pixel circuit and a fifth sub-pixel circuit are electrically connected to the same chip pad.

11. The drive backplane according to claim 9, characterized in that, The width of the positive power line is greater than the width of the negative power line.

12. The drive backplane according to claim 8, characterized in that, The pixel circuit is electrically connected to N chip pads, N positive power lines and N negative power lines, where N is greater than or equal to 2 and is an integer. The N positive power lines include a first positive power line, a second positive power line, ..., an Nth positive power line; the N negative power lines include a first negative power line, a second negative power line, ..., an Nth negative power line; The positive power line and the negative power line extend along the second direction and along the first direction. The positive power line and the negative power line are arranged in a cyclical manner in the order of first positive power line, first negative power line, second positive power line, second negative power line... Nth positive power line, Nth negative power line; the first direction and the second direction intersect.

13. The drive backplate according to any one of claims 4 to 7, characterized in that, The drive backplate includes a display area and a peripheral area located on at least one side of the display area; the drive backplate also includes: A spacer is disposed on the side of the second conductive layer away from the substrate and located in the peripheral region; the distance between the surface of the spacer away from the substrate and the substrate is equal to the distance between the surface of the chip pad away from the substrate and the substrate.

14. The drive backplane according to claim 13, characterized in that, The positive power line and the negative power line are arranged along a first direction and extend along a second direction; the first direction and the second direction intersect. Along the first direction, a portion of the positive power line and the negative power line are disposed in the display area, and another portion of the positive power line and the negative power line are disposed in the peripheral area; and in the display area, the positive power line and the negative power line extend along the second direction to the peripheral area; in the peripheral area, the positive power line and the negative power line are provided with hollow openings, and the spacer is located in the hollow openings.

15. A light-emitting substrate, characterized in that, include: Drive backplate as described in any one of claims 1 to 14; The light-emitting chip is disposed on one side of the driving backplate and connected to the driving backplate.

16. The light-emitting substrate according to claim 15, characterized in that, The driving backplane includes pixel circuits, chip pads, and power pads. The power pads and chip pads are made of the same material and are disposed on the same layer. One pixel circuit is electrically connected to multiple chip pads, and the light-emitting chip is connected to the chip pads. The light-emitting substrate further includes: A fourth conductive layer is disposed on the side of the light-emitting chip away from the driving backplane; the fourth conductive layer includes: The first adapter cable connects multiple light-emitting chips electrically connected to the same pixel circuit in series. In the second adapter cable, among the multiple light-emitting chips connected in series, the first light-emitting chip is electrically connected to the chip pad along the current direction through the second adapter cable; or, the last light-emitting chip is electrically connected to the power pad through the second adapter cable, and the power pad is electrically connected to the negative power line.

17. The light-emitting substrate according to claim 15 or 16, characterized in that, The driving backplane includes a third conductive layer disposed on the side of the second conductive layer away from the substrate; the third conductive layer includes a plurality of chip pads, the chip pads being electrically connected to at least one of the transistors; the thickness of the third conductive layer is less than the thickness of the second conductive layer; the light-emitting chip is connected to the chip pads, and the light-emitting chip is close to the surface of the substrate, located within the range of the chip pads away from the surface of the substrate.

18. The light-emitting substrate according to claim 15 or 16, characterized in that, The second conductive layer further includes chip pads, which are electrically connected to at least one of the transistors; the distance between the chip pads and the substrate is greater than the distance between the positive power line and the negative power line and the substrate; the light-emitting chip is connected to the chip pads, and the surface of the chip pads away from the substrate is located within the range of the surface of the light-emitting chip close to the substrate.

19. A display device, characterized in that, include: The light-emitting substrate as described in any one of claims 15 to 18; The circuit board is connected to the light-emitting substrate.

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