Direct current mobile energy storage system commercial power wake-up circuit

Abstract

The utility model discloses a kind of DC mobile energy storage system commercial power wake-up circuit, including power supply electronic circuit;Energy storage delay subcircuit, energy storage delay subcircuit is parallelly connected in power supply electronic circuit;Current amplification subcircuit, current amplification subcircuit includes primary amplification branch and secondary amplification branch, primary amplification branch is parallelly connected in energy storage delay subcircuit, secondary amplification branch is parallelly connected in primary amplification branch;Load filter subcircuit, load filter subcircuit is connected in secondary amplification branch;Wake-up subcircuit, wake-up subcircuit is parallelly connected in load filter subcircuit.The utility model when commercial power is accessed, power supply electronic circuit starts power supply, energy storage delay subcircuit stores energy and delays false trigger, to output charging current is amplified after primary amplification branch, again secondary amplification branch is amplified, filter out ripple by load filter subcircuit, trigger wake-up subcircuit starts to wake up BMS, simplify commercial power power-up wake-up process, to improve operating convenience and wake-up efficiency.

Description

Technical Field

[0001] This utility model relates to the field of mains power wake-up technology, specifically, it mainly relates to a mains power wake-up circuit for a DC mobile energy storage system. Background Technology

[0002] In the field of DC mobile energy storage, when the system is powered off, the BMS (Battery Management System) needs to be woken up by pressing the system power-on button before the system can enter the working state. Currently, existing methods for waking up the system mainly rely on physical buttons / keys to wake up the BMS. When the user wants to select AC power input, they need to press the physical button first to wake up the system for AC power connection. This adds extra steps, reduces user convenience, and cannot automatically trigger wake-up based on the AC power connection status, thus reducing the efficiency of wake-up operations when AC power is connected. Utility Model Content

[0003] To address the shortcomings of existing technologies, this utility model provides a DC mobile energy storage system mains power wake-up circuit to solve the problems of existing wake-up methods relying on physical buttons, requiring manual button pressing before mains power connection when replenishing mains power, and low wake-up operation efficiency.

[0004] This utility model discloses a DC mobile energy storage system mains power wake-up circuit, including a power supply circuit; an energy storage delay sub-circuit connected in parallel to the power supply circuit; a current amplification sub-circuit, which includes a primary amplification branch and a secondary amplification branch, with the primary amplification branch connected in parallel to the energy storage delay sub-circuit and the secondary amplification branch connected in parallel to the primary amplification branch; a load filter sub-circuit connected in series with the secondary amplification branch; and a wake-up sub-circuit connected in parallel with the load filter sub-circuit.

[0005] According to one embodiment of the present invention, the energy storage delay sub-circuit includes a charging branch and a discharging branch; the charging branch and the discharging branch are connected in parallel and then connected in parallel to the power supply circuit.

[0006] According to one embodiment of the present invention, the charging branch includes a charging current-limiting resistor R2 and a first capacitor C1. One end of the charging current-limiting resistor R2 is connected to the output terminal of the power supply circuit, and the other end is connected in series with one end of the first capacitor C1. The other end of the first capacitor C1 is connected to the discharge branch.

[0007] According to one embodiment of the present invention, the discharge branch includes a discharge resistor R1, a first diode D1, and a second diode D2; the discharge resistor R1 is connected in parallel to the power supply circuit; the first diode D1 is connected in parallel to the charging current limiting resistor R2, the cathode of the first diode D1 is connected to the output terminal of the power supply circuit, and the anode of the first diode D1 is connected to one end of the first capacitor C1; the cathode of the second diode D2 is connected to the other end of the first capacitor C1, and the anode of the second diode D2 is connected to the input terminal of the power supply circuit.

[0008] According to one embodiment of the present invention, the first-stage amplification branch includes a first transistor Q1 and a collector current limiting resistor R3; the first transistor Q1 and the collector current limiting resistor R3 are connected in series and then connected in parallel to the charging branch; the second-stage amplification branch is connected in parallel to the collector current limiting resistor R3.

[0009] According to one embodiment of the present invention, the first transistor Q1 is an NPN transistor.

[0010] According to one embodiment of the present invention, the second-stage amplification branch includes an emitter limiting current resistor R4, a second transistor Q2, and a base limiting current resistor R5; one end of the emitter limiting current resistor R4 is connected in series with the second transistor Q2, and the other end is connected to the output terminal of the power supply circuit; after the second transistor Q2 is connected to the base limiting current resistor R5, it is connected in parallel to the first-stage amplification branch.

[0011] According to one embodiment of the present invention, the second transistor Q2 is a PNP transistor.

[0012] According to one embodiment of the present invention, the load filter sub-circuit includes a filter discharge resistor R6 and a second capacitor C2; one end of the filter discharge resistor R6 is connected in series with the second stage amplification branch, and the other end is connected to the input terminal of the power supply circuit; the second capacitor C2 is connected in parallel with the filter discharge resistor R6.

[0013] According to one embodiment of the present invention, the wake-up sub-circuit includes an equivalent input resistance R7, which is connected in parallel with the second capacitor C2.

[0014] The beneficial effects of this application are as follows: When the mains power is connected to the mains power wake-up circuit of the DC mobile energy storage system, the power supply circuit starts to output the working signal voltage, and the energy storage delay sub-circuit connected in parallel with the power supply circuit starts to charge and store electrical energy and realizes the delay function, avoiding the BMS false triggering caused by the instantaneous conduction of the mains power wake-up circuit of the DC mobile energy storage system; the energy storage delay sub-circuit delivers charging current to the parallel current amplification sub-circuit, the first-stage amplification branch first amplifies the charging current to generate the first-stage amplified current, and then delivers the first-stage amplified current to the second-stage amplification branch connected in parallel with the first-stage amplification branch for second-stage amplification to generate the second-stage amplified current. After the second-stage amplified current flows through the series-connected load filter sub-circuit, the noise signal in the second-stage amplified current is filtered out to ensure the output current is stable; finally, the stabilized current acts on the parallel wake-up sub-circuit, triggering the wake-up sub-circuit to start, thereby waking up the BMS to enter the working state, realizing automatic wake-up after the mains power is connected. The entire process does not require manually pressing a physical button. After the mains power is connected, the DC mobile energy storage system's mains power wake-up circuit automatically completes energy storage, current amplification, noise filtering, and wake-up triggering, eliminating additional manual operation steps, simplifying the wake-up process when the mains power is replenished, and improving the user's ease of operation. At the same time, the circuit automatically responds to the mains power connection status to achieve rapid wake-up, thereby improving the wake-up operation efficiency when the mains power is connected. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of the mains power wake-up circuit of the DC mobile energy storage system in the embodiment; Figure 2 This is a schematic diagram of the pulse waveform of the high-level pulse signal in the embodiment; Figure 3 This is a schematic diagram of the circuit current direction when the mains power is connected in the embodiment; Figure 4 This is a schematic diagram showing the direction of the circuit current when the mains power is disconnected in the embodiment.

[0016] Explanation of reference numerals in the attached figures 1. Power supply circuit; 2. Energy storage delay sub-circuit; 21. Charging branch; 22. Discharging branch; 3. Current amplification sub-circuit; 31. First-stage amplification branch; 32. Second-stage amplification branch; 4. Load filter sub-circuit; 5. Wake-up sub-circuit. Detailed Implementation

[0017] The following drawings will disclose several embodiments of this utility model. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit this utility model. That is, in some embodiments of this utility model, these practical details are not essential. In addition, for the sake of simplicity, some conventional structures and components will be shown in the drawings in a simple schematic manner.

[0018] It should be noted that all directional indicators in this utility model embodiment, such as up, down, left, right, front, back, etc., are only used to explain the relative positional relationship and movement of the components in a specific posture as shown in the attached figure. If the specific posture changes, the directional indicator will also change accordingly.

[0019] Furthermore, in this utility model, the use of terms such as "first" and "second" is for descriptive purposes only and does not specifically refer to any order or sequence, nor is it intended to limit the utility model. They are merely used to distinguish items or operations described with the same technical terminology and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, such a combination should be considered non-existent and not within the scope of protection claimed by this utility model.

[0020] To further understand the utility model's content, features, and effects, the following embodiments are provided, along with detailed descriptions in conjunction with the accompanying drawings: Please refer to Figure 1-3 , Figure 1 This is a schematic diagram of the mains power wake-up circuit of the DC mobile energy storage system in the embodiment; Figure 2 This is a schematic diagram of the pulse waveform of the high-level pulse signal in the embodiment; Figure 3 This is a schematic diagram of the circuit current direction when mains power is connected in the embodiment. This embodiment provides a mains power wake-up circuit for a DC mobile energy storage system, including a power supply circuit 1, an energy storage delay sub-circuit 2, a current amplification sub-circuit 3, a load filter sub-circuit 4, and a wake-up sub-circuit 5. The energy storage delay sub-circuit 2 is connected in parallel with the power supply circuit 1. The current amplification sub-circuit 3 includes a primary amplification branch 31 and a secondary amplification branch 32. The primary amplification branch 31 is connected in parallel with the energy storage delay sub-circuit 2, and the secondary amplification branch 32 is connected in parallel with the primary amplification branch 31. The load filter sub-circuit 4 is connected in series with the secondary amplification branch 32. The wake-up sub-circuit 5 is connected in parallel with the load filter sub-circuit 4.

[0021] The power supply circuit 1 provides a continuous and stable DC power supply to the mains wake-up circuit of the DC mobile energy storage system. When the mains power is connected to the mains wake-up circuit of the DC mobile energy storage system, the power supply circuit 1 starts to work and outputs a working signal voltage. In this example, the power supply circuit 1 consists of a 24V auxiliary power supply, which can provide a 24V DC power supply to the mains wake-up circuit of the DC mobile energy storage system and output a working signal voltage.

[0022] The energy storage delay sub-circuit 2 is connected in parallel to the power supply circuit 1. The energy storage delay sub-circuit 2 receives the working signal voltage and charges itself to store energy, and then outputs the charging current. During the charging process, the energy storage delay sub-circuit 2 is connected to the current amplification sub-circuit 3 to adjust the pulse duration.

[0023] The current amplification sub-circuit 3 includes a first-stage amplification branch 31 and a second-stage amplification branch 32. The first-stage amplification branch 31 is connected in parallel with the energy storage delay sub-circuit 2, and the second-stage amplification branch 32 is connected in parallel with the first-stage amplification branch 31. The charging current output from the energy storage delay sub-circuit 2 and the working signal voltage output from the power supply circuit 1 flow into the first-stage amplification branch 31. When the working signal voltage flows through the first-stage amplification branch 31, it generates a corresponding first current to be amplified. The charging current output from the energy storage delay sub-circuit 2 drives the first-stage amplification branch 31 to amplify the generated first current before outputting the first-stage amplified current. Then, the first-stage amplified current flows to the input terminal of the power supply circuit 1, and then is output through the output terminal of the power supply circuit 1. The first-stage amplified current output by the first-stage amplified branch 31 and the working signal voltage output through the output terminal of the power supply circuit 1 flow into the second-stage amplified branch 32. When the working signal voltage flows through the second-stage amplified branch 32, it generates the corresponding second current to be amplified. The first-stage amplified current output by the first-stage amplified branch 31 drives the second-stage amplified branch 32 to amplify the generated second current to be amplified, thereby generating a second-stage amplified current. This ensures that the output second-stage amplified current meets the wake-up requirements of the subsequent wake-up sub-circuit 5.

[0024] The load filter sub-circuit 4 is connected in series with the secondary amplifier branch 32 to filter out the noise of the secondary amplifier current output by the secondary amplifier branch 32, thereby generating the filter current.

[0025] The wake-up sub-circuit 5 is connected in parallel to the load filter sub-circuit 4, serving as the signal receiver for the filtered current. After receiving the filtered current, it generates a high-level pulse signal (e.g., ...) at the BMS-ACWAKEUP terminal of the wake-up sub-circuit 5. Figure 2 As shown in the figure, the high-level pulse signal disappears after the energy storage delay sub-circuit 2 is fully charged, thereby realizing the automatic wake-up of the BMS.

[0026] Therefore, when the mains power is connected to the DC mobile energy storage system's mains power wake-up circuit, the output terminal of the power supply circuit 1 outputs a working signal voltage. The energy storage delay sub-circuit 2 receives the working signal voltage and performs energy storage charging, then outputs a charging current. The charging current output by the energy storage delay sub-circuit 2 and the working signal voltage output by the power supply circuit 1 flow into the first-stage amplification branch 31. The charging current drives the first-stage amplification branch 31 to amplify the first current to be amplified generated by the working signal voltage, generating a first-stage amplified current, which is then output through the output terminal of the power supply circuit 1. The first-stage amplified current output by the first-stage amplification branch 31 and the working signal voltage output by the power supply circuit 1 flow into the second-stage amplification branch 32. The first-stage amplified current drives the second-stage amplification branch 32 to amplify the second current to be amplified generated by the working signal voltage, generating a second-stage amplified current. The second-stage amplified current flows through the load filter sub-circuit 4 to filter and generate a filtered current. Then, the filtered current flows through the BMS-ACWAKEUP terminal of the wake-up sub-circuit 5 to generate a high-level pulse signal. The circuit current direction of the DC mobile energy storage system's mains power wake-up circuit when the mains power is connected is as follows: Figure 3 As shown. When the mains power is disconnected, the 24V auxiliary power supply stops outputting, and the DC mobile energy storage system's mains wake-up circuit stops working after losing power. At this time, it discharges through the energy storage delay sub-circuit 2 until the next mains power input, at which point it will recharge and send a high-level pulse signal. That is, a high-level pulse signal is only generated at the moment the mains power is connected, and the duration is short and the power consumption is low, so as to quickly wake up the BMS-ACWAKEUP terminal of the wake-up sub-circuit 5.

[0027] For further details, please review. Figure 1 The energy storage delay sub-circuit 2 includes a charging branch 21 and a discharging branch 22; the charging branch 21 and the discharging branch 22 are connected in parallel and then connected in parallel to the power supply circuit 1.

[0028] The charging branch 21 and the discharging branch 22 are connected in parallel to the power supply circuit 1. When the mains power is connected, the charging branch 21 is used to achieve delayed triggering, and when the mains power is disconnected, the discharging branch 22 is used to achieve circuit reset. This ensures that the corresponding pulse duration can be adjusted when the mains power is connected, and the initial state can be quickly restored after the mains power is disconnected, so as to prepare for the next wake-up.

[0029] In this example, charging branch 21 and discharging branch 22 are connected in parallel, with both ends directly connected to the output and input terminals of the power supply circuit 1, forming independent branches. This layout not only facilitates circuit debugging and troubleshooting but also reduces signal interference between the two branches. The function of charging branch 21 is to utilize the time delay generated during the charging process. When mains power is connected, the working signal voltage output by power supply circuit 1 slowly stores energy through charging branch 21. As the energy storage process progresses, the charging voltage across charging branch 21 gradually changes, thereby controlling the gradual change in charging current and adjusting the pulse duration to control the conduction timing of the subsequent current amplification sub-circuit 3. Discharging branch 22 works in parallel with charging branch 21. The function of discharging branch 22 is to quickly release the energy stored in charging branch 21 after the mains power is disconnected, allowing the DC mobile energy storage system's mains power wake-up circuit to return to its initial state. Without discharging branch 22, charging branch 21 would remain energized for an extended period, failing to generate an effective delay pulse the next time mains power is connected, resulting in the wake-up function failing.

[0030] Furthermore, the charging branch 21 includes a charging current-limiting resistor R2 and a first capacitor C1. One end of the charging current-limiting resistor R2 is connected to the output terminal of the power supply circuit 1, and the other end is connected in series with one end of the first capacitor C1. The other end of the first capacitor C1 is connected to the discharge branch 22.

[0031] The function of the charging current-limiting resistor R2 is to limit the current and protect the first capacitor C1, so that the energy stored in the first capacitor C1 can achieve a delay. The first capacitor C1 and the charging current-limiting resistor R2 are connected in series to form an RC charging circuit, and the corresponding charging current is output to provide the corresponding conduction trigger signal for the subsequent current amplification sub-circuit 3. The first capacitor C1 and the charging current-limiting resistor R2 are connected in parallel to the discharge branch 22, which ensures the electrical isolation between the charging branch 21 and the discharge branch 22, avoids current interference between the two branches, and makes the charging and discharging processes of the first capacitor C1 independent.

[0032] In this example, the resistance of the charging current limiting resistor R2 can be set to 100kΩ. Its main function is to limit the peak current of the first capacitor C1 during initial charging. When the mains power is first connected, the voltage across the first capacitor C1 is 0V. At this time, the charging current will instantly reach a large value. If there is no charging current limiting resistor R2, the excessive charging current will impact the subsequent current amplification sub-circuit 3, causing the components in the current amplification sub-circuit 3 to burn out. The resistance of 100kΩ can limit the initial charging current of the first capacitor C1 to within 240μA (for example, according to Ohm's law I=U / R=24V / 100kΩ=240μA), effectively protecting the circuit safety. When the capacitance of the first capacitor C1 is set to 20μF according to the specified parameters, and when the mains power is connected, the working signal voltage of 24V output from the output terminal of the power supply circuit 1 charges the first capacitor C1 through the charging current limiting resistor R2. The charging voltage across the first capacitor C1 gradually increases over time, and its voltage change follows the RC circuit charging formula: V1(t)=U(1-e^(-t / τ1)), where τ1=R2×C1=100kΩ×20μF=2s, and U is the working signal voltage of 24V output from the output terminal of the power supply circuit 1. When t=5τ1 has elapsed, the voltage across the first capacitor C1 is very close to the working signal voltage of 24V, for example, it can reach 99.3% of the working signal voltage of 24V. In engineering applications, it is approximately considered that the first capacitor C1 has been fully charged.

[0033] For further details, please review. Figure 1 And refer to them together Figure 4 , Figure 4 This is a schematic diagram of the circuit layout when the mains power is disconnected in the embodiment. The discharge branch 22 includes a discharge resistor R1, a first diode D1, and a second diode D2; the discharge resistor R1 is connected in parallel to the power supply circuit 1; the first diode D1 is connected in parallel to the charging current limiting resistor R2, the cathode of the first diode D1 is connected to the output terminal of the power supply circuit 1, and the anode of the first diode D1 is connected to one end of the first capacitor C1; the cathode of the second diode D2 is connected to the other end of the first capacitor C1, and the anode of the second diode D2 is connected to the input terminal of the power supply circuit 1.

[0034] When mains power is connected, the conduction direction of the first diode D1 is opposite to the direction of the working signal voltage output from the output terminal of the power supply circuit 1. Simultaneously, the conduction direction of the second diode D2 is opposite to the direction of the charging current output through the charging current-limiting resistor R2 and the first capacitor C1. This ensures that the first capacitor C1 is reverse-biased during charging through the first diode D1 and the second diode D2, preventing the charging current generated by the working signal voltage output from the output terminal of the power supply circuit 1 flowing through the charging current-limiting resistor R2 from being shunted through the discharge branch 22. This ensures that all charging current flows to the first capacitor C1. When the mains power is disconnected, the first diode D1 conducts forward. The electrical energy stored in the first capacitor C1 flows through the discharge resistor R1 to the input terminal of the power supply circuit 1, generating a corresponding discharge current. The magnitude of the discharge current is determined by the resistance value of the discharge resistor R1. At this time, the discharge resistor R1 and the second diode D2 conduct forward, and the first capacitor C1, the first diode D1, the discharge resistor R1, and the second diode D2 form a complete discharge circuit (e.g., ...). Figure 4 As shown in the figure, the discharge branch 22 and the first capacitor C1 can form a discharge circuit when the mains power is disconnected, ensuring that the first capacitor C1 can discharge quickly after the mains power is disconnected, while avoiding the current shunting of the discharge branch 22 during charging, and ensuring the stability of the first capacitor C1 in adjusting the corresponding pulse duration.

[0035] In this example, a carbon film resistor can be used for the discharge resistor R1. When the charging current-limiting resistor R2 is set to 100kΩ, the discharge resistor R1 can be set to 10kΩ. The two ends of the discharge resistor R1 are directly connected in parallel to the output and input terminals of the power supply circuit 1, forming the main discharge circuit. When the mains power is disconnected, the electrical energy stored in the first capacitor C1 is discharged to the input terminal of the power supply circuit 1 through the discharge resistor R1. The magnitude of the discharge current is determined by the resistance value of the discharge resistor R1; a resistance value of 10kΩ allows for control of the discharge current. The current is controlled at around 2.4mA (for example, according to Ohm's law I=U / R=24V / 10kΩ=2.4mA), which ensures rapid discharge without causing the discharge resistor R1 to overheat and be damaged due to excessive discharge current. The first diode D1 can be a silicon switching diode, connected in parallel with the charging current-limiting resistor R2. Its conduction direction is opposite to the direction of the working signal voltage output from the power supply circuit 1. During the charging process of the first capacitor C1, the 24V working signal voltage output from the power supply circuit 1 causes the cathode of the first diode D1 to... When the potential is higher than the anode potential, the first diode D1 is reverse-biased and cut off, preventing the charging current output from the 24V working signal voltage through the charging current limiting resistor R2 from being shunted through the discharge branch 22, ensuring that all charging current flows to the first capacitor C1. During the discharge process of the first capacitor C1, the anode potential of the first diode D1 is higher than the cathode potential, and the first diode D1 is forward-biased, providing a fast discharge path for the first capacitor C1 and accelerating energy dissipation. The second diode D2 is also a silicon switching diode, connected in series at the end of the first capacitor C1 away from the charging current limiting resistor R2. Its conduction direction is consistent with the direction of the discharge current generated by the discharge resistor R1. During the discharge process, the anode potential of the second diode D2 is higher than the cathode potential, and the second diode D2 is forward-biased, forming a complete discharge circuit with the first diode D1, the discharge resistor R1, and the first capacitor C1. During the charging process, the second diode D2 is reverse-biased and cut off, preventing the charging current from flowing back into the discharge branch 22, further isolating the signal interference between the charging branch 21 and the discharge branch 22.

[0036] Therefore, when the mains power is disconnected and the power supply circuit 1 stops outputting the working signal voltage, the voltage stored across the first capacitor C1 is discharged through the following path: the stored voltage is output through the anode of the first capacitor C1, causing the anode potential of the first diode D1 to be higher than the cathode potential, thus the first diode D1 is forward-biased. The voltage output through the first diode D1 flows through the discharge resistor R1 to generate a discharge current. This discharge current causes the anode potential of the second diode D2 to be higher than the cathode potential, thus the second diode D2 is forward-biased. The voltage then flows through the second diode D2 to the cathode of the first capacitor C1 (e.g., ...). Figure 4 (As shown).

[0037] When the charging current limiting resistor R2 is set to 100kΩ, the discharging resistor R1 is set to 10kΩ, and the capacitance of the first capacitor C1 is set to 20μF, the entire discharge process also follows the RC discharge formula: V2(t)=Ue^(-t / τ2), where τ2=R1×C1=10kΩ×20μF=0.2s. Based on experience, after 5τ2 (1s), the voltage across the first capacitor C1 drops to 0.67% of the initial voltage (approximately 0.16V), which can be considered as the discharge being completed. The DC mobile energy storage system's mains power wake-up circuit returns to its initial state, ensuring that the first capacitor C1 can be recharged and the corresponding pulse duration adjusted when the mains power is connected next time, so that the subsequent wake-up sub-circuit 5 can generate a high-level pulse signal normally.

[0038] For further details, please review. Figure 1 The first-stage amplification branch 31 includes a first transistor Q1 and a collector current limiting resistor R3; the first transistor Q1 and the collector current limiting resistor R3 are connected in series and then connected in parallel to the charging branch 21; the second-stage amplification branch 32 is connected in parallel to the collector current limiting resistor R3.

[0039] When the charging current output from the charging branch 21 flows through the first transistor Q1, it drives the first transistor Q1 to conduct. At the same time, when the working signal voltage output from the power supply circuit 1 flows through the collector current limiting resistor R3, it generates the corresponding first current to be amplified. After the first transistor Q1 conducts, it amplifies the first current to be amplified in one stage, outputting the first stage amplified current. The second stage amplification branch is connected in parallel across the collector current limiting resistor R3. The output first stage amplified current can provide sufficient drive current signal for the second stage amplification branch 32. At the same time, the collector current limiting resistor R3 protects the first transistor Q1 to prevent it from burning out, ensuring the output of the subsequent high-level pulse signal.

[0040] In this example, when the mains power is connected, the charging process of the first capacitor C1 can be divided into three stages: the initial stage (t<τ), the charging voltage across the first capacitor C1 rises rapidly and the charging current is relatively large; the intermediate stage (τ≤t≤3τ), the charging voltage rises gradually slows down and the charging current gradually decreases; the stable stage (t≥5τ), the charging voltage approaches the working signal voltage of 24V and the charging current approaches zero. Meanwhile, for example, by setting the parameters of the charging current limiting resistor R2=100kΩ, the discharging resistor R1=10kΩ and the first capacitor C1=5μF, the time for the first capacitor C1 to charge from the emitter conduction threshold voltage (approximately 0.6~0.7V, here we take 0.7) corresponding to the first transistor Q1 to near saturation voltage (approximately 24V) is specifically based on V1(t')=U(1-e^(-t' / τ')), where τ'=R2×C1=0.5s. When t'=5τ', V1(t')=23.838V has reached 99.3% of the working signal voltage 24V, proving that charging and conduction have been completed. The first capacitor C1 ensures that the current amplification sub-circuit 3 continues to conduct for a pulse duration of 5τ', thereby outputting a high-level pulse signal exceeding 5τ' in the subsequent wake-up sub-circuit 5, which just meets the pulse duration required for the wake-up of the BMS-ACWAKEUP terminal of the wake-up sub-circuit 5.

[0041] Furthermore, the first transistor Q1 is an NPN transistor. Specifically, the first transistor Q1 is connected in series with the collector current-limiting resistor R3 and then connected in parallel across the charging branch 21. The base of the first transistor Q1 is connected to the end of the first capacitor C1 furthest from the charging current-limiting resistor R2. The emitter of the first transistor Q1 is connected to the input terminal of the power supply circuit 1, and the collector of the first transistor Q1 is connected to the collector current-limiting resistor R3. One end of the collector current limiting resistor R3 is connected to the output terminal of the power supply circuit 1, and the other end is connected to the collector of the first transistor Q1. The two ends of the series-connected first-stage amplification branch 31 are respectively connected to the two ends of the charging branch 21, forming a parallel relationship. This connection method allows the first-stage amplification branch 31 to directly detect the charging state of the first capacitor C1. The charging current output by the charging branch 21 flows into the base of the first transistor Q1, driving the collector of the first transistor Q1 to conduct. When the working signal voltage flows through the collector current limiting resistor R3, the corresponding first current to be amplified is output and flows into the first transistor. The collector of Q1 amplifies the first current flowing into it through the first transistor Q1, and then outputs the first-stage amplified current from the emitter of the first transistor Q1. The emitter of the first transistor Q1 is connected to the input terminal of the power supply circuit 1. At the same time, the second-stage amplification branch 32 is connected in parallel with the collector current limiting resistor R3. The first-stage amplified current is delivered to the input terminal of the power supply circuit 1 through the emitter of the first transistor Q1, and the corresponding first-stage amplified current and working signal voltage are output from the output terminal of the power supply circuit 1. After being amplified a second time through the second-stage amplification branch 32, it is input to the subsequent load filter sub-circuit 4.

[0042] In this example, the collector current limiting resistor R3 can be a metal film resistor. When the charging current limiting resistor R2 is set to 100kΩ, the discharging resistor R1 is set to 10kΩ, and the capacitance of the first capacitor C1 is set to 5μF, the collector current limiting resistor R3 can be set to 10kΩ. One end of the collector current limiting resistor R3 is connected to the output terminal of the power supply circuit 1, and the other end is connected to the collector of the first transistor Q1. The first transistor Q1 is an NPN transistor. The emitter of the first transistor Q1 is connected to the input terminal of the power supply circuit 1, and the base is connected to the end of the first capacitor C1 away from the charging current limiting resistor R2. The two ends of the series-connected first-stage amplification branch 31 are respectively connected to the two ends of the charging branch 21, forming... In parallel connection, when the voltage across the first capacitor C1 reaches the emitter conduction threshold voltage (approximately 0.6~0.7V, here we take 0.7V) of the first transistor Q1 (i.e., NPN transistor), the amplification process is immediately started. For example, using the parameters R2=100kΩ and C1=5μF in the above example, it can be seen that the time for the first capacitor C1 to charge from the emitter conduction threshold voltage (approximately 0.7V) of the first transistor Q1 to near saturation voltage (approximately 24V) is approximately 5τ'. The base of the first transistor Q1 is connected to one end of the first capacitor C1, so that the first transistor Q1 can be continuously turned on for 5τ', ensuring that a high-level pulse signal of more than 5τ' can be output subsequently. When the first capacitor C1 is charged to 0.7V, the output charging current flows through the first capacitor C1 to the base of the first transistor Q1, causing the emitter of the first capacitor C1 to be forward biased and conducting. This charging current is the switch that starts the first stage of amplification in the first transistor Q1, not the target current to be directly amplified. The main function of the collector current limiting resistor R3 is to limit the first amplified current I_B1 of the first transistor Q1, preventing the transistor Q1 from burning out due to excessive I_B1. When the first transistor Q1 is conducting, the first amplified current I_B1 is determined by the operating signal voltage 24V of the power supply circuit 1 and the resistance value of the collector current limiting resistor R3 (10kΩ). The operating signal voltage 24V output from the power supply circuit 1 is connected to the first stage of amplification through the collector current limiting resistor R3. Based on Ohm's law, the collector voltage of transistor Q1 is estimated to be I_B1≈(24V-U_CE) / R3, where U_CE is the collector saturation voltage of transistor Q1 (approximately 0.2~0.4V, for example, 0.3V here). Therefore, I_B1≈(24V-0.3V) / 10kΩ≈2.37mA. Combining this with the current amplification factor of transistor Q1 (typically 100), the first current to be amplified from the collector of transistor Q1 can be amplified to 2.37mA×100=237mA, thus generating a first-stage amplification current. This first-stage amplification current can meet the driving requirements of the second-stage amplification branch 32 and is within the safe operating current range of transistor Q1 (for example, the maximum I_C of an NPN transistor is 500mA).

[0043] When the mains power is connected, the first capacitor C1 begins to charge, and the voltage across its terminals gradually increases. When the voltage across the first capacitor C1 reaches 0.7V from 0, the base of the first transistor Q1 receives a forward bias voltage, and the first transistor Q1 saturates and conducts. At this time, the collector saturation voltage of the first transistor Q1 is about 0.3V, and the emitter conduction voltage is about 0.7V. After the first transistor Q1 conducts, the first current to be amplified flows through the collector current limiting resistor R3 to the collector of the first transistor Q1. After being amplified by the first stage of the first transistor Q1, it flows from the emitter of the first transistor Q1 into the input terminal of the power supply circuit 1, and then through the output terminal of the power supply circuit 1 to the input terminal of the second stage amplification branch 32, providing a drive current signal for the subsequent second stage amplification. During the charging process of the first capacitor C1, the first transistor Q1 remains in a saturated conducting state to ensure a stable output of the first-stage amplified signal. When the first capacitor C1 is fully charged, the voltage across the first capacitor C1 approaches 24V, the charging current approaches zero, the base current of the first transistor Q1 is insufficient, the first transistor Q1 changes from the saturated conducting state to the cutoff state, the first current to be amplified disappears, and the first-stage amplification branch 31 stops outputting the first-stage amplification current.

[0044] For further details, please review. Figure 1 The secondary amplification branch 32 includes an emitter limiting current resistor R4, a second transistor Q2, and a base limiting current resistor R5; one end of the emitter limiting current resistor R4 is connected in series with the second transistor Q2, and the other end is connected to the output terminal of the power supply circuit 1; after the second transistor Q2 is connected to the base limiting current resistor R5, it is connected in parallel to the primary amplification branch 31.

[0045] The first-stage amplified current, after being amplified by the first-stage amplification branch 31, flows through the base current limiting resistor R5 and then through the second transistor Q2, triggering the second transistor Q2 to conduct as a small current. One end of the emitter current limiting resistor R4 is connected in series with the second transistor Q2, and the other end is connected to the output terminal of the power supply circuit 1. The working signal voltage output by the power supply circuit 1 flows through the base current limiting resistor R5 and is current-limited to generate the corresponding second current to be amplified. Then, the second current to be amplified flows into the second transistor Q2, and is amplified by the second transistor Q2. It is emitted to the input terminal of the power supply circuit 1 through the emitter of the first transistor Q1, and is output from the output terminal of the power supply circuit 1 to the emitter current limiting resistor R4 connected in series with the emitter of the second transistor Q2. After current limiting, it is output through the collector of the second transistor Q2 to generate the corresponding second-stage amplified current. After the second-stage amplified current is generated, it flows into the subsequent load filter sub-circuit 4 for filtering, and then flows into the wake-up sub-circuit 5 to meet the drive current requirements of BMS wake-up, while ensuring the output of the high-level pulse signal.

[0046] Furthermore, the second transistor Q2 is a PNP transistor. The base of the second transistor Q2 is connected to the base limiting resistor R5, the emitter of the second transistor Q2 is connected to the emitter limiting resistor R4, and the collector of the second transistor Q2 is connected to the load filter circuit 4. One end of the emitter limiting resistor R4 is connected to the output terminal of the power supply circuit 1 (sharing a common node with the input terminal of the collector limiting resistor R3), and the other end is connected to the emitter of the second transistor Q2. The second transistor Q2 is a PNP transistor, and its base is connected to the collector of the first transistor Q1 through the base limiting resistor R5. The collector of the second transistor Q2 is directly connected to the input terminal of the load filter sub-circuit 4. The base current limiting resistor R5 is connected in series between the base of the second transistor Q2 and the collector of the first transistor Q1 to limit the first-stage amplification current flowing into the base of the second transistor Q2, preventing the second transistor Q2 from burning out due to excessive base current. The first-stage amplification current after the first-stage amplification branch 31 is emitted from the emitter of the second transistor Q2 to the base of the second transistor Q2, and then flows through the base current limiting resistor R5 to drive the second transistor. When transistor Q2 is turned on, the base of the second transistor Q2 is connected to the collector of the first transistor Q1. The base potential of the second transistor Q2 is clamped to the collector potential of the first transistor Q1, pulling it down to the collector saturation voltage. Simultaneously, the emitter of the second transistor Q2 is connected to the working signal voltage through the emitter limiting current resistor R4. Therefore, the emitter of the second transistor Q2 receives a reverse bias voltage (the conduction condition for a PNP transistor), causing the second transistor Q2 to saturate and conduct. After the second transistor Q2 is saturated and conducting, the working signal voltage is supplied from power supply circuit 1. The current flows from the emitter of the second transistor Q2 to the base of the second transistor Q2 to generate the corresponding second current to be amplified. This current is then amplified by the second transistor Q2 and emitted through the emitter of the first transistor Q1 to the input of the power supply circuit 1. The output of the power supply circuit 1 is then output to the emitter current limiting resistor R4, which is connected in series with the emitter of the second transistor Q2. After the second-stage amplified current is generated, it flows into the subsequent load filter sub-circuit 4 for filtering and then into the wake-up sub-circuit 5 to meet the drive current for BMS wake-up and ensure the output of the high-level pulse signal.

[0047] In this example, the emitter current limiting resistor R4 and the base current limiting resistor R5 can be metal film resistors. When the charging current limiting resistor R2 is set to 100kΩ, the discharging resistor R1 is set to 10kΩ, the first capacitor C1 is set to 5μF, and the collector current limiting resistor R3 is set to 10kΩ, the emitter current limiting resistor R4 can be set to 100Ω and the base current limiting resistor R5 can be set to 4.7kΩ. The base current limiting resistor R5 is connected in series between the base of the second transistor Q2 and the collector of the first transistor Q1 to limit the first-stage amplification current flowing into the base of the second transistor Q2. The function of the base current limiting resistor R5 is to control the second amplified current I_B2 of the second transistor Q2 to prevent the second transistor Q2 from burning out due to excessive current. The first-stage amplified current flowing through the base of the second transistor Q2 drives it to conduct. When the second transistor Q2 is saturated and conducting, since its base is connected to the collector of the first transistor Q1 through the base-limiting current resistor R5, the base potential of the second transistor Q2 is clamped to the collector potential of the first transistor Q1, approximately 0.3V, when the first transistor Q1 is saturated and conducting. Therefore, the emitter potential of the second transistor Q2 is approximately 0.3V, supplying the 24V output signal voltage of electronic circuit 1. The voltage difference between the base-limiting current resistor R5 and the base of the second transistor Q2 is approximately 24V - 0.3V = 23.7V. According to ohms... According to the law, I_B2≈23.7V / 4.7kΩ≈5.04mA. Considering the current amplification factor of the second transistor Q2 (typically 100), the second amplified current of the second transistor Q2, I_C2≈β×I_B2≈100×5.04mA=504mA. This current is then emitted through the emitter of the first transistor Q1 to the input of the power supply circuit 1. After being limited by the emitter current limiting resistor R4 connected in series with the emitter of the second transistor Q2, the final output of the second transistor Q2's collector is the corresponding second-stage amplified current, approximately 50mA, which meets the drive current requirements for BMS wake-up in the subsequent wake-up sub-circuit 5. Another key function of the emitter current limiting resistor R4 (100Ω) is to stabilize the operating point of the second transistor Q2, preventing output current drift caused by fluctuations in the operating signal voltage of the power supply circuit 1 or temperature changes, ensuring that the second-stage amplified current output during the pulse period remains stable at 50mA. When the secondary amplification current increases and is limited, the voltage across the emitter current limiting resistor R4 (U_R4=I_O×R4) increases, and the emitter voltage U_BE2=U_E-U_R4 of the second transistor Q2 decreases, thereby suppressing the increase of the second current to be amplified I_B2 and achieving stable control of the output current.

[0048] When the first transistor Q1 is saturated and conducting (collector potential 0.3V), the base potential of the second transistor Q2 is clamped to the collector potential of the first transistor Q1, pulling it down to 0.3V. The emitter of the second transistor Q2 is connected to the working signal voltage through the emitter limiting current resistor R4, thus the emitter of the second transistor Q2 receives a reverse bias voltage (the conduction condition for a PNP transistor), and the second transistor Q2 is saturated and conducting. After the second transistor Q2 is saturated and conducting, the working signal voltage flows from the output terminal of the power supply circuit 1 through the emitter of the second transistor Q2 to the base of the second transistor Q2. The corresponding second current to be amplified is generated, and then amplified in two stages by the second transistor Q2. It is then emitted to the input terminal of the power supply circuit 1 through the emitter of the first transistor Q1. After being output by the output terminal of the power supply circuit 1, the current is limited by the emitter current limiting resistor R4 connected in series with the emitter of the second transistor Q2, so that the second-stage amplified current output from the collector of the second transistor Q2 is stabilized at 50mA. The signal strength of this second-stage amplified current is sufficient to trigger the wake-up terminal of the subsequent wake-up sub-circuit 5. At the same time, a high-level pulse signal is generated according to the pulse duration adjusted by the first capacitor C1. During the continuous conduction of the first transistor Q1, the second transistor Q2 synchronously maintains a saturated conduction state, stably outputting a 50mA secondary amplification current. When the mains power is disconnected, that is, when the first transistor Q1 is turned off, its collector potential rises back to 24V, and the base potential and emitter potential of the second transistor Q2 are close (both are 24V), the emitter is zero biased, the second transistor Q2 is turned off, the secondary amplification branch 32 stops outputting the secondary amplification current, ensuring the end of the high-level pulse signal.

[0049] For further details, please review. Figure 1 The load filter sub-circuit 4 includes a filter discharge resistor R6 and a second capacitor C2; one end of the filter discharge resistor R6 is connected in series with the second stage amplification branch 32, and the other end is connected to the input terminal of the power supply circuit 1; the second capacitor C2 is connected in parallel with the filter discharge resistor R6.

[0050] The function of the load filter sub-circuit 4 is to filter out the high-frequency noise of the secondary amplification current output by the secondary amplification branch 32, so as to ensure that the current signal output to the wake-up sub-circuit 5 is smooth and stable. At the same time, the second capacitor C2 is connected in parallel with the filter discharge resistor R6. The filter discharge resistor R6 can prevent the residual energy of the second capacitor C2 during filtering from affecting the next signal output.

[0051] In this example, the filter discharge resistor R6 can be a metal film resistor. When the charging current limiting resistor R2 is set to 100kΩ, the discharging resistor R1 is set to 10kΩ, the first capacitor C1 is set to 5μF, the collector current limiting resistor R3 is set to 10kΩ, the emitter current limiting resistor R4 is set to 100Ω, and the base current limiting resistor R5 is set to 4.7kΩ, the filter discharge resistor R6 can be set to 10kΩ. One end of the filter discharge resistor R6 is connected to the collector of the second transistor Q2, and the other end is connected to the input terminal of the power supply circuit 1. The capacitance of the second capacitor C2 can be set to 100nF. The two ends of the second capacitor C2 are directly connected in parallel with the two ends of the filter discharge resistor R6 to form an RC filter circuit. The cutoff frequency of the RC filter circuit is f_c = 1 / (2πR6C2). Substituting R6 = 10kΩ and C2 = 100nF, we calculate f_c ≈ 1 / (2 × 3.14 × 10kΩ × 100nF) ≈ 159Hz. This cutoff frequency is much higher than the frequency of the secondary amplification current output by the secondary amplification branch 32. For example, with the parameters of charging current limiting resistor R2 = 100kΩ and first capacitor C1 = 5μF, the frequency of the output secondary amplification current is f = 1 / (2t') = 0.2Hz. Therefore, it can effectively filter out high-frequency interference noise in the DC mobile energy storage system's mains wake-up circuit, making the output secondary amplification current smoother and avoiding noise causing false wake-up or wake-up failure at the BMS-ACWAKEUP terminal of the subsequent wake-up sub-circuit 5. Another function of the filter discharge resistor R6 is to quickly release the energy stored in the second capacitor C2 when the DC mobile energy storage system's mains wake-up circuit is cut off. When the second transistor Q2 is turned off, the electrical energy stored in the two ends of the second capacitor C2 is discharged to the input end through the filter discharge resistor R6. The discharge time constant τ3 = R6 × C2 = 10kΩ × 100nF = 1ms. After 5τ3 = 5ms, the voltage across the second capacitor C2 can drop to close to 0V, ensuring that there is no residual electrical energy interference when the next wake-up pulse is output.

[0052] For further details, please review. Figure 1 The wake-up sub-circuit 5 includes an equivalent input resistor R7, which is connected in parallel with the second capacitor C2. The equivalent input resistor R7 serves as the signal receiving interface for the BMS-ACWAKEUP terminal, transmitting the filtered, amplified signal to the BMS-ACWAKEUP terminal to trigger automatic BMS wake-up and generate a high-level pulse signal, requiring no manual operation from the user. The equivalent input resistor R7 is essentially the internal equivalent resistor of the wake-up sub-circuit 5, and its value can be set to 2kΩ. No additional external resistor is needed; the equivalent input resistor R7 is directly connected in parallel across the second capacitor C2 via wiring.

[0053] In this example, after the mains power is connected, the current is amplified twice to 50mA by the energy storage delay sub-circuit 2, and then filtered by the load filter sub-circuit 4 to remove noise. At the same time, the wake-up sub-circuit 5 generates a corresponding high-level pulse signal (the voltage is approximately 24V×(R7 / (R6+R7))≈24V×(2kΩ / (10kΩ+2kΩ))=4V, which meets the voltage threshold requirement for wake-up of the BMS-ACWAKEUP terminal). The BMS-ACWAKEUP terminal monitors this high-level pulse signal in real time. When a high-level pulse signal with a pulse duration ≥5τ' is detected, the internal wake-up logic of the BMS-ACWAKEUP terminal is triggered, thereby completing the entire automatic wake-up process. When the first capacitor C1 is fully charged, the first transistor Q1 and the second transistor Q2 are successively cut off, the high-level pulse signal at both ends of the wake-up sub-circuit 5 disappears, the voltage drops to 0V, the BMS remains in the wake-up state, ensuring that the mains power replenishment process proceeds normally; when the mains power is disconnected, the first capacitor C1 discharges through the discharge branch 22 corresponding to the discharge resistor R1, the first diode D1, and the second diode D2, and the second capacitor C2 discharges through the filter discharge resistor R6, so that the DC mobile energy storage system mains power wake-up circuit returns to the initial state, and the wake-up pulse can be triggered repeatedly when the mains power is connected next time.

[0054] In summary, when the mains power is connected to the DC mobile energy storage system's mains wake-up circuit, the power supply circuit 1 immediately triggers the 24V auxiliary power supply to start. The power supply circuit 1 outputs a 24V working signal voltage to provide continuous power to the entire DC mobile energy storage system's mains wake-up circuit. This working signal voltage is preferentially input to the charging branch 21, flowing through the charging current-limiting resistor R2 and charging the first capacitor C1, thereby outputting a charging current. The charging process of the first capacitor C1 creates a time delay, regulating the duration of subsequent pulses. During this charging process, the first diode D1, the first... Diode D2 is reverse-biased to prevent current shunting during charging, ensuring that capacitor C1 gradually accumulates energy according to the RC charging law. When the voltage across capacitor C1 rises to the conduction threshold of transistor Q1, the first-stage amplification branch 31 is triggered, transistor Q1 saturates and conducts. The collector potential of transistor Q1 drops to the collector saturation voltage, and the operating signal voltage output from electronic circuit 1 is current-limited, generating a first current to be amplified between the charging current-limiting resistor R2 and the collector of transistor Q1. After amplification by transistor Q1, a first-stage amplified current is output. The feedback is sent to the input terminal of the power supply circuit 1 and output again with the working signal voltage. The first-stage amplified current flows through the base-limiting current resistor R5 and drives the second transistor Q2 to conduct. The base of the second transistor Q2 is connected to the collector of the first transistor Q1. The base potential of the second transistor Q2 is clamped to the collector potential of the first transistor Q1, pulling it down to the collector saturation conduction voltage. The emitter of the second transistor Q2 is connected to the working signal voltage through the emitter-limiting current resistor R4. Therefore, the emitter of the second transistor Q2 obtains a reverse bias voltage (the conduction condition of a PNP transistor), making the second transistor... When transistor Q2 is saturated and conducting, the working signal voltage flows from the output terminal of the power supply circuit 1 through the emitter of transistor Q2 to the base of transistor Q2, generating the corresponding second current to be amplified. This current is then amplified by transistor Q2, emitted through the emitter of transistor Q1 to the input terminal of power supply circuit 1, and output from the output terminal of power supply circuit 1 to the emitter current limiting resistor R4 connected in series with the emitter of transistor Q2. Finally, the current is amplified by the collector of transistor Q2 to meet the BMS wake-up requirements of the subsequent wake-up sub-circuit 5.

[0055] Subsequently, the secondary amplified current flows into the load filter sub-circuit 4, where high-frequency noise is filtered out through the RC circuit composed of the filter discharge resistor R6 and the second capacitor C2, forming a smooth filtered current to prevent noise from causing false triggering or failure of BMS wake-up. This filtered current is transmitted to the wake-up sub-circuit 5. Specifically, when it flows through the equivalent input resistor R7, a high-level pulse signal is generated across the equivalent input resistor R7. After the BMS-ACWAKEUP terminal of the wake-up sub-circuit 5 detects the high-level pulse signal, the internal wake-up logic is triggered, automatically starting and keeping the BMS in a wake-up state to ensure normal mains power replenishment.

[0056] When the first capacitor C1 is fully charged, its voltage approaches 24V, and the charging current approaches zero. The base current of the first transistor Q1 is insufficient, causing it to cut off. Simultaneously, the second transistor Q2 loses its drive signal and cuts off. The current amplification sub-circuit 3 stops outputting current, and the wake-up pulse ends. At this time, the BMS remains in the wake-up state, ensuring the subsequent mains power replenishment process continues.

[0057] When the mains power is disconnected, the 24V auxiliary power supply stops outputting, the power supply circuit 1 stops supplying power, and the discharge branch 22 immediately starts. The electrical energy stored in the first capacitor C1 is quickly discharged through the discharge resistor R1, the first diode D1, and the second diode D2 to complete the discharge reset and prevent residual electrical energy from remaining in the first capacitor C1 when the mains power is connected again. At the same time, the second capacitor C2 discharges residual electrical energy through the filter discharge resistor R6 and returns to its initial state. At this time, the static power consumption of the DC mobile energy storage system mains power wake-up circuit approaches zero, waiting for the next mains power connection to repeat the above process, realizing an automatic wake-up cycle without manual operation.

[0058] The above description is merely an embodiment of this utility model and is not intended to limit the scope of this utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of this utility model should be included within the scope of the claims of this utility model.

Claims

1. A mains power wake-up circuit for a DC mobile energy storage system, characterized in that, include: Power supply electronic circuit; An energy storage delay sub-circuit is connected in parallel to the power supply circuit; A current amplification sub-circuit, comprising a first-stage amplification branch and a second-stage amplification branch, wherein the first-stage amplification branch is connected in parallel to the energy storage delay sub-circuit, and the second-stage amplification branch is connected in parallel to the first-stage amplification branch; A load filter sub-circuit, wherein the load filter sub-circuit is connected in series with the secondary amplifier branch; A wake-up sub-circuit is connected in parallel to the load filter sub-circuit.

2. The DC mobile energy storage system mains power wake-up circuit according to claim 1, characterized in that, The energy storage delay sub-circuit includes a charging branch and a discharging branch; the charging branch and the discharging branch are connected in parallel and then connected in parallel to the power supply circuit.

3. The DC mobile energy storage system mains power wake-up circuit according to claim 2, characterized in that, The charging branch includes a charging current-limiting resistor R2 and a first capacitor C1. One end of the charging current-limiting resistor R2 is connected to the output terminal of the power supply circuit, and the other end is connected in series with one end of the first capacitor C1. The other end of the first capacitor C1 is connected to the discharge branch.

4. The DC mobile energy storage system mains power wake-up circuit according to claim 3, characterized in that, The discharge branch includes a discharge resistor R1, a first diode D1, and a second diode D2; the discharge resistor R1 is connected in parallel to the power supply circuit; the first diode D1 is connected in parallel to the charging current limiting resistor R2, the cathode of the first diode D1 is connected to the output terminal of the power supply circuit, and the anode of the first diode D1 is connected to one end of the first capacitor C1; the cathode of the second diode D2 is connected to the other end of the first capacitor C1, and the anode of the second diode D2 is connected to the input terminal of the power supply circuit.

5. The DC mobile energy storage system mains power wake-up circuit according to claim 2, characterized in that, The first-stage amplification branch includes a first transistor Q1 and a collector current limiting resistor R3; the first transistor Q1 and the collector current limiting resistor R3 are connected in series and then connected in parallel to the charging branch; the second-stage amplification branch is connected in parallel to the collector current limiting resistor R3.

6. The DC mobile energy storage system mains wake-up circuit according to claim 5, characterized in that, The first transistor Q1 is an NPN transistor.

7. The DC mobile energy storage system mains wake-up circuit according to claim 1, characterized in that, The secondary amplification branch includes an emitter current limiting resistor R4, a second transistor Q2, and a base current limiting resistor R5; one end of the emitter current limiting resistor R4 is connected in series with the second transistor Q2, and the other end is connected to the output terminal of the power supply circuit; the second transistor Q2 is connected in parallel with the base current limiting resistor R5 and then connected in parallel with the primary amplification branch.

8. The DC mobile energy storage system mains wake-up circuit according to claim 7, characterized in that, The second transistor Q2 is a PNP transistor.

9. The DC mobile energy storage system mains power wake-up circuit according to claim 1, characterized in that, The load filter sub-circuit includes a filter discharge resistor R6 and a second capacitor C2; one end of the filter discharge resistor R6 is connected in series with the second-stage amplification branch, and the other end is connected to the input terminal of the power supply circuit; the second capacitor C2 is connected in parallel with the filter discharge resistor R6.

10. The DC mobile energy storage system mains wake-up circuit according to claim 9, characterized in that, The wake-up sub-circuit includes an equivalent input resistance R7, which is connected in parallel with the second capacitor C2.

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