Pulse delay circuit and A / D converters featuring pulse delay circuits

Abstract

Pulse delay circuit (10; 30) with: - several delay units (DUs) connected in series or as a ring, each delay unit (DU) being constructed from at least one inverter-gate circuit (INV) connected to a ground line and designed to delay a passing pulse signal (PA) by its delay time depending on an input signal (Vin) applied to it; and - a capacitor (13; 33) connected between a signal line, through which the input signal (Vin) is applied to each of the delay units (DU), and the ground line, wherein the capacitor (13; 33) has a capacitance (C), wherein - the capacitor (13; 33) serves as a current source to supply a current that each of the delay units (DU) consumes to invert its state, - the input signal (Vin) is applied to the signal line via a buffer circuit (12; 32), wherein the buffer circuit (12, 32) has an output resistance (R) with a resistance value (R), and - a time constant, determined by the capacitance (C) of the capacitor (13; 33) and the resistance value (R) of an output resistor of the buffer circuit (12; 32), is set to a value less than the reciprocal of a permissible maximum frequency of the input signal (Vin).

Description

[0001] The present invention relates to a pulse delay circuit comprising several delay units, each of which is designed to delay a pulse signal applied to it with a delay time depending on the voltage level of an input voltage applied to it, and to an A / D converter comprising the pulse delay circuit.

[0002] A known A / D converter is of the pulse delay type (TAD type), which is built entirely from digital circuits.

[0003] The TAD-type analog-to-digital converter (ADC) features a pulse delay circuit composed of delay units connected in series or as a ring. Each delay unit is designed to delay an applied pulse signal by a specified delay time, depending on the voltage level of an input voltage signal applied to it. This ADC outputs numerical data indicating the number of delay units the pulse signal has traversed. Since it consists solely of digital circuits, the TAD-type ADC can be manufactured easily and cost-effectively using a CMOS digital circuit fabrication process.

[0004] Furthermore, for stable operation of the TAD-type A / D converter, it is necessary that all delay units forming the pulse delay circuit have a uniform delay time, so that the pulse signal is delayed uniformly when passing through them sequentially (see Fig. 6A). Fig. Figure 6A shows a schematic diagram illustrating a change in the output level of each of the delay units as the pulse signal passes through the pulse delay circuit. In this figure, "Pi" denotes a delay pulse output by the i-th stage delay unit after the pulse signal has passed through this i-th stage delay unit.

[0005] With the development of CMOS circuit miniaturization, the influence of manufacturing tolerances and even the smallest amounts of dust during the transistor formation process on the performance of the manufactured transistors has become increasingly important. If there is a high transistor-to-transistor variation in drive capability, as in Fig. Figure 6B shows that a high unit-to-unit deviation occurs in the delay time, and the resolution of the A / D converted data (the voltage width of the input voltage signal corresponding to 1 LSB) varies to an unacceptable degree.

[0006] To solve such a problem, JP 2007-006369A, for example, proposes to design the transistors forming the pulse delay circuit, which affect the resolution of the A / D converted data, to be larger than the transistors forming other circuits or units of the A / D converter that do not affect the resolution of the A / D converted data, in order to reduce the effects of manufacturing tolerances or minute amounts of dust on the performance of the transistors forming the pulse delay circuit.

[0007] However, since each of the delay units forming the pulse delay circuit is usually built from CMOS inverter gate circuits, switching noise is superimposed on the power supply line of the delay line, which corresponds to the signal line through which the input voltage signal is applied to each delay unit, every time the output of each CMOS inverter gate circuit inverts its state.

[0008] Consequently, switching noise increases when the transistors forming the pulse delay circuit are oversized, as the current consumed by each delay unit increases.

[0009] This leads to the situation that, as in Fig. Figure 6B shows that a deviation in the delay time occurs among the delay units because the level of the input voltage signal varies significantly due to switching noise, and the pulse delay circuit cannot output the delay signals P1, P2, ..., at the same time intervals while the pulse signal passes through the pulse delay circuit.

[0010] From DE 10 2007 022 815 A1, an A / D converter is also known which comprises: a pulse delay circuit provided with a plurality of delay units, wherein the plurality of delay units each contain at least one logic gate and operate based on a level of an input signal, wherein the pulse delay circuit is able to transmit a pulse signal through the plurality of delay units while the pulse signal is delayed by the plurality of delay units, wherein a delay time of each of the plurality of delay units depends on the level of the input signal, and wherein the at least one logic gate is formed from at least one transistor and the at least one first transistor has a first threshold voltage;and a generating circuit capable of obtaining a number of delay units through which the pulse signal has passed within a certain period, in order to generate digital data based on the obtained number, wherein the generating circuit is formed by at least one second transistor, wherein the at least one second transistor has a second threshold voltage, and wherein the first threshold voltage of the at least one first transistor is lower than the second threshold voltage of the at least one second transistor. US 6,928,128 B1 relates to circuits and methods for generating clock signals that have predetermined timing relationships to reference signals.

[0011] The purpose of the present disclosure is to provide a pulse delay circuit and an A / D converter with which the influence of noise components on signals for A / D conversion can be suppressed.

[0012] The problem is solved by the subject matter of the independent claims. Advantageous further developments are specified in the dependent claims.

[0013] According to the present invention, a pulse delay circuit designed to output delay signals at uniform or regular intervals and an A / D converter designed to output A / D converted data with high resolution are provided.

[0014] Further advantages and features of the present invention will become more apparent from the following detailed description, which is made with reference to the accompanying drawing. The drawing shows: Fig. 1A An illustration of the overall structure of an A / D converter with a pulse delay circuit according to a first embodiment of the present invention; Fig. 1B a diagram illustrating the structure of the delay units forming the pulse delay circuit; Fig. 2. An illustration to demonstrate the effects of the capacitor used in the first embodiment compared with a conventional setup without such a capacitor; Fig. 3 an illustration of the overall structure of an A / D converter with a pulse delay circuit according to a second embodiment of the present invention; Fig. 4 an illustration of the overall structure of a frequency converter according to a third embodiment of the present invention; Fig. 5A and Fig. 5B Illustrations to demonstrate the respective structure of modifications of the delay units used in the above embodiments of the invention; and Fig. 6A and Fig. 6B Illustrations to demonstrate the problems of a conventional A / D converter. First embodiment

[0015] Fig. Figure 1A shows an illustration of the overall structure of an A / D converter 1 with a pulse delay circuit 10 according to a first embodiment of the present invention.

[0016] The A / D converter 1, as shown in Fig. Figure 1A shows the pulse delay circuit 10 as an SDL (straight delay line) and a locking and coding circuit 11 as a coding circuit. The pulse delay circuit 10 is composed of M (M is an integer greater than 2) cascaded delay units DU, each of which delays a passing pulse signal PA. The locking and coding circuit 11 detects (locks) a position reached by the pulse signal PA within the pulse delay circuit 10 and outputs digital data (A / D converted data) DT, which consists of a predetermined number of bits indicating which stage of the delay units DU the pulse signal PA has reached. In the drawings, "Pi" (i = 1, 2, ..., M) denotes the output (delay signal) of the i-th stage of the delay unit DU.

[0017] Each delay unit DU is, as in Fig. Figure 1B shows a circuit constructed from a first and a second CMOS inverter-gate circuit (INV) connected in a cascade configuration. Both the first and second CMOS inverter-gate circuits (INV) consist of a p-channel MOSFET and an n-channel MOSFET connected in series between a signal line and a ground line.

[0018] Each delay unit DU receives an input voltage signal Vin as the A / D conversion target via a buffer circuit 12, whose output terminal is connected to the signal line. The pulse signal PA is applied to the control terminals of the first CMOS inverter-gate circuit INV of the delay unit DU in the first stage. The interconnect node of the second CMOS inverter-gate circuit INV is connected to the control terminals of the first CMOS inverter-gate circuit INV of the delay unit DU in the following stage. The delay time of each delay unit DU depends on the voltage level of the input voltage signal Vi. Consequently, the number of delay units DU through which the pulse signal PA traverses during one period of a sampling clock CKS (one sampling period TS) is proportional to the voltage level of the input voltage signal Vin (more precisely, to the average voltage level of the input voltage signal Vin during the sampling period TS).

[0019] A capacitor 13 is connected between the signal line and the ground line. The capacitance C of the capacitor 13 is set such that the time constant, which is determined by the output resistance R of the buffer circuit 12 and the capacitance C of the capacitor 13, is less than the reciprocal of a permissible maximum frequency of the input voltage signal Vin (or a wavelength period of a signal component with the permissible maximum frequency of the input voltage signal Vin).

[0020] The interlocking and coding circuit 11 comprises at least one interlocking circuit for locking or temporarily storing the outputs (delay signals) P1 to PM of the M delay units DU forming the pulse delay circuit 10, and an encoder for converting the output of the interlocking circuit into digital data DT. The interlocking circuit and the encoder operate with a constant power supply voltage.

[0021] All parts of the A / D converter 1, including the capacitor 13, are formed as a semiconductor IC on a semiconductor substrate (IC chip) using a CMOS manufacturing process.

[0022] The locking and coding circuit 11, which serves as the logic working unit of the A / D converter 1, is constructed from transistors designed in accordance with the minimum size defined by a CMOS digital circuit design rule applied in this embodiment (for example, the 90 nm linewidth standard), while the pulse delay circuit 10 is constructed from transistors designed to be larger than the transistors forming the locking and coding circuit 11 in order to ensure that the delay units DU have a uniform delay time.

[0023] The buffer circuit 12 and the capacitor 13 are arranged such that the total value of the output resistance of the buffer circuit 12 and the wiring resistance of the signal line leading from the output terminal of the buffer circuit 12 to each delay unit is approximately 1 / 10 (preferably approximately 1 / 100) of the on-resistance of each delay unit DU. Consequently, according to this embodiment, they are arranged within 1 mm (preferably within 100 µm) of the pulse delay circuit 10.

[0024] The operation of the A / D converter 1, which has the structure described above, is described below. When the A / D converter 1 is supplied with the pulse signal PA and with the sampling clock CKS, which increases each time the sampling period TS elapses, at the delay unit DU of the first stage, the locking and coding circuit 11 outputs the digital data DT describing the voltage level of the input voltage signal Vin.

[0025] Fig. Figure 2 shows a schematic diagram illustrating a change in the voltage level VL over time on the signal line, via which the output of the buffer circuit 12 is supplied to each delay unit DU. In the Fig. 2 The dashed line shows the case in which the capacitor 13 is not provided, as in a conventional A / D converter, and the solid line shows the case in which the capacitor 13 is provided, as in this embodiment.

[0026] If capacitor 13 is not included, the current flows as shown in Fig. As shown in Figure 2, each time the inverter-gate circuits INV of each delay unit DU invert their state, a temporary operating current flows through the inverter-gate circuits INV (and consequently through the delay unit DU). Since this operating current causes a voltage drop due to the output resistance R of the buffer circuit 12 and the wiring resistance, the voltage level VL temporarily drops. In contrast, the magnitude of the voltage drop caused by the output resistance R of the buffer circuit 12 can be reduced if the capacitor 13 is provided, because the capacitor 13 supplies current when the delay unit DU switches, thus reducing the current flowing through the buffer circuit 12.

[0027] The first embodiment described above offers the following advantages. The A / D converter 1 is configured such that the capacitor 13 supplies a current corresponding to the operating current, which flows temporarily each time each delay unit DU inverts its state. Consequently, the magnitude of a drop in the voltage level VL of the input voltage signal Vin applied to each delay unit DU is significantly reduced, since very little current flows through the output resistance of the buffer circuit 12 and the wiring resistance on the input side of the buffer circuit 12.

[0028] Consequently, according to this embodiment, it is possible to generate the A / D converted data with a lower deviation and a higher resolution, since the delay units DU have a uniform delay time.

[0029] In the A / D converter 1, the capacitance C of capacitor 13, together with the output resistance R of the buffer circuit 12, forms a low-pass filter to remove noise components with frequencies above the maximum permissible frequency of the input voltage signal Vin. This enables the removal of the effects (errors) of the noise components on the A / D-converted data DT.

[0030] Furthermore, according to this embodiment, the transistors forming the pulse delay circuit 10 are smaller than other transistors forming the locking and coding circuit 11. Consequently, the proportion of transistors forming the pulse delay circuit 10 whose gate pattern areas lie outside the applied design area due to manufacturing tolerances or a very small amount of dust can be significantly reduced.

[0031] The advantage that the delay units DU can be formed in such a way that they have a uniform delay time, in conjunction with the advantage of providing the capacitor 13 to reduce the extent of a drop in the voltage level VL, makes it possible to further reduce a change in resolution or a DNL (Differential Nonlinearity) error of the A / D converted data DT in order to improve performance.

[0032] The circuit size of the pulse delay circuit 10 is smaller than that of the locking and coding circuit 11. Consequently, the extent of an increase in the circuit size of the entire A / D converter 1 due to an increase in the size of the transistors forming the pulse delay circuit 10 can be very small. Second embodiment

[0033] A second embodiment of the present invention is described below. Fig. Figure 3 shows an illustration of the overall structure of an A / D converter 3 with a pulse delay circuit 30 according to a second embodiment of the present invention. The A / D converter 3 has, as shown in Fig. Figure 3 shows the pulse delay circuit 30 and a locking and coding circuit 31. The pulse delay circuit 30 is constructed from M (= 2a : a is a positive integer) delay units DU, which are connected in a ring to form a ring delay line RDL, with each of the delay units DU being designed to delay the pulse signal PA applied to it. The locking and coding circuit 31 detects (locks) a position reached by the pulse signal PA within the pulse delay circuit 30 and outputs digital data (A / D-converted data) DT, which consists of a bits indicating which stage of the delay units DU the pulse signal PA has reached.

[0034] The delay unit DU of the first stage is constructed from an AND gate, one input of which serves as the start input. The other delay units DU have the same structure as the delay units DU of the first embodiment. The other input of the delay circuit DU of the first stage is connected to the output of the delay unit DU of the last stage. Although not shown in the drawings, the pulse delay circuit 30 is designed to adjust the signal level at the one input of the delay unit DU of the first stage so that the pulse signal PA can continue through the pulse delay circuit 30. Since the construction of such a pulse delay circuit is known, for example, from JP 6-216721, the pulse delay circuit 30 will not be described in detail below.

[0035] The input voltage signal Vin is fed as a drive signal via the buffer circuit 12 to each delay unit DU for analog-to-digital conversion. The delay time of each delay unit DU depends on the voltage level of the input voltage signal Vin. Consequently, the number of delay units DU through which the pulse signal PA passes during one sampling period TS of the sampling clock CKS is proportional to the voltage level of the input voltage signal Vin (more precisely, to the average voltage level of the input voltage signal Vin during the sampling period TS).

[0036] A capacitor 33 is connected between the signal line, through which the output of the buffer circuit 32 is supplied to each delay unit DU, and the ground line. The capacitance C of the capacitor 33 is set such that the time constant, determined by the output resistance R of the buffer circuit 32 and the capacitance C of the capacitor 33, is less than the reciprocal of a permissible maximum frequency of the input voltage signal Vin (or a wavelength period of a signal component with the permissible maximum frequency of the input voltage signal Vin).

[0037] The A / D converter 3 comprises a revolution counter 36, a latching circuit 38, a drive buffer circuit 35, and a delay buffer circuit 37. The revolution counter 36 is a b-bit (b is a positive integer) synchronous counter that performs counting in accordance with a clock signal CKA. The latching circuit 38 latches the count value of the revolution counter 36 at times when a latching pulse LP is rising. The output of the delay unit DU of the last stage is fed as a clock signal CKC to the drive buffer circuit 35, which outputs this signal from its output terminal as a clock signal CKA to the revolution counter 36. The delay buffer circuit 37 is supplied with the sampling clock CKS, which it outputs at its output terminal as a latching pulse LP to the latching circuit 38.

[0038] The drive buffer circuit 35 is composed of several cascaded CMOS inverter-gate circuits. The inverter-gate circuit of the last stage has a drive capability that is sufficiently high with respect to the input capacitance of the clock line of the revolution counter 36. The other inverter-gate circuits have drive capabilities that increase stepwise from the inverter-gate circuit of the first stage.

[0039] The delay buffer circuit 37 has the same structure as the control buffer circuit 35. Consequently, both have the same delay time.

[0040] As in the first embodiment, all parts of the A / D converter 3, which includes the capacitor 33, are formed as a semiconductor IC on a semiconductor substrate (IC chip) using a CMOS manufacturing process.

[0041] Of the components of the A / D converter 3, the latching and coding circuit 31, the revolution counter 36, and the latching circuit 38 are designed in accordance with the minimum size defined by the CMOS digital circuit design rule applied in this embodiment. The pulse delay circuit 30, whose delay units DU should have a uniform delay time, and likewise the drive buffer circuit 35 and the delay buffer circuit 37, which should have the same delay time, are constructed from transistors designed to be larger than the transistors forming the latching and coding circuit 31, the revolution counter 36, or the latching circuit 38.

[0042] The buffer circuit 32 and the capacitor 33 are arranged such that the total value of the output resistance of the buffer circuit 32 and the wiring resistance of the signal line leading from the output terminal of the buffer circuit 32 to each delay unit is approximately 1 / 10 (preferably approximately 1 / 100) of the on-resistance of each delay unit Du. Consequently, in this embodiment, they are arranged within 1 mm (preferably 100 µm) of the pulse delay circuit 10.

[0043] The operation of the A / D converter 3, which has the structure described above, is described below. The locking and coding circuit 31 of the A / D converter 3 operates in the same way as the locking and coding circuit 11 of the first embodiment. The revolution counter 36 counts the number of revolutions of the pulse signal PA passing through the pulse delay circuit 30 (the number of times the pulse signal PA has passed through the pulse delay circuit 30) in accordance with the operating clock CKA. The locking circuit 38 locks the count value of the revolution counter 36 in accordance with the locking pulse LP.

[0044] Since the revolution counter 36 is supplied with the operating clock CKA via the control buffer circuit 35, it can operate stably even if the number of bits of the revolution counter 36 and the input capacitance of the clock line are high.

[0045] The operating times of the revolution counter 36 are delayed from the times of the operating clock CKC output by the pulse delay circuit 30 by the delay time by which the revolution clock CKA is delayed within the control buffer circuit 35. Furthermore, the operating times of the interlock circuit 38 are delayed from the times of the sampling clock CKS by the delay time by which the interlock pulse LP is delayed within the delay buffer circuit 37.

[0046] That is, by delaying the timing of locking or temporarily storing the counter value by the delay time with which the operating time of the revolution counter 36 is delayed, the times at which the locking circuit 38 locks or temporarily stores the counter value of the revolution counter 36 in accordance with the locking pulse LP can be aligned with the times at which the locking and coding circuit 31 locks or temporarily stores the delay pulses from the pulse delay circuit 30 (the outputs from the delay units) in accordance with the sampling clock CKS.

[0047] Following the input of the pulse signal PA and the sampling clock CKS, which increases each time the sampling period TS elapses, the A / D converter outputs 3 (a+b) bits of digital data (A / D converted data DT), which are formed from the a bits of digital data that describe the voltage level of the input voltage signal Vin, which is output by the locking and coding circuit 31, as low-order bit data, and the b bits of digital data that describe the count value that is output by the locking circuit 38, as high-order bit data.

[0048] The second embodiment described above offers the following advantages. The A / D converter 3 offers the same advantages as the A / D converter 1 of the first embodiment, since the capacitor 33 is provided, which is connected between the signal line that supplies the output of the buffer circuit 32 to each delay unit DU and the ground line.

[0049] The A / D converter 3 has a structure in which the pulse delay circuit 30 is built from a ring delay line and the number of cycles of the pulse signal PA passing through the pulse delay circuit 30 is counted by the revolution counter 36. This allows the number of delay unit DU stages to be significantly reduced.

[0050] Furthermore, the transistors forming the pulse delay circuit 30, the drive buffer circuit 35, and the delay buffer circuit 37 are smaller than the other transistors forming the latching and coding circuit 31, the revolution counter 36, and the latching circuit 38. Consequently, the proportion of transistors forming the pulse delay circuit 30, the drive buffer circuit 35, and the delay buffer circuit 37 whose gate pattern areas lie outside the applied design range due to manufacturing tolerances or a very small amount of dust can be significantly reduced.

[0051] The advantage that the delay units DU can be easily formed to have a uniform delay time, in conjunction with the advantage of providing the capacitor 33 to reduce the extent of a drop in the voltage level VL, makes it possible to further reduce a deviation in resolution or a DNL (Differential Nonlinearity) error of the A / D converted data, and to obtain a correspondence between the data of higher-order bits (higher-bit data) and the data of lower-order bits (lower-bit data) of the A / D converted data, due to delay time matching between the drive buffer circuit 35 and the delay buffer circuit 37, thus improving performance. Third embodiment

[0052] A third embodiment of the present invention is described below.

[0053] Fig. Figure 4 shows an illustration of the overall structure of a frequency converter 5 according to a third embodiment of the present invention. The frequency converter 5 serves to divide or multiply the frequency of an external reference signal PB in order to generate an output signal (pulse signal) Pout of a predetermined frequency.

[0054] The frequency converter 5 shows, as in Fig. Figure 4 shows a pulse delay circuit 51, a pulse phase difference coding circuit 52, a computing circuit 53, and a digitally controlled resonant circuit 54. The pulse delay circuit 51 is constructed from several delay units connected as a ring oscillator in the form of a ring, in which a pulse signal PA circulates while being successively delayed by each delay unit. The pulse phase difference coding circuit 52 converts a phase difference (or time period) between a moment at which the reference signal PB rises and a moment at which the reference signal PB next rises into a binary data value Dout.The computing circuit 53 generates control data Din, which indicates the output period of a pulse signal Pout to be output by the digitally controlled resonant circuit 54. This output is achieved by multiplying or dividing the digital binary data value Dout received by the pulse phase difference coding circuit 52 by a predetermined value. The digitally controlled resonant circuit 54 outputs the pulse signal Pout at intervals equal to the period of the reference signal PB, which is frequency-multiplied or frequency-divided, in accordance with the control data Din output by the computing circuit 53 and the delay signal successively output by the pulse delay circuit 51.

[0055] The pulse delay circuit 51 has a structure corresponding to that of the pulse delay circuit 51, plus the buffer circuit 32 and the capacitor 33 of the second embodiment.

[0056] Since the structures of the pulse phase difference coding circuit 52, the computing circuit 53 and the digitally controlled resonant circuit 54 are known, for example, from JP 7-183800, they will not be described in more detail below.

[0057] In short, the setup in which a capacitor is connected between the signal line, through which the input voltage signal Vin is supplied to each delay unit DU, and the ground line, can be applied to a frequency converter with the setup described above. It will be apparent to those skilled in the art that the embodiments described above can be modified in various ways.

[0058] Each of the delay units D forming the pulse delay circuit 10 or 30 is described as being constructed from two cascaded CMOS inverter-gate circuits INV, each comprising a p-channel transistor (PMOSFET) and an n-channel transistor (NMOSFET) connected in series, and supplied with the input voltage signal Vin at the source terminals of their p-channel transistors. However, if each CMOS inverter-gate circuit INV of each delay unit DU is, as in Fig. As shown in Figure 5A, a control transistor (FET) Trc is used to allow external control of the drive current. The input voltage signal Vin can be applied as a control signal to the control terminal of the control transistor Trc. In this case, the signal line through which the input voltage signal Vin is supplied to the control transistor of each of the delay units is connected to the buffer circuit 12 or 32 and the capacitor 13 or 33.

[0059] In short, since the operating period of the inverter gate circuits INV varies depending on the drive current supplied by a DC voltage source, the same advantages as in the above embodiments can be achieved by controlling the drive current through the input voltage signal Vin.

[0060] In this case, the buffer circuit 12 can be omitted, since the input impedance increases with each delay unit DU.

[0061] The delay unit DU does not necessarily have to be composed of two cascaded inverter-gate circuits INV. It can, for example, be configured as shown in Fig. 5B shows that it may consist of only a single inverter-gate circuit, or of three or more than three inverter-gate circuits connected in a cascade.

[0062] Furthermore, the delay unit DU does not necessarily have to be built from inverter-gate circuits. It can, for example, be built from a standard logic gate, such as an AND gate, an OR gate, a NAND gate, or a NOR gate.

[0063] Furthermore, the buffer circuit 12 or 32 can be constructed from only one resistor.

[0064] The preferred embodiments described above serve as examples of the invention of the present application, the scope of protection of which is defined by the appended claims. It should be noted that the preferred embodiments can be modified in various ways, as will be apparent to those skilled in the art.

Claims

[1] Pulse delay circuit (10; 30) with: - several delay units (DUs) connected in series or as a ring, each delay unit (DU) being constructed from at least one inverter-gate circuit (INV) connected to a ground line and designed to delay a passing pulse signal (PA) by its delay time depending on an input signal (Vin) applied to it; and - a capacitor (13; 33) connected between a signal line, through which the input signal (Vin) is applied to each of the delay units (DU), and the ground line, wherein the capacitor (13; 33) has a capacitance (C), wherein - the capacitor (13; 33) serves as a current source to supply a current that each of the delay units (DU) consumes to invert its state, - the input signal (Vin) is applied to the signal line via a buffer circuit (12; 32), wherein the buffer circuit (12, 32) has an output resistance (R) with a resistance value (R), and - a time constant, determined by the capacitance (C) of the capacitor (13; 33) and the resistance value (R) of an output resistor of the buffer circuit (12; 32), is set to a value less than the reciprocal of a permissible maximum frequency of the input signal (Vin). [2] Pulse delay circuit (10; 30) according to claim 1, characterized by , that the capacitor (13; 33) is formed using a CMOS process. [3] Pulse delay circuit (10; 30) according to claim 1, characterized by , that each of the delay units (DU) is built from at least one CMOS inverter gate circuit (INV), to which the input signal (Vin) is applied as the drive voltage of this. [4] Pulse delay circuit (10; 30) according to claim 1, characterized by , that each of the delay units (DU) is constructed from at least one CMOS inverter gate circuit (INV) connected to the ground line and is provided with a current control transistor (Trc) via which the CMOS inverter gate circuit (INV) is connected to a power supply line in order to be supplied with a drive voltage (VDD), wherein the signal line is connected to a control terminal of each of the current control transistors (Trc) such that the drive voltage (VDD) is applied as the input signal (Vin) to each of the delay units (DU). [5] (10; 30) according to claim 1, characterized by , that each of the delay units (DU) is built from a commercially available logic circuit cell. [6] A / D converter (1; 3) with: - a pulse delay circuit (10; 30) according to claim 1; and - a coding circuit (11; 31) that generates numerical data indicating the number of delay units (DU) that the pulse signal (PA) has passed through within a predetermined time, wherein - the numerical data, which is output as A / D converted data, describe a voltage level of the input signal (Vin). [7] A / D converter (1; 3) according to claim 6, characterized by , that the transistors forming the pulse delay circuit (10; 30) are larger than the transistors forming the coding circuit (11; 31). [8] A / D converter (3) according to claim 6, characterized by , that the delay units (DU) are connected in a ring to form a ring delay line (RDL), and the coding circuit (31) includes: - a revolution counter (36) which counts the number of times the pulse signal (PA) has passed through the pulse delay circuit (30); - a low-order bit encoder (31) which outputs data indicating the position of the pulse signal (PA) within the pulse delay circuit (30) as low-order bit data; and a higher-order bit encoder (38) which outputs data indicating a count value of the revolution counter (36) as higher-order bit data.

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