Devices and methods for shifting a digital signal by a shift time to provide a shifted signal

Abstract

A device (100) for shifting a digital signal (111) with a first sampling rate by a shift time to provide a shifted signal (112) with a second sampling rate, comprising: a sample rate converter (110) configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal (112), wherein the interpolated signal is based on the digital signal (111), and wherein the value of the interpolated signal is a time-shifted version of the digital signal at the second sample rate; wherein the sample rate converter is configured to modify a time interval between a sample time of the digital signal (111) and the compensated sample time based on the shift time, wherein the compensated sample time is determined based on a nominal sample time corresponding to the second sample rate and the shift time.

Description

Area

[0001] Examples relate to the temporal shifting of digital signals. In particular, examples relate to devices and methods for shifting a digital signal by a shift time to provide a shifted signal. background

[0002] In various applications, it is necessary to shift a digital signal in time. For example, a digital signal can be shifted in time to delay its transmission. In mobile communication applications, for instance, data values ​​or symbols of a digital signal are represented by complex numbers or complex-valued symbols, which can generally be described by an in-phase (I) and quadrature (IQ) component, or a radius (R) and phase (p) component. The I and Q components, or the R and p components, of the complex-valued samples or symbols are often processed individually before being combined to create a combined signal; for example, a transmit signal can be generated by combining the individual components of a baseband signal.In individual processing, the propagation delay (PDD) for each component can differ due to its respective processing path. Therefore, when combined after individual processing, the individual components may be temporally misaligned, causing signal distortion. To avoid this, a digital delay block is typically placed within the faster of the processing paths. This ensures that the PDDs of the individual processing paths match and that the I and Q components, or the R and p components, are temporally aligned when combined. An example of such a digital delay block is a first-order all-pass filter, which allows for fine-tuning of the delay. However, such digital filter elements have a comparatively high power consumption, especially as the bandwidth increases.For universal mobile telecommunications systems (UMTS) with a bandwidth of 3.84 MHz, the power consumption of such digital filters can still be an acceptable fraction of a transmitter's total power budget. However, for carrier-aggregated signals with a bandwidth of, for example, 40 MHz, as used in long-term evolution communication networks (LTE networks), the power consumption of such digital filter elements can consume a large portion of a transmitter's power budget. Therefore, there is a need to improve the time-shifting of digital signals.

[0003] US 2010 / 0091922A1 relates to a sample rate converter circuit that receives a first signal with a first sampling frequency and outputs a second signal that is representative of the first signal and has a second sampling frequency. The sample rate converter includes: a buffer for storing data samples received from the first signal; a first loop circuit for receiving a first clock signal corresponding to the first sampling frequency and a second clock signal corresponding to the second sampling frequency, and for generating an estimate of the ratio of the first sampling frequency to the second sampling frequency;and a second loop circuit for receiving the first clock signal, the second clock signal, and estimating the ratio of the first sampling frequency to the second sampling frequency, and for outputting a write pointer so that the data samples can be stored in the buffer, and for outputting a read pointer so that the data samples can be read from the buffer, with a first offset between the read pointer and the write pointer such that the first offset is essentially independent of the ratio of the first sampling frequency to the second sampling frequency.

[0004] US 2013 / 0002457A1 relates to a sample rate converter that converts an incoming data stream clocked at a first frequency into an output data stream that can be clocked at a second frequency. The sample rate converter up-samples an incoming data stream, filters the up-sampled incoming data stream, interpolates the filtered up-sampled data stream, and then stores the interpolated, filtered up-sampled incoming data stream in a FIFO at the first frequency. The interpolated, filtered up-sampled data can then be read from the FIFO at the second frequency. A control block containing a numerically controlled oscillator (NCO) that generates the first frequency is provided.The control of the generation of the first frequency by the NCO is based on the status of the FIFO, the modulation of the data stream, and the ratio of the sampling rate of the incoming data stream to the output or read rate of the data stream.

[0005] US 2013 / 0003894A1 relates to a method and apparatus for adjusting the delay of a first data stream relative to a second data stream. A device receives first and second data streams with identical content. A time difference between the first and second data streams is estimated. At least the leading data stream is fed to a sample rate converter. The sample rate converter is configured to receive a data stream at an input sample rate and output the data stream at an output sample rate. Based on the estimated time difference, a delay is applied to the leading data stream by changing the sample rate of the sample rate converter. The output sample rate of the sample rate converter can be adjusted until both data streams are synchronized. Brief description of the characters

[0006] Some examples of devices and / or methods are described below only by way of example and with reference to the accompanying figures, in which Fig. 1 represents an example of a device for shifting a digital signal with a first sampling rate by a shift time to provide a shifted signal with a second sampling rate; Fig. 2 represents an example of an implementation for providing a compensated sampling time for a sample of the shifted signal; Fig. 3 represents another example of an implementation to provide a compensated sampling time for a sample of the shifted signal; Fig. 4 represents another example of an implementation for providing a compensated sampling time for a sample of the shifted signal; Fig. 5 represents an example of a device for shifting a digital signal by a shift time to provide a shifted signal; Fig. 6 examples of a time history diagram for a digital signal and a shifted signal; Fig. 7 an example of a transmitter comprising a digital modulator comprising a device for shifting a digital signal with a first sampling rate by a shift time to provide a shifted signal with a second sampling rate, or an example of a device for shifting a digital signal by a shift time to provide a shifted signal; Fig. 8 an example of a mobile communication device that includes a device for shifting a digital signal with a first sampling rate by a . includes a shift time to provide a shifted signal with a second sampling rate, an example of a device for shifting a digital signal by a shift time to provide a shifted signal, an example of a digital modulator, or an example of a transmitter; Fig. 9 presents a flowchart of an example of a procedure for shifting a digital signal with a first sampling rate by a shift time to provide a shifted signal with a second sampling rate; and Fig. Figure 10 shows a flowchart of an example of a procedure for shifting a digital signal by a shift time to provide a shifted signal. Detailed description

[0007] Several examples will now be described in more detail with reference to the accompanying drawings, which illustrate some of these examples. For the sake of clarity, the thickness of the lines, layers, and / or regions in the figures may be exaggerated.

[0008] The following examples refer to devices (e.g., mobile phone, base station) or components (e.g., transmitter, transceiver) of devices used in wireless or mobile communication systems. A mobile communication system may, for example, correspond to one of the mobile communication systems standardized by the 3rd Generation Partnership Project (3GPP), e.g.,the Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), High Speed ​​Packet Access (HSPA), Universal Terrestrial Radio Access Network (UTRAN) or Evolved UTRAN (E-UTRAN), Long Term Evolution (ETE) or Advanced LTE (LTE-A), or mobile communication systems with different standards, e.g., Worldwide Interoperability for Microwave Access (WIMAX) IEEE 802.16 or Wireless Local Area Network (WLAN) IEEE 802.16.11, generally any system based on time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal frequency division multiple access (OFDMA), code division multiple access (CDMA), etc. The terms mobile communication system and mobile communication network may be used synonymously.

[0009] The mobile communication system can comprise multiple transmit points or base station transceivers that effectively communicate radio signals to a mobile transceiver. In these examples, the mobile communication system can include mobile transceivers, relay transceivers, and base station transceivers. The relay transceivers and base station transceivers can consist of one or more central units and one or more remote units.

[0010] A mobile transceiver or mobile device can be a smartphone, mobile phone, user equipment (UE), laptop, notebook, personal computer, personal digital assistant (PDA), universal serial bus (USB) connector, tablet computer, car, etc. A mobile transceiver or port can also be referred to as a UE or user, according to 3 GPP terminology. A base station transceiver can be located in the fixed or stationary part of the network or system. A base station transceiver can be a radio remote head, transmit point, access point, macrocell, small cell, microcell, picocell, femtocell, metrocell, etc. The term small cell can refer to any cell smaller than a macrocell, i.e.,A microcell, picocell, femtocell, or metrocell. A femtocell is considered smaller than a picocell, which is considered smaller than a microcell. A base station transceiver can be a wireless interface of a wired network that enables the transmission and reception of radio signals to a UE, mobile transceiver, or relay transceiver. Such a radio signal may correspond to radio signals standardized, for example, by 3GPP, or generally to one or more of the systems listed above. Thus, a base station transceiver can correspond to a NodeB, an eNodeB, a BTS, an access point, etc. A relay transceiver can correspond to an intermediate network node in the communication path between a base station transceiver and a mobile transceiver.A relay station transceiver can forward a signal received from a mobile transceiver to a base station transceiver, or signals received from the base station transceiver to the mobile station transceiver.

[0011] The mobile communications system can be cellular. The term cell refers to a coverage area of ​​radio services provided by a transmit point, remote unit, remote head, remote radio head, base station transceiver, repeater transceiver, or NodeB / eNodeB. The terms cell and base station transceiver can be used interchangeably. In some examples, a cell may correspond to a sector. For example, sectors can be achieved using sector antennas, which provide a characteristic for covering a rectangular section around a base station transceiver. In some examples, a base station transceiver or remote unit may operate, for example, three to six cells, covering sectors of 120° (in the case of three cells) or 60° (in the case of six cells).Similarly, a relay transceiver can establish one or more cells within its coverage area. A mobile transceiver can be registered with or assigned to at least one cell, meaning it can be associated with a cell such that data can be exchanged between the network and the mobile device within the coverage area of ​​the assigned cell using a dedicated channel, link, or connection. A mobile transceiver can thus be registered with or assigned to a relay or base station transceiver directly or indirectly, with indirect registration or assignment occurring through one or more relay transceivers.

[0012] Fig. Figure 1 represents an example of a device 100 for shifting a digital signal 111 with a first sampling rate by a shift time to provide a shifted signal 112 with a second sampling rate.

[0013] The device 100 comprises a sample rate converter 110 for converting the first sample rate of the digital signal 111 into the second sample rate. The first sample rate can be the same as the second sample rate or it can differ from the second sample rate. For example, the first sample rate can be lower than the second sample rate, or vice versa. The ratio between the first and second sample rates, also called the sample rate conversion factor, can be an integer or a non-integer. That is, in some examples, the sample rate converter 110 can be a fractional sample rate converter.

[0014] The sample rate converter HO provides a value of an interpolated signal at a compensated sampling time as a sample of the shifted signal 112. The interpolated signal is based on (depends on) the digital signal 111 and can be represented as a continuous or discontinuous waveform encompassing the samples of the digital signal 111. For example, the sample rate converter 110 can

[0015] Determine the signal from samples of the digital signal 111. The sampling rate converter 100 can, for example, provide the value of the interpolated signal as the sample value of the shifted signal 112 by evaluating the interpolated signal at the compensated sampling time.

[0016] A time interval between a sampling time of the digital signal 111 and the compensated sampling time is modified based on the time shift by the sampling rate converter. Accordingly, the shifted signal 112 can be shifted in time relative to the digital signal 111 by the device 100. The time interval can be constant or it can be time-varying, for example, to implement a variable delay.

[0017] For example, the time interval can be reduced or increased by the shift time with respect to a time interval between the sampling time of digital signal 111 and a compensated (additional) sampling time for a shift time of zero. A shift time of zero can be considered a nominal sampling time corresponding to the second sampling rate. Accordingly, the shifted signal 112 is not intentionally shifted in time with respect to digital signal 111 when the shift time is zero. However, a delay between the signals may exist due to an intrinsic propagation delay of the sampling rate converter 110. By reducing the time interval, the shifted signal 112 can be delayed with respect to digital signal 111.By increasing the time interval, a third signal can be effectively delayed with respect to the shifted signal 112, since the shifted signal 112 effectively progresses in time with respect to the third signal.

[0018] Device 100 allows a digital signal to be shifted in time using inherent characteristics of the HO sample rate converter. Device 100 allows a digital signal to be shifted in time while changing or maintaining a constant sample rate. Accordingly, Device 100 can be used in various applications, such as delaying a digital signal. For example, Device 100 can be used in a loudspeaker or headphone circuit to compensate for temperature-dependent propagation delays in the analog circuitry of the loudspeaker or headphone. Furthermore, Device 100 can be used, for example, to implement signal delays for beamforming in a multiple-input, multiple-output antenna structure (MIMO antenna structure; MIMO = Multiple Input Multiple Output).The device 100 can also be used in various other applications related to mobile communications. In general, the device 100 can be used in any application for time-shifting a digital signal. Since the time shift is achieved by utilizing the inherent characteristics of the... By implementing the sampling rate converter 110, additional delay elements in a circuit arrangement can be avoided using the device 100. Accordingly, the power consumption of the circuit arrangement can be reduced, and the required area on a semiconductor substrate supporting the circuit arrangement can be minimized.

[0019] The device may have one or more additional optional features that correspond to one or more aspects of the proposed concept or to one or more of the examples described below.

[0020] Generally speaking, some examples refer to a means of shifting a digital signal with a first sampling rate by a shift time to provide a shifted signal with a second sampling rate. The means of shifting includes a means of providing a value of an interpolated signal at a compensated sampling time as a sample of the shifted signal, where the interpolated signal depends on the digital signal. A time interval between a sampling time of the digital signal and the compensated sampling time is modified based on the shift time. The means of shifting can be defined by a preceding or following (e.g., Fig. 1) The device described for shifting a digital signal with a first sampling rate by a shift time to provide a shifted signal with a second sampling rate may be implemented. The means for providing a value of an interpolated signal may be a pre- and post-processor (e.g., Fig. 1) described sample rate converter be implemented.

[0021] Fig. Figure 2 presents an example 200 of an implementation for providing a compensated sampling time for a sample of the shifted signal. Example 200 can be found, for example, in the section on Fig. 1 represented sample rate converter 110 implemented.

[0022] An interpolation unit 210 is used in a sample rate converter (e.g., the one in Fig. The sample rate converter 110 (shown in Figure 1) is provided to determine an interpolated signal from input samples of the digital signal 111, for example, a signal based on an interpolation function determined from the input sample of the digital signal 111. To be able to provide a sample of the shifted signal 112, it is necessary to provide an output sample time, for example, the compensated sample, to the interpolation unit 210. Example 200 presents a specific implementation for providing the compensated sample time to the interpolation unit 210.

[0023] A nominal sampling time, corresponding to the second sampling rate, is calculated by a nominal sampling time calculation unit 220. As shown above, the nominal sampling time corresponds to a compensated sampling time for a shift time of zero; that is, the nominal sampling time is a sampling time for which a sample rate converter is merely used to convert sample rates, i.e., to provide a time moment for an output sample of the signal to the second sampling rate. In other words, for a shift time of zero, a sample rate converter, according to the examples described herein, merely converts the digital signal 111 at the first sampling rate to the second sampling rate without intentionally shifting it in time; that is, only the sampling rate of the shifted signal 112 is changed compared to the digital signal 111.

[0024] The compensated sampling time of this particular implementation is provided by adding or subtracting the shift time At from the nominal sampling time using an adder 230. The shift time At is provided by a shift time provisioning unit 240. The interpolation unit 210 provides a value of the interpolated signal as the sample value of the shifted signal 112, for example by evaluating the interpolated function at the compensated sampling time.

[0025] Depending on how the time between the adder 230 and the shift time provision unit 240 is encoded, a format conversion for the shift time At may be required. Therefore, a format conversion unit 250 is provided. For sample rate converters, time can be encoded, for example, as a ratio between an input rate and an output rate, or vice versa. For a static output rate or limited time accuracy requirements, the format conversion can be performed when the sample rate converter is started up; for example, the format conversion unit 250 can be implemented as a firmware routine that is executed when the sample rate converter is started up. In the case of a dynamically varying output rate with high time accuracy requirements, the format conversion unit 250 can be implemented as a hardware or software block for format conversion.Implementing an additional hardware block for the format conversion unit 250 to the sample rate converter 110 to provide time shift capabilities can be advantageous in terms of power consumption and the required area on the chip, compared to providing digital filters as delay elements.

[0026] In other words, the time shift can be implemented using an adder in the sample rate converter 110. Depending on the actual way in which the time between the two blocks is adjusted in Fig. If the output rate is encoded (typically as a ratio between input and output rate or vice versa), format conversion may be necessary. For a static output rate or limited accuracy requirements, format conversion can be performed once at startup, i.e., as a firmware routine. In the case of a dynamically varying output rate with high accuracy requirements, a hardware block may be required to perform the conversion. However, even this hardware block may be more economical in terms of area and power consumption than a digital filter to generate a shifted signal.

[0027] Example 200 of an implementation for providing a compensated sampling time may include one or more additional optional features corresponding to one or more aspects of the proposed concept or to one or more of the examples described above.

[0028] Fig. Figure 3 presents another example 300 of an implementation for providing a compensated sampling time for a sample of the shifted signal. Example 300 can be found, for example, in the Fig. The sample rate converter 110 shown in the diagram is implemented.

[0029] An interpolation unit 210 is used in a sample rate converter (e.g., the one in Fig. The sample rate converter 110 (shown in Figure 1) is provided to determine an interpolated signal from input samples of the digital signal 111, for example, a signal based on an interpolation function determined from the input sample of the digital signal 111. To be able to provide a sample of the shifted signal 112, it may be necessary to provide an output sample time, for example, the compensated sample, to the interpolation unit 210. Example 300 presents a specific implementation for providing the compensated sample time to the interpolation unit 210.

[0030] The compensated sampling time is provided by a compensated sampling time calculation unit 320. The compensated sampling time calculation unit 320 can be a calculation unit suitable for calculating sampling times when the offset time At is static. A compensated sampling time is calculated using a preprocessing unit 321, an integrator 322, and a postprocessing unit 323. The static offset time At allows the compensated sampling time to be provided by modifying a start value for the integrator 322 by a value relative to the offset time At.

[0031] At the in Fig. In Example 200, the shift time At is added to or subtracted from the nominal sample time output by the nominal sample time calculation unit 220. Compared to Example 200, Example 300 allows additional units for adding the shift time At to the output of a unit. Calculating the sampling time is eliminated. Modifying a starting value for an integrator by the shift time within the unit to calculate the sampling time eliminates the power consumption of the additional units. Furthermore, no additional area on a semiconductor substrate is required for the additional units. For a static shift time At, Example 300 can therefore be advantageous with regard to power consumption and the required area on a semiconductor substrate.

[0032] In other words, for a static offset At, one can exploit the fact that an output time calculation block typically uses some kind of integrator. Adding a constant to the output of an integrator is equivalent to starting the integrator with an offset. Adding the time offset as the initial value of an integrator consumes no additional processing power.

[0033] Example 300 of an implementation for providing a compensated sampling time may include one or more additional optional features that correspond to one or more aspects of the proposed concept or to one or more of the examples described above.

[0034] Fig. Figure 4 presents another example of an implementation for providing a compensated sampling time for a sample of the shifted signal. Example 400 can be found, for example, in the section on Fig. The sample rate converter 110 shown in the diagram is implemented.

[0035] Determining the interpolation signal from input samples of the digital signal 111 is divided into a first part 440-1, which runs at the first sampling rate, and a part 4402, which runs at the second sampling rate. Accordingly, an interface between the first part 440-1 and the second part 440-2 can be asynchronous if the second sampling rate differs from the first. Reliable data transfer through the interface is required. Therefore, a first-in, first-out (FIFO) memory 450 can be provided as the interface between the first part 440-1 and the second part 4402.

[0036] The fill level of the FIFO 450 corresponds to a temporal relationship between the first and second sampling rates. Therefore, modifying the fill level of the FIFO 450 allows for modification of this temporal relationship. For stable operation of a sampling rate converter, it is essential that the temporal relationship between the two sampling rates remains unchanged. Accordingly, it is necessary to maintain a constant average fill level in the FIFO 450.

[0037] To control the fill level of the FIFO 450, a controller or control loop can be provided which includes a fill level detector 460 for detecting the fill level of the FIFO 450, a comparator 470 for comparing the detected fill level with a target fill level value and a sampling time calculation unit 430 for calculating the compensated sampling times.

[0038] A FIFO generally introduces a delay to the data supplied to it, with the delay being relative to the FIFO's fill level. The target fill level determines the desired fill level of the FIFO. Accordingly, controlling the fill level of FIFO 450 can be used to control the temporal relationship between the first sampling rate and the second sampling rate, and thus to shift the output samples of the shifted signal 112 relative to the input samples of the digital signal 111.

[0039] The fill level of FIFO 450 is detected by the level detector 460 and compared with a target fill level value by the comparator 470. The target fill level value can be manipulated by adding or subtracting a value related to a displacement time At to / from the target fill level value using a first processing unit, e.g., an adder 480. The result of the comparison between the detected fill level and the target fill level value, determined by the comparator 470, is provided to a second processing unit, e.g., the sampling time calculation unit 430. The sampling time calculation unit 430 uses the given result (e.g., in an integration process such as in conjunction with Fig. 3 described) for calculating the compensated sampling time.

[0040] The sampling time calculation unit 430 also provides information to the FIFO 450 relating to the result of the comparison between the detected fill level and the fill level target value, which is determined by the comparator 470.

[0041] The temporal relationship between the first and second sampling rates, i.e., the time interval between the digital signal sampling time and the compensated sampling time, can be adapted to a desired temporal relationship by manipulating the target level value. A correspondingly adjusted, compensated sampling time can be provided for the FIFO 450 by manipulating the target level value.

[0042] In other words, the interpolation function calculation can be split into a part that runs on an input rate and one that runs on an output rate. Since the interface between the two can be considered asynchronous, it is necessary to implement some form of safe data transfer between them. A FIFO (Field-In, First-Out) can be one such option. For stable system operation even in the case of errors or inaccuracies, a control loop can be in place to keep the average FIFO level constant, which is equivalent to maintaining a stable temporal relationship between the input and output sampling rates. The control loop can measure the FIFO level (i.e., the temporal relationship between input and output), compare it to a target value, and feed the error back into the timing function.Since the FIFO implements a delay for the sampled values, a change in its average fill level can delay the output sampled values. Therefore, a desired time delay At can be added to the FIFO fill level target, and the control loop can effectively adjust the sampled value generated by the output time calculation block by inserting the required offset into the integrator.

[0043] Example 400 of an implementation for providing a compensated sampling time may include one or more additional optional features that may correspond to one or more aspects of the proposed concept or to one or more of the examples described above.

[0044] Fig. Figure 5 represents an example of a device 500 for shifting a digital signal by a shift time to provide a shifted signal 514.

[0045] The device 500 includes a sample rate converter 510 for converting the digital signal 511 with a first sample rate into the shifted signal 514 with a second sample rate. The first sample rate and the second sample rate can be the same or different. For example, the first sample rate can be lower than the second sample rate, or vice versa. The ratio between the first and second sample rates, which can also be called the sample rate conversion factor, can be an integer or a non-integer. That is, in some examples, the sample rate converter 510 can be a fractional sample rate converter.

[0046] The sampling rate converter 510 adjusts a time interval between a sampling time of a sample of the digital signal 511 and a sampling time of a sample of the shifted signal 514 based on the shift time. For example, the sampling rate converter 510 can increase or decrease the time interval based on the shift time. Accordingly, the device 500 can shift the shifted signal 514 in time with respect to the digital signal 511.

[0047] For example, the time interval can be reduced or increased with respect to a hypothetical time interval between the sampling time of the digital signal 511 and the sampling time of a sample of a shifted signal for a shift time of zero. A shift time of zero can be considered a nominal sampling time corresponding to the second sampling rate. Accordingly, the shifted signal 514 is not shifted in time with respect to the digital signal 511 when the shift time is zero. However, a delay exists between the signals due to an intrinsic propagation delay of the sample rate converter 510. By reducing the time interval, the shifted signal 514 can be shifted with respect to the digital signal 511.By increasing the time interval, a third signal can be effectively delayed with respect to the shifted signal 514, since the shifted signal 514 effectively progresses in time with respect to the third signal.

[0048] The device 500 allows a digital signal to be shifted in time using inherent characteristics of the sampling rate converter 510. The device 500 allows a digital signal to be shifted in time while changing or maintaining a sampling rate of the digital signal. Accordingly, the device 500 can be used in various applications, such as delaying a digital signal. For example, the device 500 can be used in a loudspeaker or headphone circuit to compensate for temperature-dependent propagation delay variations in the analog circuitry of the loudspeaker or headphone. Furthermore, the device can be used, for example, to implement signal delays for beamforming in a multi-input, multi-output (MIMO) antenna array.The device 100 can also be used in various other applications related to mobile communications. In general, the device 500 can be used in any application for time-shifting a digital signal. Since the time shift is achieved by utilizing the inherent characteristics of the sample rate converter 510, additional delay elements in a circuit arrangement can be avoided when using the device 500. Accordingly, the power consumption of the circuit arrangement can be reduced, and the required area on a semiconductor substrate supporting the circuit arrangement can be minimized.

[0049] In some examples, the device 500 may optionally include a first input 520 for receiving the digital signal 511, a second input 530 for receiving a first control signal 512 containing information about the shift time, and a third input 540 for receiving a second control signal 513 containing information about the ratio of the first sampling rate to the second sampling rate. The device 500 may optionally also include an output 550 for providing the shifted signal 514.

[0050] The device may include one or more additional optional features corresponding to one or more aspects of the proposed concept or to one or more of the examples described above or below. In particular, the sample rate converter 510 may include examples of an implementation for providing the sample time of the sampled value of the shifted signal, similar to examples 200, 300, and 400 of an implementation for providing a compensated sample time for a sampled value of the shifted signal, as described in Fig. 2 to 4 are shown.

[0051] Generally speaking, some examples refer to a means of shifting a digital signal by a shift time to provide a shifted signal. The shifting means includes a means of converting the digital signal at a first sampling rate into the shifted signal at a second sampling rate. The conversion means adjusts a time interval between a sampling time of a sample of the digital signal and a sampling time of a sample of the shifted signal based on the shift time.The means for converting the digital signal can be configured to receive the digital signal at a first means of receiving a signal, to receive a first control signal, which includes information about the shift time, at a second means of receiving a signal, and to receive a second control signal, which includes information about a ratio of the first sampling rate to the second sampling rate, at a third means of receiving a signal. Furthermore, the means for converting the digital signal can include a means for providing the shifted signal. The shifting means can be implemented by a pre- or post-processor (e.g., a ). Fig. 5) The device described for shifting a digital signal by a shift time to provide a shifted signal may be implemented. The conversion means may be a preceding or subsequent (e.g., Fig. 5) the sample rate converter described. The first, second, and third means of receiving a signal can be implemented by a pre- or post-processor (e.g., Fig. 5) the input described above. The means for providing the shifted signal can be implemented by a preceding or subsequent input (e.g. Fig. 5) described output must be implemented.

[0052] Fig. Figure 6 presents examples of a time-history diagram for a digital signal and a shifted signal. The upper and lower parts of Fig. Figure 6 presents two time-based graphs for sample rate conversion processes of a digital signal according to one or more aspects of the proposed concept or one or more examples described above or below. In the following time-based graphs, the abscissa (t) represents the time axis in arbitrary units, and the ordinate (Amp, Phi) represents the absolute value (magnitude) of the signal samples in arbitrary units.

[0053] In the upper part of Fig. In the sample rate conversion process shown in Figure 6, a first sample rate is converted into a second sample rate. That is, a digital input signal is represented by a series of discrete first samples (solid line with a filled circle on top) at first sample times ti, ..., ts. The first sample times ti, ..., ts are separated by equidistant first time intervals Atl, which correspond to the first sample rate. A shifted output signal is represented by a series of discrete second samples (solid line with an empty circle on top) at second sample times ti', ..., tis'. The second sample times are separated by equidistant second time intervals At2, which correspond to the second sample rate. The first time interval Atl differs from the second time interval At2 if the first sample rate differs from the second sample rate. In the upper part of Figure 6, the first time interval Atl differs from the second time interval At2. Fig. In the time-history diagram shown in Figure 6, it is assumed that the first sampling rate is lower than the second sampling rate. That is, the first time interval Atl between values ​​of the first sample is larger than the second time interval At2 between values ​​of the second sample.

[0054] During the sample rate conversion process, a continuous interpolation function can be determined from the discrete first samples. The continuous interpolation function for the digital signal is shown as the dashed line 600 in the upper part of Fig. Figure 6 shows that to calculate the output sample values ​​of the shifted signal, the interpolation function 600 can be evaluated at the second sampling times tf, ..., tis'.

[0055] The one in the upper part of Fig. The sample rate conversion process shown in Figure 6 can be an example of a process for converting a digital signal where the shift time is zero. The second sampling times ti', ..., tis' can be considered nominal sampling times corresponding to the second sampling rate.

[0056] In the lower part of Fig. The sample rate conversion process shown in Figure 6 depicts a similar situation. However, the shift time is not zero.

[0057] Again, a digital input signal is represented by a series of discrete first samples (solid line with a filled circle on top) at the first sampling times ti, ..., ts. The first sampling times ti, ..., ts are separated by the equidistant first time interval Atl, which corresponds to the first sampling rate. A continuous interpolation function can be determined from the discrete first samples. The continuous interpolation function for the digital signal is shown as the dashed line 610 in the lower part of Fig. 6 shown.

[0058] A shifted output signal is represented by a series of discrete third samples (solid line with an empty circle on top) at the third sampling times (tf-At), (ti5'-At), where At represents the shift time. The third sampling times are separated by the equidistant second time interval At2, which corresponds to the second sampling rate. To calculate the output samples of the shifted signal, the interpolation function 610 can be evaluated at the third sampling times (ti'-At), ..., (tis'-At).

[0059] For those in the upper part of Fig. The situation depicted in Figure 6 is a time interval between a sampling time of the digital signal and a sampling time of the shifted signal, e.g., titi'. For the information in the lower part of Fig. The situation depicted in Figure 6 is a time interval between a sampling time of the digital signal and a sampling time of the shifted signal, e.g., ti-(ti'-At). That is, a time interval between a sampling time of a sample of the digital signal and a sampling time of a sample of the shifted signal is adjusted based on the shift time At. In other words, the sampling times tf and (ti'-At) for the shifted signal, i.e., the compensated sampling times, are adjusted based on the shift time At.

[0060] For illustrative purposes only, a second interpolation function 620 is shown as a dashed line in the lower part of Fig. Figure 6 shows the second interpolation function 620. The second interpolation function represents the interpolated signal for a hypothetical digital signal that is delayed by a time difference At with respect to the input digital signal. That is, the hypothetical signal is input to the sample rate conversion process at a time moment that differs by the time difference At from the time moment at which the digital signal is provided to the sample rate conversion process. The second interpolation function 620 is evaluated for the second sample times ti', ..., tis' similarly to that in the upper part of Figure 6. Fig. The situation depicted in Figure 6, i.e., a hypothetical output signal is represented by a series of discrete second samples (dashed line with an empty circle on top) at second sampling times ti', ..., tis'. This is similar to the situation in the upper part of Figure 6. Fig. 6. The output sample values ​​at the second sampling times can be an example of a process for shifting a digital signal, where the shift time is zero.

[0061] As seen from the lower part of Fig. As can be seen in Figure 6, the absolute value of the output samples calculated at sampling times (tl'-At), ..., (tl5'-At) for the digital signal is the same as that of the output samples calculated at sampling times tl', ..., tl5' for the hypothetical signal. This is because the digital signal and the hypothetical signal are identical except for the time difference At. Accordingly, calculating output samples at sampling times (tl'-At), ..., (tl5'-At) is equivalent to delaying the signal by a time interval At to provide a delayed signal to the sample rate conversion process, which is sampled at nominal sampling times tl', ..., 115', corresponding to the second sampling rate.

[0062] It is obviously from Fig. 6. Sample rate conversion processes for a digital signal, according to one or more aspects of the proposed concept or one or more examples described above or below, can be used to adjust a temporal relationship between two digital signals. For example, one signal can be delayed relative to the other by adjusting the shift time for one or both sample rate conversion processes.

[0063] The in Fig. The six time-history diagrams shown can provide examples of temporal relationships between input samples of the digital signal and output samples of the shifted signal for the in Fig. 1 device 100 or the one shown in Fig. 5. Device shown: 500.

[0064] An example of an implementation using sample rate conversion processes for a digital signal according to one or more aspects of the proposed concept or one or more of the examples described above is shown in Fig. 7 shown.

[0065] Fig. Figure 7 represents an example of a transmitter 700 comprising a device 100 for shifting a digital signal with a first sampling rate by a shift time to provide a shifted signal with a second sampling rate according to an example described herein and / or a device 500 for shifting a digital signal by a shift time to provide a shifted signal according to an example described herein.

[0066] The transmitter 700 is depicted as a digital, polar, wireless transmitter with envelope tracking. The transmitter 700 includes a 1 / Q digital signal processor (DSP) 701 for filtering operations on data samples or symbols of an input signal. The data samples or symbols are represented in a Cartesian representation, i.e., by their respective in-phase (I) and quadrature (Q) components. Furthermore, the transmitter 700 includes a polar coordinate provisioning unit 702, e.g., a processing unit configured to execute a CORDIC (Coordinate Rotation Digital Computer) algorithm to convert the I / Q representation of the input signal into a polar representation with a radius R and a phase (p). A separate processing path is provided for each of the radius component, the phase component, and an envelope component.Accordingly, a power amplifier (PA; PA =.) can be used. The power amplifier (704) can be operated in an energy-efficient manner based on envelope tracking. In a polar representation, the envelope component corresponds to the radius component. A first processing path 741 is provided for the radius component, a second processing path 742 is provided for the phase component, and a third processing path 743 is provided for the envelope component. Within these processing paths, the respective DSPs 711, 712, and 713 can be provided to process the specific signal component.

[0067] As indicated by the dashed line 799, the transmitter 700 is divided into a first frequency clock range, which may be a set of DSP clock ranges, and a second frequency clock range, which may be an RF clock range determined by an RF clock frequency. The DSP clock ranges are typically not synchronized with the RF clock frequency. Therefore, an interface between the first frequency clock range and the second frequency clock range is required. The interface is provided by a digital modulator 750. The digital modulator 750 comprises at least a first device 100-1 for shifting a digital signal and a second device 100-2 for shifting a digital signal according to an example described herein. Optionally, the digital modulator 750 may include a third device 100-1 for shifting a digital signal according to an example described herein.Alternatively, devices 500-1, 500-2, 500-3 for shifting a digital signal according to an example described herein may be provided instead of devices 100-1, 100-2, 100-3. In some examples, a device 100 may be provided for one of the signal paths 741, 742, 743, and a device 500 may be provided for another of the signal paths 741, 742, 743. For the sake of simplicity, the following description refers only to devices 100-1, 100-2, 100-3.

[0068] Devices 100-1, 100-2, 100-3 convert the fixed, constant sampling rate in the DSP clock range for each of the processing paths for the radius component, the phase component and the envelope component into the sampling rate of the RF clock range, which can be variable.

[0069] The propagation times for the specific components within their respective processing paths 741, 742, 743 can differ, meaning that the components may arrive at their respective devices 100-1, 100-2, 100-3 at different times. These differing propagation times across the processing paths 741, 742, 743 can be compensated for by accurately adjusting the respective offset times of the devices 100-1, 100-2, 100-3. Thus, the devices 100-1, 100-2, 100-3 can provide offset signals at the sampling rate of the second frequency clock range at the same time. In other words, the devices 100-1, 100-2, 100-3 can align the offset signals in time.

[0070] The phase component provides the information for the phase of the time-varying phase of the resulting radio frequency (RF) signal. After sample rate conversion (and optional time shifting) in the device 100-2, the phase information provided in the phase component is converted into a clock signal for the other parts of the transmitter 700 by a phase-to-digital-to-analog converter (DAC) 792. The phase DAC 732 can be implemented, for example, by a digitally controlled oscillator (DCO), a phase mixer, or a digital-to-time converter (DTC). Furthermore, the phase DAC 732 can be part of a phase-locked loop (PLL) 705, which compensates for a time-varying phase. To compensate for the time-varying phase, accurate temporal alignment between the output signal of the phase DAC 732 and a reference signal in the PLL 705 is essential.The temporal alignment between these signals can be provided by the device 100-2 by providing the shifted signal with a defined shift time compared to the digital input signal.

[0071] The radius information provided in the output signal of device 100-1 is fed into a radius DAC 731, which is clocked by the output signal of phase DAC 732. Therefore, at a time instant determined by the clock signal derived from the phase component, a signal with an amplitude determined by the radius information is provided by the radius DAC 731. Thus, the RF signal is provided by the radius DAC 731. The output of the radius DAC 731 is provided to the PA 704 for amplification and routing to an antenna element.

[0072] To ensure good performance of the Transmitter 700 and excellent signal characteristics, the radius signal and the phase signal must be precisely aligned in time. For carrier-aggregated LTE signals, an accuracy in the range of 10 is required. -12 A time interval of 1 second (1 ps) is required. The temporal alignment of these signals can be achieved by accurately adjusting the respective offset time of devices 100-1 and 100-2.

[0073] Amplifier efficiency is generally defined as the level of RF power achieved at the output signal compared to the power input into the overall amplification process. To improve amplifier efficiency, envelope tracking of the input signal to the amplifier can be used to vary the amplifier operation based on the detected envelope. Envelope tracking employs a variable power supply to power the PA 704. The absolute value of the input (baseband) signal is monitored, and the supply voltage to the PA 704 is varied based on this monitored absolute value. More precisely, the supply voltage to the PA 704 is varied to be just sufficient to reproduce the power level required by the PA 704 at a given instant.Therefore, at low input power levels, corresponding to a low absolute value of the input (baseband) signal, a low supply voltage is provided to the PA 704, and a maximum supply voltage is only provided when maximum power is required, i.e., at absolute value peaks of the input (baseband) signal. The sampling rate of the envelope (absolute value) component of the input signal, which is the radius component in the polar representation, is converted by the device 100-3 into the sampling rate of the RF clock range. The output signal of the device 100-3 is fed into the envelope DAC 733, which provides its output to the DC-DC converter (DC-DC) 703. The output of the envelope DAC 733 can vary according to the absolute value of the envelope component, i.e., according to the required power level. Accordingly, the supply voltage provided by the DC-DC converter to the PA 704 varies.Thus, the PA 704 is supplied with sufficient power to reproduce the power level of the signal to be sent to the antenna element with the required output power. To ensure correct operation of the PA 704, it is necessary that the supply voltage signal for the PA 704 is closely time-aligned with the output radius signal of the radius DAC 731, to which the PA 704 is supplied for amplification. This time alignment can be achieved, for example, by accurately adjusting the offset time of the device 100-3.

[0074] Referring to the in Fig. The situation shown in section 6 can result in a runtime difference At between the phase component (in the lower part of Fig. 6 shown) and the radius component (in the upper part of Fig. (Figure 6) of transmitter 700 are compensated by devices 100-1 and 100-2. Since the timing alignment of the various signals in transmitter 700 can be achieved by devices 100-1, 100-2, and 100-3, additional delay elements, such as digital filters in DSPs 711, 712, and 713, can be omitted in transmitter 700. Therefore, power consumption and the required area on a semiconductor substrate for transmitter 700 can be reduced.

[0075] Fig. Figure 8 schematically represents an example of a mobile communication device or mobile phone or user device 800, which includes a device 100 for shifting a digital signal with a first sampling rate by a shift time to provide a shifted signal with a second sampling rate according to a method described herein

[0076] Example and / or a device 500 for shifting a digital signal by a shift time to provide a shifted signal according to an example described herein.

[0077] Device 100 and / or device 500 may be contained within transmitter 700. In some examples, device 100 and / or device 500 may be contained within a digital modulator 750 according to an example described herein. In some examples, the digital modulator 750 may be contained within transmitter 700. An antenna element 810 of the mobile communication device 800 may be coupled to transmitter 700 to radiate a signal into the environment and to transmit the signal wirelessly. For this purpose, mobile communication devices may be provided which have reduced power consumption caused by delay elements used therein.

[0078] An example of a method for shifting a digital signal with a first sampling rate by a shift time to provide a shifted signal with a second sampling rate is shown by means of a flowchart in Fig. Figure 9 illustrates the method. The method comprises providing a measured value of an interpolated signal at a compensated sampling time as a sample of the shifted signal, wherein the interpolated signal depends on the digital signal. Furthermore, the method comprises modifying a time interval between a sampling time of the digital signal and the compensated sampling time based on the shift time.

[0079] Further details and aspects of the procedure are available in connection with the proposed concept or one or more preceding or following sections (e.g. Fig. The examples described in sections 1-8 are mentioned. The procedure may include one or more additional optional features that correspond to one or more aspects of the proposed concept or to one or more of the examples described above or below.

[0080] An example of a procedure for shifting a digital signal by a shift time to provide a shifted signal is shown using a flowchart in Fig. Figure 10 illustrates the method. The procedure comprises converting the digital signal with a first sampling rate into the shifted signal with a second sampling rate. Furthermore, the procedure comprises adjusting a time interval between a sampling time of a sample of the digital signal and a sampling time of a sample of the shifted signal based on the shift time.

[0081] Further details and aspects of the procedure are available in connection with the proposed concept or one or more preceding or following sections (e.g. Fig. The examples described in sections 1-8 are mentioned. The procedure may include one or more additional optional features that correspond to one or more aspects of the proposed concept or to one or more of the examples described above or below.

[0082] The examples described herein can be summarized as follows: Example 1 is a device for shifting a digital signal with a sampling rate by a shift time to provide a shifted signal with a second sampling rate, comprising a sampling rate converter configured to provide a value of an interpolated signal at a compensated sampling time as a sample of the shifted signal, wherein the interpolated signal is based on the digital signal, and wherein the sampling rate converter is configured to modify a time interval between a sampling time of the digital signal and the compensated sampling time based on the shift time. In Example 2, the sampling rate converter of the device of Example 1 is configured to reduce or increase the time interval by the displacement time with respect to a time interval between the sampling time of the digital signal and a compensated sampling time for a displacement time of zero. In Example 3, the sampling rate converter of the device of Example 1 or Example 2 is configured to provide the compensated sampling time by adding or subtracting the shift time from a nominal sampling time corresponding to the second sampling rate. In Example 4, the sampling rate converter of the device of Example 1 or Example 2 comprises at least one integrator to provide the compensated sampling time, and wherein the sampling rate converter is configured to provide the compensated sampling time by modifying a start value for the integrator by a value related to the displacement time. In Example 5, the sampling rate converter of the device of Example 1 or Example 2 comprises a first-in-first-out memory and a controller configured to control a fill level of the first-in-first-out memory. In Example 6, the control system of the device of Example 5 comprises a level detector configured to detect a current level of the first-in-first-out memory; a first processing unit configured to adjust a target level value for the first-in-first-out memory; a comparator configured to compare the current level of the first-in-first-out memory with the target level value; and a second processing unit configured to control the compensated sampling time based on a comparison result of the comparator. In Example 7, the sampling rate converter of the device is a fractional sampling rate converter from one of the preceding examples. Example 8 is a device for shifting a digital signal by a shift time to provide a shifted signal, comprising a sample rate converter configured to convert the digital signal with a first sample rate into the shifted signal with a second sample rate, wherein the sample rate converter is configured to adjust a time interval between a sample time of a sample of the digital signal and a sample time of a sample of the shifted signal based on the shift time. In Example 9, the sampling rate converter of the device of Example 8 is configured to receive the digital signal at a first input, to receive a first control signal, which includes information about the shift time, at a second input, and to receive a second control signal, which includes information about a ratio of the first sampling rate to the second sampling rate, at a third input. In Example 10, the sampling rate converter of the device from Example 9 includes an output configured to provide the shifted signal. In Example 11, the sampling time of the sampled value of the shifted signal is provided in the apparatus of one of Examples 8 to 10 by adding or subtracting the shift time from a nominal sampling time corresponding to the second sampling rate. In Example 12, the sampling rate converter of the device of one of Examples 8 to 10 comprises at least one integrator to provide the sampling time of the sampled value of the shifted signal, and the sampling time of the sampled value of the shifted signal is provided by modifying a start value for the integrator by a value related to the shift time. In Example 13, the sampling rate converter of the device from one of Examples 8 to 10 comprises a first-in-first-out memory and a controller configured to control a fill level of the first-in-first-out memory. In Example 14, the control system of the device of Example 13 comprises a level detector configured to detect a current level of the first-in-first-out memory; a first processing unit configured to adjust a target level value for the first-in-first-out memory; a comparator configured to compare the current level of the first-in-first-out memory with the target level value; and a second processing unit configured to control the sampling time of the sampled value of the shifted signal based on a comparison result of the comparator. In Example 15, the sampling rate converter of the device is from one of Examples 8 to 14 a fractional sampling rate converter. Example 16 is a digital modulator for generating a radio frequency signal using a first digital signal and a second digital signal, comprising a first device for shifting a digital signal according to any one of Examples 1 to 7 to convert a sampling rate of the first digital signal from a first sampling rate to a second sampling rate; and a second device for shifting a digital signal according to any one of Examples 1 to 7 to convert a sampling rate of the second digital signal from the first sampling rate to the second sampling rate, wherein the time interval between the sampling time of the first digital signal and the compensated sampling time for the first device differs by an offset from the time interval between the sampling time of the second digital signal and the compensated sampling time for the second device. In Example 17, the offset is chosen such that the shifted signal relative to the first digital signal and the shifted signal relative to the second digital signal are temporally aligned in the digital modulator of Example 16. Example 18 is a digital modulator for generating a radio frequency signal using a first digital signal and a second digital signal, comprising a first device for shifting a digital signal according to any one of Examples 8 to 15 to convert a sampling rate of the first digital signal from a first sampling rate to a second sampling rate;and a second device for shifting a digital signal according to any one of Examples 8 to 15 for converting a sampling rate of the second digital signal from the first sampling rate to the second sampling rate, wherein the time interval between the sampling time of the sample value of the first digital signal and the sampling time of the sample value of the shifted signal for the first device differs by an offset from the time interval between the sampling time of the sample value of the second digital signal and the sampling time of the sample value of the shifted signal for the second device. In Example 19, the offset is chosen such that the shifted signal relative to the first digital signal and the shifted signal relative to the second digital signal are temporally aligned in the digital modulator of Example 18. Example 20 is a transmitter comprising a device for shifting a digital signal according to any one of Examples 1 to 7, a device for shifting a digital signal according to any one of Examples 8 to 15, or a digital modulator according to any one of Examples 16 to 19. Example 21 is a mobile communication device that includes a transmitter according to Example 20. In Example 22, the mobile communication device from Example 21 further includes at least one antenna element that is coupled to the transmitter. Example 23 is a means of shifting a digital signal with a first sampling rate by a shift time to provide a shifted signal with a second sampling rate, comprising a means of providing a value of an interpolated signal at a compensated sampling time as a sample of the shifted signal, wherein the interpolated signal depends on the digital signal, wherein a time interval between a sampling time of the digital signal and the compensated sampling time is modified based on the shift time. In Example 24, the time interval by the displacement time is reduced or increased with respect to a time interval between the sampling time of the digital signal and a compensated sampling time for a displacement time of zero in the mean of Example 23. Example 25 is a means for shifting a digital signal by a shift time to provide a shifted signal, comprising a means for converting the digital signal with a first sampling rate into the shifted signal with a second sampling rate, wherein the means for conversion is configured to fit a time interval between a sampling time of a sample of the digital signal and a sampling time of a sample of the shifted signal based on the shift time. In Example 26, the means for converting the digital signal of the means from Example 25 is configured to transmit the digital signal to a first means for receiving a

[0083] to receive signals in order to receive a first control signal, which includes information about the displacement time, at a second means of receiving a signal and to receive a second control signal, which includes information about a ratio of the first sampling rate to the second sampling rate, at a third means of receiving a signal.

[0084] In Example 27, the means for converting the digital signal of the means from Example 26 includes a means for providing the shifted signal.

[0085] Example 28 is a method for shifting a digital signal with a first sampling rate by a shift time to provide a shifted signal with a second sampling rate, comprising providing a value of an interpolated signal at a compensated sampling time as a sample of the shifted signal, wherein the interpolated signal depends on the digital signal; and modifying a time interval between a sampling time of the digital signal and the compensated sampling time based on the shift time.

[0086] In Example 29, modifying the time interval in the procedure of Example 28 involves reducing or increasing the time interval by the shift time with respect to a time interval between the sampling time of the digital signal and a compensated sampling time for a shift time of zero.

[0087] In Example 30, the compensated sampling time is provided by adding or subtracting the shift time from a nominal sampling time corresponding to the second sampling rate in the procedure of Example 28 or 29.

[0088] In Example 31, the compensated sampling time is provided by integration, and the compensated sampling time is provided by modifying a starting value for integration by a value related to the shift time in the procedure of Example 28 or 29.

[0089] Example 32 is a method for shifting a digital signal by a shift time to provide a shifted signal, comprising converting the digital signal at a first sampling rate into the shifted signal at a second sampling rate; and adjusting a time interval between a sampling time of a sample of the digital signal and a sampling time of a sample of the shifted signal based on the shift time.

[0090] In Example 33, the procedure of Example 32 further comprises receiving the digital signal; receiving a first control signal containing information about the shift time; and receiving a second control signal containing information about a ratio of the first sampling rate to the second sampling rate.

[0091] In Example 34, the procedure of Example 33 further includes providing the shifted signal.

[0092] Example 35 is a computer-readable storage medium on which a program containing program code for carrying out the procedure of any of Examples 28 to 34 is stored when the program is executed on a computer or processor.

[0093] Example 36 is a computer program with program code trained to perform the procedure of any one of Examples 28 to 34 when the computer program is run on a computer or processor.

[0094] Examples may further include a computer program with program code for performing one of the above procedures when the computer program is executed on a computer or processor. A person skilled in the art would readily recognize that steps of various procedures described above can be performed by programmed computers. Here, some examples are intended to include program storage devices, such as digital data storage media, that are machine- or computer-readable and encode machine-executable or computer-executable programs of instructions, the instructions performing some or all of the steps of the procedures described above. The program storage devices may be, for example, digital storage devices, magnetic storage media such as magnetic disks and magnetic tapes, hard disk drives, or optically readable digital data storage media.Further examples should also cover computers programmed to perform the steps of the procedures described above, or (field) programmable logic arrays ((F)PLA = (Field) Programmable Logic Arrays) or (field) programmable gate arrays ((F)PGA = (Field) Programmable Gate Arrays) programmed to perform the steps of the procedures described above.

[0095] Functional blocks designated as "means for..." (performing a certain function) are to be understood as comprehensive circuits, each designed to perform a specific function. Therefore, a "means for something" can also be understood as "means designed for or suitable for something." A means designed to perform a certain function does not necessarily mean that such a means will actually perform the function (at any given time).

[0096] The functions of various elements depicted in the figures, including each functional block designated as "means," "means for providing a sensor signal," "means for generating a transmit signal," etc., can be provided by dedicated hardware such as "a signal provider," "a signal processing unit," "a processor," "a controller," etc., as well as by hardware capable of executing software in conjunction with associated software. Furthermore, each instance described herein as "means" could be implemented as or correspond to "one or more modules," "one or more devices," "one or more units," etc. When provided by a processor, the functions can be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared.Furthermore, the explicit use of the terms "processor" or "controller" should not be interpreted as referring exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (DSP) hardware, network processors, application-specific integrated circuits (AS1Cs), field-programmable gate arrays (FPGAs), read-only memory (ROMs) for storing software, random-access memory (RAMs), and non-volatile storage devices. Other hardware, both conventional and / or custom-designed, may also be included.

[0097] The person skilled in the art should understand that all block diagrams herein represent conceptual views of exemplary circuits embodying the principles of the disclosure. Similarly, it is understood that all flowcharts, process diagrams, state transition diagrams, pseudocode, and the like represent various processes that are essentially represented in a computer-readable medium and can thus be executed by a computer or processor, irrespective of whether such a computer or processor is explicitly depicted.

[0098] It should also be noted that methods disclosed in the description or in the claims may be implemented by a device with means for carrying out each of the respective steps of these methods.

Claims

[1] A device (100) for shifting a digital signal (111) with a first sampling rate by a shift time to provide a shifted signal (112) with a second sampling rate, comprising: a sample rate converter (110) configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal (112), wherein the interpolated signal is based on the digital signal (111), and wherein the value of the interpolated signal is a time-shifted version of the digital signal at the second sample rate; wherein the sample rate converter is configured to modify a time interval between a sample time of the digital signal (111) and the compensated sample time based on the shift time, wherein the compensated sample time is determined based on a nominal sample time corresponding to the second sample rate and the shift time. [2] The device according to claim 1, wherein the sampling rate converter (110) is configured to reduce or increase the time interval by the displacement time with respect to a time interval between the sampling time of the digital signal (111) and a compensated sampling time for a displacement time of zero. [3] The device according to claim 1 or claim 2, wherein the sampling rate converter (110) is configured to provide the compensated sampling time by adding or subtracting the shift time from a nominal sampling time corresponding to the second sampling rate. [4] The device according to claim 1 or 2, wherein the sampling rate converter (110) comprises at least one integrator (322) to provide the compensated sampling time, and wherein the sampling rate converter (110) is configured to provide the compensated sampling time by modifying a start value for the integrator (322) by a value related to the shift time. [5] The device according to claim 1 or claim 2, wherein the sampling rate converter (110) comprises a first-in-first-out memory (450) and a controller configured to control a fill level of the first-in-first-out memory (450). [6] The device according to claim 5, wherein the control comprises: a level detector (460) configured to detect a current level of the first-in-first-out storage (450); a first processing unit (480) configured to adjust a target fill level value for the first-in-first-out storage (450); a comparator (470) configured to compare the current fill level of the first-in-first-out reservoir (450) with the target fill level; and a second processing unit (430) which is configured to control the compensated sampling time based on a comparison result of the comparator (470). [7] The device according to one of the preceding claims, wherein the sampling rate converter (110) is a fractional sampling rate converter. [8] A device (500) for shifting a digital signal (511) by a shift time to provide a shifted signal (514), comprising: a sample rate converter (510) configured to convert the digital signal (511) with a first sample rate into the shifted signal (514) with a second sample rate, wherein the sampling rate converter (510) is configured to adapt a time interval between a sampling time of a sample of the digital signal (511) and a sampling time of a sample of the shifted signal (514) based on the shift time, and wherein the sampling time of the sample of the shifted signal (514) is determined based on a nominal sampling time corresponding to the second sampling rate and the shift time. [9] The device according to claim 8, wherein the sampling rate converter (510) is configured to receive the digital signal at a first input (520), to receive a first control signal (512) comprising information about the shift time at a second input (530), and to receive a second control signal (513) comprising information about a ratio of the first sampling rate to the second sampling rate at a third input (540). [10] The device according to claim 9, wherein the sampling rate converter (510) comprises an output (550) configured to provide the shifted signal (514). [11] The device according to one of claims 8 to 10, wherein the sampling time of the sampled value of the shifted signal (514) is provided by adding or subtracting the shift time from a nominal sampling time corresponding to the second sampling rate. [12] A digital modulator (750) for generating a radio frequency signal using a first digital signal and a second digital signal, comprising: a first device (100) for shifting a digital signal according to one of claims 1 to 7 for converting a sampling rate of the first digital signal from a first sampling rate to a second sampling rate; and a second device (100) for shifting a digital signal according to one of claims 1 to 7 for converting a sampling rate of the second digital signal from the first sampling rate to the second sampling rate, wherein the time interval between the sampling time of the first digital signal and the compensated sampling time for the first device differs by an offset from the time interval between the sampling time of the second digital signal and the compensated sampling time for the second device. [13] The digital modulator according to claim 12, wherein the offset is selected such that the shifted signal is time-aligned with respect to the first digital signal and the shifted signal is time-aligned with respect to the second digital signal. [14] A digital modulator (750) for generating a radio frequency signal using a first digital signal and a second digital signal, comprising: a first device (500) for shifting a digital signal according to one of claims 8 to 11 for converting a sampling rate of the first digital signal from a first sampling rate to a second sampling rate; and a second device (500) for shifting a digital signal according to any one of claims 8 to 11 for converting a sampling rate of the second digital signal from the first sampling rate to the second sampling rate; and wherein the time interval between the sampling time of the sampled value of the first digital signal and the sampling time of the sampled value of the shifted signal for the first device differs by an offset from the time interval between the sampling time of the sampled value of the second digital signal and the sampling time of the sampled value of the shifted signal for the second device. [15] The digital modulator according to claim 14, wherein the offset is selected such that the shifted signal is time-aligned with respect to the first digital signal and the shifted signal is time-aligned with respect to the second digital signal. [16] A transmitter (700) comprising a device (100) for shifting a digital signal according to any one of claims 1 to 7, a device (500) for shifting a digital signal according to any one of claims 8 to 11 or a digital modulator (750) according to any one of claims 12 to 15. [17] A mobile communication device (800) comprising a transmitter (700) according to claim 16. [18] A method for shifting a digital signal with a first sampling rate by a shift time to provide a shifted signal with a second sampling rate, comprising: Providing (900) a value of an interpolated signal at a compensated sampling time as a sample of the shifted signal, wherein the interpolated signal depends on the digital signal, and wherein the value of the interpolated signal is a time-shifted version of the digital signal at the second sampling rate; and Modifying (902) a time interval between a sampling time of the digital signal and the compensated sampling time based on the shift time, wherein the compensated sampling time is determined based on a nominal sampling time corresponding to the second sampling rate and the shift time. [19] The method according to claim 18, wherein modifying the time interval comprises: Decreasing or increasing the time interval by a shift time with respect to a time interval between the sampling time of the digital signal and a compensated sampling time for a shift time of zero. [20] The method according to claim 18 or claim 19, wherein the compensated sampling time is provided by adding or subtracting the shift time from a nominal sampling time corresponding to the second sampling rate. [21] The method according to claim 18 or claim 19, wherein the compensated sampling time is provided by integration, and wherein the compensated sampling time is provided by modifying a starting value for integration by a value related to the displacement time. [22] A method for shifting a digital signal by a shift time to provide a shifted signal, comprising: Converting (1000) the digital signal with a first sampling rate into the shifted signal with a second sampling rate; and Adjusting (1002) a time interval between a sampling time of a sample of the digital signal and a sampling time of a sample of the shifted signal based on the shift time, and wherein the sampling time of the sample of the shifted signal (514) is determined based on a nominal sampling time corresponding to the second sampling rate and the shift time. [23] The method according to claim 22, comprising: Receiving the digital signal; Receiving an initial control signal that includes information about the displacement time; and Receiving a second control signal that includes information about the ratio of the first sampling rate to the second sampling rate. [24] The method according to claim 23, further comprising: Providing the shifted signal. [25] A computer-readable storage medium on which a program containing program code for carrying out the method according to any one of claims 18 to 24 is stored when the program is executed on a computer or processor.

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