Three-dimensional semiconductor device

Abstract

Three-dimensional, 3D, semiconductor device comprising: a stack structure (ST1, ST2) extending in a first direction and having electrodes (EL) stacked vertically on a substrate (10); a channel structure (CHS) coupled to the electrodes (EL) to form a plurality of memory cells arranged three-dimensionally on the substrate (10), the channel structure (CHS) comprising: first vertical channels (VS1) and second vertical channels (VS2) penetrating the stack structure (ST1, ST2); and a first horizontal channel (HS1) which is below the stack structure (ST1, ST2) and which laterally connects the first vertical channels (VS1) and the second vertical channels (VS2), the first horizontal channel (HS1) having an upper horizontal section (HP1), a lower horizontal section (HP2) and wall sections (VP), one of the wall sections (VP) being connected between one end of the upper horizontal section (HP1) and one end of the lower horizontal section (HP2), and the other of the wall sections (VP) being connected between another end of the upper horizontal section (HP1) and another end of the lower horizontal section (HP2); a second horizontal channel (HS2) connected to a sidewall of the first horizontal channel (HS1) of the channel structure and a top surface of the substrate (10), the second horizontal channel (HS2) having a first conductivity type; conductive plugs located at upper ends of the second vertical channels (VS2), the conductive plugs having a second conductivity type; a conductive line extending in a first direction on the stack structure (ST1, ST2) and connected to the second vertical channels (VS2), the first direction being parallel to a top surface of the substrate; and a bit line (BL1, BL2) extending in a second direction perpendicular to the first direction on the conductive line, the bit line (BL1, BL2) being connected to the vertical channels (VS1, VS2), the second direction being parallel to a top surface of the substrate.

Description

BACKGROUND

[0001] The inventive concepts relate to three-dimensional (3D) semiconductor devices and, more particularly, to 3D semiconductor devices capable of improving reliability and integration density.

[0002] Semiconductor devices have been highly integrated to provide high performance and low cost. The integration density of semiconductor devices can affect the cost of semiconductor devices, leading to a demand for a highly integrated semiconductor device. An integration density of a conventional two-dimensional (2D) or planar semiconductor device can be mainly determined by an area occupied by a unit memory cell. Thus, the integration density of conventional 2D semiconductor devices can be greatly influenced by a technique for forming fine patterns. However, since extremely high-cost devices are required to form fine patterns, the integration density of 2D semiconductor devices is continuously increasing but remains limited.Therefore, three-dimensional (3D) semiconductor devices, which have three-dimensionally arranged memory cells, have been developed.

[0003] US 9 099 348 B2 discloses: A semiconductor device including vertical channel layers; a tube channel layer configured to connect the lower ends of the vertical channel layers; and a tube gate surrounding the tube channel layer and including a first region in contact with the tube channel layer and containing a first type impurity, and remaining second regions containing a second type impurity different from the first type impurity.

[0004] US 9 012 974 B2 discloses: A vertical memory device includes a channel, a basic select line (GSL), word lines, a string select line (SSL), and a contact. The channel includes a vertical portion and a horizontal portion. The vertical portion extends in a first direction substantially perpendicular to a top surface of a substrate, and the horizontal portion is connected to the vertical portion and parallel to the top surface of the substrate. The GSL, the word lines, and the SSL are formed on a sidewall of the vertical portion of the channel sequentially in the first direction and are spaced apart from each other. The contact is located on the substrate and is electrically connected to the horizontal portion of the channel.

[0005] US 8 654 587 B2 relates to non-volatile memory devices, channel enhancement methods therefor, programming methods therefor and memory systems incorporating them.

[0006] US 8 829 598 B2 discloses: A method of manufacturing a non-volatile memory device, the method comprising alternately stacking interlayer dielectrics and sacrificial layers over a substrate, etching the interlayer dielectrics and sacrificial layers to form trenches to expose a surface of the substrate, etching the interlayer dielectrics exposed by the trenches to a predetermined thickness, forming interconnect layers over etched portions of the interlayer dielectrics, and burying a layer for a channel within the trenches in which the interconnect layers have been formed to form a channel.

[0007] US 2015 / 0 115 348 A1 discloses: A vertical-type non-volatile memory device includes a first vertical channel structure and first and second stacked structures. The first vertical channel structure extends vertically on a substrate. The first stacked structure includes gate electrodes and first insulating interlayers. The gate layers and the first insulating interlayers are alternately and vertically stacked one above the other. The first stacked structure is arranged on a first sidewall of the first vertical channel structure. The second stacked structure includes first sacrificial layers and second insulating interlayers. The first sacrificial layers and the second insulating interlayers are alternately and vertically stacked one above the other. The second stacked structure is arranged on a second sidewall of the first vertical channel structure. The first sacrificial layer is formed from a polysilicon layer. SUMMARY

[0008] The invention is defined in the appended claims. Embodiments of the inventive concepts can provide three-dimensional (3D) semiconductor devices capable of improving reliability and integration density.

[0009] Embodiments of the inventive concepts are set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The inventive concepts will become clearer in view of the attached drawings and the accompanying detailed description. Fig. 1 is a schematic block diagram illustrating a three-dimensional (3D) semiconductor device according to some embodiments of the inventive concepts. Fig. 2 is a circuit diagram illustrating a cell arrangement of a 3D semiconductor device according to some embodiments of the inventive concepts. Fig. 3 is a top view illustrating a 3D semiconductor device according to some embodiments of the inventive concepts. Fig. 4A is a top view illustrating a cell arrangement region of a 3D semiconductor device according to some embodiments of the inventive concepts. Fig. 4B is a top view illustrating a channel structure of a 3D semiconductor device according to some embodiments of the inventive concepts. Fig. 5 and Fig. 6 are cross-sectional views along line II' and II-II' in Fig. 4A to illustrate a 3D semiconductor device according to some embodiments of the inventive concepts. Fig. 7A to 7E are enlarged views of a section “A” of the Fig. 5. Fig. 8A and Fig. 8B are views illustrating methods of operating a 3D semiconductor device according to some embodiments of the inventive concepts. Fig. 9 is a cross-sectional view illustrating a 3D semiconductor device according to some embodiments of the inventive concepts. Fig. 10 is an enlarged view of a section “A” of the Fig. 9. Fig. 11, Fig. 12, Fig. 13 and Fig. 14 are cross-sectional views illustrating 3D semiconductor devices according to some embodiments of the inventive concepts. Fig. 15 is a plan view illustrating a 3D semiconductor device according to some embodiments of the inventive concepts. Fig. 16 is a cross-sectional view taken along a line II' in Fig. 15 to illustrate a 3D semiconductor device according to some embodiments of the inventive concepts. Fig. 17 is a schematic block diagram illustrating a 3D semiconductor device according to some embodiments of the inventive concepts. Fig. 18 is a cross-sectional view illustrating a 3D semiconductor device according to some embodiments of the inventive concepts. Fig. 19 to 29 are cross-sectional views along line II' in Fig. 4A to illustrate methods of manufacturing a 3D semiconductor device according to some embodiments of the inventive concepts. Fig. 30 to 35 are enlarged views of sections “A” of the Fig. 21 to 26 to illustrate manufacturing methods for a 3D semiconductor device according to some embodiments of the inventive concepts. Fig. 36 to 40 are cross-sectional views illustrating methods of forming a conductive pad and a source plug of a 3D semiconductor device according to some embodiments of the inventive concepts. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0011] Exemplary embodiments of aspects of the present inventive concepts explained and illustrated herein include or include their complementary counterparts. Throughout the description, like reference numerals or like reference signs refer to the same elements.

[0012] Fig. 1 is a schematic block diagram illustrating a three-dimensional (3D) semiconductor device according to some embodiments of the inventive concepts.

[0013] Referring to Fig. 1, a 3D semiconductor device may include a memory cell array 1, a row decoder 2, a page buffer 3, a column decoder 4, and a control circuit 5. The 3D semiconductor device may be a 3D semiconductor memory device.

[0014] The memory cell array 1 may include a plurality of memory blocks BLKO to BLKn. Each of the memory blocks BLKO to BLKn may include a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. The word lines and the bit lines may be electrically connected to the memory cells.

[0015] The row decoder 2 may decode an address signal supplied from an external system to select one of the word lines. The address signal decoded in the row decoder 2 may be provided to a row driver (not shown). The row driver may provide a selected word line voltage and non-selected word line voltages, generated by a voltage generation circuit (not shown), to the selected word line and non-selected word lines in response to a control signal of the control circuit. The row decoder 2 may be commonly connected to the plurality of memory blocks BLKO to BLKn and may provide drive signals for the word lines of a memory block selected by a block selection signal.

[0016] The page buffer 3 may be connected to the memory cell array 1 via the bit lines to sense data stored in the memory cells. The page buffer 3 may be connected to a bit line selected by an address signal decoded in the column decoder 4. According to an operation mode, the page buffer 3 may temporarily store data to be stored in the memory cells or may sense data stored in the memory cells. For example, the page buffer 3 may operate as a switch driver during a programming mode of operation and may operate as a sense amplifier during a sensing mode of operation. The page buffer 3 may receive power (e.g., a voltage or a current) from the control circuit 5 and may provide the received power to the selected bit line.

[0017] Column decoder 4 may provide a data transmission path between page buffer 3 and an external device (e.g., a memory controller). Column decoder 4 may decode an address signal input from the external device to select one of the bit lines. Column decoder 4 may be commonly connected to the plurality of memory blocks BLKO to BLKn and may provide data to the bit lines of the memory block selected by the block selection signal.

[0018] The control circuit 5 can control the overall operation of the 3D semiconductor device. The control circuit 5 can receive control signals and an external voltage and can operate in response to the received control signals. The control circuit 5 can include a voltage generator that generates voltages (e.g., a programming voltage, a scanning voltage, and an erasing voltage) necessary for internal operations using the external voltage. The control circuit 5 can control a scanning operation, a writing operation, and / or an erasing operation in response to the control signals.

[0019] Fig. 2 is a circuit diagram illustrating a cell arrangement of a 3D semiconductor device according to some embodiments of the inventive concepts.

[0020] Referring to Fig. 2, a cell arrangement of a 3D semiconductor device according to some embodiments of the inventive concepts may include a common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR connected between the common source line CSL and the bit lines BL.

[0021] The bit lines BL may be arranged two-dimensionally. A plurality of cell strings CSTR may be connected in parallel to each of the bit lines BL. The cell strings CSTR may be commonly connected to the common source line CSL. In other words, a plurality of cell strings CSTR may be arranged between a common source line CSL and the plurality of bit lines BL. In some embodiments, the common source line CSL may include a plurality of common source lines CSL arranged two-dimensionally. The same voltage may be applied to the plurality of common source lines CSL, or the common source lines CSL may be electrically controlled independently of one another.

[0022] Each of the cell strings CSTR may include a ground selection transistor GST connected to the common source line CSL, a string selection transistor SST connected to the bit line BL, and a plurality of memory cell transistors MCT interposed between the ground and string selection transistors GST and SST. The ground selection transistor GST, the memory cell transistors MCT, and the string selection transistor SST may be connected in series with each other in the order named.

[0023] The common source line CSL may be commonly connected to sources of the ground select transistors GST. A ground select line GSL, a plurality of word lines WL0 to WL3, and a string select line SSL arranged between the common source line CSL and the bit lines BL may be used as a gate electrode of the ground select transistor GST, gate electrodes of the memory cell transistors MCT, and a gate electrode of the string select transistor SST, respectively. Each of the memory cell transistors MCT may include a data storage element. In addition, channel regions of the transistors constituting the cell strings CSTR may be commonly electrically connected to a P-type well (P-well).

[0024] Fig. 3 is a top view illustrating a 3D semiconductor device according to some embodiments of the inventive concepts. Fig. 4A is a top view illustrating a cell arrangement region of a 3D semiconductor device according to some embodiments of the inventive concepts. Fig. 4B is a top view illustrating a channel structure of a 3D semiconductor device according to some embodiments of the inventive concepts. Fig. 5 and Fig. 6 are cross-sectional views along lines II' and II-II' in Fig. 4A to illustrate a 3D semiconductor device according to some embodiments of the inventive concepts. Fig. 7A to 7E are enlarged views of a section “A” of the Fig. 5.

[0025] Referring to the Fig. 3, Fig. 4A, Fig. 4B, Fig. 5 and Fig. 6, a substrate 10 may include a cell array region CAR, contact regions CTR, and dummy regions DMY. The contact regions CTR may be arranged on both sides of the cell array region CAR in a first direction D1. The dummy regions DMY may be arranged on both sides of the cell array region CAR in a second direction D2 perpendicular to the first direction D1. A plurality of first stack structures ST1 and a plurality of second stack structures ST2 may extend parallel to each other in the first direction D1 on the substrate and may be spaced from each other in the second direction D2. As shown in Fig. As illustrated in Figure 3, the first stack structures ST1 and the second stack structures ST2 may be arranged alternately along the second direction D2 when viewed from a top view. In some embodiments, the first and second directions D1 and D2 may be parallel to a top surface of the substrate 10.

[0026] In some embodiments, the substrate 10 may be formed from a semiconductor material and may include a well dopant layer 11 doped with dopants of a first conductivity type. For example, the substrate 10 may include at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or any combination thereof. For example, the substrate 10 may be a bulk silicon substrate, a silicon-on-insulator (SoI) substrate, a germanium substrate, a germanium-on-insulator (GoI) substrate, a silicon germanium substrate, and / or a substrate including an epitaxial layer obtained by performing a selective epitaxial growth (SEG) process.

[0027] In certain embodiments, substrate 10 may include an insulating material and may include a single layer or a plurality of thin layers. For example, substrate 10 may include at least one of a silicon oxide layer, a silicon nitride layer, or a low-k dielectric layer.

[0028] Each of the first and second stack structures ST1 and ST2 may include electrodes EL stacked vertically on the substrate 10 and insulating layers ILD disposed between the electrodes EL. In other words, the electrodes EL may be stacked along a third direction D3 perpendicular to the first and second directions D1 and D2. In some embodiments, the third direction D3 may be perpendicular to the top surface of the substrate 10. The electrodes EL of the first and second stack structures ST1 and ST2 may include a conductive material. For example, the electrodes EL may include at least one of a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), or a transition metal (e.g., titanium or tantalum).

[0029] In some embodiments, the top electrode of each of the first and second stack structures ST1 and ST2 may be divided into segments that are laterally spaced from each other. In other words, the top electrode of each of the first and second stack structures ST1 and ST2 may include a first strand selection electrode SEL1 and a second strand selection electrode SEL2 that extend in the first direction D1 and are spaced from each other in the second direction D2, and a separation insulation structure 115 may be disposed between the first and second strand selection electrodes SEL1 and SEL2.

[0030] In each of the first and second stack structures ST1 and ST2, the thicknesses of the insulating layers ILD can be varied according to characteristics of the 3D semiconductor device. In some embodiments, the thicknesses of the insulating layers ILD can be substantially equal to each other. In some embodiments, one or some of the insulating layers ILD can be thicker than another or others of the insulating layers ILD. In some embodiments, each of the insulating layers ILD can include at least one of a silicon oxide layer or a low-k dielectric layer. In some embodiments, the insulating layers ILD can include pores and / or air gaps.

[0031] In some embodiments, the 3D semiconductor device may be a vertical NAND flash memory device. In this case, some of the electrodes EL of each of the first and second stack structures ST1 and ST2 may be used as control gate electrodes of the memory cell transistors MCT of the Fig. 2 can be used.

[0032] In some embodiments, the electrodes EL of each of the first and second stack structures ST1 and ST2 may be coupled to a channel structure CHS to connect the memory cell transistors MCT of the Fig. 2, the string selection transistors SST of the Fig. 2 and the ground selection transistors GST of the Fig. 2. In each of the first and second stack structures ST1 and ST2, the first and second string selection electrodes SEL1 and SEL2 corresponding to the uppermost electrode may be used as the gate electrodes of the string selection transistors SST of the Fig. 2, controlling an electrical connection between a bit line BL and the channel structure CHS, the lowest electrode EL can be used as the gate electrodes of the ground selection transistors GST of the Fig. 2, controlling the electrical connection between the channel structure CHS and the common source line CSL. The electrodes EL between the top electrode and the bottom electrode can be used as the control gate electrodes of the memory cell transistors MCT of the Fig. 2 and the word lines connecting the control gate electrodes.

[0033] In some embodiments, a channel structure CHS may include first vertical channels VS1, second vertical channels VS2, dummy vertical channels DVS, and a first horizontal channel HS1. The first and second vertical channels VS1 and VS2 and the dummy vertical channels DVS may penetrate each of the first and second stack structures ST1 and ST2. The first horizontal channel HS1 may be arranged below each of the first and second stack structures ST1 and ST2 and may laterally or horizontally interconnect the first and second vertical channels VS1 and VS2 and the dummy vertical channels DVS.

[0034] The first vertical channels VS1 may be spaced apart from each other and may be arranged in the first direction D1 and the second direction D2. The second vertical channels VS2 may be spaced apart from each other and may be arranged in the first direction D1 and the second direction D2. At this time, each of the second vertical channels VS2 may be arranged at a position shifted from a corresponding one of the first vertical channels VS1 in a direction diagonal to the second direction D2. In other words, the first and second vertical channels VS1 and VS2, which are adjacent to each other, may be arranged in a zigzag shape along the first direction D1. The dummy vertical channels DVS of each of the first and second stack structures ST1 and ST2 may be arranged in the first direction D1 and may be arranged between the first and second strand selection electrodes SEL1 and SEL2.Each of the vertical dummy channels DVS may be disposed between the first vertical channels VS1 arranged in the second direction D2, and may be aligned with each of the second vertical channels VS2 adjacent thereto in a direction diagonal to the second direction D2. In some embodiments, each of the vertical channels VS1, VS2, and DVS may have a hollow tube or macaroni shape. In certain embodiments, each of the vertical channels VS1, VS2, and DVS may have a cylindrical shape.

[0035] In some embodiments, the first horizontal channel HS1 may extend from lower ends of the vertical channels VS1, VS2, and DVS to be disposed below each of the first and second stack structures ST1 and ST2. The first horizontal channel HS1 may extend along the first direction D1. In other words, the first horizontal channel HS1 may be commonly connected to the first and second vertical channels VS1 and VS2, which are arranged in the first and second directions D1 and D2, and the vertical dummy channels DVS, which are arranged in the first direction D1. In some embodiments, the first and second vertical channels VS1 and VS2, the vertical dummy channels DVS, and the first horizontal channel HS1 may form a single semiconductor layer that extends continuously without an interface.

[0036] In some embodiments, the first horizontal channel HS1 may have a hollow tube or macaroni shape, which is connected to the vertical channels VS1, VS2, and DVS. For example, the first and second vertical channels VS1 and VS2, the vertical dummy channels DVS, and the first horizontal channel HS1 may form a tube shape that is within one body.

[0037] As in Fig. As illustrated in Figure 4B, the first horizontal channel HS1 may overlap with the first or second stacking structure ST1 or ST2 when viewed from a top view. Additionally, the first horizontal channel HS1 may have rounded sidewalls, and each rounded sidewall of the first horizontal channel HS1 may be in contact with a second horizontal channel HS2. A width of the first horizontal channel HS1 may be smaller than that of each of the first and second stacking structures ST1 and ST2.

[0038] In some embodiments, the first and second vertical channels VS1 and VS2, the vertical dummy channels DVS and the first horizontal channel HS1 may be formed of a semiconductor material and may be undoped or doped with dopants of the same conductivity type (e.g., the first conductivity type) as the well dopant layer 11. The vertical channels VS1, VS2 and DVS and the first horizontal channel HS1 may have a crystal structure comprising at least one of a single-crystalline structure, an amorphous structure, or a polycrystalline structure.

[0039] In some embodiments, first and second vertical channels VS1 and VS2, the dummy vertical channels DVS, and the first horizontal channel HS1 may form the single semiconductor layer having no interface, as described above. The semiconductor layer may have a substantially uniform thickness and may extend from inner sidewalls of the first or second stack structure ST1 or ST2 to a bottom surface of the first or second stack structure ST1 or ST2. In other words, the thicknesses of the first and second vertical channels VS1 and VS2 may be substantially equal to a thickness of the first horizontal channel HS1.

[0040] A fill insulation structure VI can fill the inner spaces of the vertical channels VS1, VS2, and DVS and the first horizontal channel HS1. For example, the fill insulation structure VI can extend from the inner spaces of the vertical channels VS1, VS2, and DVS into the inner space of the first horizontal channel HS1.

[0041] The second horizontal channels HS2 may be arranged on both sides of the first horizontal channel HS1 of the channel structure CHS to connect the first horizontal channel HS1 to the well dopant layer 11. In some embodiments, the second horizontal channel HS2 may be formed of a semiconductor material and may be undoped or doped with dopants of the same conductivity type (i.e., the first conductivity type) as the well dopant layer 11. The second horizontal channel HS2 may have a crystal structure comprising at least one of a single-crystalline structure, an amorphous structure, or a polycrystalline structure.

[0042] In more detail, the second horizontal channel HS2 may be arranged between the first and second stack structures ST1 and ST2 in a plan view and may extend parallel to the first horizontal channel HS1 along the first direction D1. The second horizontal channels HS2 may be in contact with both sidewalls of the first horizontal channel HS1 among the first and second stack structures ST1 and ST2. An interface may exist between the first horizontal channel HS1 and the second horizontal channel HS2, which are formed of semiconductor materials. The second horizontal channel HS2 may be electrically connected to the vertical channels VS1, VS2, and DVS via the first horizontal channel HS1.

[0043] The second horizontal channel HS2 may include a dopant region 13 disposed between the first and second stack structures ST1 and ST2 when viewed from a top view. Here, the dopant region 13 may be doped with dopants of the first conductivity type. A dopant concentration of the dopant region 13 may be higher than that of the second horizontal channel HS2.

[0044] In some embodiments, conductive pads PAD may be arranged at upper ends of the first and second vertical channels VS1 and VS2, and source plugs CPLG may be arranged at upper ends of the vertical dummy channels DVS. In some embodiments, the upper ends of the vertical channels VS1, VS2, and DVS may be lower than the upper surface of each of the first and second stack structures ST1 and ST2, and upper surfaces of the conductive pad PAD and the source plug CPLG may be substantially coplanar with the upper surface of each of the first and second stack structures ST1 and ST2. A vertical length of each of the source plugs CPLG may be greater than that of the conductive pads PAD.In other words, the lower surfaces of the conductive pads PAD may be higher than the upper surface of the top electrodes SEL1 and SEL2, and the lower surfaces of the source plugs CPLG may be lower than the lower surfaces of the top electrodes SEL1 and SEL2. For example, the source plug CPLG may extend vertically toward the substrate 10 such that the lower surface of the source plug CPLG is adjacent to the first horizontal channel HS1.

[0045] The conductive pads PAD and the source plugs CPLG may be dopant regions doped with dopants or formed from a conductive material. In some embodiments, the conductive pads PAD and the source plugs CPLG may have a second conductivity type opposite to the first conductivity type of the dopant region 13 and the well dopant layer 11.

[0046] In some embodiments, a data storage layer DS may be disposed between each of the vertical channels VS1, VS2, and DVS, and each of the first and second stack structures ST1 and ST2 may extend between the first horizontal channel HS1 and a bottom surface of each of the first and second stack structures ST1 and ST2. Additionally, a residual data storage structure DSP may be disposed between the first horizontal channel HS1 and the well dopant layer 11 and may be spaced apart from the data storage layer DS.

[0047] In some embodiments, when the 3D semiconductor device is the vertical NAND flash memory device, each of the data storage layer DS and the residual data storage structure DSP may include a tunnel insulation layer TIL, a charge storage layer CIL, and a barrier insulation layer BLK, as shown in the Fig. 7A to 7E. Data stored in the data storage layer DS may be changed using Flower-Nordheim tunneling caused by a voltage difference between the electrode EL and each of the first and second vertical channels VS1 and VS2 comprising the semiconductor material. In some embodiments, the data storage layer DS may be a thin layer capable of storing data based on other operating principles. For example, the data storage layer DS may be a thin layer for a phase-change memory cell and / or a thin layer for a variable resistance memory cell.

[0048] A horizontal isolation structure HIL may extend from between the data storage layer DS and each of the electrodes EL on upper and lower surfaces of each of the electrodes EL. The horizontal isolation structure HIL on upper and lower surfaces of the first and second string selection electrodes SEL1 and SEL2 may further extend between the isolation isolation structure 115 and the first and second string selection electrodes SEL1 and SEL2. In some embodiments, when the 3D semiconductor device is the vertical NAND flash memory device, the horizontal isolation structure HIL may be used as a barrier layer.

[0049] A cover insulation structure 125 may be arranged on each of the first and second stack structures ST1 and ST2 to cover upper surfaces of the conductive pads PAD and upper surfaces of the source plugs CPLG.

[0050] A fill insulating layer 130 may be disposed on an entire upper surface of the substrate 10 to cover the first and second stack structures ST1 and ST2 and to completely fill a space between the first and second stack structures ST1 and ST2. In some embodiments, the fill insulating layer 130 may be in contact with an upper surface of the second horizontal channel HS2, i.e., an upper surface of the dopant region 13.

[0051] A common source line CSL extending in the first direction D1 may be arranged on the fill insulating layer 130. The common source line CSL may be connected to the source plugs CPLG through contact plugs CSP. The common source line CSL may be arranged on each of the first and second stack structures ST1 and ST2 and may be electrically connected in common to the vertical dummy channels DVS arranged along the first direction D1.

[0052] A first insulating layer 140 may be disposed on the fill insulating layer 130 to cover the common source lines CSL. First, second, third, and fourth assist interconnections SBL1, SBL2, SBL3, and SBL4 may be disposed on the first insulating layer 140. The first and third assist interconnections SBL1 and SBL3 may be disposed on the first stack structure ST1, and the second and fourth assist interconnections SBL2 and SBL4 may be disposed on the second stack structure ST2. The first and third assist interconnections SBL1 and SBL3 may intersect the common source line CSL disposed on the first stack structure ST1, and the second and fourth assist interconnections SBL2 and SBL4 may intersect the common source line CSL disposed on the second stack structure ST2.

[0053] The first assistance interconnections SBL1 may be electrically connected to the first vertical channels VS1 penetrating the first stack structure ST1 through lower contact plugs LCP. The third assistance interconnections SBL3 may be electrically connected to the second vertical channels VS2 penetrating the first stack structure ST1 through lower contact plugs LCP.

[0054] The second assistance interconnections SBL2 may be electrically connected to the first vertical channels VS1 penetrating the second stack structure ST2 through lower contact plugs LCP. The fourth assistance interconnections SBL4 may be electrically connected to the second vertical channels VS2 penetrating the second stack structure ST2 through lower contact plugs LCP.

[0055] A second insulating layer 150 may be disposed on the first insulating layer 140 to cover the first to fourth assist interconnections SBL1 to SBL4, and first and second bit lines BL1 and BL2 may be disposed on the second insulating layer 150. The first and second bit lines BL1 and BL2 may extend in the second direction D2 and may be arranged alternately along the first direction D1.

[0056] The first bit lines BL1 may be connected to the first assistance interconnections SBL1 and the third assistance interconnections SBL3 via upper contact plugs UCP, and the second bit lines BL2 may be connected to the second assistance interconnections SBL2 and the fourth assistance interconnections SBL4 via upper contact plugs UCP.

[0057] The channel structures according to various embodiments of the inventive concepts are described in detail with reference to the Fig. 7A to 7E are described.

[0058] Referring to the Fig. 7A to 7E, the first and second vertical channels VS1 and VS2 may be continuously connected to the first horizontal channel HS1 without a boundary layer therebetween. In some embodiments, the first horizontal channel HS1 may include an upper horizontal section HP1, a lower horizontal section HP2, and wall sections VP. The upper and lower horizontal sections HP1 and HP2 may be spaced from each other by the fill insulation structure VI. One of the wall sections VP may be connected between one end of the upper horizontal section HP1 and one end of the lower horizontal section HP2, and the other of the wall sections VP may be connected between another end of the upper horizontal section HP1 and another end of the lower horizontal section HP2. The upper and lower horizontal sections HP1 and HP2 and the wall sections VP may have a substantially uniform thickness.The second horizontal channels HS2 may be arranged on both sides of the first horizontal channel HS1 to be in direct contact with the wall portion VP of the first horizontal channel HS1.

[0059] Referring to the Fig. 7A to 7D, the second horizontal channel HS2 may be in direct contact with the well dopant layer 11. The second horizontal channel HS2 may be doped with dopants of the first conductivity type, and the dopant concentration of the second horizontal channel HS2 may be lower than or substantially equal to that of the well dopant layer 11. In the case where the dopant concentration of the second horizontal channel HS2 is lower than that of the well dopant layer 11, the dopant region 13 of the first conductivity type may be arranged in the second horizontal channel HS2. Here, the dopant region 13 of the first conductivity type may extend in the first direction D1 and may be in contact with the well dopant layer 11. The dopant concentration of the dopant region 13 may be substantially equal to that of the well dopant layer 11.In other words, during an erase operation of the vertical NAND flash memory device, an erase voltage applied to the well dopant layer 11 may be provided for the dopant region 13 of the first conductivity type.

[0060] Referring to Fig. 7E, the first and second stack structures ST1 and ST2, the first and second vertical channels VS1 and VS2, the vertical dummy channels DVS, and the first and second horizontal channels HS1 and HS2 may be arranged on the substrate 10 formed of an insulating material. Here, the second horizontal channel HS2 may be in contact with the substrate 10 formed of the insulating material and may include the first conductivity type dopant region 13. In this case, the erase voltage may be applied to the first conductivity type dopant region 13 during the erase operation of the vertical NAND flash memory device.

[0061] The data storage layer DS may extend from between the stack structure ST1 or ST2 and each of the first and second vertical channels VS1 and VS2 into between the first horizontal channel HS1 and the lowermost isolation layer ILD. The residual data storage structure DSP may be disposed between the well dopant layer 11 and the lower horizontal portion HP2 of the first horizontal channel HS1. The data storage layer DS may have the same thin layer(s) as the residual data storage structure DSP. In some embodiments, each of the data storage layer DS and the residual data storage structure DSP may include the tunnel isolation layer TIL, the charge storage layer CIL, and the barrier isolation layer BLK.

[0062] In the data storage layer DS and the residual data storage structure DSP, the charge storage layer CIL may include at least one of a trap-rich insulating layer, a floating gate electrode, or an insulating layer including conductive nanodots (or nanoparticles). The charge storage layer CIL may be formed using a chemical vapor deposition (CVD) technique and / or an atomic layer deposition (ALD) technique. For example, the charge storage layer CIL may include at least one of, but not limited to, a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, and / or a laminated trap layer.The tunnel insulation layer TIL may include at least one of materials having energy band gaps larger than that of the charge storage layer CIL and may be formed by a CVD process and / or an ALD process. For example, the tunnel insulation layer TIL may include a silicon oxide layer formed using the CVD process or the ALD process. In some embodiments, the tunnel insulation layer TIL may include one of high-k dielectric layers such as an aluminum oxide layer and a hafnium oxide layer. The barrier insulation layer BLK may include at least one of materials having energy band gaps smaller than those of the tunnel insulation layer TIL and larger than that of the charge storage layer TIL. For example, the barrier insulation layer BLK may include at least one of a high-k dielectric layer such as an aluminum oxide layer and a hafnium oxide layer.The barrier insulation layer BLK can be formed using at least one of a CVD process or an ALD process. At least one of the layers TIL, CIL, and BLK can be formed using a wet oxidation process. In some embodiments, the barrier insulation layer BLK can include first and second barrier insulation layers. In this case, the first barrier insulation layer can include at least one of high-k dielectric layers, such as an aluminum oxide layer and a hafnium oxide layer, and the second barrier insulation layer can include a material having a lower dielectric constant than the first barrier insulation layer. Some embodiments provide that the second barrier insulation layer can include at least one high-k dielectric layer, and the first barrier insulation layer can include a material having a lower dielectric constant than the second barrier insulation layer.

[0063] According to some embodiments described in Fig. 7A, the second horizontal channel HS2 may be in contact with the sidewall of the first horizontal channel HS1 and a portion of the data storage layer DS. In each of the first and second stack structures ST1 and ST2, the lowermost insulating layer ILD may have a first thickness t1 on the first horizontal channel HS1 and may have a second thickness t2 on the second horizontal channel HS2. Here, the second thickness t2 may be smaller than the first thickness t1.

[0064] According to some embodiments described in Fig. 7B, a protective insulation structure PP may be arranged between a bottom surface of the lowermost insulation layer ILD and the data storage layer DS. The second horizontal channel HS2 may be in contact with the sidewall of the first horizontal channel HS1, a portion of the data storage layer DS, and the protective insulation structure PP. The protective insulation structure PP may be formed of a different material from the lowermost insulation layer ILD. Here, the lowermost insulation layer ILD may be in contact with a portion of the second horizontal channel HS2, and may have a substantially uniform thickness.

[0065] According to some embodiments described in Fig. 7C, a protective insulation structure PP may be disposed between the bottom surface of the lowermost insulation layer ILD and the data storage layer DS, and between the second horizontal channel HS2 and the lowermost insulation layer ILD. In other words, the second horizontal channel HS2 may be in contact with the sidewall of the first horizontal channel HS1 and a portion of the data storage layer DS, and may be spaced apart from the lowermost insulation layer ILD.

[0066] According to some embodiments described in Fig. 7D, a protective isolation structure PP may be disposed between the bottom surface of the lowest insulation layer ILD and the data storage layer DS and may include a plurality of thin layers. For example, the protective isolation structure PP may have the same stacked structure as the data storage layer DS. For example, the protective isolation structure PP may include a silicon oxide layer L1, a silicon nitride layer L2, and a silicon oxide layer L3, which are sequentially stacked. The protective isolation structure PP may extend between the lowest insulation layer ILD and the second horizontal channel HS2.

[0067] The Fig. 8A and Fig. 8B are views illustrating methods of operating a 3D semiconductor device according to some embodiments of the inventive concepts. Fig. 8A is a view illustrating a read operation of a 3D semiconductor device, and Fig. 8B is a view illustrating an erase operation of a 3D semiconductor device.

[0068] Referring to the Fig. 8A and Fig. 8B, a first string select line SSL0, word lines WL0 to WL3, and a ground select line GSL may be coupled to one of the first vertical channels VS1 to form a first string STR1. A second string select line SSL1, the word lines WL0 to WL3, and the ground select line GSL may be coupled to another of the first vertical channels VS1 to form a second string STR2. The word lines WL0 to WL3 and the ground select line GSL may be coupled to the vertical dummy channels DVS to form a dummy string DSTR. The upper ends of the vertical dummy channel DVS may be electrically connected to the source plug CPLG. The upper ends of the first and second vertical channels VS1 and VS2 may be electrically connected to the first bit line BL1.The first and second strings STR1 and STR2 may be jointly connected to the common source line CSL via the first horizontal channel HS1 and the vertical dummy channel DVS. Additionally, the first and second strings STR1 and STR2 may be connected to the second horizontal channel HS2 and the well dopant layer (11) via the first horizontal channel HS1.

[0069] According to some embodiments of the inventive concepts, a path through which electrons move during the read operation may be different from a path through which holes move during the erase operation.

[0070] Referring to Fig. 8A, in the read operation of the 3D semiconductor device, a ground voltage GND may be applied to a selected word line WL2, and a read voltage Vread may be applied to unselected word lines WL0, WL1, and WL3. Here, the read voltage Vread may be higher than the threshold voltages of the transistors to create inversion layers in the first vertical channels VS1. A predetermined bit line voltage V BL can be applied to a selected bit line BL1, and the ground voltage GND can be applied to unselected bit lines. The power supply voltage Vcc for turning on the string and ground select transistors can be applied to a selected string select line SSLO or SSL1 and a ground select line GSL. The ground voltage GND can be applied to an unselected string select line SSLO or SSL1, the common source line CSL, and the well impurity layer (11).

[0071] Under the above voltage conditions, a read current path may be created between the selected bit line BL1 and the common source line CSL during the read operation. When the first string select line SSL0 is selected, a current of electrons may flow through the first vertical channel VS1 of the first string STR1, the first horizontal channel HS1, and the vertical dummy channel DVS between the selected bit line BL1 and the common source line CSL. When the second string select line SSL1 is selected, a current of electrons may flow through the first vertical channel VS1 of the second string STR2, the first horizontal channel HS1, and the vertical dummy channel DVS between the selected bit line BL1 and the common source line CSL.

[0072] Referring to Fig. 8B, in the erase operation of the 3D semiconductor device, a ground voltage Vss can be applied to the word lines WL0 to WL3. In addition, the bit line BL1, the string selection lines SSL0 and SSL1, and the common source line CSL can be floated. Furthermore, an erase voltage Vera can be applied to the well impurity layer 11 through a well pickup region 11p of the Fig. 3. The quenching voltage Vera can be transmitted to the second horizontal channel HS2.

[0073] Under these stress conditions, holes can be provided in the first and second vertical channels VS1 and VS2 through the first and second horizontal channels HS1 and HS2 during the erase operation. In other words, the path through which the holes are provided can be created in the first and second horizontal channels HS1 and HS2 and the first and second vertical channels VS1 and VS2 during the erase operation.

[0074] Fig. 9 is a cross-sectional view illustrating a 3D semiconductor device according to some embodiments of the inventive concept. Fig. 10 is an enlarged view of a section “A” of the Fig. 9. In the present embodiment, the descriptions of the same technical features as in the embodiment of Fig. 3, Fig. 4A, Fig. 4B, Fig. 5 and Fig. 6 may be omitted or briefly mentioned in the Declaration for the purpose of convenience and expediency.

[0075] Referring to the Fig. 9 and Fig. 10, the first and second stack structures ST1 and ST2, which extend in the first direction D1, may be arranged on the substrate 10 so as to be spaced apart from each other in the second direction D2. The channel structure CHS may be provided for each of the first and second stack structures ST1 and ST2. The channel structure CHS may include the first and second vertical channels VS1 and VS2, the vertical dummy channels DVS, and the first horizontal channel HS1.

[0076] The first and second vertical channels VS1 and VS2 and the vertical dummy channels DVS may penetrate each of the first and second stack structures ST1 and ST2, and the first horizontal channel HS1 may be arranged under each of the first and second stack structures ST1 and ST2. The first horizontal channel HS1 may extend continuously from the vertical channels VS1, VS2, and DVS and may extend parallel to each of the first and second stack structures ST1 and ST2 along the first direction D1, as described with reference to FIG. Fig. 4A and Fig. 4B. The second horizontal channels HS2 may be arranged on both sides of the first horizontal channel HS1. The second horizontal channels HS2 may extend in the first direction D1 and may each be in contact with both sidewalls of the first horizontal channel HS1. The first horizontal channel HS1 may be connected to the first and second vertical channels VS1 and VS2 without an interface therebetween, but an interface may be formed between the first horizontal channel HS1 and the second horizontal channel HS2 by semiconductor crystals.

[0077] In some embodiments, the first horizontal channel HS1 may completely fill a space between the substrate 10 and each of the first and second stack structures ST1 and ST2 without the filler insulation structure VI. In more detail, the first horizontal channel HS1 may have upper and lower horizontal portions HP1 and HP2 that are in contact with each other. At this time, an interface between the upper and lower horizontal portions HP1 and HP2 may be formed by semiconductor crystals. The upper horizontal portion HP1 may cover the data storage layer DS covering the lower surface of each of the first and second stack structures ST1 and ST2, and the lower horizontal portion HP2 may cover the residual data storage structure DSP arranged on the substrate 10.

[0078] The filling insulation structure VI can fill the inner space of each of the vertical channels VS1, VS2, and DVS having the hollow tube shapes. The filling insulation structures VI of the vertical channels VS1, VS2, and DVS can be in contact with the first horizontal channel HS1 and can be separated from each other.

[0079] The data storage layer DS may be disposed between each of the first and second stack structures ST1 and ST2 and the vertical channels VS1, VS2, and DVS. The data storage layer DS may extend to the lower surface of the lowermost insulation layer ILD of each of the first and second stack structures ST1 and ST2.

[0080] The conductive pads PAD may be arranged on the first and second vertical channels VS1 and VS2, respectively, and the source plugs CPLG may be arranged on the vertical dummy channels DVS, respectively. In some embodiments, the conductive pads PAD and the source plugs CPLG may be dopant regions. In this case, the conductive pads and the source plugs CPLG may have the second conductivity type opposite to the first conductivity type of the dopant region 13 formed in the second horizontal channel HS2.

[0081] The Fig. 11, Fig. 12, Fig. 13 and Fig. 14 are cross-sectional views illustrating 3D semiconductor devices according to some embodiments of the inventive concepts. Hereinafter, descriptions of the same technical features as in the embodiment of Fig. 3, Fig. 4A, Fig. 4B, Fig. 5 and Fig. 6 may be omitted or briefly mentioned in the declaration for the sake of convenience and expediency.

[0082] Referring to Fig. 11, the first and second vertical channels VS1 and VS2 and the dummy vertical channels DVS may penetrate each of the first and second stack structures ST1 and ST2, and the first horizontal channel HS1 may be arranged under each of the first and second stack structures ST1 and ST2. The first horizontal channel HS1 may extend continuously from the vertical channels VS1, VS2, and DVS and may extend parallel to each of the first and second stack structures ST1 and ST2 along the first direction D1. The second horizontal channels HS2 may be arranged on both sides of the first horizontal channel HS1. The second horizontal channels HS2 may extend in the first direction D1 and may each be in contact with both sidewalls of the first horizontal channel HS1.

[0083] The conductive pads PAD may be arranged on the first and second vertical channels VS1 and VS2, respectively, and the source plugs CPLG may be arranged on the vertical dummy channels DVS, respectively. In some embodiments, the conductive pads PAD and the source plugs CPLG may have the second conductivity type opposite to the first conductivity type of the dopant region 13 of the second horizontal channel HS2.

[0084] In some embodiments, the lower surfaces of the source plugs CPLG connected to the vertical dummy channels DVS may be higher than the upper surface of the top electrode. For example, the lower surfaces of the source plugs CPLG may be arranged at the same level as the lower surfaces of the conductive pads PAD arranged on the upper ends of the first and second vertical channels VS1 and VS2.

[0085] The source plugs CPLG may be electrically connected to the common source line CSL through the contact plugs CSP, and the conductive pads PAD may be electrically connected to the bit lines BL1 and BL2 via the lower and upper contact plugs LCP and UCP and the assistant interconnections SBL1 and SBL2.

[0086] Referring to Fig. 12, the first and second stack structures ST1 and ST2, which extend in the first direction D1, may be spaced apart from each other in the second direction D2 on the substrate 10. The first and second vertical channels VS1 and VS2 and the dummy vertical channels DVS may penetrate each of the first and second stack structures ST1 and ST2, and the first horizontal channel HS1 may be arranged below each of the first and second stack structures ST1 and ST2. The first horizontal channel HS1 may extend continuously from the vertical channels VS1, VS2, and DVS and may extend parallel to each of the first and second stack structures ST1 and ST2 along the first direction D1.

[0087] Second horizontal channels HS2 may be arranged on both sides of the first horizontal channel HS1. The second horizontal channels HS2 may extend in the first direction D1 and may each be in contact with both sidewalls of the first horizontal channel HS1. In some embodiments, the second horizontal channel HS2, which is arranged below an edge of the first stack structure ST1 adjacent to the second stack structure ST2, may be separated from the second horizontal channel HS2, which is arranged below an edge of the second stack structure ST2 adjacent to the first stack structure ST1.In other words, the fill insulating layer 130 disposed between the first and second stack structures ST1 and ST2 may penetrate the second horizontal channel HS2 to be in contact with the substrate 10, and the second horizontal channels HS2 may have sidewalls aligned with sidewalls of the first and second stack structures ST1 and ST2.

[0088] In some embodiments, the second horizontal channels HS2 may be doped with dopants of the first conductivity type, and the dopant concentration of the second horizontal channel HS2 may be higher than that of the first horizontal channel HS1. The dopant concentration of the first horizontal channel HS1 may be substantially equal to that of the well dopant layer 11.

[0089] Referring to Fig. 13, the first and second stack structures ST1 and ST2, which extend in the first direction D1, may be spaced from each other in the second direction D2 on the substrate 10. The first and second vertical channels VS1 and VS2 and the vertical dummy channels DVS may penetrate each of the first and second stack structures ST1 and ST2, and the first horizontal channel HS1 may be arranged below each of the first and second stack structures ST1 and ST2. The first horizontal channel HS1 may extend continuously from the vertical channels VS1, VS2, and DVS and may extend parallel to each of the first and second stack structures ST1 and ST2 along the first direction D1. The second horizontal channels HS2 may be arranged on both sides of the first horizontal channel HS1.The second horizontal channels HS2 may extend in the first direction D1 and may each be in contact with both sidewalls of the first horizontal channel HS1. The first and second vertical channels VS1 and VS2 may be continuously connected to the horizontal channel HS1 without an interface therebetween, but an interface between the first horizontal channel HS1 and the second horizontal channel HS2 may be formed by semiconductor crystals.

[0090] In some embodiments, a common source region 15 may be arranged in each of the second horizontal channels HS2. The common source region 15 may have the second conductivity type opposite to the first conductivity type of the well dopant layer 11. The common source region 15 may extend in the first direction D1 between the first and second stack structures ST1 and ST2 when viewed from a top view. The common source region 15 may be spaced apart from the well dopant layer 11.

[0091] In some embodiments, the conductive pads PAD may be arranged on the upper ends of the first and second vertical channels VS1 and VS2, and receiving plugs PPLG may be arranged on the upper ends of the vertical dummy channels DVS. The conductive pads PAD and the receiving plugs PPLG may be dopant regions doped with dopants or may be formed of a conductive material. In some embodiments, the receiving plugs PPLG may have the same conductivity type (i.e., the first conductivity type) as the well dopant layer 11, but the conductive PADs may have the second conductivity type opposite to the first conductivity type.

[0092] In some embodiments, a vertical length of the receiving plug PPLG may be longer than that of the conductive pad PAD. In other words, the lower surface of the conductive pad PAD may be higher than the upper surface of the top electrode, and a lower surface of the receiving plug PPLG may be lower than the lower surface of the top electrode. In certain embodiments, the lower surfaces of the receiving plug PPLG and the conductive pad PAD may be higher than the upper surface of the top electrode.

[0093] In some embodiments, a conductive well line PCL may be disposed on the fill insulating layer 130, which is disposed on each of the first and second stack structures ST1 and ST2, and may extend in the first direction. The conductive well line PCL may be connected to the receiving plugs PPLG, which are arranged along the first direction D1, through contact plugs CSP. In the erase operation of the 3D semiconductor device, the erase voltage may be applied to the conductive well line PCL and the receiving plugs PPLG. The conductive contact pads PAD may be connected to the bit lines BL1 and BL2 through the upper and lower contact plugs LCP and UCP and the assist interconnects SBL1 and SBL2.

[0094] In some embodiments, a common source line CSL may penetrate the fill insulating layer 130 between the first and second stack structures ST1 and ST2 to be connected to the common source region 15. In other words, a common source voltage may be applied to the common source line CSL and the common source region 15 in a programming operation or the reading operation of the 3D semiconductor device.

[0095] Referring to Fig. 14, the first and second stack structures ST1 and ST2 may extend in the first direction D1 on the substrate 10 and may be spaced apart from each other in the second direction D2. As described above, the one channel structure CHS may penetrate each of the first and second stack structures ST1 and ST2, and the second horizontal channels HS2 may be arranged on both sides of the first horizontal channel HS1.

[0096] In some embodiments, the conductive contact pads PAD may be arranged on the upper ends of the first and second vertical channels VS1 and VS2 and the upper ends of the vertical dummy channels DVS. The conductive contact pads PAD may be dopant regions doped with dopants and / or may be formed from a conductive material. In some embodiments, the conductive contact pads PAD may have the second conductivity type opposite to the first conductivity type.

[0097] In some embodiments, the common source region 15 may be disposed in the second horizontal channel HS2, which is located on one side of the first horizontal channel HS1, and a receiving dopant region 13 may be disposed in the second horizontal channel HS2, which is located on another side of the first horizontal channel HS1. The common source region 15 may be doped with dopants. Here, the common source region 15 may have the second conductivity type opposite to the first conductivity type of the well dopant layer 11, but the receiving dopant region 13 may have the same conductivity type (i.e., the first conductivity type) as the well dopant layer 11.

[0098] In some embodiments, the common source region 15 and the receiving dopant region 13 may extend in the first direction D1 and may be spaced apart from the well dopant layer 11. The first stack structure ST1 may have a first sidewall and a second sidewall opposite each other. The common source region 15 may be arranged between the first stack structure ST1 and the second stack structure ST1 adjacent to the first sidewall of the first stack structure ST1 in a plan view, and the receiving dopant region 13 may be arranged between the first stack structure ST1 and the second stack structure ST2 adjacent to the second sidewall of the first stack structure ST2 in a plan view.

[0099] In some embodiments, the common source line CSL may penetrate the fill insulating layer 130 between the first stack structure ST1 and the second stack structure ST2 adjacent to the first sidewall of the first stack structure ST1 to be connected to the common source region 15. In the programming or reading operation of the 3D semiconductor device, the common source voltage may be applied to the common source line CSL and the common source region 15.

[0100] A conductive well line PCL may penetrate the fill insulating layer 130 between the first stack structure ST1 and the second stack structure ST2 adjacent to the second sidewall of the first stack structure ST1 to be connected to the receiving dopant region 13. Accordingly, the erase voltage for the first and second horizontal channels HS1 and HS2 and the first and second vertical channels VS1 and VS2 may be provided through the conductive well line PCL and the receiving dopant region 13 in the erase operation of the 3D semiconductor device.

[0101] Fig. 15 is a plan view illustrating a 3D semiconductor device according to some embodiments of the inventive concept. Fig. 16 is a cross-sectional view taken along a line II' of the Fig. 15 to illustrate a 3D semiconductor device according to some embodiments of the inventive concepts.

[0102] Referring to the Fig. 15 and Fig. 16, the first and second stacked structures ST1 and ST2 may extend in the first direction D1 on the substrate 10 and may be spaced from each other in the second direction D2. Each of the first and second stacked structures ST1 and ST2 may include electrodes EL stacked vertically on the substrate 10, and the uppermost electrode of each of the first and second stacked structures ST1 and ST2 may be divided into the first strand selection electrode SEL1 and the second strand selection electrode SEL2, which are spaced from each other by the separation insulation structure 115. The first and second strand selection electrodes SEL1 and SEL2 may extend in the first direction.

[0103] A channel structure CHS may be provided in each of the first and second stack structures ST1 and ST2. The channel structure CHS may include a plurality of first to fourth vertical channels VS1, VS2, VS3, and VS4, vertical dummy channels DVS, and a first horizontal channel HS1.

[0104] The plurality of first to fourth vertical channels VS1, VS2, VS3, and VS4 and the vertical dummy channels DVS may penetrate each of the first and second stack structures ST1 and ST2. The vertical dummy channels DVS may be arranged along the first direction D1 between the first and second strand selection electrodes SEL1 and SEL2. The first vertical channels VS1 may be arranged along the first direction D1 to form a first column, and the second vertical channels VS2 may be arranged along the first direction D2 to form a second column. The third vertical channels VS3 may be arranged along the first direction D1 to form a third column, and the fourth vertical channels may be arranged along the first direction D2 to form a fourth column.

[0105] The first to fourth vertical channels VS1 to VS4, which penetrate the first strand selection electrode SEL1, and the first to fourth vertical channels VS1 to VS4, which penetrate the second strand selection electrode SEL2, may be arranged in mirror symmetry with respect to the vertical dummy channels DVS. The first and third vertical channels VS1 and VS3 may be aligned with the second and fourth vertical channels VS2 and VS4, respectively, in a direction diagonal to the second direction D2.

[0106] The first to fourth vertical channels VS1 to VS4 and the vertical dummy channels DVS may have hollow tube, hose, and / or macaroni shapes. In some embodiments, the first to fourth vertical channels VS1 to VS4 and the vertical dummy channels DVS may have cylindrical shapes.

[0107] The first horizontal channel HS1 may be disposed under each of the first and second stack structures ST1 and ST2, and may extend continuously from the first to fourth vertical channels VS1, VS2, VS3, and VS4 and the vertical dummy channels DVS. In other words, the first to fourth vertical channels VS1, VS2, VS3, and VS4, the vertical dummy channels DVS, and the first horizontal channel HS1 may form a semiconductor layer that extends continuously to have a tubular shape in one body.

[0108] The first horizontal channel HS1 may extend parallel to the first and second stack structures ST1 and ST2 and may have rounded side walls, as described with reference to Fig. 4B. In addition, a width of the first horizontal channel HS1 may be smaller than that of each of the first and second stack structures ST1 and ST2. The second horizontal channels HS2 may be arranged on both sides of the first horizontal channel HS1. The second horizontal channels HS2 may extend in the first direction D1 and may be in contact with the sidewalls of the first horizontal channel HS1. The first to fourth vertical channels VS1, VS2, VS3, and VS4 may be continuously connected to the first horizontal channel HS1 without an interface therebetween. An interface may be formed between the first horizontal channel HS1 and the second horizontal channel HS2 by semiconductor crystals.

[0109] The second horizontal channel HS2 may have the same conductivity type (ie, the first conductivity type) as the well dopant layer 11. The second horizontal channel HS2 may have the dopant region 13 disposed between the first and second stack structures ST1 and ST2 when viewed from a top view. The dopant region 13 may have the first conductivity type, and the dopant concentration of the dopant region 13 may be higher than that of the second horizontal channel HS2.

[0110] The conductive pads PAD may be disposed at upper ends of the first to fourth vertical channels VS1, VS2, VS3, and VS4, respectively, and the source plugs CPLG may be disposed at the upper ends of the vertical dummy channels DVS, respectively. The vertical length of the source plug CPLG may be longer than that of the conductive pad PAD. In other words, the lower surfaces of the conductive pads PAD may be higher than the upper surface of the topmost electrode, and the lower surfaces of the source plugs CPLG may be lower than the lower surface of the topmost electrode. For example, the source plug CPLG may extend vertically toward the substrate 10 such that the lower surface of the source plug CPLG is adjacent to the first horizontal channel HS1.

[0111] The conductive contact pads PAD and the source plugs CPLG may be dopant regions doped with dopants or may be formed from a conductive material. In some embodiments, the conductive contact pads and the source plugs CPLG may have the second conductivity type opposite to the first conductivity type of the dopant region 13 and the well dopant layer 11. In some embodiments, as described with reference to Fig. 13, the receiving plug PPL1 having the first conductivity type may be arranged at the upper end of the vertical dummy channel DVS, and the common source region 15 having the second conductivity type may be arranged in the second horizontal channel HS2.

[0112] The common source line CSL may be arranged on the fill insulating layer 130 covering the first and second stack structures ST1 and ST2. The common source line CSL may be connected to the source plugs CPLG via the contact plugs CSP. The common source line CSL may be arranged on each of the first and second stack structures ST1 and ST2 and may be electrically connected in common to the vertical dummy channels arranged along the first direction D1.

[0113] The first insulating layer 140 may be disposed on the filling insulating layer 130 to cover the common source lines CSL, and the first to fourth assist interconnections SBL1, SBL2, SBL3, and SBL4 may be disposed on the first insulating layer 140.

[0114] In some embodiments, each of the first assistance interconnections SBL1 may be connected to the first vertical channels VS1 adjacent to each other in the second direction D2 via lower contact plugs LCP. Each of the second assistance interconnections SBL2 may be connected to the second vertical channels VS2 adjacent to each other in the second direction D2 via lower contact plugs LCP. In some embodiments, the lengths of the second assistance interconnections SBL2 may be shorter than those of the first assistance interconnections SBL1.

[0115] Each of the third assistance interconnections SBL3 may be connected to the third vertical channels VS3 adjacent to each other in the second direction D2 via lower contact plugs LCP. Each of the fourth assistance interconnections SBL4 may be connected to the fourth vertical channels VS4 adjacent to each other in the second direction D2 via lower contact plugs LCP. In some embodiments, the lengths of the fourth assistance interconnections SBL4 may be shorter than those of the third assistance interconnections SBL3.

[0116] The first and second assistance interconnections SBL1 and SBL2 may intersect the common source line CSL on each of the first and second stack structures ST1 and ST2, and the third and fourth assistance interconnections SBL3 and SBL4 may intersect the dopant region 13.

[0117] The second insulating layer 150 may be disposed on the first insulating layer and the first to fourth assist interconnections SBL1 to SBL4, and the first and second bit lines BL1 and BL2 may be disposed on the second insulating layer 150. The first and second bit lines BL1 and BL1 may extend in the second direction D2 and may be alternately arranged in the first direction D1.

[0118] Each of the first bit lines BL1 may be connected to the first assistance interconnections SBL1 or the second assistance interconnections SBL2 via upper contact plugs UCP. Each of the second bit lines BL2 may be connected to the third assistance interconnections SBL3 or the fourth intermediate interconnections SBL4 via upper contact plugs UCP.

[0119] In the embodiment of the Fig. 15 and Fig. 16, the first to fourth vertical channels VS1 to VS4 may be commonly connected to the common source line CSL via the first horizontal channel HS1 and the vertical dummy channels DVS during the read operation. In the erase operation, the first to fourth vertical channels VS1 to VS4 may be connected to the second horizontal channel HS2, which is supplied with the erase voltage by the first horizontal channel HS1.

[0120] Fig. 17 is a schematic block diagram illustrating a 3D semiconductor device according to some embodiments of the inventive concepts.

[0121] Referring to Fig. 17, a 3D semiconductor device according to some embodiments may include a peripheral logic structure PS and cell array structures CS stacked on the peripheral logic structure PS. In other words, the peripheral logic structure and the cell array structures may overlap with each other when viewed from a top view.

[0122] In some embodiments, the peripheral logic structure PS may include the row and column decoders 2 and 4, the page buffer 3, and the control circuit 5, which are described with reference to Fig. 1. The cell array structure CS may include a plurality of memory blocks BLKO to BLKn, each of which corresponds to a data erase unit. Each of the memory blocks BLKO to BLKn may have a structure stacked on a plane defined by first and second directions D1 and D2 along a third direction D3. Each of the memory blocks BLKO to BLKn may include a memory cell array having a three-dimensional structure (or a vertical structure). The memory cell array may include the three-dimensionally arranged memory cells, the word lines, and the bit lines described with reference to Fig. 2 are described.

[0123] Fig. Fig. 18 is a cross-sectional view illustrating a 3D semiconductor device according to some embodiments of the inventive concepts. Hereinafter, descriptions of the same technical features as in the embodiment of Fig. 3, Fig. 4A, Fig. 4B, Fig. 5 and Fig. 6 may be omitted or briefly mentioned in the Declaration for the purpose of convenience and expediency.

[0124] Referring to Fig. 18, a peripheral logic structure PS and a cell array structure CS may be sequentially stacked on a semiconductor substrate 10. In other words, the peripheral logic structure PS may be arranged between the semiconductor substrate 10 and the cell array structure CS when viewed from a cross-sectional view. That is, the peripheral logic structure PS may overlap with the cell array structure CS when viewed from a top view.

[0125] The semiconductor substrate 10 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, and / or a substrate having an epitaxial layer obtained by performing a selective epitaxial growth (SEG) process.

[0126] The peripheral logic structure PS can implement peripheral circuits including the row and column decoders 2 and 4 of the Fig. 1, of the page buffer 3 of the Fig. 1 and the control circuit 5 of the Fig. 1. In other words, the peripheral logic structure PS may include NMOS and PMOS transistors, a resistor, and a capacitor, which form the peripheral circuits and are electrically connected to the cell array structure CS. These peripheral circuits may be formed on an entire upper surface of the semiconductor substrate 10. The semiconductor substrate 10 may include an N-well region NW doped with N-type dopants and a P-well region PW doped with P-type dopants. Active regions may be defined in the N-well region NW and the P-well region PW by a device isolation layer 20.

[0127] The peripheral logic structure PS may include peripheral gate electrodes PG, source and drain dopant regions arranged in the active area on both sides of each of the peripheral gate electrodes PG, peripheral contact plugs CP, peripheral circuit interconnections ICL, and a lower fill insulating layer 100 covering the peripheral circuits. The PMOS transistor may be formed on the N-well region NW, and the NMOS transistor may be formed on the P-well region PW. The peripheral circuit interconnections ICL may be electrically connected to the peripheral circuits through the peripheral contact plugs CP. In some embodiments, the peripheral contact plugs CP and the peripheral circuit interconnections ICL may be connected to the NMOS and PMOS transistors.

[0128] The lower fill insulating layer 100 may cover the peripheral circuits, the peripheral contact plugs CP, and the peripheral circuit interconnections ICL. The lower fill insulating layer 100 may include a plurality of stacked insulating layers.

[0129] The cell array structure CS may include the first and second stack structures ST1 and ST2 extending in the first direction D1 and spaced apart from each other in the second direction D2 on the lower fill insulating layer 100. Each of the first and second stack structures ST1 and ST2 may include a plurality of electrodes EL stacked vertically on the lower fill insulating layer 100. In some embodiments, a channel structure CHS may be provided in each of the first and second stack structures ST1 and ST2. The channel structure CHS may include the first and second vertical channels VS1 and VS2, the vertical dummy channels DVS, and the first horizontal channel HS1.

[0130] The first and second vertical channels VS1 and VS2 and the vertical dummy channels DVS may penetrate each of the first and second stack structures ST1 and ST2, and the first horizontal channel HS1 may be arranged under each of the first and second stack structures ST1 and ST2. The first horizontal channel HS1 may extend continuously from the first and second vertical channels VS1 and VS2 and the vertical dummy channels DVS and may extend parallel to each of the first and second stack structures ST1 and ST2, as described with reference to FIG. Fig. 4A and Fig. 4B. The first horizontal channel HS1 may overlap with each of the first and second stack structures ST1 and ST2 when viewed from a top view. The width of the first horizontal channel HS1 may be smaller than that of the first and second stack structures ST1 and ST2. In addition, the first horizontal channel may have rounded sidewalls, as described with reference to Fig. 4B is described.

[0131] The second horizontal channels HS2 may be arranged on both sides of the first horizontal channel HS1. The second horizontal channels HS2 may extend in the first direction D1 and may be in contact with the sidewalls of the first horizontal channel HS1. The first and second vertical channels VS1 and VS2 may be continuously connected to the first horizontal channel HS1 without an interface therebetween, but an interface may be formed between the first horizontal channel HS1 and the second horizontal channel HS2 by semiconductor crystals.

[0132] In some embodiments, the second horizontal channel HS2 may be in direct contact with the lower fill insulating layer 100, and the dopant region having the first conductivity type may be arranged in the second horizontal channel HS2.

[0133] The data storage layer DS may be disposed between each of the first and second stack structures ST1 and ST2 and the vertical channels VS1, VS2, and DVS. The data storage layer DS may extend to the bottom surface of the lowermost insulation layer ILD of each of the first and second stack structures ST1 and ST2. In some embodiments, the residual data storage structure may be vertically spaced from the data storage layer DS and may be disposed between the first horizontal channel HS1 and the lower fill insulation layer 100.

[0134] The conductive pads PAD may be arranged on the upper ends of the first and second vertical channels VS1 and VS2, and the source plugs CPLG may be arranged on the upper ends of the vertical dummy channels DVS. In some embodiments, when the conductive pads PAD and the source plugs CPLG are dopant regions doped with dopants, the conductive pads PAD and the source plugs CPLG may have the second conductivity type opposite to the first conductivity type of the dopant region 13.

[0135] The cover insulation structure 125 may be arranged on each of the first and second stack structures ST1 and ST2 to cover the upper surfaces of the conductive pads PAD and the upper surfaces of the source plugs CPLG.

[0136] An upper fill insulating layer 130 may be disposed on an entire upper surface of the lower fill insulating layer 100 to cover the first and second stack structures ST1 and ST2, and may completely fill a space between the first and second stack structures ST1 and ST2. In some embodiments, the upper fill insulating layer 130 may be in contact with the upper surface of the dopant region 13.

[0137] The common source line CSL may be arranged on the upper fill insulating layer 130. The common source line CSL may be electrically connected to the source plugs CPLG through the contact plugs CSP. The common source line CSL may be arranged on each of the first and second stack structures ST1 and ST2 and may be electrically connected in common to the vertical dummy channels DVS arranged along the first direction D1.

[0138] The first insulating layer 140 may be disposed on the upper fill insulating layer 130 to cover the common source lines CSL, and the first to fourth assist interconnections SBL1 to SBL4 may be disposed on the first insulating layer 140. The first and third assist interconnections SBL1 and SBL3 may be disposed on the first stack structure ST1, and the second and fourth assist interconnections SBL1 and SBL4 may be disposed on the second stack structure ST2. The first and third assist interconnections SBL1 and SBL3 may intersect the common source line CSL disposed on the first stack structure ST1, and the second and fourth assist interconnections SBL2 and SBL4 may intersect the common source line CSL disposed on the second stack structure ST2.

[0139] The second insulating layer 150 may be disposed on the first insulating layer 140 to cover the first to fourth assist interconnections SBL1 to SBL4, and the first and second bit lines BL1 and BL2 may be disposed on the second insulating layer 150. The first and second bit lines BL1 and BL2 may extend in the second direction D2 and may be alternately arranged in the first direction D1.

[0140] The first bit lines BL1 may be connected to the first assistance interconnections SBL1 and the third assistance interconnections SBL3 through upper contact plugs UCP, and the second bit lines BL2 may be connected to the second assistance interconnections SBL2 and the fourth assistance interconnections SBL4 through upper contact plugs UCP.

[0141] The Fig. 19 to 29 are cross-sectional views taken along the line I-I' of the Fig. 4A to illustrate methods of manufacturing a 3D semiconductor device according to some embodiments of the inventive concepts. Fig. 30 to 35 are enlarged views of sections “A” of the Fig. 21 to 26 to illustrate a method of manufacturing a 3D semiconductor device according to some embodiments of the inventive concepts.

[0142] Referring to the Fig. 4A and Fig. 19, a first sacrificial layer SL1 may be formed on a substrate 10. Insulating layers ILD and second sacrificial layers SL2 may be alternately and repeatedly formed on the first sacrificial layer SL1 to form a thin layer structure 110.

[0143] In some embodiments, the substrate 10 may be formed from a semiconductor material. For example, the substrate 10 may be a bulk silicon substrate, an SOI substrate, a germanium substrate, a GOI substrate, a silicon-germanium substrate, and / or a substrate having an epitaxial layer obtained by performing an SEG process. In some embodiments, the substrate 10 may include a well dopant layer 11 doped with dopants of a first conductivity type, and the first sacrificial layer SL1 may be formed on an upper surface of the well dopant layer 11.

[0144] In some embodiments, the substrate 10 may be formed from an insulating material. In some embodiments, the substrate 10 may comprise a single layer or a plurality of thin layers. For example, the substrate 10 may be formed from at least one silicon oxide layer, a silicon nitride layer, or a low-k dielectric layer. In this case, the first sacrificial layer SL1 may be formed on a top surface of the substrate 10.

[0145] The first sacrificial layer SL1 may be formed from a material that has etch selectivity with respect to the insulating layers ILD and the second sacrificial layers SL2. For example, the first sacrificial layer SL1 may comprise at least one of a silicon oxide layer, a silicon carbide layer, a silicon germanium layer, a silicon oxynitride layer, and / or a silicon nitride layer.

[0146] In the thin layer structure 110, the second sacrificial layers SL2 may be formed of a material having etch selectivity with respect to the insulating layers ILD. For example, a difference between an etching rate of the second sacrificial layers SL2 and an etching rate of the insulating layers ILD may be large in a wet etching process using a chemical solution, but a difference between an etching rate of the second sacrificial layers SL2 and an etching rate of the insulating layers ILD may be small in a dry etching process using an etching gas.

[0147] In some embodiments, the second sacrificial layers SL2 and the insulating layers ILD may be formed of insulating materials, and the second sacrificial layers SL2 may have etch selectivity with respect to the insulating layers ILD. For example, the second sacrificial layers SL2 may comprise at least one of a silicon layer, a silicon oxide layer, a silicon carbide layer, a silicon germanium layer, a silicon oxynitride layer, and / or a silicon nitride layer. At this time, the second sacrificial layers SL2 may comprise a different material from the first sacrificial layer SL1. The insulating layers ILD may comprise at least one of a silicon layer, a silicon oxide layer, a silicon carbide layer, a silicon oxynitride layer, and / or a silicon nitride layer. At this time, the insulating layers ILD may comprise a different material from the first and second sacrificial layers SL1 and SL2.

[0148] For example, the first sacrificial layer SL1 may be formed from a polysilicon layer, the second sacrificial layers SL2 may be formed from silicon nitride layers, and the insulating layers ILD may be formed from low-k dielectric layers. In some embodiments, the second sacrificial layers SL2 may be formed from a conductive material, and the insulating layers ILD may be formed from an insulating material.

[0149] Each of the layers SL1, SL2 and IDL can be deposited using a thermal vapor deposition (thermal CVD) technique, a plasma-enhanced CVD technique, a physical CVD technique and / or an atomic layer deposition (ALD) technique.

[0150] In some embodiments, the second sacrificial layers SL2 may have the same thickness, and the first sacrificial layer SL1 may be thicker than the second sacrificial layers SL2. In some embodiments, the first sacrificial layer SL1 may be thinner than the second sacrificial layers SL2. In certain embodiments, the bottommost one and the topmost one of the second sacrificial layers SL2 may be thicker than other second sacrificial layers SL2 disposed therebetween. In some embodiments, the insulating layers ILD may have the same thickness, or one or some of the insulating layers ILD may have a different thickness from each other or from other of the insulating layers ILD.

[0151] Referring to the Fig. 4A and Fig. 20, vertical holes H and DH may be formed to penetrate the thin layer structure 110. The vertical holes H and DH may expose an upper surface of the first sacrificial layer SL1.

[0152] A mask pattern MP may be formed on the thin film structure 110, and the thin film structure 110 may be anisotropically etched using the mask pattern MP as an etching mask to form the vertical holes H and DH. In the anisotropic etching process, the upper surface of the first sacrificial layer SL1 may be over-etched such that the first sacrificial layer SL1, which is exposed through the vertical holes H and DH, may be recessed by a predetermined depth. In some embodiments, a width of a lower portion of each of the vertical holes H and DH may be smaller than that of an upper portion of each of the vertical holes H and DH. In some embodiments, the vertical holes H and DH may be arranged in a matrix shape along the first and second directions D1 and D2 when viewed from a top view.In certain embodiments, the vertical holes H and DH forming two columns adjacent to each other and parallel to the first direction D1 may be arranged in a zigzag shape along the first direction D1 when viewed from a plan view.

[0153] In some embodiments, the vertical holes H and DH may comprise first and second vertical holes H and vertical dummy holes DH. The first and second vertical holes H may correspond to the first and second vertical channels VS1 and VS2 described with reference to Fig. 4A, and the vertical dummy holes DH may correspond to the vertical dummy channels DVS described with reference to Fig. 4A.

[0154] Referring to the Fig. 4A, Fig. 21 and Fig. 30, the first sacrificial layer SL1 exposed through the vertical holes H and DH may be laterally etched to form first recess regions HR1.

[0155] The first recess regions HR1 may be formed by isotropic etching of the first sacrificial layer SL1 using an etching recipe that has etch selectivity with respect to the second sacrificial layers SL2, the insulating layers ILD, and the substrate 10. Accordingly, the first recess regions HR1 may be connected to the vertical holes H and DH arranged along the first and second directions D1 and D2, and may have rounded sidewalls, as shown in Fig. 4A is illustrated.

[0156] When the first recess regions HR1 are formed, a portion of the first sacrificial layer SL1 may remain under the thin film structure 110 between the vertical holes H and DH, which are widely spaced from each other. The remaining portion of the first sacrificial layer SL1 may be defined as a first sacrificial structure SLP. The first sacrificial structure SLP may extend in the first direction D1 between the first recess regions HR1, which are adjacent to each other in the second direction D2. The first sacrificial structures SLP remaining under the thin film structure 110 may serve as supports that support the thin film structure 110.

[0157] In addition, a protective insulating layer PL may be formed between the thin layer structure 110 and the first sacrificial layer SL1, as shown in Fig. 30. The vertical holes H and DH may further penetrate the protective insulating layer PL. The protective insulating layer PL may prevent the lowermost insulating layer ILD of the thin film structure 110 from being etched during the formation of the first recess regions HR1.

[0158] Referring to the Fig. 4A, Fig. 22 and Fig. 31, a data storage layer DSL and a semiconductor layer SCL may be sequentially formed on inner surfaces of the first recessed areas HR1 and inner surfaces of the vertical holes H and DH. The data storage layer DSL and the semiconductor layer SCL may also be formed on the upper surface of the thin film structure 110.

[0159] The data storage layer DSL may be formed from a single layer or a plurality of thin layers. In some embodiments, the data storage layer DSL may include a barrier insulation layer BLK, a charge storage layer CIL, and a tunnel insulation layer TIL, which are sequentially stacked. The data storage layer DSL may be formed to have a substantially uniform thickness on the inner surfaces of the vertical holes H and DH and the inner surfaces of the first recess regions HR1. In other words, the data storage layer DSL may extend from the inner surfaces of the vertical holes H and DH to a lower surface of the thin layer structure 110 and a surface of the substrate 10.

[0160] The semiconductor layer SCL may be formed to have a substantially uniform thickness on the data storage layer DSL and may extend from the inner surfaces of the vertical holes H and DH to the lower surface of the thin film structure 110 and the surface of the substrate 10.

[0161] The semiconductor layer SCL and the data storage layer DSL may be formed using a CVD technique and / or an ALD technique. The semiconductor layer SCL may have a hollow tube or a macaroni shape that extends continuously through the vertical holes H and DH and the first recess region HR1. The semiconductor layer SCL may comprise silicon (Si), germanium (Ge), or a combination thereof. The semiconductor layer SCL may be doped with dopants or may be an intrinsic semiconductor that is not doped with dopants. The semiconductor layer may have a crystal structure that includes at least one of a single-crystalline structure, an amorphous structure, or a polycrystalline structure.

[0162] In some embodiments, a sum of thicknesses of the data storage layer DSL and the semiconductor layer SCL may be less than one-half of a thickness of the first sacrificial structure SLP. Accordingly, a gap region in the first recess region HR1 may be defined by the data storage layer DSL and the semiconductor layer SCL. In certain embodiments, the thickness of the data storage layer DSL may be less than one-half of a thickness of the first sacrificial structure SLP, and the semiconductor layer SCL may have a hollow tube shape in each of the vertical holes H and DH, but may completely fill the first recess region HR1.

[0163] Referring to the Fig. 4A, Fig. 23 and Fig. 32, after the formation of the semiconductor layer SCL, a filler insulation structure VI may be formed to fill an internal space surrounded by the semiconductor layer SCL, specifically in the vertical holes H and DH and the first recess region HR1. The data storage layer DSL and the semiconductor layer SCL on the upper surface of the thin film structure 110 may be removed by a planarization process, exposing the uppermost insulation layer ILD. Thus, a channel structure including vertical channels VS1, VS2, and DVS and a first horizontal channel HS1 may be formed. The vertical channels VS1, VS2, and DVS may be formed in the vertical holes H and DH, respectively, and the first horizontal channel HS1 may be formed under the thin film structure 110.

[0164] Next, conductive pads PAD may be formed on the vertical channels VS1 and VS2, and source plugs CPLG may be formed on the vertical dummy channels DVS. The conductive pads PAD and the source plugs CPLG may be dopant regions doped with dopants or may be formed of a conductive material. In some embodiments, lower surfaces of the conductive pads PAD and the source plugs CPLG may be higher than an upper surface of the uppermost one of the second sacrificial layers SL2. In some embodiments, as in Fig. 5, a vertical length of the source plug CPLG may be longer than that of the conductive pad PAD. In other words, the lower surface of the source plug CPLG may be lower than a lower surface of the uppermost one of the second sacrificial layers SL2. The methods for forming the conductive pads PAD and the source plug CPLG will be described in more detail later with reference to FIG. Fig. 36 to 40 are described.

[0165] In some embodiments, the uppermost insulating layer ILD and the uppermost second sacrificial layer SL2 may be patterned before or after the formation of the conductive pads PAD and the source plugs CPLG. Accordingly, second sacrificial structures, which are laterally spaced apart from each other, may be formed on the uppermost second sacrificial layer of the thin layer structure 110. The isolation insulating structure 115 of the Fig. 6 can be formed between the second sacrificial structures. The isolation structure 115 of the Fig. 6 can be connected to the data storage layer DSL, which surrounds the vertical dummy channel DVS in the first direction.

[0166] Subsequently, a capping insulating layer covering the conductive pads PAD and the source plugs CPLG may be formed on the thin layer structure 110. The capping insulating layer and the thin layer structure 110 may be patterned to form trenches T, each of which exposes the first sacrificial structure SLP between the channel structures adjacent to each other.

[0167] Forming the trenches T may include forming a mask pattern (not shown) defining planar positions of the trenches T on the capping insulating layer, and anisotropically etching the capping insulating layer and the thin film structure 110 using the mask pattern (not shown) as an etching mask.

[0168] The trenches T may be spaced apart from the vertical channels VS1, VS2, and DVS and may expose sidewalls of the insulating layers ILD and sidewalls of the second sacrificial layers SL2. Each of the trenches T may have a linear or rectangular shape extending in the first direction D1 in a plan view and may expose a top surface of the first sacrificial structure SLP in a cross-sectional view. When the trenches T are formed, the first sacrificial structures SLP may be recessed below the trenches T by a predetermined depth due to over-etching. In some embodiments, each of the trenches T may have an inclined sidewall.

[0169] Since the trenches T are formed, the thin film structure 110 may be divided into a plurality of mold structures 110m. In addition, a capping insulation structure 125 may be formed on each of the mold structures 110m. The capping insulation structures 125 may correspond to portions of the capping insulation layer. The mold structures 110m may have linear shapes extending in the first direction D1 and may be spaced from each other in the second direction D2. In addition, a portion of the first sacrificial structure SLP may be exposed through the trench T between the mold structures 110 that are adjacent to each other. Furthermore, since the trenches T are formed, a protective insulation structure PP may be formed on the lower surface of the lowermost insulation layer ILD of each of the mold structures 110m.

[0170] Referring to the Fig. 4A, Fig. 24 and Fig. 33, the first sacrificial structure SLP exposed through the trench T may be removed to form a second recess region HR2 exposing a portion of the data storage layer DSL.

[0171] The second recess region HR2 may be formed by isotropic etching of the first sacrificial structure SLP using an etching recipe having etch selectivity with respect to the second sacrificial structures SL2, the insulating layers ILD, and the substrate 10. The second recess region HR2 may expose a portion of the substrate 10. In addition, as shown in Fig. 33, the protective insulation structure PP prevents the lowermost insulation layer ILD from being etched during the formation of the second recess region HR2. Accordingly, a variation in the thickness of the lowermost insulation layer ILD during the formation of the second recess region HR2 can be reduced or minimized.

[0172] Referring to the Fig. 4A, Fig. 25 and Fig. 34, the portion of the data storage layer CSL exposed by the second cutout region HR2 may be removed to form a third cutout region HR3 exposing a portion of the first horizontal channel HS1.

[0173] The third recess region HR3 may be formed by isotropic etching of the data storage layer DSL using an etching recipe that has etch selectivity with respect to the second sacrificial layers SL2, the insulating layers ILD, and the substrate 10. For example, the process of forming the third recess region HR3 may include a process of isotropic etching of the barrier insulating layer BLK, a process of isotropic etching of the charge storage layer CIL, and a process of isotropic etching of the tunnel insulating layer TIL, which are performed sequentially.

[0174] Since the third recess region HR3 is formed, a residual data storage structure DSP may be formed between the first horizontal channel HS1 and the substrate 10, and a portion of the first horizontal channel HS1 and a portion of the data storage layer DS may be exposed through the third recess region HR3. The data storage layer DS may be arranged on the first horizontal channel HS1 and may be spaced apart from the residual data storage structure DSP. In some embodiments, below the mold structure 110m, a sidewall of the data storage layer DS may be recessed laterally from the sidewall of the first horizontal channel HS1.

[0175] In some embodiments, a portion of the protective insulation structure PP exposed by the second recess region HR2 may also be etched in the process of etching the portion of the data storage layer DSL. Accordingly, the third recess region HR3 may also expose a portion of the lower surface of the lowermost insulation layer ILD. In some embodiments, the protective insulation structure PP may be used as an etch stop layer during the formation of the third recess region HR3, and thus, it is possible to prevent the lower surface of the lowermost insulation layer ILD from being exposed.

[0176] Referring to the Fig. 4A, Fig. 26 and Fig. 35, a second horizontal channel HS2 may be formed in the third recess region HR3. The second horizontal channel HS2 may be in contact with the first horizontal channel HS1.

[0177] In some embodiments, a semiconductor layer may be deposited in the trench T and the third recess region HR3, and the semiconductor layer disposed in the trench T may be removed to form the second horizontal channel HS2. Here, the semiconductor layer for the second horizontal channel HS2 may be formed using a CVD technique or an ALD technique. The semiconductor layer for the second horizontal channel HS2 may be doped with dopants or may include an intrinsic semiconductor that is not doped with dopants. In some embodiments, the semiconductor layer for the second horizontal channel HS2 may be doped with dopants of the first conductivity type. Additionally, the semiconductor layer for the second horizontal channel HS2 may have a crystal structure that includes at least one of a single-crystalline structure, an amorphous structure, or a polycrystalline structure.The second horizontal channel HS2 may be in contact with the sidewall of the first horizontal channel HS1, the data storage layer DS, and the residual data storage structure disposed below the mold structure 110m. Additionally, the second horizontal channel HS2 may be in direct contact with the well dopant layer 11 formed in the substrate 10.

[0178] Referring to the Fig. 4A and Fig. 27, the second sacrificial layers SL2 exposed by the trenches T may be removed to form gate regions GR between the insulating layers ILD.

[0179] The gate regions GR can be formed by isotropic etching of the second sacrificial layers SL2 using an etching recipe that has etch selectivity with respect to the insulating layers ILD, the vertical channels VS1, VS2, and DVS, the data storage layer DS, and the second horizontal channel HS2. Here, the second sacrificial layers SL2 can be completely removed by the isotropic etching process. For example, in the case where the second sacrificial layers SL2 are silicon nitride layers and the insulating layers ILD are silicon oxide layers, the second sacrificial layers SL2 can be removed by the isotropic etching process using an etching solution containing phosphoric acid. In addition, the data storage layer DS can be used as an etch stop layer in the isotropic etching process for forming the gate regions GR.The gate regions GR may extend laterally from the trench T between the insulating layers ILD and may expose portions of a sidewall of the data storage layer DS or portions of sidewalls of the vertical channels VS1 and VS2. In other words, each of the gate regions GR may be defined or bounded by the sidewall of the data storage layer DS and the insulating layers ILD, which are vertically adjacent to each other.

[0180] Referring to the Fig. 4A and Fig. 28, a horizontal insulating layer may be formed on inner surfaces of the trenches T and inner surfaces of the gate regions GR. The horizontal insulating layer may have a substantially uniform thickness on the inner surface of the gate regions GR. The horizontal insulating layer may be formed from a single layer or a plurality of thin layers. In some embodiments, the horizontal insulating layer may be a portion of a data storage layer of a charge trap-type flash memory transistor.

[0181] Electrodes EL may be formed in each of the gate regions GR in which the horizontal insulating layer is formed. The electrodes EL may partially or completely fill the gate regions GR. In some embodiments, forming the electrodes EL may comprise sequentially depositing a barrier metal layer and a metal layer. For example, the barrier metal layer may comprise a metal nitride layer such as a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, and / or a tungsten nitride (WN) layer. For example, the metal layer may comprise at least one of metallic materials such as W, Al, Ti, Ta, Co, and / or Cu. The barrier metal layer and the metal layer arranged outside the gate regions GR may be removed to form the electrodes EL confined in the gate regions GR.After the formation of the electrodes EL, the horizontal insulating layer arranged outside the gate regions GR can be removed to form horizontal insulating structures HIL in the gate regions GR.

[0182] Since the electrodes EL are formed, first and second stacked structures ST1 and ST2 may be formed on the substrate 10. Each of the first and second stacked structures ST1 and ST2 may include the insulating layers ILD and the electrodes EL alternately and repeatedly stacked on the substrate 10. The first and second stacked structures ST1 and ST2 may extend in the first direction D1, and sidewalls of the first and second stacked structures ST1 and ST2 may be exposed through the trenches T. In addition, the second horizontal channel HS2 may be exposed between the first and second stacked structures ST1 and ST2, which are adjacent to each other.

[0183] A dopant region 13 may be formed in the second horizontal channel HS2 between the first and second stack structures ST1 and ST2. The dopant region 13 may be doped with dopants of the first conductivity type. Dopants of the same conductivity type as the well dopant layer 11 may be injected into the second horizontal channel HS2 to form the dopant region 13. In certain embodiments, the second horizontal channel HS2 may be doped with dopants during the formation of the second horizontal channel HS2. In such cases, the process of forming the dopant region 13 may be omitted.

[0184] Referring to the Fig. 4A and Fig. 29, a fill insulating layer 130 may be formed to fill the trench T between the first and second stack structures ST1 and ST2. The fill insulating layer 130 may be in contact with the second horizontal channel HS2 and may cover the first and second stack structures ST1 and ST2.

[0185] A common source line CSL extending in the first direction D1 may be formed on the fill insulating layer 130. The common source line CSL may be electrically connected to the vertical dummy channels DVS arranged in the first direction D1. The common source line CSL may be electrically connected to the source plugs CPLG arranged on the vertical dummy channels DVS through contact plugs CSP penetrating the fill insulating layer 130 and the cap insulating structure 125. The common source line CSL may be formed on the fill insulating layer 130 arranged on each of the first and second stack structures ST1 and ST2.

[0186] Below, as with reference to the Fig. 4A, Fig. 5 and Fig. 6, the first insulating layer 140 may be formed on the fill insulating layer 130, and the lower contact plugs LCP may be formed to penetrate the first insulating layer 140, the fill insulating layer 130, and the cap insulating structure 125. The lower contact plugs LCP may be connected to the vertical channels VS1 and VS2. Next, the first to fourth assist interconnections SBL1 to SBL4 may be formed on the first insulating layer 140. The second insulating layer 150 may be formed on the first insulating layer 140 and the assist interconnections SBL1 to SBL4, and the upper contact plugs UCP may be formed to penetrate the second insulating layer 150. The upper contact plugs UCP may be connected to the assist interconnections SBL1 to SBL4. The first and second bit lines BL1 and BL2 may be formed on the second insulating layer 150.

[0187] The Fig. 36 to 40 are cross-sectional views illustrating methods for forming a conductive pad and a source plug of a 3D semiconductor device according to some embodiments of the inventive concepts. Hereinafter, the description will be given of the same technical features as in the embodiment of Fig. 19 to 29 will be omitted or briefly mentioned for the purpose of convenience and expediency in explanation. Accordingly, processes for forming conductive pads and source plugs according to the present embodiment will be performed after the processes described with reference to Fig. 22 are described.

[0188] Referring to Fig. 36, the data storage layer DSL and the semiconductor layer SCL may have substantially uniform thicknesses and may continuously cover the inner surfaces of the vertical holes H, the inner surfaces of the vertical dummy holes DH, and the inner surface of the first recess region HR1. Here, the vertical holes H may correspond to the first and second vertical channels VS1 and VS2, which in Fig. 4A, and the vertical dummy holes DH may correspond to the vertical dummy channels DVS shown in Fig. 4A. The semiconductor layer SCL may have a hollow tube shape. After the formation of the semiconductor layer SCL, an insulating layer VIL may be formed on an entire upper surface of the substrate 10 to cover the internal space of the semiconductor layer SCL.

[0189] Referring to Fig. 37, a hard mask structure HMP having openings OP may be formed on the insulating layer VIL. Each of the openings OP may have a linear shape extending in the first direction D1 and may be formed on the vertical dummy holes DH (see the vertical dummy channels DVS of the Fig. 4A and Fig. 4B) arranged along the first direction D1. Next, the insulating layer VIL may be etched using the hard mask pattern HMP as an etching mask. In other words, portions of the insulating layer VIL filling the vertical dummy holes DH may be removed to form preliminary holes R that expose portions of the semiconductor layer SCL formed in the vertical dummy holes DH. Accordingly, upper surfaces of the insulating layer VIL exposed by the preliminary holes R may be lower than the bottom surface of the uppermost one of the sacrificial layers SL2. After the formation of the preliminary holes R, the hard mask pattern HMP may be removed to expose the upper surface of the insulating layer VIL.

[0190] Referring to Fig. 38, an anisotropic overlay etching process may be performed on the insulating layer VIL to form fine holes R1 exposing portions of the semiconductor layer SCL formed in the vertical holes H, and to form fine dummy holes R2 exposing portions of the semiconductor layer SCL formed in the vertical dummy holes DH. Since the fine holes R1 and R2 are formed, the filling insulating structure VI can be formed to fill the interior of the semiconductor layer SCL.

[0191] Since the preliminary holes are formed before the formation of the fill insulation structure VI, the upper surface of the fill insulation structure VI exposed by the fine dummy hole R2 may be lower than the upper surface of the fill insulation structure VI exposed by the fine hole R1. In other words, a vertical depth of the fine dummy hole R2 may be greater than that of the fine dummy hole R1. The upper surface of the fill insulation structure VI exposed by the fine hole R1 may be higher than the upper surface of the uppermost one of the second sacrificial layers SL2.

[0192] Referring to Fig. 39, a conductive layer CL may be formed on an entire upper surface of the substrate 10 to fill the fine holes R1 and the dummy fine holes R2. In some embodiments, the conductive layer CL may have the second conductivity type opposite to the first conductivity type of the well dopant layer 11. In some embodiments, the conductive layer CL may be formed of polysilicon doped with dopants of the second conductivity type or a metal.

[0193] Referring to the Fig. 4A and Fig.40, the conductive layer CL, the semiconductor layer SCL, and the data storage layer DSL may be sequentially etched until the upper surface of the thin film structure 110 is exposed. Accordingly, the vertical channels VS1 and VS2 may be formed in the vertical holes H, and the vertical dummy channels DVS may be formed in the vertical dummy holes DH. At the same time, the conductive pad PAD may be disposed on an upper end of each of the vertical channels VS1 and VS2, and the source plug CPLG may be formed on an upper end of each of the vertical dummy channels CVS. In some embodiments, the conductive pad PAD may include a first portion of the conductive layer CL and a first portion of the semiconductor layer SCL.The first portion of the conductive layer CL may fill the fine hole R1, and the first portion of the semiconductor layer SCL may be in contact with the first portion of the conductive layer CL. Similarly, the source plug CPLG may include a second portion of the conductive layer CL and a second portion of the semiconductor layer SCL. The second portion of the conductive layer CL may fill the dummy fine hole R2, and the second portion of the semiconductor layer SCL may be in contact with the second portion of the conductive layer CL. In some embodiments, the first and second portions of the semiconductor layer SCL may have the second conductivity type through an ion implantation process or a thermal diffusion process. In the thermal diffusion process, the dopants of the first conductivity type may be diffused from the conductive layer CL into the first and second portions of the semiconductor layer CSL.In certain embodiments, the semiconductor layer SCL formed by the pinholes R1 and the dummy pinholes R2 may be removed before the formation of the conductive layer CSL. In this case, the conductive pad may be formed from a portion of the conductive layer CL, and the source plug CPLG may be formed from another portion of the conductive layer CL.

[0194] According to some embodiments of the inventive concept, the vertical channels and the vertical dummy channels penetrating the stacked structure may be connected to the first horizontal channel to form a semiconductor layer extending continuously without an interface therein. Thus, a process of connecting the first horizontal channel to the vertical channels may be omitted. In addition, since the source plugs are formed on the vertical dummy channels, the vertical channels may be connected together with the source plugs through the first horizontal channel. Thus, a current flow may be generated through the vertical channels and the first horizontal channel, thereby electrically connecting the bit line to the source plugs.In addition, since the second horizontal channel is formed to be in contact with the sidewall of the second horizontal channel and the well dopant layer, electrical holes for the vertical channels may be provided through the first and second horizontal channels.

Claims

[1] Three-dimensional, 3D, semiconductor device comprising: a stack structure (ST1, ST2) extending in a first direction and having electrodes (EL) stacked vertically on a substrate (10); a channel structure (CHS) coupled to the electrodes (EL) to form a plurality of memory cells arranged three-dimensionally on the substrate (10), the channel structure (CHS) comprising: first vertical channels (VS1) and second vertical channels (VS2) penetrating the stack structure (ST1, ST2); and a first horizontal channel (HS1) which is below the stack structure (ST1, ST2) and which laterally connects the first vertical channels (VS1) and the second vertical channels (VS2), the first horizontal channel (HS1) having an upper horizontal section (HP1), a lower horizontal section (HP2) and wall sections (VP), one of the wall sections (VP) being connected between one end of the upper horizontal section (HP1) and one end of the lower horizontal section (HP2), and the other of the wall sections (VP) being connected between another end of the upper horizontal section (HP1) and another end of the lower horizontal section (HP2); a second horizontal channel (HS2) connected to a sidewall of the first horizontal channel (HS1) of the channel structure and a top surface of the substrate (10), the second horizontal channel (HS2) having a first conductivity type; conductive plugs located at upper ends of the second vertical channels (VS2), the conductive plugs having a second conductivity type; a conductive line extending in a first direction on the stack structure (ST1, ST2) and connected to the second vertical channels (VS2), the first direction being parallel to a top surface of the substrate; and a bit line (BL1, BL2) extending in a second direction perpendicular to the first direction on the conductive line, the bit line (BL1, BL2) being connected to the vertical channels (VS1, VS2), the second direction being parallel to a top surface of the substrate. [2] The 3D semiconductor device according to claim 1, wherein the stack structure (ST1, ST2), the first horizontal channel (HS1) and the second horizontal channel (HS2) extend parallel to each other along one direction. [3] The 3D semiconductor structure according to claim 1, wherein the first vertical channels (VS1) are arranged along the first direction and along the second direction which is perpendicular to the first direction, and wherein the first horizontal channel (HS1) is connected to the first vertical channels (VS1) arranged along the first direction and the first vertical channels (VS1) arranged along the second direction, and wherein the first and second directions are parallel to a top surface of the substrate. [4] The 3D semiconductor device according to claim 1, wherein the first horizontal channel (HS1) overlaps with the stack structure (ST1, ST2) when viewed in a plan view. [5] The 3D semiconductor device according to claim 1, wherein the first horizontal channel (HS1) has a rounded sidewall which is in contact with the second horizontal channel (HS2). [6] The 3D semiconductor device according to claim 1, wherein the first vertical channels (VS1), the second vertical channels (VS2) and the first horizontal channel (HS1) form a semiconductor layer extending continuously without an interface therein. [7] The 3D semiconductor device of claim 1, wherein the first horizontal channel (HS1) and the second horizontal channel (HS2) comprise a semiconductor material, and wherein an interface exists between the first horizontal channel (HS1) and the second horizontal channel (HS2). [8] A 3D semiconductor device according to claim 1, wherein the substrate (10) comprises a well dopant layer (11) doped with dopants of the first conductivity type, and wherein the second horizontal channel (HS2) is in direct contact with the well dopant layer (11). [9] The 3D semiconductor device of claim 1, wherein the substrate (10) comprises an insulating material, and wherein the second horizontal channel (HS2) is in direct contact with the substrate (10). [10] The 3D semiconductor device according to claim 1, further comprising: a data storage layer (DSL) which is between the stack structure (ST1, ST2) and the first vertical channels (VS1), and which is between the stack structure (ST1, ST2) and the second vertical channels (VS2); and a residual data storage structure (DSP) which is between the first horizontal channel (HS1) and the substrate (10). [11] The 3D semiconductor device according to claim 10, wherein the stack structure (ST1, ST2) further comprises: insulating layers (ILD) which are between the electrodes (EL), and wherein the data storage layer (DSL) extends between a lower surface of a lowermost insulating layer (ILD) of the stack structure (ST1, ST2) and the first horizontal channel (HS1). [12] The 3D semiconductor device of claim 10, wherein the second horizontal channel (HS2) is in contact with a portion of the data storage layer (DSL) and a portion of the residual data storage structure (DSP). [13] The 3D semiconductor device according to claim 1, wherein lower surfaces of the conductive plugs are lower than a lower surface of an uppermost one of the electrodes (EL). [14] The 3D semiconductor device according to claim 1, further comprising: a conductive pad (PAD) which is on an upper end of each of the vertical channels (VS1, VS2), wherein the conductive pad (PAD) has the second conductivity type, and wherein a lower surface of the conductive pad (PAD) is higher than an upper surface of a topmost one of the electrodes (EL). [15] A 3D semiconductor device according to claim 1, wherein an uppermost one of the electrodes (EL) comprises: a first strand selection electrode (SEL1) and a second strand selection electrode (SEL2) which are laterally spaced from each other, and wherein the second vertical channels (VS2) are between the first strand selection electrode (SEL1) and the second strand selection electrode (SEL2). [16] Three-dimensional, 3D, semiconductor device comprising: a stack structure (ST1, ST2) extending in a first direction and which has a plurality of electrodes (EL) stacked vertically on a substrate (10); first vertical channels (VS1) and second vertical channels (VS2) penetrating the stack structure (ST1, ST2); a first horizontal channel (HS1) extending in the first direction under the stack structure (ST1, ST2) and connecting the first vertical channels (VS1) and the second vertical channels (VS2), the first horizontal channel (HS1) having an upper horizontal section (HP1), a lower horizontal section (HP2), and wall sections (VP), one of the wall sections (VP) being connected between one end of the upper horizontal section (HP1) and one end of the lower horizontal section (HP2), and the other of the wall sections (VP) being connected between another end of the upper horizontal section (HP1) and another end of the lower horizontal section (HP2); a second horizontal channel (HS2) extending in the first direction and contacting both side walls of the first horizontal channel (HS1) and an upper surface of the substrate (10); conductive plugs located at upper ends of the second vertical channel (VS2), the conductive plugs having a second conductivity type different from the first conductivity type; a conductive line extending in a first direction on the stack structure (ST1, ST2) and connected to the second vertical channels (VS2), the first direction being parallel to a top surface of the substrate; and a bit line (BL1, BL2) extending in a second direction perpendicular to the first direction on the conductive line, the bit line (BL1, BL2) being connected to the vertical channels (VS1, VS2), the second direction being parallel to a top surface of the substrate. [17] The 3D semiconductor device according to claim 16, wherein the first vertical channels (VS1) are arranged along the first direction and along the second direction which is perpendicular to the first direction, wherein the first horizontal channel (HS1) is connected to the first vertical channels (VS1) arranged along the first direction and the first vertical channels (VS1) arranged along the second direction, and wherein the first and second directions are parallel to a top surface of the substrate. [18] A 3D semiconductor device according to claim 16, wherein the vertical channels, the second vertical channels (VS2) and the first horizontal channel (HS1) form a semiconductor layer which extends continuously without an interface therein, and wherein an interface is present between the first horizontal channel (HS1) and the second horizontal channel (HS2). [19] A 3D semiconductor device according to claim 16, further comprising: Source plugs (CPLG), which are located at the upper ends of the second vertical channels (VS2), wherein the source plugs (CPLG) have a conductivity type opposite to a conductivity type of the second horizontal channel (HS2), wherein lower surfaces of the source plugs (CPLG) are lower than a lower surface of a top one of the electrodes (EL). [20] The 3D semiconductor device of claim 16, further comprising: a data storage layer (DSL) which is between the stack structure (ST1, ST2) and the first vertical channels (VS1), and which is between the stack structure (ST1, ST2) and the second vertical channels (VS2); and a residual data storage structure (DSP) which is between the first horizontal channel (HS1) and the substrate (10), wherein the stack structure (ST1, ST2) further comprises: insulating layers (ILD) which are between the electrodes (EL), and wherein the data storage layer (DSL) extends between a lower surface of a lowermost insulation layer (ILD) of the stack structure (ST1, ST2) and the first horizontal channel (HS1), wherein the second horizontal channel (HS2) is in contact with a portion of the data storage layer (DSL) and a portion of the residual data storage structure (DSP). [21] The 3D semiconductor device of claim 16, further comprising: a conductive pad (PAD) which is on an upper end of each of the vertical channels (VS1, VS2), wherein the conductive pad (PAD) has the second conductivity type, and wherein a lower surface of the conductive pad (PAD) is higher than an upper surface of a topmost one of the electrodes (EL).

Images