FINFET STRUCTURES AND METHODS FOR THEIR MANUFACTURING

Abstract

Procedure with the following steps: Creating a first semiconductor fin (24') that protrudes from a substrate (20); Manufacturing a gate stack (80) over the first semiconductor fin (24'), wherein manufacturing the gate stack comprises the following: Deposition of a dielectric gate layer (54, 56) over the first semiconductor fin (24'), Deposition of a first seed layer (72) over the dielectric gate layer, Deposition of a second seed layer (74) over the first seed layer (72), wherein the second seed layer has a different structure than the first seed layer, and Deposition of a conductive layer (76) over the second seed layer (74), wherein the first seed layer (72), the second seed layer and the conductive layer have the same conductive material, wherein the first seed layer (72) is the same material as the second seed layer (74); and Creating source and drain areas (42) adjacent to the gate stack.

Description

background

[0001] Semiconductor devices are used in a large number of electronic devices, such as computers, mobile phones, and the like. Semiconductor devices include integrated circuits, which are fabricated on semiconductor wafers by depositing many types of thin material layers onto the wafers and structuring these thin layers into integrated circuits. Integrated circuits include field-effect transistors (FETs), such as metal-oxide-semiconductor (MOS) transistors.

[0002] One goal of the semiconductor industry is to continue reducing the size and increasing the speed of individual FETs. To achieve this goal, finned field-effect transistors (FinFETs) or multi-gate transistors are being researched and implemented. However, with this new device structure and the ongoing miniaturization of FinFETs, new problems are emerging.

[0003] Semiconductor devices with amorphous and crystalline structural layers are known from US 2015 / 0061042A1 and US 6306743B1. US 2003 / 0170942A1 discloses a gate electrode structure comprising a tungsten silicide layer, a tungsten nitride layer, and a tungsten layer. Brief description of the drawings

[0004] Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. The Fig. Figures 1 to 18 show sectional views and perspective representations of intermediate stages in the manufacture of a fin field-effect transistor (FinFET) according to some embodiments. Detailed description

[0005] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples. For instance, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and it may also include embodiments in which additional elements can be formed between the first and second elements such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0006] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the component in use or operation beyond the orientation shown in the figures. The device can be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0007] Finned field-effect transistors (FinFETs) and methods for their fabrication according to various embodiments are provided. The intermediate stages of the FinFET fabrication according to some embodiments are explained. In particular, methods for fabricating a multilayer seed layer as part of the fabrication of a gate stack are described. The multilayer seed layer can comprise a crystalline layer and an amorphous layer. While method implementations are discussed here in a specific order, various other method implementations can be carried out in any logical sequence and may include fewer or more steps than are mentioned here. Similar reference symbols are used in all the different representations and explanatory embodiments to denote similar elements.In the illustrated exemplary embodiments, the fabrication of a FinFET is used as an example to explain the embodiments of the present invention. The principle of the present invention can also be applied to planar transistors.

[0008] Fig. Figure 1 shows a perspective view of an initial structure. The initial structure includes a wafer 100, which in turn has a substrate 20. The substrate 20 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 20 can be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material deposited on an insulating layer. The insulating layer can be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, usually a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, can also be used.In some embodiments, the semiconductor material of the substrate 20 may comprise: silicon; germanium; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Separation regions 22, such as STI regions (STI: shallow trench isolation), may be fabricated to extend into the substrate 20 from a top surface, wherein the top surface of the substrate 20 is a major face 100A of the wafer 100. The portions of the substrate 20 between adjacent STI regions 22 are referred to as semiconductor strips 24. In some embodiments, the top surfaces of the semiconductor strips 24 and the top surfaces of the STI areas 22 can be essentially at the same level.

[0009] The STI regions 22 can be an oxide, such as silicon dioxide, a nitride, or the like, or a combination thereof. The STI regions 22 can be produced by the following processes: high-density plasma chemical vapor deposition (HDPCVD), flowable continuous vapor deposition (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert to another material, such as an oxide), spin deposition, conformal oxide process, or the like, or a combination thereof. In other embodiments, other insulating materials deposited by a suitable process can be used. The STI regions 22 can have an oxide coating (not shown). The oxide coating can consist of a thermal oxide produced by thermal oxidation of a surface layer of the substrate 20.The oxide coating can also be a deposited silicon oxide layer, produced, for example, by atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI areas 22 can also have a dielectric material over the oxide coating, which can be deposited by flowable chemical vapor deposition (FCVD), spin deposition, or similar processes.

[0010] In Fig. 2. The STI regions 22 are recessed so that upper parts of the semiconductor strips 24 project beyond the top surfaces of the STI regions 22, forming projecting fins 24'. The etching can be carried out using a dry etching process with HF3 and NH3 as etching gases. A plasma can be generated during the etching process. Argon can also be used. In alternative embodiments of the present invention, the recession of the STI regions 22 is carried out using a wet etching process. The etching chemical can, for example, be dilute HF.

[0011] The procedure, which refers to the Fig. 1 and Fig. The representation described in Figure 2 is only one example of how the semiconductor strips 24 and the projecting fins 24' can be fabricated. In some embodiments, a dielectric layer can be fabricated over a top surface of the substrate 20; trenches can be etched through the dielectric layer; homoepitaxial structures can be epitaxially grown in the trenches; and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer, forming projecting fins. In some embodiments, heteroepitaxial structures can be used for the semiconductor strips 24. For example, the semiconductor strips 24 can be in Fig. 1 can be left out, and a material different from that of the semiconductor strip 24 can be epitaxially grown in its place.

[0012] In Fig. In embodiment 3, a dummy gate stack 30 is produced on the top surfaces and side walls of the projecting fins 24'. The dummy gate stack 30 can comprise a gate dielectric 32 and a dummy gate electrode 34 above the dummy gate dielectric 32. The dummy gate dielectric 32 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown by suitable methods. The dummy gate electrode 34 can comprise a conductive material, such as polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, metals, or the like. In one embodiment, amorphous silicon is deposited and recrystallized to produce polysilicon.The dummy gate electrode 34 can be deposited by physical vapor deposition (PVD), continuous vapor deposition (CVD), sputtering, or other methods known and used in the field of conductive material deposition. The dummy gate electrode 34 can be made of materials that exhibit high etch selectivity by etching interfaces. In some cases, the dummy gate electrode 34 can be deposited over the dummy gate dielectric 32 and then planarized, for example, by chemical-mechanical polishing (CMP). The dummy gate stack 30 can also have one or more hard mask layers 36 over the dummy gate electrode 34. The hard mask layer 36 can be made of silicon nitride (SiN), silicon oxide nitride (SiON), silicon carbonitride (SiCN), or the like. The dummy gate stack 30 can pass over one or more of the protruding fins 24' and / or STI areas 22.The dummy gate stack 30 can also have a longitudinal direction that is essentially perpendicular to the longitudinal direction of the projecting fins 24'.

[0013] Then, gate spacers 38 are manufactured on the side walls of the dummy gate stack 30. In some embodiments of the present invention, the gate spacers 38 consist of a dielectric material, such as silicon carboxide nitride (SiCN), silicon nitride, or the like, and they can have a single-layer structure or a multi-layer structure with a plurality of dielectric layers.

[0014] Then an etching step (referred to below as the source / drain recess) is performed to etch the portions of the protruding fins 24' that are not covered by the dummy gate stack 30 and the gate spacers 38, so that the in Fig. The structure shown in Figure 4 is formed. The recess can be anisotropic, thus protecting the portions of the fins 24' located directly beneath the dummy gate stack 30 and the gate spacers 38, preventing etching. In some embodiments, the top surfaces 24A of the recessed semiconductor strips 24 can be lower than the top surfaces 22A of the STI areas 22. Accordingly, recesses 40 are formed between the STI areas 22. The recesses 40 are located on opposite sides of the dummy gate stack 30.

[0015] Then, epitaxial regions 42 (source / drain regions) are produced by selectively growing a semiconductor material in the recesses 40, so that the structure of Fig. 5. In some embodiments, several adjacent epitaxial regions 42 can fuse together, resulting in a fused epitaxial structure. In some embodiments, the epitaxial regions 42 consist of silicon germanium or silicon. Depending on whether the resulting FinFET is a p-FinFET or an n-FinFET, a p- or an n-type dopant can be added in situ during epitaxy. For example, if the resulting FinFET is a p-FinFET, the epitaxial regions 42 can consist of SiGe, SiGeB, Ge, GeSn, or the like. In some cases, the epitaxial regions 42 of an n-FinFET can consist of silicon, SiC, SiCP, SiP, or the like. In alternative embodiments of the present invention, the epitaxial regions comprise 42 III-V compound semiconductors, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof or multiple layers thereof.After the recesses 40 have been filled with the epitaxial areas 42, the epitaxial areas 42 extend horizontally through further epitaxial development, and chamfers may be formed.

[0016] After the epitaxy step, the epitaxy regions 42 can be further implanted with a p- or n-type dopant to create source and drain regions, which are also designated by reference symbol 30. In alternative embodiments of the present invention, the implantation step is omitted because the epitaxy regions 42 are doped in situ with the p- or n-type dopant during epitaxy. The epitaxy regions 42 have lower parts 42A, which are produced in the STI regions 22, and upper parts 42B, which are produced over the upper surfaces 22A of the STI regions 22. The lower parts 42A, whose side walls are defined by the shapes of the recesses 40 ( Fig. 4) can be formed, can have (essentially) straight edges, which can also be essentially vertical edges, which can be essentially perpendicular to the main surfaces (such as a bottom surface 20B) of the substrate 20.

[0017] Fig. Figure 6 shows a perspective view of the structure after the fabrication of an interlayer dielectric (ILD) 46. In some embodiments of the present invention, a buffer oxide layer (not shown) and a contact etch stop layer (CESL; not shown) are fabricated on the source and drain regions 42 prior to the fabrication of the ILD 46. The buffer oxide layer can consist of silicon oxide, and the CESL can consist of silicon nitride, silicon carbonitride, or the like. The buffer oxide layer and the CESL can be fabricated by a conformal deposition method, such as atomic layer deposition (ALD). The ILD 46 can comprise a dielectric material that is deposited, for example, by FCVD, spin coating, CVD, plasma-enhanced chemical vapor deposition (PECVD), or other deposition methods.The ILD 46 can also be made of phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), tetraethyl orthosilicate (TEOS) oxide, or the like. A chemical-mechanical polishing (CMP) process can be performed to bring the top surfaces of the ILD 46, the dummy gate stack 30, and the gate spacers 38 to the same level.

[0018] In a subsequent step, parts 46A of the ILD 46 are removed to create contact openings. Then, source / drain silicide areas 48 ( Fig. 7A) on the surfaces of the epitaxial regions 42. The manufacturing process includes depositing a metal layer into the contact openings and performing an anneal to cause the metal layer to react with the exposed surface portions of the epitaxial regions 42, forming the silicide regions 48. In some embodiments, the unreacted portions of the metal layer are removed. In alternative embodiments, the unreacted portions of the metal layer are not removed. Then, a conductive material, such as tungsten, is filled into the contact openings to produce contact pins 50, as shown in Fig. 7A is shown.

[0019] A sectional view of the in Fig. The structure shown in 7A is in Fig. 7B shows the section view obtained from the vertical plane that defines line A - A of Fig. 7A contains. Then the dummy gate stack 30 with the hard mask layer 36, the dummy gate electrode 34 and the dummy gate dielectric 32 is replaced by a metal gate and a replacement gate dielectric, as shown in the Fig. shown in sections 8 to 18. The sectional views shown in the Fig. The numbers 8 to 18 shown are obtained from the same vertical plane, which is the line A - A of Fig. 7A contains. In the Fig. Figures 8 to 18 show the top surfaces 22A of the STI areas 22 as a dotted line for reference, and the semiconductor fins 24' in the channel area extend over the top surfaces 22A.

[0020] Then the hard mask layer 36, the dummy gate electrode 34 and the dummy gate dielectric 32 of the dummy gate stack 30, which are in the Fig. 7A and Fig. 7B are shown, removed, so that an opening 47 is created, which is in Fig. Figure 8 shows that the top surfaces and side walls of the projecting fins 24' are exposed at the opening 47. In some embodiments, the dummy gate stack 30 is removed by an anisotropic dry etching process. The etching process can, for example, be a dry etching process using reactive gases that selectively etch the dummy gate stack 30 without etching the ILD 46 or the gate spacers 38. In some cases, the dummy gate dielectric 32 can be used as an etch stop layer when the dummy gate electrode 34 is etched.

[0021] Then in Fig. 9 a gate dielectric 58 is produced which extends into the opening 47. In some embodiments, the gate dielectric 58 comprises more than one dielectric layer. As an example, the gate dielectric 58 which extends into the Fig. As shown in Figures 9 to 18, an interfacial layer (IL) 54 forms a lower part. The IL 54 can be an oxide layer, such as a silicon oxide layer, which can be produced by thermal oxidation of the protruding fins 24', chemical oxidation, or a deposition process. In some cases, the IL 54 can be a silicon nitride layer, and in some cases, the IL 54 can comprise one or more layers of silicon oxide, silicon nitride, or another material. The gate dielectric 58 can also include a high-k dielectric layer 56 produced above the IL 54. The high-k dielectric layer 56 can be a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or combinations thereof. The dielectric constant (k-value) of the dielectric high-k material is higher than 3.9 and can be higher than about 7.0, and in some cases can be 21.0 or higher.The dielectric high-k layer 56 is arranged above and can contact the IL 54. The dielectric high-k layer 56 is fabricated as a conformal layer and extends onto the sidewalls of the projecting fins 24' and the top and sidewalls of the gate spacers 38. In some embodiments, the fabrication methods for the dielectric layer 56 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like.

[0022] In Fig. In Figure 10, a capping layer 62 is fabricated by deposition. The deposition can be performed using a conformal deposition method, such as ALD or CVD. In some embodiments, the thickness of the capping layer 62 can be approximately 1 nm to approximately 3 nm (approximately 10 Å to approximately 30 Å). The capping layer 62 extends into the opening 47, and some portions of the capping layer 62 may extend over the ILD 46. The capping layer 62 comprises at least one layer and may include a plurality of layers made of different materials. In some cases, the specific materials for the layers in the capping layer 62 can be selected depending on whether the respective FinFET is an n-FinFET or a p-FinFET. The capping layer 62 can have one or more materials, such as TiAl, TiN, TiAlN, silicon-doped TiN (TiSiN), TaN or another material.

[0023] After the deposition of the capping layer 62, a sacrificial layer 64 is produced to fill the remaining portions of the opening 47. In some embodiments, the sacrificial layer 64 consists of a photoresist. In alternative embodiments, the sacrificial layer 64 consists of a different material than the materials of the underlying dielectric layer 56 or the capping layer 62. The sacrificial layer 64 can, for example, consist of silicon oxide, silicon nitride, silicon carbide, or the like. The sacrificial layer 64 can have a substantially planar top surface, which can be achieved by spin coating if the sacrificial layer 64 consists of a photoresist. In some cases, planarization, such as CMP, is performed.

[0024] Fig. Figure 11 shows the back-etching of the sacrificial layer 64, which is represented by arrows 67. The back-etching can be dry etching and / or wet etching and can be isotropic or anisotropic. In some embodiments, the back-etching is carried out using an etchant that preferably attacks the sacrificial layer 64 and the capping layer 62 above the dielectric high-k layer 56.

[0025] Fig. Figure 11 shows an intermediate step of the etching process, in which the sacrificial layer 64 is etched back, thereby exposing the capping layer 62. As in Fig. As shown in Figure 12, the back-etching process then continues, etching both the sacrificial layer 64 and the capping layer 62. This exposes the dielectric high-k layer 56. In some embodiments, the dielectric high-k layer 56 is used as an etch stop layer, and the exposed horizontal portions of the dielectric high-k layer 56 are not etched or are only minimally etched. The dielectric high-k layer 56 can thus protect the underlying structure with the gate spacers 38, the ILD 46, and the metal contact pins 50.

[0026] Fig. Figure 13 shows the resulting structure after completion of the back-etching. Since the etchant attacks both the sacrificial layer 64 and the capping layer 62 during back-etching, the top surfaces of the sacrificial layer 64 and the capping layer 62 are sunk. It is clear that the etch rate of the sacrificial layer 64 can differ from that of the capping layer 62, which results in the top surface of the remaining sacrificial layer 64 being higher or lower than the top edges of the remaining capping layer 62. In some cases, the height H1 of the remaining capping layer 62 can be in the range of about 4.5 nm to about 40 nm (about 45 Å to about 400 Å).

[0027] After the etching process is complete, the remaining part of the sacrificial layer 64 is removed, for example, by a wet etching process or a peeling process, leaving a residual opening 47. A working layer 66 can then be produced in the residual opening 47, as shown in Fig. Figure 14 shows that the work function layer 66 can be a material suitable for the conductivity type of the respective FinFET, and its position in the metal gate can influence or determine the work function of the respective FinFET. For example, if the FinFET is an n-type FinFET, the work function metal can have a relatively low work function, and if the FinFET is a p-type FinFET, the work function metal can have a relatively high work function. In some embodiments, the work function layer 66 can be TiAl if the FinFET is an n-type FinFET, and it can be TiN if the FinFET is a p-type FinFET. In other embodiments, the work function layer 66 can be made of materials other than TiAl or TiN, such as Ti, TiAlN, TaC, TaCN, TaSiN, TaN, combinations thereof, or another material.In some embodiments, the exit working layer 66 comprises several layers of different materials. The exit working layer 66 can be produced by physical vapor deposition, ALD, CVD, or the like. In some cases, the exit working layer 66 can have a thickness of approximately 1.5 nm (15 Å) to approximately 40 nm (400 Å), e.g., approximately 3.5 nm (35 Å).

[0028] Then a barrier layer 68 can be created above the exit working layer 66, as also described in Fig. Figure 14 shows the barrier layer 68 being a material such as Ti, TiAl, TiN, TiAlN, TaAlN, TaN, a combination thereof, or another material. In some cases, the barrier layer 68 may be a layer of TiN with a thickness of about 0.5 nm (5 Å) to about 20 nm (200 Å), e.g., about 1.5 nm (15 Å). In some embodiments, the barrier layer 68 has several layers of different materials. The barrier layer 68 may be produced by physical vapor deposition, ALD, CVD, or the like.

[0029] A seed layer 70 is then produced over the barrier layer 68. The seed layer 70 can provide an improved interface between the barrier layer 68 and a subsequently deposited conductive material, such as a solid metal 76. The seed layer 70 can, for example, provide nucleation sites for the deposition of the solid metal 76. In some embodiments, the seed layer 70 has multiple layers. As an illustrative example, Figure 1 shows... Fig. 15 the seed layer 70 comprising a first sublayer 72 and a second sublayer 74. The first sublayer 72 can be the same material as the second sublayer 74, which can be a conductive material such as W, Cu, or Al, or another conductive material, or a combination thereof. In some embodiments, the first sublayer 72 can be the same material as the second sublayer 74, but have a different structure. For example, the first sublayer 72 or the second sublayer 74 can have an amorphous structure, and the other can have a crystalline structure.

[0030] After the seed layer 70 is deposited, the solid metal 76 is deposited in such a way that it fills the opening 47, as shown in Fig. Figure 16 shows that the solid metal 76 can be W, Cu, Al, or another conductive material, or a combination thereof. In some embodiments, the solid metal 76 can be deposited by CVD, ALD, or another method. For example, the solid metal 76 can be W and can be prepared using precursor materials such as a combination of B₂H₆ and WF₆, or other compounds.

[0031] In some embodiments, both sublayers 72 and 74 of the seed layer 70 can be W, and the solid metal 76 can also be W. In some embodiments, the first sublayer 72 is produced as crystalline W, and the second sublayer 74 is produced as amorphous W. The first sublayer 72 can be produced as crystalline W, for example, by PVD, CVD, ALD, or by another method. In some cases, the first sublayer 72 can be produced as crystalline W using a fluorine-free precursor material, such as WCl5. In other embodiments, a different precursor material or a combination of precursor materials can be used, such as other forms of WCl5. x , or other materials. In some cases, the first sublayer 72 can have a thickness of about 1 nm (10 Å) to about 5 nm (50 Å), e.g., about 3 nm (30 Å), as crystalline W.

[0032] The second sublayer 74 can be produced as amorphous W, for example by CVD, ALD, or another method. In some cases, the second sublayer 74 can be produced as amorphous W using precursor materials, such as a combination of B₂H₆ and WF₆, but in other embodiments, other precursor materials can be used. In some cases, the second sublayer 74 as amorphous W can have a thickness of about 1 nm (10 Å) to about 5 nm (50 Å), e.g., about 2 nm (20 Å). In some embodiments, the seed layer 70 can consist of three or more layers of alternating crystalline and amorphous W sublayers. In some cases, the seed layer 70, which consists of sublayers of crystalline and amorphous W, can have a thickness of about 3 nm (30 Å) to about 6 nm (60 Å). B. about 5 nm (50 Å).

[0033] In some cases, the first sublayer 72 of crystalline W can prevent fluorine (F) from penetrating into underlying layers (e.g., the barrier layer 68, the exit work layer 66, the dielectric high-k layer 56, or other layers that may be present). Fluorine may originate, for example, from one or more deposits of amorphous W (e.g., from the second sublayer 74 or the bulk metal 76), and crystalline W can block all or some of the fluorine. In some cases, a seed layer consisting of both a sublayer of crystalline W and a sublayer of amorphous W can block more F than a seed layer consisting of only crystalline W or only amorphous W. In some cases, using both a sublayer of crystalline W and a sublayer of amorphous W can reduce the concentration of F to less than about 1%.

[0034] In some cases, the presence of F can lead to a change in the voltage limit (Vt). Thus, by using both a sublayer of crystalline W and a sublayer of amorphous W as described, the Vt change due to F can be reduced. By reducing the Vt change due to F, more process options can be available for adjusting Vt. In some embodiments, some FinFETs on a wafer can be fabricated using both a sublayer of crystalline W and a sublayer of amorphous W, and other FinFETs on a wafer can be fabricated using either a sublayer of crystalline W or a sublayer of amorphous W. This allows the FinFETs with only one sublayer to have a greater Vt change than the FinFETs with both sublayers.In this way, the Vt of specific FinFETs on a wafer can be adjusted or set by changing the composition of the seed layer 70. Other parameters of the seed layer 70, such as the thickness of each sublayer, the number of sublayers, the process or precursors used to fabricate each sublayer, or other parameters, can also be adjusted to change the Vt.

[0035] Then a planarization process (such as CMP) is performed to remove portions of the dielectric high-k layer 56, the exit work layer 66, the barrier layer 68, the seed layer 70, and the solid metal 76. Horizontal portions of the dielectric high-k layer 56 above the ILD 46 are also removed. The remaining portions of layers 56, 62, 66, 68, 70, and 76 together form a replacement gate stack 80. The remaining portions of layers 56, 62, 66, 68, 70, and 76 each have a bottom portion and sidewall portions that are arranged above and connected to the bottom portion. As in Fig. As shown in Figure 17, layers 66, 68, 70, and 76 are then recessed, and the corresponding recess is filled with a hard mask 82, which is a dielectric hard mask made of silicon nitride, silicon oxide nitride, silicon oxide carbide, or the like. The hard mask 82 is also planarized so that its top surface is coplanar with the top surface of the ILD 46. In some embodiments, the seed layer 70 and / or the solid metal 76 of the replacement gate stack 80 have smaller lateral widths near the bottom of the replacement gate stack 80 and larger lateral widths near the top of the replacement gate stack 80, as shown in Figure 17. Fig. Figure 17 shows that in some cases the seed layer 70 and the solid metal 76 can form a conductive gate structure, and an upper lateral cross-section of the conductive gate structure can have a smaller area than a lower lateral cross-section of the conductive gate structure. In some cases, the seed layer 70 and / or the solid metal 76 can have a funnel shape.

[0036] In the illustrated embodiments, source / drain contact pins 50 are manufactured before the replacement gate stack 80 is produced. In alternative embodiments of the present invention, the source / drain contact pins 50 are manufactured after the replacement gate stack 80 has been produced.

[0037] In Fig. In 18, an etch stop layer 88 is fabricated over the replacement gate stack 80. The etch stop layer 88 consists of a dielectric material that may include silicon carbide, silicon nitride, silicon oxide nitride, or the like. An ILD 84 is fabricated over the etch stop layer 88, and contact pins 86 are fabricated in the ILD 84. The fabrication process may include creating contact pin openings in the ILD 84 to expose the replacement gate stack 80 and the source / drain contact pins 50, and filling the contact pin openings with a conductive material to fabricate contact pins 86. The hard mask 82 is also shown in the plane ( Fig. 17) removed so that the gate contact pin 86 extends into the recess left by the removed hard mask 82.

[0038] The embodiments of the present invention have several advantages. For example, by using a seed layer that has both crystalline and amorphous sublayers, the amount of fluorine present on or near the gate dielectric can be reduced, thereby minimizing Vt changes due to the presence of fluorine. This allows for greater flexibility in device design. The crystalline and amorphous source / drain layers described here can also be used in transistors other than FinFETs, such as planar MOSFETs, or in other types of transistors.

[0039] In some embodiments of the present invention, a method comprises fabricating a first semiconductor fin projecting from a substrate and fabricating a gate stack over the first semiconductor fin. Fabricating the gate stack comprises the following steps: depositing a dielectric gate layer over the first semiconductor fin; depositing a first seed layer over the dielectric gate layer; depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer; and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer comprise the same conductive material. The method further comprises fabricating source and drain regions adjacent to the gate stack.

[0040] In some embodiments of the present invention, a method comprises the following steps: fabricating a dummy gate stack on a semiconductor region; fabricating gate spacers on sidewalls of the dummy gate stack; removing the dummy gate stack to create an opening; and fabricating a dielectric gate layer extending into the opening. The method further comprises fabricating a seed layer over the dielectric gate layer extending into the opening, wherein the fabrication of the seed layer comprises depositing a first seed sublayer by a first deposition process and depositing a second seed sublayer over the first seed sublayer by a second deposition process. The method further comprises filling the remaining opening with a conductive material.

[0041] In some embodiments of the present invention, a device has a gate stack arranged over a semiconductor channel region. The gate stack comprises: a dielectric gate material arranged over the semiconductor channel region; a seed layer arranged over the dielectric gate material, the seed layer comprising a plurality of sublayers, wherein at least one sublayer is crystalline and at least one sublayer is amorphous; and a conductive material arranged over the seed layer. The device also has source / drain regions adjacent to the gate stack and on opposite sides of the gate stack.

Claims

[1] Procedure with the following steps: Creating a first semiconductor fin (24') that protrudes from a substrate (20); Manufacturing a gate stack (80) over the first semiconductor fin (24'), wherein manufacturing the gate stack comprises the following: Deposition of a dielectric gate layer (54, 56) over the first semiconductor fin (24'), Deposition of a first seed layer (72) over the dielectric gate layer, Deposition of a second seed layer (74) over the first seed layer (72), wherein the second seed layer has a different structure than the first seed layer, and Deposition of a conductive layer (76) over the second seed layer (74), wherein the first seed layer (72), the second seed layer and the conductive layer have the same conductive material, wherein the first seed layer (72) is the same material as the second seed layer (74); and Creating source and drain areas (42) adjacent to the gate stack. [2] Method according to claim 1, wherein the first seed layer (72) has a crystalline structure and the second seed layer (74) has an amorphous structure. [3] Method according to claim 1 or 2, wherein the seed layer (70) has a thickness between 3 nm and 6 nm. [4] Method according to any of the preceding claims, wherein the production of the gate stack comprises: Deposition of a capping layer (62) over the dielectric gate layer (54, 56); and Etching back the capping layer (62), wherein remaining parts of the capping layer have edges that are lower than a top surface of the dielectric gate layer (H1). [5] Method according to claim 4, wherein the production of the gate stack comprises: Deposition of an exit work layer (66) over the capping layer (62) and the dielectric gate layer (54, 56); and Separation of a barrier layer (68) above the exit working layer (66). [6] Method according to any of the preceding claims, wherein the first seed layer (72) is deposited by a first deposition process and the second seed layer (74) is deposited by a second deposition process which is different from the first deposition process. [7] Procedure with the following steps: Manufacturing a dummy gate stack (30) on a semiconductor area; Manufacturing gate spacers (38) on side walls of the dummy gate stack; Removing the dummy gate stack (30) to create an opening (47); Creating a dielectric gate layer (58) that extends into the opening; Forming a seed layer (70) over the dielectric gate layer (54, 56) extending into the opening, wherein the formation of the seed layer comprises the following: Deposition of a first seed sublayer (72) by a first deposition process, and Deposition of a second seed sublayer (74) over the first seed sublayer using a second deposition process, wherein the first seed sublayer (72) is the same material as the second seed sublayer (74), wherein the second seed sublayer (74) has a different structure than the first seed sublayer (72); and Filling the remaining opening with a conductive material (76). [8] Method according to claim 7, wherein in the first deposition process a crystalline material (72) is deposited and in the second deposition process an amorphous material (74) is deposited. [9] Method according to claim 7 or 8, wherein the deposition of the first seed sublayer (72) by the first deposition process comprises the use of WCl5 as a precursor material. [10] Method according to any one of claims 7 to 9, wherein the deposition of the second seed sublayer (74) by the second deposition process comprises the use of WF6 as a precursor material. [11] Method according to any one of claims 7 to 10, wherein the production of a seed layer (70) further comprises the deposition of a third seed sublayer over the second seed sublayer by a third deposition process. [12] Method according to claim 11, wherein a crystalline material is deposited in the third deposition process. [13] Method according to any one of claims 7 to 12, wherein the first deposition process comprises chemical evaporation [14] Device with: a gate stack (80) arranged over a semiconductor channel region, the gate stack comprising the following: a dielectric gate material (54, 56) arranged above the semiconductor channel region, a seed layer (70) arranged above the dielectric gate material (54, 56), wherein the seed layer comprises several sublayers (72, 74), wherein at least one sublayer is crystalline and at least one sublayer is amorphous, wherein the first seed layer (72) is the same material as the second seed layer (74) and a conductive material (76) arranged above the seed layer (70); and Source / drain areas (48) adjacent to the gate stack (80) and on opposite sides of the gate stack [15] Device according to claim 14, wherein the semiconductor channel area has a fin (24'), and the gate stack (80) is arranged on side walls (38) and a top of the fin (24'). [16] Device according to claim 14 or 15, wherein the seed layer (70) has a first amorphous sublayer (72) arranged over a first crystalline sublayer (74). [17] Device according to claim 16, wherein the seed layer has a second crystalline (74) sublayer arranged above the first amorphous sublayer (72). [18] The device according to any one of claims 14 to 17, wherein the concentration of fluorine in the dielectric gate layer is less than 1%. [19] Device according to one of claims 14 to 18, wherein the gate stack further comprises a barrier layer (68) arranged between the seed layer (70) and the dielectric gate layer (54, 56). [20] Device according to any one of claims 14 to 19, wherein the seed layer (70) and the conductive material (76) form a conductive gate structure, wherein a first lateral cross-section of the conductive gate structure (80) has a smaller area than a second lateral cross-section of the conductive gate structure, wherein the second lateral cross-section is further away from the semiconductor channel region than the first lateral cross-section.

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