Splitting of bidirectional signals

Abstract

System (100) for converting a bidirectional bus (212) into two unidirectional buses, comprising a first bus (222) which communicates data in a first direction and a second bus (224) which communicates data in a second direction, wherein the system (100) comprises: a first logic circuit (220), which is coupled to the first bus (222) and to the second bus (224) and configured to: Determine that the first bus (222) will be dominant over the second bus (224); and Generating an indication that communication is in the first direction, based on the determination that the first bus (222) becomes dominant before the second bus (224); and a second logic circuit (210) which reacts to the first logic circuit (220), which is coupled to the bidirectional bus (212) and configured to: Allowing communication between the bidirectional bus (212) and the first bus (222) based on the indication that the communication is in the first direction; and Blocking communication between the bidirectional bus (212) and the second bus (224) based on the indication that the communication is in the first direction, wherein the first logic circuit (220) comprises a timer circuit coupled to a logic element to generate the indication that the communication is in the first direction, wherein the first bus (222) is configured to transmit the data to an external device (150, 160), and wherein the second bus (224) is configured to receive the data from the external device (150, 160).

Description

Territory of Revelation

[0001] This document refers generally, but not exclusively, to signal splitting in a bidirectional communication system. background

[0002] Electronic circuits and systems often communicate with each other via a communication link known as a "bus." A variety of bus architectures are well-known. Simple buses use only two active lines, although they may include additional lines for other functions. An Inter-Integrated Circuit (I2C) bus, for example, consists of two communication lines, a serial data line (SDA), and a serial clock line (SCL).

[0003] I2C buses are used to provide communication between two integrated circuits (ICs), for example, two or more ICs on a single printed circuit board (PCB) or ICs on different PCBs. The I2C bus can also be used as a network connection between electronic systems, such as in automation or control system applications. Architectures like the I2C bus are easy to implement, but their applicability is limited to short-distance communication (for example, less than 155 meters) due to the asymmetric nature of the lines. Splitting each bidirectional I2C bus into two unidirectional buses allows devices using the I2C bus protocol to communicate over greater distances by employing a differential transceiver.However, typical systems lack the ability to efficiently, quickly and at minimal cost split the bidirectional signal into two unidirectional buses for this purpose.

[0004] US 2014 / 023365 A1 pertains to the field of communication buses, and in particular to systems and methods for adapting Controller Area Network (CAN) buses for underwater optical communication. Messages on CAN buses are transmitted via underwater optical links. An adapter connects a CAN bus to an optical link. The adapter detects the direction of transmission, i.e., whether a signal originates on the CAN bus connected to the adapter or on the optical link connected to the adapter. Signals from the CAN bus are transmitted to the optical link depending on the detected direction of transmission. The adapter can operate at the physical layer without analyzing the content of the CAN bus communication.

[0005] US 2009 / 028226A1 concerns an open-collector / open-drain interface, such as the I2C interface between two or more integrated circuits, which uses isolation techniques to ensure electrical isolation of a digital signal for transmission between devices. Unidirectional isolator channels are used to transmit bidirectional digital signals, and the selection of an isolator channel operating in an intended transmission direction is performed by direction control logic. Edge detection logic is used to detect changes in the edges of a digital signal and thus determine a transmitting device and transmission direction. The direction status is stored in a direction status register. This state is maintained until the corresponding edge is detected on the transmitting side, at which point the isolator returns to its idle state.In its idle state, neither side of the isolator is in a controlled state. During transmission, the digital signal is transmitted through an isolator channel and sent to a receiving device.

[0006] US 2006 / 075 170 A1 relates to a system and method for providing an interface between a first-voltage-referenced master device and a second-voltage-referenced slave device. The system includes a bidirectional communication link between the master device and the slave device, and a bidirectional transceiver device in the communication link for decomposing bidirectional signals on the communication link into transmissions from the slave device to the master device on a first bus and transmissions from the master device to the slave device on a second bus. A first isolating device is included in the bidirectional link and connected to the first bus to transmit signals over the bidirectional link from the first-voltage-referenced master device to the second-voltage-referenced slave device.A second isolating device is also included in the bidirectional connection and connected to the second bus to transmit signals via the bidirectional connection from the slave device related to the second voltage to the master device related to the first voltage. Summary of Revelation

[0007] This disclosure describes techniques for extending the range of bidirectional bus communication (for example, I2C bus protocol communication) by using a differential signal path. The discussed techniques involve first splitting the bidirectional bus into a first and a second unidirectional bus, which send and receive signals, respectively, and then communicating the signals from the first and second unidirectional buses via a differential signal path. The splitting of the bidirectional bus into the first and second unidirectional buses is accomplished using a logic circuit that either blocks or allows communication between a given first or second bus and the bidirectional bus, based on which of the first or second buses becomes dominant first.If the logic circuit determines that the first bus will become dominant over the second bus, the logic circuit allows communication between the first bus and the bidirectional bus and blocks communication between the second bus and the bidirectional bus.

[0008] A system with the features of claim 1 is provided.

[0009] In certain embodiments, the first logic circuit is further configured to trigger a change in the specification that communication takes place in the first direction when the first bus becomes recessive for a specified duration.

[0010] According to the disclosure, the first logic circuit comprises a timer circuit which is coupled to a logic element for generating the indication that the communication is in the first direction, wherein the first bus is configured to transmit the data to an external device, and wherein the second bus is configured to receive the data from the external device.

[0011] In certain embodiments, the timer circuit is configured to: bring into an active state a signal indicating that communication is taking place in the first direction, in response to the detection that the first bus is becoming dominant; and delay the reset of the signal in response to the detection that the first bus is becoming recessive, until the timer circuit reaches a specified value.

[0012] In certain embodiments, the first bus is configured to receive data from an external device, the second bus is configured to transmit data to the external device, and the first logic circuit comprises a first and a second timer circuit coupled to a plurality of logic elements for generating the indication that communication is in the first direction.

[0013] In certain embodiments, the first and second timer circuits receive a signal indicating that the first bus has become recessive, wherein the plurality of logic elements is coupled to the bidirectional bus, and wherein the plurality of logic elements is configured to: determine that the bidirectional bus has become recessive; determine that the bidirectional bus is rotating towards a recessive state; and generate a signal indicating that the first bus has become recessive.

[0014] In certain embodiments, the multitude of logic elements is configured to trigger a change in the indication that communication is in the first direction, based on determining that: the first timer circuit reaches a first specified value and the bidirectional bus becomes recessive; the first timer circuit reaches the first specified value and the bidirectional bus is determined not to be rotating in the direction of a recessive state; or the second timer circuit reaches a second specified value that is greater than the first specified value.

[0015] In certain embodiments, the second logic circuit blocks communication between the bidirectional bus and the second bus by keeping a value communicated on the second bus in an inactive state.

[0016] In certain embodiments, the first logic circuit is configured to determine that the first bus becomes dominant when a logic value of the first bus goes low; the first logic circuit comprises a first NOR logic element having inputs directly coupled to the first bus, an output of a first latch, and an output of a second latch, wherein an input of the first latch is coupled to the first bus; the first NOR logic element has an output coupled to the first latch, wherein an output of the first latch is coupled to the second logic circuit via at least one timer circuit; and the output of the first latch generates the indication that communication is in the first direction.

[0017] In certain embodiments, the first logic circuit comprises a second NOR logic element having inputs directly connected to the second bus, an output of the first latch, and an output of the second latch, wherein an input of the second latch is connected to the second bus; the second NOR logic element has an output connected to the second latch, wherein an output of the second latch is connected to the second logic circuit via at least one additional timer circuit; the second logic circuit comprises a first OR logic element and a third NOR logic element; the first OR logic element has inputs connected to the bidirectional bus and to the signal generated by the first logic circuit, wherein an output of the first OR logic element is connected to the first bus;and the third NOR logic element has inputs which are coupled to the second bus and to the output generated by the first logic circuit, wherein an output of the third NOR logic element is coupled to the bidirectional bus via a transistor.

[0018] A method with the features of claim 10 is provided.

[0019] In certain embodiments, the method involves triggering a change in the specification that communication occurs in the first direction when the first bus becomes recessive for a specified duration.

[0020] According to the disclosure, the determination that the first bus becomes dominant over the second bus is carried out using a timer circuit coupled to a logic element, wherein the first bus is configured to transmit the data to an external device, and wherein the second bus is configured to receive the data from the external device.

[0021] In certain embodiments, the timer circuit is configured to: bring into an active state a signal indicating that communication is taking place in the first direction, in response to the detection that the first bus is becoming dominant; and delay the reset of the signal in response to the detection that the first bus is becoming recessive, until the timer circuit reaches a specified value.

[0022] In certain embodiments, the first bus is configured to receive data from an external device, the second bus is configured to transmit data to the external device, and the determining and generating steps are performed using a first and a second timer circuit coupled to a plurality of logic elements.

[0023] In certain embodiments, the first and second timer circuits receive a signal indicating that the first bus has become recessive, wherein the plurality of logic elements is coupled to the bidirectional bus, and wherein the plurality of logic elements is configured to: determine that the bidirectional bus has become recessive; determine that the bidirectional bus is rotating towards a recessive state; and generate a signal indicating that the first bus has become recessive.

[0024] In certain embodiments, the multitude of logic elements is configured to trigger a change in the indication that communication is in the first direction, based on determining that: the first timer circuit reaches a first specified value and the bidirectional bus becomes recessive; the first timer circuit reaches the first specified value and the bidirectional bus is determined not to be rotating in the direction of a recessive state; or the second timer circuit reaches a second specified value that is greater than the first specified value.

[0025] In certain embodiments, the method further involves blocking communication between the bidirectional bus and the second bus by keeping a value communicated on the second bus in an inactive state.

[0026] In certain embodiments, the method further includes determining, using the first logic circuit, that the first bus becomes dominant when a logic value of the first bus goes low; wherein: the first logic circuit comprises a first NOR logic element having inputs directly coupled to the first bus, an output of a first latch, and an output of a second latch, with one input of the first latch being coupled to the first bus; the first NOR logic element has an output coupled to the first latch, with one output of the first latch being coupled to the second logic circuit via at least one timer circuit; the output of the first latch generates the indication that communication is in the first direction;The first logic circuit comprises a second NOR logic element, which has inputs directly coupled to the second bus, an output of the first latch, and an output of the second latch, wherein an input of the second latch is coupled to the second bus; the second NOR logic element has an output coupled to the second latch, wherein an output of the second latch is coupled to the second logic circuit via at least one additional timer circuit; the second logic circuit comprises a first OR logic element and a third NOR logic element; wherein the first OR logic element has inputs coupled to the bidirectional bus and to the output generated by the first logic circuit, wherein an output of the first OR logic element is coupled to the first bus;and the third NOR logic element has inputs which are coupled to the second bus and to the output generated by the first logic circuit, wherein an output of the third NOR logic element is coupled to the bidirectional bus via a transistor.

[0027] A system with the features of claim 18 is provided.

[0028] This overview is intended to provide a general understanding of the subject matter of the present patent application. It is not intended to be an exclusive or complete explanation of the inventive step. The detailed description is attached for further information on the present patent application. Brief description of the drawings

[0029] In the drawings, which are not necessarily drawn to scale, the same reference numerals may describe similar components in different views. The same reference numbers with different letter suffixes may denote different instances of similar components. The drawings illustrate, generally, by way of example, but not exclusively, various embodiments that are explained in this document. Fig. Figure 1 is a block diagram of an example of a differential signal communication system that uses a bidirectional bus, in accordance with various embodiments. Fig. Figure 2 is a block diagram of an example of a bidirectional signal isolating device in accordance with various embodiments. Fig. Figure 3 is a block diagram of an example of various components of the bidirectional signal isolating device in accordance with different embodiments. Fig. Figures 4-6 are flowcharts showing exemplary processes for performing a split of a bidirectional signal, in accordance with different embodiments. Fig. Figure 7 is a block diagram showing an example of a machine on which one or more embodiments can be implemented. Detailed description

[0030] This disclosure describes, among other things, techniques for splitting a bidirectional bus (for example, the I2C bus signals) into two unidirectional buses (for example, a transmit and a receive bus) to allow devices using bidirectional buses to communicate over greater distances (for example, more than 1.5 meters). After the bidirectional bus has been split into the transmit and receive buses, data can be communicated between two or more devices using the transmit and receive buses via a differential signal transceiver (for example, a Controller Area Network (CAN) transceiver). Because differential signal buses are less susceptible to noise than unbalanced buses, data can be transmitted between devices over greater distances.

[0031] The following disclosure provides examples of splitting the bidirectional bus signals of the I2C bus protocol, but can be applied similarly to any other bidirectional bus communication protocol.

[0032] According to the disclosed embodiments, to split the bidirectional bus into two unidirectional buses, each bidirectional signal of the I2C bus protocol (for example, the SCL and SDA buses) is provided to a logic circuit, which splits the given signal into two unidirectional buses. For example, the logic circuit receives the SCL bus and splits the SCL bus into a transmit and a receive bus. One of the challenges in splitting a bidirectional bus into a transmit and a receive bus is knowing the direction of the data on the bidirectional bus. Specifically, when data is communicated on the bidirectional bus from a first device to a second device, the data should be placed on the transmit bus of the first device and on the receive bus of the second device.Whereas data which the first device is to receive from the second device on the bidirectional bus should be placed on the transmit bus of the second device and on the receive bus of the first device.

[0033] A common method for splitting a bidirectional bus into transmit and receive buses involves a static offset method. This method compares precise voltages on the bidirectional bus with various threshold voltages, using comparators and voltage references to determine the direction of communication. However, the use of precise comparators and voltage references is expensive, inflexible, and inefficient. This is because comparators and voltage references occupy a relatively large area on a semiconductor device, and using multiple closely spaced voltage thresholds on an asymmetric bus (i.e., the bidirectional bus) reduces the system's noise immunity.

[0034] Another well-known way to split the bidirectional bus into transmit and receive buses requires measuring the current direction on the bidirectional bus using a pull-up resistor integrated within the integrated circuit (IC). However, this method is also expensive, inflexible, and inefficient. In particular, the pull-up resistor's value depends on the bus capacitance to ensure that the rise and fall times meet the bus specifications. Because this pull-up resistor is internal to the IC, its value must be determined during the IC's design phase, limiting the applicability of this method to devices with the bus capacitance for which the resistor was designed. This increases the system design cost and reduces its overall flexibility.

[0035] The described techniques for splitting a bidirectional signal efficiently, quickly, and at minimal cost divide a bidirectional signal bus into a transmit and a receive bus. These techniques use a logic circuit combined with transistors to perform the signal separation, requiring minimal space on a semiconductor device and allowing for flexible application in a wide range of situations. The way in which the direction of the signal path is determined to control whether the bidirectional signal communicates with the transmit or receive bus is based on determining whether the transmit or receive bus becomes dominant first. More precisely, if the logic circuit determines that the transmit bus will become dominant before the receive bus, it allows communication between the transmit bus and the bidirectional bus and blocks communication between the receive bus and the bidirectional bus.On the other hand, if the logic circuit determines that the receive bus becomes dominant over the transmit bus, the logic circuit allows communication between the receive bus and the bidirectional bus, and blocks communication between the transmit bus and the bidirectional bus.

[0036] According to the disclosed embodiments, the logic circuit uses one or more timer circuits to avoid the possibility of bus conflicts (for example, due to an erroneous determination that a given unidirectional bus should no longer communicate with the bidirectional bus). In particular, the timer circuits are activated as soon as the unidirectional bus that is allowed to communicate with the bidirectional bus becomes recessive. These timer circuits communicate with the logic circuit to ensure that the logic circuit continues to allow one unidirectional bus to communicate with the bidirectional bus, while the other remains blocked from communicating with the bidirectional bus, until its specified threshold duration is reached.

[0037] According to the disclosed techniques, a unidirectional bus becomes dominant when a logic value of a signal on the bus is low, and the unidirectional bus becomes recessive when the logic value of a signal on the unidirectional bus is high. The disclosed techniques can be applied similarly to a system in which a bus becomes dominant when a logic value of a signal on the unidirectional bus is high, and the unidirectional bus becomes recessive when the logic value of a signal on the unidirectional bus is low.

[0038] Fig. Figure 1 is a block diagram of an example of a differential signal communication system 100, which uses a bidirectional bus, in accordance with various embodiments. The differential signal communication system 100 includes a first device 150 and a second device 160. Although only two devices are shown in the differential signal communication system 100, any number of additional devices can communicate with the first device 150 and the second device 160 using the same techniques. Specifically, the first device 150 can be coupled with any number of devices using the differential transceivers 120A and 120B.

[0039] The first device 150 includes a bidirectional signal isolator 110A and 110B. Each bidirectional signal isolator 110A and 110B is coupled to a respective bidirectional bus 112 and 114 of the bidirectional bus protocol. In the case of the I2C bidirectional bus protocol, for example, the bidirectional signal isolator 110A is coupled to the bidirectional bus 112, which may be used to communicate SDA data of the I2C bidirectional bus protocol; and the bidirectional signal isolator 110B is coupled to the bidirectional bus 114, which may be used to communicate SCL data of the I2C bidirectional bus protocol.

[0040] For the sake of brevity and simplicity, an implementation of the bidirectional signal isolating circuit 110A, which communicates (sends and receives) SDA signals of the bidirectional bus 112, is described below in conjunction with Fig. 2 and Fig. 3 is given, but similar implementations apply to all other bidirectional bus signals (for example, SCL bus signals). In certain cases, only a single bidirectional bus is used in the differential signal communication system 100. In such cases, only one of the bidirectional signal isolating circuits 110A and 110B is used and required for the first device 150 and the second device 160.

[0041] The bidirectional signal isolator 110A splits or isolates the bidirectional signal received from bus 112 into two unidirectional buses, each communicating signals in a different direction (for example, a transmit bus (TXD) and a receive bus (RXD)). Similarly, the bidirectional signal isolator 110B splits or isolates the bidirectional signal received from bus 114 into two unidirectional buses, each communicating signals in a different direction (for example, a transmit bus (TXD) and a receive bus (RXD)).For example, the transmit bus represents data from the bidirectional bus 112, which the first device 150 sends to an external device (for example, the second device 160), and the receive bus represents data that is received by the first device 150 from an external device (for example, the second device 160) to be fed onto the bidirectional bus 112.

[0042] Each unidirectional bus generated by the 110A / B bidirectional signal isolator is provided to a 120A / B differential transceiver. For example, the transmit and receive buses (corresponding to the SDA bidirectional bus signals) generated by the 110A bidirectional signal isolator are output to the 120A transceiver, and the transmit and receive buses (corresponding to the SCL bidirectional bus signals) generated by the 110B bidirectional signal isolator are provided to the 120B differential transceiver. The 120A and 120B differential transceivers can be implemented as Controller Area Network (CAN) transceivers, although other suitable differential transceiver implementations may be used.The differential transceivers 120A and 120B convert the asymmetric transmit signal (e.g., TXD) received by the respective bidirectional signal isolators 110A and 110B into their respective differential half-duplex buses 121 and 122 (COMH and COML) (e.g., CANH and CANL). The differential transceivers 120A and 120B also convert the differential half-duplex bus 121 and 122 into a receive signal (e.g., RXD) and send the received signal to the bidirectional signal isolators 110A and 110B.

[0043] For example, if data is sent out from the first device 150 (e.g., data is present on the TXD bus and not on the RXD bus), the differential transceiver 120A converts the TXD bus signals into a differential signal bus 121 (COMH and COML). These differential signals can be communicated over greater distances than the bidirectional bus signals themselves (e.g., over 1.5 m). In this way, the second device 160 can be located at a great distance of more than 1.5 m from the first device 150 and can receive the bidirectional bus data of the bidirectional bus 112 via the differential signal bus 121, which is sent by the differential transceiver 120A, using a corresponding differential transceiver 130A.Once the second device 160 receives the differential signal via bus 121 or 122 using differential transceiver 130A or 130B, the differential transceiver 130A or 130B converts the received signals into the unidirectional RXD signal. The data on the RXD bus is received by the bidirectional signal isolator 140A of the second device 160 and communicated on the SDA bidirectional bus 142 of the second device 160. The second device 160 can use similar circuitry and functions to send or receive the SCL bidirectional bus 144 signal via differential transceiver 130B and bidirectional signal isolator 140B.

[0044] Fig. Figure 2 is a block diagram of an example of a bidirectional signal isolator 200 in accordance with various embodiments. The bidirectional signal isolator 200 represents an implementation of the bidirectional signal isolators 110A, 110B, 140A, and 140B. The bidirectional signal isolator 200 includes a bus domination logic circuit 210 (for example, first logic circuit) and a bidirectional bus access logic circuit 220 (for example, second logic circuit). The bidirectional bus access logic circuit 220 is coupled to a bidirectional bus 212 (for example, the bidirectional bus 112 (SDA)), a first unidirectional bus 222 (for example, a TXD bus), and a second unidirectional bus 224 (for example, an RXD bus).The bidirectional bus access logic circuit 220 controls which of the two unidirectional buses 222 and 224 are allowed to communicate with the bidirectional bus 212, and which of the two unidirectional buses 222 and 224 is blocked from communicating with the bidirectional bus 212. The bidirectional bus access logic circuit 220 performs this control based on a signal 230 received from the bus domination logic circuit 210, which informs the bidirectional bus access logic circuit 220 which of the two unidirectional buses 222 and 224 became dominant first.

[0045] The bus domination logic circuit 210 is, for example, coupled to the two unidirectional buses 222 and 224 and determines which one becomes dominant first. More precisely, the bus domination logic circuit 210 includes logic that determines that the unidirectional bus 222 becomes dominant before the unidirectional bus 224 if a signal on the unidirectional bus 222 changes from a logical high state to a logical low state before a signal on the unidirectional bus 224 changes from a logical high state to a logical low state. The bus domination logic circuit 210 can determine that the unidirectional bus 222 communicates data in a specific direction (for example, sending data from the device to an external device).In response to such a determination, the bus domination logic circuit 210 sends a logical signal, denoted as 230, to the bidirectional bus access logic circuit 220, indicating which unidirectional bus 222 or 224 became dominant first, and the direction of communication (e.g., sending or receiving). Upon receiving this denotation 230, the bidirectional bus access logic circuit 220 allows the unidirectional bus 222 to communicate with the bidirectional bus 212 and blocks the unidirectional bus 224 from communicating with the bidirectional bus 212.

[0046] In some implementations, the bidirectional bus access logic circuit 220 can block the unidirectional bus 224 from communicating with the bidirectional bus 212 by holding a logic value received by the unidirectional bus 224 in a recessive state (for example, by holding a logic high value in the signal received by the unidirectional bus 224), regardless of whether the unidirectional bus 224 transitions to a dominant state or receives data from an external device. The bidirectional bus access logic circuit 220 can similarly block the unidirectional bus 222 from communicating with the bidirectional bus 212.For example, the bidirectional bus access logic circuit 220 can keep a logic value provided to the unidirectional bus 222 in a recessive state (for example, by maintaining a logic high value in the signal provided to the unidirectional bus 222), regardless of whether the bidirectional bus 212 transitions to a dominant state.

[0047] The bidirectional bus access logic circuit 220 can connect the unidirectional bus 224 to the bidirectional bus 212, for example, via a NOR logic gate. The NOR logic gate has two inputs (a first input, which is coupled to receive signals from the unidirectional bus 224, and a second input, which is coupled to a blocking signal). The output of the NOR logic gate is coupled to the bidirectional bus 212. To block the signals received from the unidirectional bus 224 so that they do not communicate with the bidirectional bus 212, the bidirectional bus access logic circuit 220 holds the blocking signal at a logic high value, which causes the output of the NOR logic gate to be held at a logic low value, regardless of changes in the unidirectional bus 224.This prevents the bidirectional bus 212 from receiving any signal from the unidirectional bus 224, thus blocking communication between the unidirectional bus 224 and the bidirectional bus 212.

[0048] The bus domination logic circuit 210 continues to monitor signals on the unidirectional buses 222 and 224. The bus domination logic circuit 210 determines that the unidirectional bus 222 has transitioned from a dominant state to a recessive state. In response to this determination, the bus domination logic circuit 210 activates a timer circuit contained within it. After the timer circuit reaches a given threshold (for example, 90 nanoseconds), the bus domination logic circuit 210 can send a signal 230 (for example, a signal containing two or more signals – TXDBLNK and RXDBLNK) to the bidirectional bus access logic circuit 220 indicating that the unidirectional bus 222 has transitioned from a dominant state to a recessive state.In response to receiving this information 230, the bidirectional bus access logic circuit 220 can block the unidirectional bus 224 from communicating with the bidirectional bus 212. More precisely, the bidirectional bus access logic circuit 220 can allow both unidirectional buses 222 and 224 to communicate with the bidirectional bus 212.

[0049] Fig. Figure 3 is a block diagram of an example of various components of the bidirectional signal isolator 300 in accordance with different embodiments. The bidirectional signal isolator 300 represents an implementation of the bidirectional signal isolator 200 ( Fig. 2) More precisely, the bidirectional signal isolator 300 includes a second logic circuit 320, which represents an implementation of the bidirectional bus access logic circuit 220. The remaining logic circuit outside the second logic circuit 320 corresponds to the first logic circuit, which represents the bus domination logic circuit 210. In some implementations, the bidirectional bus access logic circuit 220 and the bus domination logic circuit 210 can be combined into a single logic circuit.

[0050] The bidirectional signal isolator 300 includes a bidirectional bus 312 (for example, an SDA or SCL bus), a first unidirectional bus 322 (for example, a TXD bus), and a second unidirectional bus 324 (for example, an RXD bus). In simple terms, the bidirectional signal isolator 300 waits for one of the signals from the bidirectional bus 312 or the unidirectional receive signal (RXD) from the second bus 324 to become dominant first (for example, a logic low value) in order to determine the direction of communication. Once the direction of communication has been established by one bus becoming dominant (for example, assuming a logic low value), its corresponding bus is set to a low state, and the opposing bus signal is blocked.The bus communicating in the opposite direction remains blocked until the bus can communicate safely without blocking a bus or misunderstanding the direction of communication.

[0051] The logic elements (devices) NOR1 331, LATCH1 330, NOR2 341, and LATCH2 340 of the bidirectional signal isolator 300 are responsible for determining the direction of communication. In a default state, when the bidirectional bus 312 (e.g., SDA), the unidirectional bus 324 (RXD), and the unidirectional bus 322 (TXD) are inactive (e.g., in a logic high state) and no communication direction is set, LATCH1 330 and LATCH2 340 are set, and the signals / TXDQ and / RXDQ, which are output by LATCH1 330 and LATCH2 340 respectively, are low.

[0052] If a device first pulls the bidirectional bus 312 low (for example, if the device implementing the bidirectional signal isolator 300 attempts to send I2C data on the bidirectional bus 312 to an external device), the first unidirectional bus 322 becomes dominant (for example, it is set to the active state), while the second unidirectional bus 324 is recessive (for example, it is inactive). The state of NOR1 331 changes, causing LATCH1 330 to reset, which sets / TXDQ high. At this point, the direction of communication is recognized as being from the bidirectional bus 312 to the differential bus via the first unidirectional bus 322. The blanking signal RXDBLNK 345 assumes a logic high value, which prevents the second unidirectional bus 324 from driving the bidirectional bus 312.When the bidirectional bus 312 is released by the device transmitting data on it and reverts to a recessive state, the first unidirectional bus 322 becomes recessive (e.g., deactivated), and LATCH1 330 is set. This changes / TXDQ back to a logic low, which starts the timer circuit TIMER1 332. RXDBLNK 345 remains high until TIMER1 332 reaches a given threshold (e.g., 90 ns), at which point RXDBLNK 345 returns to a logic low, allowing communication in either direction (e.g., allowing either the first unidirectional bus 322 or the second unidirectional bus 324 to communicate with the bidirectional bus 312).In some implementations, the duration of the timer circuit TIMER1 332 is set to a value that exceeds the sum of the differential bus relaxation time and the propagation delay of the differential bus to a terminal corresponding to the second unidirectional bus 324. In this way, the timer circuit TIMER1 332 prevents the second unidirectional bus 324 from driving the bidirectional bus 312 as a result of an external device driving its own bidirectional bus, which corresponds to the bidirectional bus 312.

[0053] When the second unidirectional bus 324 becomes dominant (for example, is activated) while the first unidirectional bus 322 remains recessive (for example, is disabled), NOR2 341 changes its state. This causes LATCH2 340 to reset and set / RXDQ high. At this point, communication is established from the differential bus 121 to the bidirectional bus 312. The blanking signal TXDBLNK 346 prevents the bidirectional bus 312 from driving the differential bus 121 by sending data to the first unidirectional bus 322. When the second unidirectional bus 324 returns to a recessive state, LATCH2 340 is set, which changes / RXDQ back low. This causes the timer circuit TIMER2 342 and the timer circuit TIMER3 344 to start. TXDBLNK 346 remains high and can continue to block the first unidirectional bus 322 until one of its three conditions is met.

[0054] In one case, TXDBLNK 346 can change its state and become low, thus allowing communication between the first unidirectional bus 322 and the bidirectional bus 312 when the timer circuit TIMER2 342 reaches a first threshold (for example, 30 ns) and the bidirectional bus 312 has returned to a recessive state. The return of the bidirectional bus 312 to a recessive state can be detected when logic element 350 becomes high. In this case, the signal bus HILATCHED goes high, which sets TXDBLNK 346 back to low. At this point, any activation of the bidirectional bus 312 can be safely assumed to result from data being sent to the first unidirectional bus 322. Communication can then occur in either direction.

[0055] In another case, TXDBLNK 346 can change its state and become low, allowing communication between the first unidirectional bus 322 and the bidirectional bus 312 when the timer circuit TIMER2 342 reaches its first threshold and the bidirectional bus 312 is not rotating towards a recessive state. The rotation detector 352 determines whether the bidirectional bus 312 is rotating towards the recessive state and generates the / SLEWUP signal. When the / SLEWUP signal becomes high (after the timer circuit TIMER2 342 has reached its first threshold), TXDBLNK 346 is set back to a logic low. At this point, the bidirectional bus 312 can be considered active as a result of data being sent to the first unidirectional bus 322. This data can now be safely communicated to the differential bus 121.In some implementations, the threshold (e.g., the duration) of the timer circuit TIMER2 342 is set such that it exceeds the detection time of the rotary detector 352 at the slowest rotation rate allowed at the terminal corresponding to the bidirectional bus 312. This restriction on the value of the first threshold of the timer circuit TIMER2 342 ensures that the first unidirectional bus 322 will not be activated as a result of data being received from an external device on the differential bus 121.

[0056] In another case, TXDBLNK 346 can change its state and become low, thus allowing communication between the first unidirectional bus 322 and the bidirectional bus 312 when the timer circuit TIMER3 344 reaches a second threshold (for example, 120 ns) and none of the previous conditions have been met. In this case, TXDBLNK 346 returns to a low state, opening communication in both directions. The second threshold of the timer circuit TIMER3 344 can be longer than the first threshold of the timer circuit TIMER2 342 and simply ensures that bidirectional communication is eventually reopened, even if the bidirectional bus 312 remains in a dominant state (for example, a logic low state) but is slowly rotating.In some implementations, the duration of the second threshold of the timer circuit TIMER3 344 is set to exceed the maximum permissible rise time of the bidirectional bus 312. This restriction on the value of the second threshold of the timer circuit TIMER3 344 prevents the first unidirectional bus 322 from being brought into an active state as a result of any data received on the differential bus, and ensures that bidirectional communication does not get stuck in a latch state and resume after sufficient time has elapsed, allowing the bidirectional bus 312 to revert to a recessive state as a result of the second unidirectional bus 324 becoming recessive (e.g., deactivation).

[0057] The timer circuits TIMER1 332, TIMER2 342 and TIMER3 344 are in Fig. Figure 3 shows a timer circuit using a pair of transistors coupled to a resistor and a capacitor. The duration or threshold of each of these timer circuits, 332, 342, and 344, is set based on the ratio of their respective resistors and capacitors. Any other suitable timer circuit can be implemented, which may or may not use transistors, resistors, and capacitors. For example, a timer circuit can be implemented in logic using a collection of logic delay elements connected in series, or a collection of counter circuits set to one or more values.

[0058] Fig. Figure 4 is a flowchart showing an exemplary process 400 for converting a bidirectional signal into a first bus and a second bus according to various embodiments. The operations of process 400 can be performed in parallel, in a different sequence, or omitted entirely. In some embodiments, some or all of the operations of process 400 can be embodied on a computer-readable medium and executed by one or more processors.

[0059] Operation 410 determines that a first bus becomes dominant over a second bus, where the first bus communicates data of a bidirectional bus in one direction and the second bus communicates data of the bidirectional bus in the other direction. For example, the bus domination logic circuit 210 can determine that the unidirectional bus 222 (first bus) became dominant over the unidirectional bus 224 (second bus). Alternatively, the bus domination logic circuit 210 can determine that the unidirectional bus 224 (first bus) became dominant over the unidirectional bus 222 (second bus).

[0060] Operation 420 generates an H indicating that communication occurs in the first direction, based on the determination that the first bus becomes dominant over the second bus. For example, the bus dominance logic circuit 210 can generate an H and provide this H to the bidirectional bus access logic circuit 220, which indicates the communication direction. For example, the bus dominance logic circuit 210 can indicate whether communication is in the transmit or receive direction.

[0061] Operation 430 allows communication between the bidirectional bus and the first bus based on the specification that the communication is in the first direction. For example, the bidirectional bus access logic circuit 220 can allow communication between the bidirectional bus 212 and the unidirectional bus 222 if the communication direction is in the transmit direction. Alternatively, the bidirectional bus access logic circuit 220 can allow communication between the bidirectional bus 212 and the unidirectional bus 224 if the communication direction is in the receive direction.

[0062] Operation 440 blocks communication between the bidirectional bus and the second bus based on the specification that the communication is in the first direction. For example, the bidirectional bus access logic circuit 220 can block communication between the bidirectional bus 212 and the unidirectional bus 224 if the communication direction is in the transmit direction. Alternatively, the bidirectional bus access logic circuit 220 can block communication between the bidirectional bus 212 and the unidirectional bus 222 if the communication direction is in the receive direction.

[0063] Fig. Figure 5 is a flowchart illustrating an exemplary process 500 for splitting a bidirectional signal into a first bus and a second bus according to various embodiments. The operations of process 500 can be performed in parallel, in a different order, or omitted entirely. In some embodiments, some or all of the operations of process 500 can be embodied on a computer-readable medium and executed by one or more processors.

[0064] Operation 510 determines that communication will occur in the first direction, which involves the transmission of data from the bidirectional bus to an external device via a first bus, by detecting that the bidirectional bus is dominant and a second bus is recessive. For example, NOR1 331 and NOR2 341 determine which of the first unidirectional bus 322 and the second unidirectional bus 324 became dominant first, in order to determine the direction of communication.

[0065] In operation 520, communication between the bidirectional bus and the first bus is allowed, while communication between the second bus and the bidirectional bus is blocked. For example, if NOR1 331 switches to a logic high state before NOR2 341, the direction of communication is determined to be in the transmit direction (for example, from the bidirectional bus 312 to the first unidirectional bus 322). In this case, logic circuit 320 allows communication from the bidirectional bus 312 to the first unidirectional bus 322 and, based on the RXDBLNK 345 signal and a NOR logic gate, blocks communication from the second unidirectional bus 324 to the bidirectional bus 312.

[0066] Operation 530 determines whether the first bus is in a recessive state. If the determination is that the first bus is in a recessive state, the process proceeds to operation 540; otherwise, the process proceeds to operation 520. For example, LATCH1 330 determines that the first unidirectional bus 322 is in a recessive state.

[0067] Operation 540 determines whether the timer has reached a threshold. If the timer has reached the threshold, the process proceeds to operation 550; otherwise, it proceeds to operation 530. For example, if the timer circuit TIMER1 332 reaches a given threshold, a value output by the timer circuit TIMER1 332 changes, resulting in a change in the logical state of the RXDBLNK 345 signal. This indicates a determination that the timer has reached a threshold.

[0068] Operation 550 enables communication between the bidirectional bus and the second bus. For example, RXDBLNK 345 changes its state to a logic low. When both RXDBLNK 345 and TXDBLNK 346 are in a logic low state, this causes logic circuit 320 to allow communication between the bidirectional bus and the first and second unidirectional buses 322 and 324.

[0069] Fig. Figure 6 is a flowchart showing an exemplary process 600 for splitting a bidirectional signal into a first bus and a second bus, in accordance with various embodiments. The operations of process 600 can be performed in parallel, in a different order, or omitted entirely. In some embodiments, some or all of the operations of process 600 can be embodied on a computer-readable medium and executed by one or more processors.

[0070] Operation 610 determines that communication will occur in the first direction, which involves receiving data from an external device via a second bus, by detecting that the second bus is dominant and the bidirectional bus is recessive. For example, NOR1 331 and NOR2 341 determine which of the first and second unidirectional buses 322 and 324 became dominant first, respectively, to establish the direction of communication.

[0071] Operation 620 allows communication between the bidirectional bus and the second bus, while blocking communication between the first bus and the bidirectional bus. For example, if NOR2 341 goes into a logic high state before NOR1 331 does, the direction of communication is determined to be receive-oriented (e.g., from the second unidirectional bus 324 to the bidirectional bus 312). In this case, logic circuit 320 allows communication between the bidirectional bus 312 and the second unidirectional bus 324, and, based on the TXDBLNK 346 signal and an OR logic gate, blocks communication from the bidirectional bus 312 to the first unidirectional bus 322.

[0072] Operation 630 determines whether the second bus is in a recessive state for a first threshold duration. If the determination is that the second bus is in a recessive state for a first threshold duration, process 600 proceeds to operation 640; otherwise, process 600 proceeds to operation 620. For example, when the timer circuit TIMER2 342 reaches the first threshold, a value output by the timer circuit TIMER2 342 changes, resulting in a change in the logic state of a logic element that generates the TXDBLNK 346 signal. This indicates a determination that the timer has reached the first threshold.

[0073] Operation 640 determines whether the bidirectional bus has returned to a recessive state. If the determination is that the bidirectional bus has returned to a recessive state, process 600 proceeds to operation 670; otherwise, process 600 proceeds to operation 650. For example, logic element 350 determines whether the bidirectional bus 312 has returned to a recessive state when it outputs a logic value high.

[0074] Operation 650 determines whether the bidirectional bus is rotating towards a recessive state. If it determines that the bidirectional bus is rotating towards the recessive state, process 600 proceeds to operation 660; otherwise, process 600 proceeds to operation 670. For example, rotation detector 352 determines whether the bidirectional bus 312 is rotating towards a recessive state.

[0075] Operation 660 determines whether a timer has reached a second threshold. If the timer is found to have reached the second threshold, process 600 proceeds to operation 670; otherwise, process 600 proceeds to operation 630. For example, if the timer circuit TIMER3 344 reaches the second threshold, a value output by the timer circuit TIMER3 344 changes, resulting in a change in the logic state of the logic element that generates the TXDBLNK 346 signal. This indicates that the timer has reached the second threshold.

[0076] Operation 670 enables communication between the bidirectional bus and the first bus. For example, TXDBLNK 346 changes its state, which causes logic circuit 320 to allow communication between the bidirectional bus and the first and second unidirectional buses 322 and 324.

[0077] Fig.Figure 7 shows a block diagram of an exemplary machine 700 on which one or more of the techniques (e.g., methodologies) discussed herein can be executed. In alternative embodiments, the machine 700 can be implemented as a standalone device or can be connected (e.g., networked) to other machines. In a networked environment, the machine 700 can operate as a server machine, a client machine, or both in server-client network environments. In one example, the machine 700 can function as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment.Machine 700 can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a web device, an IoT device, an automotive system, an aerospace system, or any machine capable of executing instructions (sequentially or otherwise) that define the actions to be performed by that machine. Furthermore, the term "machine," although illustrating only a single machine, also encompasses any collection of machines that, individually or collectively, execute a set (or multiple sets) of instructions to perform one or more of the methods described herein, such as cloud computing, software-as-a-service (SaaS), and other computer cluster configurations.

[0078] Examples, as described herein, can be, or can be operated by, logic, components, devices, packages, or mechanisms. A circuit is a collection (e.g., set) of circuits implemented in physical units that include hardware (e.g., simple circuits, gates, logic, etc.). Membership in a circuit can be flexible in time and in terms of the underlying hardware variability. Circuits include elements that, alone or in combination, can perform specific tasks during operation. In one example, the hardware of the circuit may be immutably configured to perform a specific operation (also hardwired). In another example, the hardware of the circuit may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) that contain a computer-readable medium that is physically modified (e.g.,(magnetic, electrical, movable arrangement of invariant bundled particles, etc.) to encode instructions for the specific operation. When the physical components are connected, the underlying electrical properties of a hardware component are changed, for example, from an insulator to a conductor or vice versa. The instructions allow the participating hardware (e.g., the execution units or a loading mechanism) to create elements of the circuit in the hardware via the variable connections in order to perform parts of the specific tasks during operation. Accordingly, the computer-readable medium is communicatively coupled with the other components of the circuit when the device is in operation. In one example, each of the physical components can be used in more than one element of more than one circuit.For example, execution units in operation can be used in a first circuit of a first circuit at one time and reused by a second circuit in the first circuit, or by a third circuit in a second circuit at another time.

[0079] The machine (e.g., computer system) 700 can include a hardware processor 702 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, such as a memory controller, etc.), main memory 704, and static memory 706, some or all of which can communicate with each other via a connection (e.g., bus) 708. The machine 700 can further include a display device 710, an alphanumeric input device 712 (e.g., a keyboard), and a user interface (UI) navigation device 714 (e.g., a mouse). In an example, the display device 710, the input device 712, and the UI navigation device 714 can be a touchscreen display. The machine 700 can additionally include a storage device 722 (e.g., drive unit), a signal generation device 718 (e.g.,The machine 700 may include a loudspeaker, a network interface device 720, one or more sensors 716, such as a GPS sensor, wing sensors, mechanical device sensors, temperature sensors, ICP sensors, bridge sensors, audio sensors, industrial sensors, compass, accelerometer, or other sensors, and one or more system-in-package data acquisition devices 790. The system-in-package data acquisition device(s) 790 may implement some or all of the functionality of the system-in-package data acquisition device(s) 100. The machine 700 may include an output controller 728, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection for communicating with or controlling one or more peripheral devices (e.g., printers, card readers, etc.).

[0080] The storage device 722 can include a machine-readable medium on which one or more sets of data structures or instructions 724 (e.g., software) are stored, embodying or utilizing one or more of the techniques or functions described herein. The instructions 724 can also reside wholly or at least partially in the main memory 704, the static memory 706, or the hardware processor 702 during execution by the machine 700. In one example, one of, or any combination of, the hardware processor 702, the main memory 704, the static memory 706, or the storage device 721 can constitute the machine-readable medium 722.

[0081] While the machine-readable medium 722 is represented as a single medium, the term "machine-readable medium" can include a single medium or multiple media (e.g., a central or distributed database, or associated caches and servers) configured to store one or more instructions 724.

[0082] The term “machine-readable medium” can include any transitory or non-transitory medium capable of storing, encoding, or carrying transitory or non-transitory instructions for execution by the Machine 700, causing the Machine 700 to perform one or more of the techniques of this disclosure, or capable of storing, encoding, or carrying data structures used by or in connection with such instructions. Non-restrictive examples of machine-readable media include solid-state storage, optical, and magnetic media. In one example, a machine-readable mass storage medium comprises a machine-readable medium with a plurality of particles having invariant (e.g., rest) mass. Accordingly, machine-readable mass storage media are not transitory propagation signals.

[0083] Specific examples of machine-readable mass storage media include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0084] The instructions 724 (e.g., software, programs, an operating system (OS), etc.) or other data stored on the storage device 721 can be accessed by the memory 704 and used by the processor 702. Memory 704 (e.g., DRAM) is typically fast but volatile, and thus a different type of memory than the storage device 721 (e.g., an SSD), which is suitable for long-term storage, even when the system is "off". Instructions 724 or data used by a user or the machine 700 are typically loaded into memory 704 and used by the processor 702.When memory 704 is full, virtual memory can be allocated from memory device 721 to supplement memory 704; however, since memory device 721 is typically slower than memory 704, and write speeds are typically at least twice as slow as read speeds, using virtual memory can significantly degrade the user experience due to the latency of the memory device (as opposed to memory 704, e.g., DRAM). Furthermore, using memory device 721 for virtual memory can substantially reduce the lifespan of memory device 721.

[0085] Instructions 724 can also be transmitted or received over a communication network 726 using a transmission medium via the network interface device 720 using one of several transmission protocols (e.g., frame relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Examples of communication networks include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), cellular networks (e.g., mobile networks), telephone (POTS) networks, and wireless data networks (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 Wi-Fi® family of standards, IEEE 802.16 WiMAX® family of standards, IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks), among others. In one example, the network interface device 720 can have one or more physical jacks (e.g.,Ethernet, coaxial, or telephone jacks) or one or more antennas for connecting to the communication network 726. In an example, the network interface device 720 may include a plurality of antennas for wireless communication, using at least one of the following techniques: SIMO (“Single Input Multiple Output”), MIMO (“Multiple Input Multiple Output”), or MISO (“Multiple Input Single Output”). The term “transmission medium” means any tangible or intangible medium capable of storing, encoding, or carrying instructions for execution by the machine 700, and which includes digital or analog communication signals or other tangible or intangible media to facilitate communication by this software.

[0086] Each of the non-restrictive aspects or examples described herein can stand alone, or be combined in various permutations or combinations with one or more of the other examples.

[0087] The detailed description above contains references to the accompanying drawings, which form part of the detailed description. The drawings illustrate specific embodiments in which the inventive subject matter can be practiced. These embodiments are hereinafter also referred to as "examples." Such examples may include additional elements beyond those shown or described. However, the present inventors also envision examples in which only the elements shown or described are provided.Furthermore, the present inventors also consider examples that use any combination or permutation of the elements shown or described (or one or more aspects thereof), either in relation to a particular example (or one or more aspects thereof), or in relation to other examples (or one or more aspects thereof) shown or described herein.

[0088] In case of inconsistent usage between this document and the documents referenced, the usage in this document shall prevail.

[0089] In this document, the term "a," as is common in patent documents, is used to denote one or more, irrespective of any other instances or uses of "at least one" or "one or more." In this document, the term "or" is used to refer to a non-exclusive or such that "A or B" includes "A but not B," "B but not A," "B but not A," and "A and B," unless otherwise specified. In this document, the terms "including" and "in which" are used as plain-language equivalents of the respective terms "comprising" and "in which." Also in subsequent claims, the terms "including" and "comprising" are open, meaning that a system, device, article, composition, formulation, or method which includes elements in addition to those listed in a claim after such a time limit will still fall within the scope of that claim.Furthermore, in the following claims the terms “first”, “second”, “third”, etc. are used only as designations and are not intended to impose any numerical requirements on their objects.

[0090] The method examples described herein may be at least partially machine- or computer-implemented. Some examples may include a computer-readable or machine-readable medium encoded with transitory or non-transitory instructions used to configure an electronic device to perform methods as described in the examples above. An implementation of such methods may include code, such as microcode, assembly language code, a higher-level language code, or the like. This code may contain transitory or non-transitory computer-readable instructions for performing various procedures. The code may form parts of computer program products. Furthermore, in an example, the code may be stored tangible on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as...during execution or at other times. Examples of these tangible, computer-readable media may include, but are not limited to, hard disks, removable hard disks, removable optical disks (e.g., compact discs and digital video discs), magnetic cassettes, memory cards or flash drives, random access memory (RAM), read-only memory (ROM), and the like.

[0091] The above description serves for illustration and not for limitation. For example, the examples described above (or one or more aspects thereof) may be used in combination with one another. Other embodiments may be used, e.g., by those skilled in the art, after reviewing the above description. The abstract is provided to enable the reader to quickly determine the nature of the technical disclosure. It is submitted with the understanding that it shall not be used to interpret or limit the scope or meaning of the claims. Furthermore, various features may be summarized in the above detailed description to simplify the disclosure. This should not be interpreted as implying that an unclaimed disclosed feature is essential to a claim.Rather, the inventive subject matter may consist of fewer than all features of a particular disclosed embodiment. Therefore, the following claims are hereby included in the detailed description as examples or embodiments, each claim constituting a separate embodiment on its own, and it is considered that such embodiments may be combined with one another in various combinations or permutations. The scope of the inventive subject matter should be determined with reference to the appended claims and the entire scope of the equivalents to which these claims refer.

Claims

[1] System (100) for converting a bidirectional bus (212) into two unidirectional buses, comprising a first bus (222) which communicates data in a first direction and a second bus (224) which communicates data in a second direction, wherein the system (100) comprises: a first logic circuit (220), which is coupled to the first bus (222) and to the second bus (224) and configured to: Determine that the first bus (222) will be dominant over the second bus (224); and Generating an indication that communication is in the first direction, based on the determination that the first bus (222) becomes dominant before the second bus (224); and a second logic circuit (210) which reacts to the first logic circuit (220), which is coupled to the bidirectional bus (212) and configured to: Allowing communication between the bidirectional bus (212) and the first bus (222) based on the indication that the communication is in the first direction; and Blocking communication between the bidirectional bus (212) and the second bus (224) based on the indication that the communication is in the first direction, wherein the first logic circuit (220) comprises a timer circuit coupled to a logic element to generate the indication that the communication is in the first direction, wherein the first bus (222) is configured to transmit the data to an external device (150, 160), and wherein the second bus (224) is configured to receive the data from the external device (150, 160). [2] System according to claim 1, wherein the first logic circuit is further configured to trigger a change in the indication that communication is in the first direction when the first bus (222) becomes recessive for a specified duration. [3] System according to claim 1, wherein the timer circuit is configured to: Bringing into an active state a signal indicating that communication is in the first direction, in response to the detection that the first bus (222) is becoming dominant; and Delaying the reset of the signal in response to the detection that the first bus (222) is becoming recessive until the timer circuit reaches a specified value. [4] System according to claim 1 or 2, wherein the first bus (222) is configured to receive the data from an external device, wherein the second bus (224) is configured to transmit the data to the external device, and wherein the first logic circuit comprises a first and a second timer circuit which are coupled to a plurality of logic elements for generating the indication that the communication is in the first direction. [5] System according to claim 4, wherein the first and second timer circuits receive a signal that the first bus (222) has become recessive, wherein the plurality of logic elements is coupled to the bidirectional bus (212), and wherein the plurality of logic elements is configured to: Determine that the bidirectional bus (212) became recessive; Determine that the bidirectional (212) bus turns towards a recessive state; and Generating a statement that the first bus (222) became recessive. [6] System according to claim 4 or 5, wherein the plurality of logic elements is configured to trigger a change in the indication that the communication is in the first direction, based on determining that: the first timer circuit reaches a first specified value and the bidirectional bus (212) becomes recessive; the first timer circuit reaches the first specified value and the bidirectional bus (212) is determined not to be rotating towards a recessive state; or The second timer circuit reaches a second specified value that is greater than the first specified value. [7] System according to one of the preceding claims, wherein the second logic circuit (210) blocks the communication between the bidirectional bus (212) and the second bus (224) by keeping a value communicated on the second bus (224) in an active state. [8] System according to any one of the preceding claims, wherein: the first logic circuit (220) is configured to determine that the first bus (222) becomes dominant when a logic value of the first bus (222) goes low; the first logic circuit (220) comprises a first NOR logic element which has inputs that are directly coupled to the first bus, an output of a first latch and an output of a second latch, wherein an input of the first latch is coupled to the first bus (222); the first NOR logic element has an output that is coupled to the first latch, wherein an output of the first latch is coupled to the second logic circuit via at least one timer circuit; and The output of the first latch generates the information that communication is in the first direction. [9] System according to claim 8, wherein: the first logic circuit comprises a second NOR logic element which has inputs that are directly coupled to the second bus (224), an output of the first latch and an output of the second latch, wherein an input of the second latch is coupled to the second bus (224); the second NOR logic element has an output that is coupled to the second latch, wherein an output of the second latch is coupled to the second logic circuit via at least one additional timer circuit; the second logic circuit comprises a first OR logic element and a third NOR logic element; wherein the first OR logic element has inputs which are coupled to the bidirectional bus (212) and to the output generated by the first logic circuit, wherein an output of the first OR logic element is coupled to the first bus (212); and the third NOR logic element has inputs which are coupled to the second bus (222) and to the input generated by the first logic circuit, wherein an output of the third NOR logic element is coupled to the bidirectional bus via a transistor. [10] Method for converting a bidirectional bus (212) into two unidirectional buses, comprising a first bus (222) which communicates data in a first direction and a second bus (224) which communicates data in a second direction, wherein the method comprises: Determine that the first bus (222) will be dominant over the second bus (224); Generating an indication that communication is in the first direction, based on the determination that the first bus (222) becomes dominant before the second bus (224); Allowing communication between the bidirectional bus (212) and the first bus (222) based on the indication that the communication is in the first direction; and Blocking communication between the bidirectional bus (212) and the second bus (224) based on the specification that the communication is in the first direction, wherein the determination that the first bus (222) becomes dominant before the second bus (224) is carried out using a timer circuit coupled to a logic element, wherein the first bus (222) is configured to transmit the data to an external device (150, 160), and wherein the second bus (224) is configured to receive the data from the external device (150, 160). [11] Method according to claim 10, further comprising triggering a change in the indication that communication is in the first direction when the first bus (222) becomes recessive for a specified duration. [12] Method according to claim 10, wherein the timer circuit is configured to: activate a signal indicating that communication is in the first direction in response to the detection that the first bus (222) is becoming dominant; and delay the reset of the signal in response to the detection that the first bus (222) is becoming recessive until the timer circuit reaches a specified value. [13] Method according to claim 10 or 11, wherein the first bus (222) is configured to receive the data from an external device, wherein the second bus (224) is configured to transmit the data to the external device (150, 160), and wherein the determining and generating steps are performed using a first and a second timer circuit coupled to a plurality of logic elements. [14] Method according to claim 13, wherein the first and second timer circuits receive a signal that the first bus (222) has become recessive, wherein the plurality of logic elements is coupled to the bidirectional bus (212), and wherein the plurality of logic elements is configured to: Determine that the bidirectional bus (212) became recessive; Determine that the bidirectional bus (212) rotates towards a recessive state; and Generating a statement that the first bus (222) became recessive. [15] Method according to claim 13 or 14, wherein the plurality of logic elements is configured to trigger a change in the indication that the communication is in the first direction, based on determining that: the first timer circuit reaches a first specified value and the bidirectional bus (212) becomes recessive; the first timer circuit reaches the first specified value and the bidirectional bus (12) is determined not to be rotating towards a recessive state; or The second timer circuit reaches a second specified value that is greater than the first specified value. [16] Method according to any one of claims 10 to 15, further comprising blocking the communication between the bidirectional bus (212) and the second bus (222) by keeping a value communicated on the second bus (224) in an active state. [17] Method according to any one of claims 10 to 16, further comprising: Determine, using a first logic circuit, that the first bus (222) becomes dominant when a logic value of the first bus (222) goes low; where: the first logic circuit comprises a first NOR logic element which has inputs which are directly coupled to the first bus (222), an output of a first latch and an output of a second latch, wherein an input of the first latch is coupled to the first bus; the first NOR logic element has an output that is coupled to the first latch, wherein an output of the first latch is coupled to the second logic circuit via at least one timer circuit; The output of the first latch generates the indication that communication is in the first direction; the first logic circuit comprises a second NOR logic element which has inputs that are directly coupled to the second bus, an output of the first latch and an output of the second latch, wherein an input of the second latch is coupled to the second bus; the second NOR logic element has an output that is coupled to the second latch, wherein an output of the second latch is coupled to the second logic circuit via at least one additional timer circuit; the second logic circuit comprises a first OR logic element and a third NOR logic element; wherein the first OR logic element has inputs which are coupled to the bidirectional bus and to the output generated by the first logic circuit, wherein an output of the first OR logic element is coupled to the first bus; and the third NOR logic element has inputs which are coupled to the second bus (224) and to the input generated by the first logic circuit, wherein an output of the third NOR logic element is coupled to the bidirectional bus (212) via a transistor. [18] System for enabling differential signal communication for a device which terminates a bidirectional bus, wherein the system comprises: a bidirectional signal isolator (200) configured to convert the bidirectional bus (212) into two unidirectional buses, comprising a first bus (22) which communicates data in a first direction and a second bus (224) which communicates data in a second direction, wherein the bidirectional signal isolator (200) comprises a logic circuit (210) configured to: Determine that the first bus (222) will be dominant over the second bus (224); Generating an indication that communication is in the first direction, based on the determination that the first bus (232) becomes dominant before the second bus (224); Allowing communication between the bidirectional bus (212) and the first bus (222) based on the indication that the communication is in the first direction; and Blocking communication between the bidirectional bus (212) and the second bus (224) based on the indication that the communication is in the first direction; and a differential signal transceiver, which is coupled to the first bus (222) and to the second bus (224) provided by the bidirectional signal isolator (200), for communicating data to and from the device (200) via a differential signal pair, wherein the determination that the first bus (222) becomes dominant over the second bus (224) is carried out using a timer circuit coupled to a logic element, wherein the first bus (222) is configured to transmit the data to an external device (150, 160), and wherein the second bus (224) is configured to receive the data from the external device (150, 160).

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