SYSTEMS AND METHODS FOR ADVANTAGED RESOLUTION AND BANDWIDTH OF A SUPPLY VOLTAGE

Abstract

Voltage monitoring device for measuring a power supply voltage on a chip, the device comprising the following: an analog-to-digital converter (ADC) (108) designed to sample the power supply voltage (Vdd) by passing through a time delay value (Tdelay) from a first number to a selected second number in order to obtain multiple samples of the power supply voltage (Vdd) for a single sampling point in time and to generate a sampling with an increased sampling rate for the single sampling point in time using the multiple samples.

Description

[0001] Devices, circuits, and the like use supply voltages to power and operate their circuitry. Power supplies generate the supply voltages used.

[0002] Supply voltages have characteristics such as noise, power supply noise, reliability, and the like. These characteristics can affect the operation of the equipment and circuits that use the supply voltages.

[0003] Additionally, the supply voltages can be generated on-chip using a different circuit arrangement that utilizes the generated supply voltages. Consequently, measuring the supply voltages can be difficult.

[0004] US 9,804,207 B1 discloses an integrated circuit (IC) located on an IC chip that includes an integrated voltage regulator circuit providing an internal supply voltage for the IC. A test-mode signal can be received from an external pin of the IC chip. In response to the test-mode signal, the IC can enter a test mode in which the internal supply voltage is delivered to components of the IC. Also in test mode, the voltage characteristics of the internal supply voltage are measured to generate an analog hold value. The measurements are performed in an analog range and across a variety of sampling and hold windows. Upon completion of a measurement window, the analog hold value is converted to a digital value. The digital value is then stored in a memory circuit. The digital value is then passed from the memory circuit to a reader outside the IC.

[0005] Techniques are needed that enable power supply generation and measurement of supply voltages in on-chip environments. Fig. Figure 1 is a block diagram illustrating an on-chip system with increased resolution and bandwidth of a supply voltage and signal-noise measurements, according to one or more embodiments.

[0006] Fig. Figure 2 is a graph illustrating exemplary signal values ​​for an on-chip system, according to one or more embodiments.

[0007] Fig. Figure 3 is a graph illustrating exemplary signal values ​​for an on-chip system, according to one or more embodiments.

[0008] Fig. Figure 4 is a diagram illustrating voltage monitoring (VMON) according to one or more embodiments.

[0009] Fig. Figure 5 is a graph illustrating an exemplary recording of values ​​showing noise superposition, according to one or more embodiments.

[0010] Fig. Figure 6 is a flowchart illustrating a method for increasing an effective sampling rate for measuring a supply voltage, according to one or more embodiments.

[0011] The present invention will now be described with reference to the accompanying drawing figures, in which reference numerals are used throughout to refer to identical elements, and in which the illustrated structures and devices are not necessarily drawn to scale.

[0012] As used herein, terms such as "component," "system," "interface," and the like are intended to refer to a computer-related entity, hardware, software (e.g., at execution), and / or firmware. For example, a component may be a processor (e.g., a microprocessor, controller, or other processing unit), a process running on a processor, a controller, an object, an executable program, a program, a storage device, a computer, a tablet PC, an electronic circuit, and / or a mobile phone with a processing unit. Some other examples of a component include a voltage regulator that provides power to various loads, including loads in motor vehicles; a processor or circuit arrangement in automotive electronics; a processor or circuit arrangement that...Examples include a component found on a credit card, a switch that actuates a valve in an anti-lock braking system (ABS), a switch that actuates an electric motor, a pressure sensor, a pressure sensor for an airbag system, a current sensor, a current sensor in an EPS system (EPS: electric power steering), and the like. For illustration, an application running on a server and the server itself can also be components. One or more components can be within a process, and a component can be located on one computer and / or distributed across two or more computers. A set of elements or a set of other components can be described herein, where the term "set" can be interpreted as "one or more."

[0013] Furthermore, these components can be executed, for example, from various computer-readable storage media that have different data structures stored on them, such as with a module. The components can communicate via local and / or remote processes, such as according to a signal that contains one or more data packets (e.g., data from one component interacting with another component in a local system, a distributed system, and / or across a network, such as the internet, a local area network, a wide area network, or a similar network, via the signal).

[0014] As another example, a component can be a device with specific functionality provided by mechanical parts operated by an electrical or electronic circuit arrangement, in which the electrical or electronic circuit arrangement can be operated by a software application or a firmware application executed by one or more processors. The one or more processors can be internal or external to the device and can execute at least part of the software or firmware application.As yet another example, a component can be a device that provides specific functionality by means of electronic components without mechanical parts; the electronic components may include one or more processors to execute software and / or firmware that at least partially provides the functionality of the electronic components.

[0015] As used herein, the term “circuit arrangement” may refer to, be part of, or include an application-specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and / or memory (shared, dedicated, or group) running on one or more software or firmware programs, a combination logic circuit, and / or other suitable hardware components that provide the described functionality. In some embodiments, the circuit arrangement may be implemented in one or more software or firmware modules, or functions associated with the circuit arrangement may be implemented therein. In some embodiments, a circuit arrangement may include logic that is at least partially executable in hardware.

[0016] Supply voltages are typically used as power sources in electronic devices. Additionally, signal lines are commonly used to communicate information between devices.

[0017] The supply voltages and signal lines can be located on a single chip, referred to as on-chip, with a separate circuit arrangement. The operation of this separate circuit arrangement may depend on the supply voltages, supply voltage generators, signal lines, and the like.

[0018] One technique for enabling the operation of the circuit arrangement, signal lines, and supply voltages involves measuring the supply voltages and signal lines. These measurements can be used to quantify and identify noise and other interference. Additionally, the measurements can be used to implement corrective measures to reduce noise and other interference.

[0019] One or more aspects / one or more embodiments are disclosed that enable on-chip measurement of signal lines, signals, power supply voltages, and / or power supply noise. It is understood that there is typically a trade-off between the sampling rate and the measurement resolution. This trade-off can limit the accuracy and bandwidth of signal lines and supply voltages. The embodiments also include a technique for combining multiple measurements to increase measurement accuracy and bandwidth.

[0020] Other approaches to achieving better measurement accuracy and bandwidth rely on complex and expensive ADCs (analog-to-digital converters) in ASICs. However, it should be noted that manufacturing process limitations and the large amount of die area occupied by these complex ADCs restrict their use in a single chip and / or product line.

[0021] Fig. Figure 1 is a block diagram illustrating an on-chip system 100 with increased resolution and bandwidth of a supply voltage and signal-to-noise measurements, according to one or more embodiments. System 100 is provided for illustrative purposes, and it is understood that suitable variations may be considered.

[0022] A relatively high sampling rate of a signal / power supply can be achieved by combining data from a high-resolution (10-bit or 12-bit) ADC operating at a low sampling rate with data from a low-resolution (5-bit or 6-bit) high-sampling-rate circuit utilizing a voltage-controlled oscillator (VCO), referred to as voltage monitoring (VMON) or voltage frequency monitoring. The System 100 utilizes the ADC and the VMON to maintain the relatively high sampling rate useful for noise analysis, signal analysis, and similar applications.

[0023] In this exemplary System 100, an ASIC is present that has the capability to start / trigger a use-case / application-related portion of code at a time defined by a timer module (IP block on the chip). The ASIC utilizes the capability of such a chip to start / trigger the ADC at varying time delays relative to the application code, thereby increasing the effective sampling rate. Furthermore, this System 100 enables the calibration of VMON frequency data against ADC data and can use a calibrated lookup table to overlay and / or combine VMON measurements on or with ADC-generated samples.

[0024] The system 100 includes a system-on-chip (SoC) 112, a phase-locked loop (PLL) 102, a divider 104, a timer 106, an analog-to-digital converter (ADC) 108, a voltage monitoring system (VMON) 110, an output amplifier 116, a memory buffer 114 and one or more power supply generators / sources 120.

[0025] The SoC 112 can be or include an application-specific integrated circuit (ASIC) and operates using the supply voltage 118. The SoC 112 is initialized or started in response to an application start signal. The SoC 112 can incorporate a variety of suitable circuit arrangements, including IP blocks.

[0026] The power supply 120 provides or generates a power supply voltage 118 (Vdd). The supply 118 is provided or coupled as an input to the ADC 108, the SoC 112, and the VMON 110.

[0027] The VMON 110 is typically free-running, and its output (VMON output) is a frequency that can be considered a clock signal. The frequency of the VMON output is related to a voltage or voltage level at an input of the VMON 110. Here, the voltage level at the input is the supply voltage 118.

[0028] The PLL 102 generates an oscillator signal (CLK) TIM ) at its output, such as a local oscillator (LO) signal. The divider receives the oscillator signal at its input and divides the oscillator signal by a selected division value to generate a divided clock signal for the ADC 108, known as CLK. ADC referenced. Thus, the oscillator signal operates at a frequency of the selected division value multiplied by the divided clock CLK. ADC It is understood that other suitable techniques for generating the clock signals will be considered.

[0029] Timer 106 receives the oscillator signal and is designed to generate an ADC trigger (Start-ADC) or a signal with a specific time delay (Tdelay) relative to the SoC 112 application startup. The Start-ADC is based on an ADC start counter value and / or Tdelay. Thus, ADC 106 starts or delays a period of time, specified as Tdelay, after the SoC 112 has started.

[0030] Timer 106 and ADC 108 operate with the same root clock, i.e., the PLL (phase-locked loop) output (CLK). TIM ) is used directly for timer 106, whereas the PLL output is divided down and used as a sampling clock CLK. ADC for the ADC 108. As soon as the application code is started in the SoC 112, one or more subsystems and IPs in the SoC 112 are activated, which leads to changes in power consumption and supply voltage (Vdd) noise.

[0031] Timer 106 can be configured with an application start counter value and an ADC start counter value. These counter values ​​can be selected and / or adjusted to control when the application code of the SoC 112 starts and when the ADC 108 starts operating. The difference between the application start counter value and the ADC start counter value is the Tdelay or ADC start delay described above.

[0032] In operation, the ADC 108 can cycle through values ​​from 1 to a selected value for various Tdelay values ​​to generate multiple iterations for a single point or sample point. These multiple iterations can then be combined, averaged, and otherwise processed.

[0033] The control circuit arrangement 122 can be designed to perform the sweep of Tdelay values ​​for the ADC 108, to set and / or adjust Tdelay values ​​for the timer 106, to adjust the selected division for the divider 104, to convert the VMON output (a frequency based on the supply voltage 118) into a voltage, to calibrate the VMON 110, to generate a lookup table of voltage values ​​indexed by the frequency for the VMON 110, to perform an analysis of sampled values, and the like.

[0034] It goes without saying that suitable variations of System 100 will be considered.

[0035] Fig. Figure 2 is a graph illustrating exemplary signal values ​​200 for an on-chip system according to one or more embodiments. The signal values ​​200 are provided as examples for illustrative purposes, and it is understood that other values, frequencies, and the like may be considered. The signal values ​​200 are for a "Case 1".

[0036] The signal values ​​200 include a supply voltage (Vdd) and an application start (code start) counter value, an ADC start counter value, and a split clock (CLK). ADC ).

[0037] An x-axis represents increasing time and a y-axis represents increasing amount.

[0038] The supply voltage is generated by a voltage source, such as source 120.

[0039] The code start is the application start counter value for the application code of the SoC 112.

[0040] The ADC start is the ADC start counter value for the ADC 108.

[0041] The split time signature (CLK) ADC ) is the clock signal used by the ADC 108. In this example, the divided clock signal is 1 / 100 of the oscillator signal (CLK). TIM ).

[0042] In this example, the code start has a value of 100 and the ADC start has a value of 101. As a result, the SoC 112, or its application code, starts after 100 CLK. TIM -cycles and the ADC starts after 101 CLK TIM -cycles. Thus, in this example, Tdelay is 1 or 1 CLK. TIM -Cycle.

[0043] Fig. Figure 3 is a graph illustrating exemplary signal values ​​300 for an on-chip system according to one or more embodiments. The signal values ​​300 are provided as examples for illustrative purposes, and it is understood that other values, frequencies, and the like may be considered. The signal values ​​300 are for a "Case 2".

[0044] The signal values ​​300 include a supply voltage (Vdd) and an application start (code start) counter value, an ADC start counter value, and a split clock (CLK). ADC ).

[0045] An x-axis represents increasing time and a y-axis represents increasing amount.

[0046] The supply voltage is generated by a voltage source, such as source 120.

[0047] The code start is the application start counter value for the application code of the SoC 112.

[0048] The ADC start is the ADC start counter value for the ADC 108.

[0049] The split time signature (CLK) ADC ) is the clock signal used by the ADC 108. In this example, the divided clock signal is 1 / 100 of the oscillator signal (CLK). TIM ).

[0050] In this example, the code start has a value of 78 and the ADC start has a value of 79. As a result, the SoC 112, or its application code, starts after 78 CLK. TIM -cycles and the ADC starts after 79 CLK TIM -cycles. Thus, in this example, Tdelay is 1 or 1 CLK. TIM -Cycle.

[0051] As soon as the application code activates IPs / modules in the SoC 112, the ADC start is triggered. Changes or noise in the Vdd are generated because the application code has started. This noise is sampled by the ADC 108. Assuming that the application code, the silicon portion, the environmental conditions, and the configuration are the same in both cases, the generated Vdd noise would also be the same (with respect to the application start point on the time axis). Consequently, the ADC 108 samples the Vdd noise at different points for the two cases (200 and 300). The Tdelay (indirectly the difference in the number of timer cycles) between the application start and the ADC start can also be changed, for example, by test code. Instead of using a timer cycle delay of 1, as shown in Case 1 and Case 2, this count difference can be iterated from 1 to another value, for example.

[0052] If it's a CLK TIM -cycles for each CLK ADC If there is a -cycle, then the ADC values ​​read for the count difference Tdelay would correspond to those values ​​obtained using the delay of Tdelay MOD N can be read.

[0053] Iterating through different Tdelay values ​​generates multiple ADC readings / measurements by the ADC 108 for the same point in the Vdd noise. These duplicated values ​​can then be averaged or otherwise combined to produce a final output (after eliminating outliers). As shown above, this technique of iterating through possible Tdelay values ​​can effectively increase the Vdd noise sampling rate by N times.

[0054] Fig. Figure 4 is a diagram illustrating a voltage monitoring device (VMON) 400, according to one or more embodiments. The VMON 400 is provided for illustrative purposes and it is understood that suitable variations may be considered.

[0055] The VMON 400, also known as a voltage frequency monitor, can be used in the System 100 as the VMON 110 described above.

[0056] A voltage-controlled high-frequency oscillator (VCO) 404 can be used as the voltage monitoring (VMON) 110. Sweeping through various time delays with the ADC 108 results in a (f ADC *N) effective sampling rate. It is understood that measuring or capturing high-frequency noise components of the supply voltage is of interest.

[0057] To focus on the high-frequency noise components, the VMON 400 can include a multiplexer 402 and a circuit arrangement 408, which provide high-frequency (HF) coupling with the VCO 404. The HF coupling operates on the supply voltage (Vdd) and a reference voltage. Thus, the input signal (the supply voltage) is AC-coupled and supplied to the VCO 404. Consequently, one output of the VCO 404 is typically sensitive only to high-frequency noise components.

[0058] The VCO 404 can be configured with a selected voltage-to-frequency linearity for a selected noise range or noise range of interest.

[0059] The VMON 400 can also be calibrated for a selected noise range. In one calibration example, a supply voltage or other signal is directly connected to an input of the VCO 404. A frequency of a VCO output signal / clock 406, along with sampled ADC values ​​from the ADC 108, is collected using a test pattern / code that generates a known Vdd signal, such as an example Vdd signal with noise. Specific ADC values ​​(with f ADC *N sampling rate) and a VCO frequency at these times are then analyzed to generate a frequency-to-voltage (Vdd in mV) lookup table (LUT).

[0060] The Vdd (or signal) is then coupled to the VCO input via a 410 DC blocking capacitor. A fixed (noise-free) voltage reference (Vref) is used to bias the VCO input to a suitable voltage, typically close to the supply voltage or the supply voltage DC value. The application code is then executed using the time delay (Tdelay) technique described above, and the VCO output frequency is also measured / captured. The LUT generated during calibration is used to interpolate voltage values ​​between read ADC values.

[0061] Fig. Figure 5 is a graph illustrating an exemplary acquisition of values ​​500, showing a noise superposition, according to one or more embodiments. The values ​​500 are provided as an example for illustrative purposes.

[0062] The values ​​500 can be generated using the system 100 described above and suitable variants thereof.

[0063] The values ​​500 illustrate how the VMON 110 can be used in a noise superposition method or noise superposition technique to obtain a measured supply voltage.

[0064] The graph represents an x-axis showing time in nanoseconds (ns) and magnitude along a y-axis.

[0065] A first graphical representation shows values ​​of Vdd in volts over time.

[0066] A second graph, shown below the first, displays measured or read values ​​of Vdd by the ADC 108. The ADC measurements can be generated by iterating through the Tdelay values, as described above.

[0067] A third graphical representation, shown below the second graphical representation, shows read ADC values ​​shifted by an amount which in this example is 30 ns.

[0068] A fourth graphic, shown below the third graphic, depicts a VCO output frequency associated with the VMON 110. The VCO output is a frequency based on the supply voltage (Vdd).

[0069] A fifth graph, shown below the fourth graph, depicts the measured Vdd over time. A lookup table, indexed by frequency, can be referenced to obtain voltages. These voltages can then be interpolated with the ADC values ​​read from the third graph to generate the measured Vdd shown in the fifth graph.

[0070] Fig. Figure 6 is a flowchart illustrating a method 600 for increasing an effective sampling rate for measuring a supply voltage, according to one or more embodiments.

[0071] Method 600 can be implemented using the system 100 described above and variants thereof.

[0072] Procedure 600 begins at block 602, which provides an on-chip system with increased resolution and bandwidth of a supply voltage and signal-noise measurements.

[0073] A phase-locked loop (PLL) of the on-chip system generates an oscillator signal (CLK) at block 604. TIM The oscillator signal can also be referred to as a local oscillator (LO) signal.

[0074] A divider generates a divided clock signal at block 606 (CLK). ADC ) by dividing the oscillator signal by a factor of N, where N is an integer.

[0075] A voltage monitoring system (VMON) is calibrated at block 608 for a selected frequency and / or noise range. In one example, a voltage lookup table (LUT) is generated using the supply voltage and a noise-free voltage reference (Vref).

[0076] At block 610, an ADC receives multiple supply voltage (Vdd) measurements using or by iterating through multiple time delay (TDelay) values ​​using counter values.

[0077] The Tdelay is the time interval between the startup of a SoC and the startup of an ADC. Counter values ​​are used in a timer to generate the startup signals / triggers (start ADC and application startup).

[0078] If it's a CLK TIM -cycles for each CLK ADC If a -cycle exists, then the ADC values ​​read for the count difference Tdelay correspond to those values ​​obtained using a delay of

[0079] Tdelay MOD N can be read.

[0080] Iterating through different Tdelay values ​​generates multiple ADC readings / measurements for the same point in the Vdd noise. These duplicated values ​​can then be averaged for a final output (after eliminating outliers). This technique of iterating through the possible Tdelay values ​​can effectively increase the Vdd noise sampling rate by N times.

[0081] The iteration generates multiple iteration values ​​(from 1 to N for Tdelay) for each point or sample point. (See Fig. 2 and Fig. 3) The multiple values ​​can be averaged or otherwise combined to generate an ADC sample based on the pass values.

[0082] A VMON or VCO output is also measured at block 612. The VMON or VCO output frequency is associated with the supply voltage measurements from block 610. A lookup table of voltages, indexed by frequency, can be used to convert the measured output frequency to a voltage or VMON-measured voltage. The VMON-measured voltage(s) can be interpolated with the ADC-generated measurements to provide an improved sampling rate of the supply voltage.

[0083] The supply voltage measurements and the VMON output measurements are analyzed for noise and the like at block 614.

[0084] It is understood that variations of the 600 procedure are taken into consideration, including the functionality and features of the arrangements and systems described above.

[0085] Although the method(s) is / are illustrated and described as a series of actions or events, it is understood that the illustrated sequence of such actions or events is not to be interpreted as restrictive. For example, some actions may occur in a different order and / or simultaneously with other actions or events than those illustrated and / or described herein. In addition, it may not be necessary to implement one or more aspects or embodiments of the present disclosure. One or more of the actions depicted herein may also be carried out in one or more separate actions and / or phases.

[0086] While the disclosed subject matter has been described in connection with various embodiments and, where applicable, corresponding figures, it is understood that other similar embodiments may be used, or modifications and additions may be made to the described embodiments, in order to perform the same, a similar, alternative, or replacement function as the disclosed subject matter without deviation from it. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, but rather should be interpreted in the sense and scope of protection of the attached claims below.

[0087] With particular consideration of the various functions performed by the components or structures (assemblies, devices, circuits, systems, etc.) described above, it is intended that the expressions (which include a reference to a “means”) used to describe such components, unless otherwise specified, correspond to any component or structure that performs the specified function of the described component (which is, for example, functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary implementations of the invention illustrated herein.Furthermore, although a particular feature may have been disclosed with respect to only one of several implementations, such a feature may be combined with one or more other features of the other implementations, as may be desirable and advantageous for any given or particular application.

[0088] It is understood that the claimed subject matter may be implemented as a method, device, or manufactured article using conventional programming and / or design methods to produce software, firmware, hardware, or any combination thereof to control a computer to implement the disclosed subject matter (e.g., the ones described in the Fig. 1, Fig.The systems, arrangements, and the like shown in Section 2, etc., are non-limiting examples that may be used to implement the above methods. The term "manufactured article" as used here is intended to include a computer program accessible by any computer-readable device, medium, or media. Naturally, those skilled in the art will recognize that many modifications to this configuration can be made without altering the scope of protection or the nature of the claimed subject matter.

[0089] It is understood that the aspects described here can be implemented by hardware, software, firmware, or any combination thereof. When implemented in software, functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that enables the transfer of a computer program from one location to another. Storage media or a computer-readable storage device can be any available media accessible by a general-purpose or specialized computer.By way of example, and not as a limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other tangible and / or non-volatile medium that can be used to carry or store desired information or executable instructions. Furthermore, any connection is appropriately referred to as a computer-readable medium.For example, if software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted-pair cable, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, then the coaxial cable, fiber optic cable, twisted-pair cable, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of medium. Disk and disc, as used herein, include a compact disc (CD), a laser disc, an optical disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, where disks typically reproduce data magnetically, whereas discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0090] Various illustrative logics, logic blocks, modules, and circuits described in connection with aspects disclosed herein may be implemented or performed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform functions described herein. A general-purpose processor may be a microprocessor, but alternatively, a processor may be any conventional processor, controller, microcontroller, or state machine.A processor can also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, several microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Additionally, at least one processor can comprise one or more modules capable of performing one or more of the functions and / or actions described herein.

[0091] For software implementation, the techniques described herein can be implemented using modules (e.g., procedures, functions, and so on) that perform the functions described herein. Software code can be stored in memory units and executed by processors. A memory unit can be implemented within a processor or externally to a processor, in which case a memory unit can be communicatively coupled to the processor by various means known in the art. Furthermore, at least one processor can contain one or more modules capable of performing the functions described herein.

[0092] Furthermore, the actions of a method or algorithm described in connection with aspects disclosed herein can be implemented directly in hardware, in a software module executed by a processor, or a combination thereof. A software module can be in RAM, flash memory, ROM, EPROM, EEPROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium can be coupled to a processor such that the processor can read information from and write information to a storage medium. Alternatively, a storage medium can be integral with a processor. Furthermore, in some aspects, a processor and storage medium can be contained within an ASIC. Additionally, an ASIC can be contained within a user terminal device.Alternatively, a processor and storage medium can exist as discrete components in a user terminal device. Furthermore, in some aspects, the steps and / or actions of a procedure or algorithm can exist as one or any combination or set of codes and / or instructions on a machine-readable and / or computer-readable medium, which may be incorporated into a computer program product.

[0093] Additionally, the phrase "or" is to be understood as an inclusive "or" rather than an exclusive "or". That is to say, "X uses A or B" is to mean any of the natural inclusive permutations unless otherwise specified or clear from the context. That is to say, if X uses A; X uses B; or X uses both A and B, then "X uses A or B" is satisfied under any of the preceding cases. Furthermore, the articles "a" and "an", as used in the item specification and the attached drawings, should generally be understood to mean "one or more", unless otherwise specified or the context clearly directs them to a singular form.

[0094] Furthermore, the articles “ein” and “eine”, as used in this application and the attached claims, should generally be understood to mean “one or more”, unless otherwise specified or the context clearly indicates a singular form.

[0095] A voltage monitoring device for measuring a power supply voltage is disclosed. The device comprises an analog-to-digital converter (ADC). The ADC is designed to sample the power supply voltage by sweeping through a time delay value from a first number to a selected second number, in order to obtain multiple samples of the power supply voltage for a single sampling point in time and to generate a sample with an increased sampling rate for the single sampling point in time using the multiple samples.

[0096] Another voltage monitoring device for measuring a power supply voltage is disclosed. The device includes an analog-to-digital converter (ADC), a voltage-controlled oscillator (VCO), and a circuit arrangement. The ADC is designed to generate supply voltage samples of the power supply voltage at an increased sampling rate based on multiple sweep samples. The VCO is designed to generate a VCO frequency output based on the power supply voltage. The circuit arrangement is designed to determine VCO-measured samples based on the VCO frequency output and to combine the determined VCO-measured samples with the ADC-generated supply voltage samples.

[0097] A method for measuring a supply voltage is disclosed. The method includes generating an oscillator signal and a split clock based on the oscillator signal; calibrating a voltage-controlled oscillator (VCO) for a selected frequency and noise range; obtaining multiple supply voltage measurements by an analog-to-digital converter (ADC) by iterating through multiple time delay values, where the time delay values ​​specify a delay between the start of application code and the start of the ADC; and generating multiple frequency measurements by the VCO based on the supply voltage.

[0098] A voltage monitoring device for measuring a power supply voltage on a chip is disclosed. The device includes an ADC, a voltage-controlled oscillator (VCO), and a circuit arrangement. The ADC is designed to generate supply voltage samples of the power supply voltage at an increased sampling rate based on multiple sweep samples. The VCO is designed to generate a VCO frequency output based on the power supply voltage. The circuit arrangement is designed to determine VCO-measured samples based on the VCO frequency output and to combine the determined VCO-measured samples with the ADC-generated supply voltage samples.

[0099] An arrangement is disclosed for an on-chip system with increased resolution for supply voltage measurements. The system includes a phase-locked loop (PLL), a divider, and a timer. The PLL is designed to generate an oscillator signal. The divider is designed to split the oscillator signal to generate a split clock signal. The timer is designed to generate an application start signal and an analog-to-digital converter (ADC) start signal based on the oscillator signal and a timer delay (Tdelay). The timer delay (Tdelay) is based on the application start signal and the ADC start signal.

[0100] With particular consideration of the various functions performed by the components or structures (assemblies, devices, circuits, systems, etc.) described above, it is intended that the expressions (which include a reference to a “means”) used to describe such components, unless otherwise specified, correspond to any component or structure that performs the specified function of the described component (which is, for example, functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary implementations of the invention illustrated herein.Furthermore, although a particular feature of the invention may have been disclosed with respect to only one of several implementations, such a feature may be combined with one or more other features of the other implementations, as may be desirable and advantageous for any given or specific application. Moreover, to the extent that the expressions "including," "includes," "comprising," "incorporating," "with," or variants thereof are used both in the detailed description and in the claims, such expressions shall be understood to mean inclusive in a manner similar to the expression "comprehensive."

Claims

[1] A voltage monitoring device for measuring a power supply voltage on a chip, the device comprising: an analog-to-digital converter (ADC) (108) configured to sample the power supply voltage (Vdd) by sweeping a time delay value (Tdelay) from a first number to a selected second number to obtain a plurality of samples of the power supply voltage (Vdd) for a single sample point in time and to generate a sample at an increased sample rate for the single sample point in time using the plurality of samples. [2] The apparatus of claim 1, wherein the generated sample is an average of the plurality of samples. [3] Apparatus according to any one of claims 1 or 2, wherein the selected second number is a number of oscillator signal (CLK TIM -)cycles for each clock cycle of the ADC (108). [4] Apparatus according to any one of claims 1 to 3, further comprising a timer configured to generate the time delay value (Tdelay) and an associated application start signal. [5] The apparatus of any one of claims 1 to 4, further comprising a system-on-chip (SoC) configured to execute application code based on the associated application start signal, wherein the SoC introduces noise into the power supply. [6] The apparatus of any one of claims 1 to 5, further comprising a voltage controlled oscillator (VCO), the VCO having a VCO frequency output proportional to a voltage level of the power. [7] The apparatus of claim 6, wherein the VCO is AC coupled to the power supply and a reference voltage. [8] Apparatus according to claim 6 or 7, further comprising a frequency-to-voltage look-up table for the VCO and circuitry arranged to interpolate an additional sample for the single sample point using the look-up table and the VCO frequency output. [9] The apparatus of any one of claims 6 to 8, further comprising circuitry configured to generate a frequency-to-voltage lookup table for the VCO based at least in part on the sample generated by the ADC (108). [10] The apparatus of any one of claims 1 to 9, further comprising a phase-locked loop (PLL) (102) and a divider (104), wherein the PLL (102) is configured to generate a CLK TIM -clock signal for a timer (106), and the divider (104) is designed to generate an ADC clock signal (CLK ADC ) for the ADC (108) based on the CLK TIM-clock signal to generate. [11] A voltage monitoring device for measuring a power supply voltage (Vdd) on a chip, the device comprising: an analog-to-digital converter (ADC) (108) configured to generate supply voltage samples of the power supply voltage (Vdd) at an increased sampling rate based on a plurality of sweep samples; a voltage-controlled oscillator (VCO) configured to generate a VCO frequency output based on the power supply voltage (Vdd); and circuitry configured to determine VCO-measured samples based on the VCO frequency output and to combine the determined VCO-measured samples with the supply voltage samples generated by the ADC (108). [12] The apparatus of claim 11, wherein the ADC (108) is configured to generate the plurality of sweep samples each clock cycle of an ADC clock used by the ADC (108). [13] The device of claim 11 or 12, further comprising a system-on-chip (SoC) including an application-specific integrated circuit (ASIC). [14] The device of claim 13, wherein the device further includes a power supply configured to generate the power supply voltage (Vdd), and the device is an on-chip system located on a single chip. [15] Apparatus according to any one of claims 11 to 14, wherein the VCO is calibrated for a selected noise range. [16] Apparatus according to any one of claims 11 to 15, further comprising additional circuitry configured to analyze the supply voltage samples of the ADC (108) and the determined VCO-measured samples to determine bandwidth and resolution of a power supply. [17] A method for measuring a supply voltage, comprising: Generating an oscillator signal and a divided clock based on the oscillator signal; Calibrating a voltage-controlled oscillator (VCO) for a selected frequency range and noise level; Obtaining a plurality of supply voltage measurements of the supply voltage by an analog-to-digital converter (ADC) (108) by passing a plurality of time delay values ​​(Tdelay), the time delay values ​​(Tdelay) indicating a delay between a start of application code and a start of the ADC (108); and Generate multiple frequency measurements by the VCO based on the supply voltage. [18] A method according to claim 17, wherein the number of time delay values ​​(Tdelay) is selected to provide an increased effective sampling rate. [19] A method according to any one of claims 17 or 18, wherein the plurality of supply voltage measurements are each based on a plurality of sweep samples generated by sweeping the plurality of time delay values ​​(Tdelay). [20] The method of any one of claims 17 to 19, further comprising generating a plurality of VCO voltage measurements using a lookup table referenced by the plurality of frequency measurements.

Images