MANUFACTURING PROCESS FOR VARIOUS ALL-ROUND GATE TRANSITOR DEVICES

Abstract

Method for forming a semiconductor device (200), comprising: Providing a substrate (208) comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers arranged over the substrate (208), wherein the first and second semiconductor layers (222, 220) have different material compositions and are arranged alternately with each other; Structuring the first semiconductor layers (222) and the second semiconductor layers (220) to form a first fin (212c) and a second fin (212b, 212d); Removing the first semiconductor layers (222) from the first fin (212c) and the second fin (212b), such that a first section of the structured second semiconductor layers (220) becomes first floating nanostructures (220) in the first fin (212c), and a second section of the structured second semiconductor layers (220) becomes second floating nanostructures (220) in the second fin (212b); Doping a threshold-modifying impurity into the first suspended nanostructures (220) in the first fin (212c), wherein the doping of the threshold-modifying impurity includes the application of a plasma-assisted low-temperature doping process; Forming a first gate stack (260c) over the first fin (212c), wherein a section of the first gate stack (260c) envelops the first floating nanostructures (220), thereby forming a first transistor with a first threshold voltage; and Forming a second gate stack (260b) over the second fin (212b), wherein a section of the second gate stack (260b, 260d) envelops the second floating nanostructures (220), thereby forming a second transistor with a second threshold voltage which is higher than the first threshold voltage.

Description

BACKGROUND

[0001] The integrated semiconductor (semiconductor) circuitry industry has recently experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. As ICs have evolved, functional density (the number of interconnected components per unit area) has generally increased, while geometric size (the smallest component or trace that can be created using a manufacturing process) has decreased. This miniaturization process typically offers advantages through increased production efficiency and a reduction in associated costs.Furthermore, such miniaturization has also increased the complexity of IC processing and manufacturing, and similar developments in IC processing and manufacturing are needed to realize these advances.

[0002] For example, multi-gate devices have been introduced with the intention of improving gate control by increasing gate-channel coupling, reducing turn-off current, and mitigating short-channel effects (SCE). Such a multi-gate device is a nanosheet device, such as a wraparound gate transistor (GAA transistor), whose gate structure extends around its horizontal channel area, thus providing access to the channel area from all sides. These nanosheet transistors are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, which allows them to be aggressively scaled while maintaining gate control and reducing SCE.Due to problems such as a smaller depletion area and channel volume, as well as reduced mobility induced by heavy doping, it is difficult to control the threshold voltage (Vt) of conventional nanosheet devices. Therefore, while conventional nanosheet transistors have generally been suitable for their intended purposes, they cannot be considered satisfactory in all respects.

[0003] A method for diffusing germanium into the nanowires of PMOS FETs while preventing this in NMOS FETs is known from US 2017 / 0229538 A1. A method for forming various GAA transistors is known from US 2019 / 0280107 A1. In this method, a PMOS FET, specifically an LVT and an SVT, is formed based on a first fin and a second fin, respectively. For tuning, a material layer is selectively applied to the surfaces of nanolayer channels of the LVT, and the tuning material, e.g., germanium, is mixed into the material, e.g., silicon, of the nanolayer channels. A device and a method are known from US 2019 / 0393350 A1. Another device and a further method are known from US 2018 / 0053690 A1. A device is known from US 2018 / 0182848 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not shown to scale. In fact, the dimensions of the various elements may have been arbitrarily enlarged or reduced for the sake of clarity. The Fig. 1A, Fig. 1B and Fig. 1C are flowcharts of procedures for forming a semiconductor device in accordance with various aspects of the present disclosure. The Fig. 2, Fig. 13 and Fig. Figure 23 are perspective views of a semiconductor structure provided in accordance with various aspects of the present disclosure. The Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 24, Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30, Fig. 31 and Fig. Figure 32 shows cross-sectional views of a semiconductor structure at various stages of fabrication, in accordance with the respective processes described in the Fig. 1A - 1C are constructed in accordance with some embodiments of the present disclosure.

[0005] The examples of Fig. Items 1B, 13 and 14 to 22 do not belong to the claimed invention. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments, or examples, for implementing various features of the disclosure, not all of which relate to the claimed invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact with each other, but may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements cannot be in direct contact with each other. Furthermore, the present disclosure may repeat reference numerals and / or symbols in the various examples.This repetition serves the purpose of simplification and clarity, and does not in itself prescribe any relationship between the various embodiments and / or arrangements discussed.

[0007] Furthermore, the formation of an element that is connected and / or coupled to another element in the present disclosure can have embodiments in which the elements are formed in direct contact with each other, and can also have embodiments in which additional elements are formed between the elements, so that the elements cannot be in direct contact with each other. In addition, terms of spatial relationships, such as "lower," "upper," "horizontal," "vertical," "above," "over," "below," "underneath," "upwards," "downwards," "above," "below," etc., as well as their derivatives (for example, adverbial forms thereof, etc.), are used in the present disclosure of the relationship of one element to another element. The terms of spatial relationships are intended to cover different orientations of the device that has the features.Furthermore, where a number or range of numbers is described herein by means of "approximately", "about", and the like, the term shall include numbers within a reasonable range containing the described number, for example, within + / - 10% of the described number or other values ​​understandable to persons skilled in the art. For example, the expression "approximately 5 nm" includes the dimensional range from 4.5 nm to 5.5 nm.

[0008] The present disclosure relates generally to semiconductor devices and methods for their formation. In particular, the present disclosure relates to the tuning of a threshold voltage (Vt) in nanolayer devices, such as all-around gate devices (GAA devices).

[0009] A nanolayer device can be any device whose gate structure, or sections thereof, is formed on four sides of a channel region (for example, surrounding a section of a channel region). It is understood from the outset that the channel region of a nanolayer device can be formed from channel elements, such as nanosheets, but also nanowires, nanobeams, and / or other suitable structures. In some embodiments, the channel region of a nanolayer device has several horizontal nanowires, nanosheets, and / or nanobeams that are vertically spaced apart, making the nanolayer device a stacked horizontal nanolayer device. Due to their nanoscale dimensions, the channel elements can also be referred to as nanostructures (or floating nanostructures).The nanolayer devices presented herein feature p-metal oxide semiconductor nanolayer devices or n-metal oxide semiconductor nanolayer devices. Furthermore, the nanolayer devices have one or more channels (for example, nanowires) associated with a single, contiguous gate structure or multiple gate structures. A person with average technical knowledge may recognize other examples of semiconductor devices that could benefit from aspects of this disclosure.

[0010] This paper presents embodiments of nanolayer devices used to realize n- and p-transistors with vertically stacked n-channels and p-channels arranged on two closely spaced fins, commonly referred to as complementary metal-oxide-semiconductor field-effect transistors (MOSFETs), which utilize complementary and symmetrical pairs of p- and n-transistors. Complementary MOSFETs implemented using GAA devices are advantageous in many integrated circuits (ICs), although shrinking the device size introduces various challenges for certain fabrication processes. For example, due to issues such as a smaller depletion region and channel volume, as well as mobility degradation induced by heavy doping, tuning the threshold voltage for p-transistors in the complementary transistor pairs becomes increasingly difficult.Achieving different threshold voltages for p-transistors in various regions (e.g., a low Vt region (LVt region), a standard Vt region (SVt region), and / or a high Vt region (HVt region)) remains a challenge. Some methods require complex metal work function control to tune threshold voltages for p-transistors. However, such an approach often increases process complexity (e.g., it is difficult to deposit complex metal work function layers in high aspect ratio gate pits) and leads to defects.

[0011] The present disclosure addresses the above problems by providing methods for forming nanosheet transistors on multiple fins. In accordance with some embodiments, after forming floating nanostructures of a first fin for an n-GAA transistor and floating nanostructures of a second fin for a p-GAA transistor, a method implants a threshold-modifying impurity into the floating nanostructures of the p-GAA transistor. In some embodiments, the threshold-modifying impurity is germanium (Ge). The implantation of the threshold-modifying impurity forms a characteristic distribution within the p-channel. Furthermore, critical dimensions (CD) of the floating nanostructures for the p-GAA transistor can be trimmed to tune the threshold voltage.CD trimming and doping with the threshold-modifying impurity can be combined to achieve a wider tuning range for the threshold voltages. The various methods in the embodiments of this disclosure can be applied to any p-FET region in an IC to achieve the same threshold voltage setting, or to specific p-FET regions to achieve multiple threshold voltages in different regions, for example, to form LVt regions, SVt regions, and / or HVt regions. Consequently, threshold voltage tuning in p-GAA transistors can be achieved with a simplified fabrication process.

[0012] Fig. Figure 1A is a flowchart of a method 100 for forming a semiconductor device 200 (also referred to as device 200) in accordance with various aspects of the present disclosure. The method 100 is only an example. Additional operations may be provided before, during, and after the method 100, and some of the described operations may be substituted, omitted, or postponed for additional embodiments of the method. Some embodiments of the method 100 are described below in conjunction with the Fig. 2 - 12 described. Fig. Figure 2 is a perspective view of device 200. Fig. Figures 3-12 are (side-by-side) cross-sectional views of the device 200 along sections AA and BB, which are shown in Fig. Figure 2 shows the respective channel regions intersecting along the longitudinal direction of the transistors (in the YZ plane). Fig. Figure 12 also shows a cross-sectional view which cuts through the channel area along the longitudinal direction of an additional p-GAA transistor of the device 200.

[0013] In process 102, procedure 100 ( Fig. 1A) the device 200, which has a first device structure 206a and a second device structure 206b, as shown in Fig. Figure 2 shows that each of the device structures 206a and 206b comprises the substrate 208, the isolation structure 210, the fin 212a or 212b, which has alternating and vertically stacked semiconductor layers 220 and 222 (also referred to as stacked fin 212a or 212b), and a dummy gate structure 216, which engages with the stacked fins 212a and 212b. As explained in more detail below, an example n-GAA transistor is formed from the first device structure 206a, and an example p-GAA transistor is formed from the second device structure 206b. The device 200 is provided for illustrative purposes and does not necessarily restrict the embodiments of the present disclosure to a specific number of components, a specific number of regions, or a specific arrangement of structures or regions.Furthermore, the device 200 is an intermediate device or a section thereof manufactured during the processing of an IC, which may include static random access memory (SRAM) and / or logic circuits, passive components such as resistors, capacitors and inductors, and active components such as p-type field-effect transistors (PFET), n-type FET (NFET), multi-gate FET such as FinFET, metal-oxide-semiconductor field-effect transistors (MOSFET), complementary metal-oxide-semiconductor transistors (CMOS transistors), bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells and combinations thereof.

[0014] In some embodiments, substrate 208 contains silicon. Alternatively or additionally, substrate 208 contains another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as silicon-germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In some embodiments, substrate 208 contains one or more materials from Groups III-V, one or more materials from Groups II-IV, or combinations thereof. In some implementations, substrate 208 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.Semiconductor-on-insulator substrates can be fabricated using oxygen implantation separation (SIMOX), wafer bonding, and / or other suitable methods. The substrate 208 can have various doped regions designed in accordance with the design requirements of the semiconductor device 200. P-doped regions can contain p-type dopants, such as boron, indium, other p-type dopants, or combinations thereof. N-doped regions can contain n-type dopants, such as phosphorus, arsenic, other n-type dopants, or combinations thereof. In some embodiments, the substrate 208 has doped regions formed with a combination of p-type and n-type dopants.The various doped regions can be formed directly on and / or in the substrate 208, which may, for example, provide a p-well structure, an n-well structure, a double-well structure, an elevated structure, or combinations thereof. An ion implantation process, a diffusion process, and / or another suitable doping process can be performed to form the various doped regions. In some embodiments, p-GAA devices and p-FinFET devices are formed over n-wells, while n-GAA devices and n-FinFET devices are formed over p-wells. Each of the device structures 206a and 206b can individually be an n-well or a p-well device.

[0015] The insulation structure 210 can contain silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a dielectric material with a low k-value, and / or other suitable insulating materials. The insulation structure 210 can have trench insulation features (STI features). Other insulation structures, such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures, are possible. The insulation structure 210 can have a multilayer structure, which, for example, includes one or more thermal oxide lining layers.

[0016] Each of the stacked fins 212a and 212b has a stack of semiconductor layers 220 and 222 arranged in a nested or alternating manner (for example, a semiconductor layer 220 arranged over a semiconductor layer 222, then another semiconductor layer 222 arranged over the semiconductor layer 220, and so on). In some embodiments, the semiconductor layers 220 and 222 are arranged alternately in a vertical direction to form a semiconductor stack. In various embodiments, the stack has any number of alternately arranged semiconductor layers 220 and 222. In some embodiments, the semiconductor layers 220 and 222 have different thicknesses. Furthermore, the semiconductor layers 220 can have different thicknesses from one layer to the next, and the semiconductor layers 222 can also have different thicknesses from one layer to the next.In some embodiments, the thickness of each of the semiconductor layers 220 and 222 is in the range of a few nanometers to a few dozen nanometers. In one embodiment, each of the semiconductor layers 220 has a thickness in the range of approximately 5 nm to approximately 10 nm, and each of the semiconductor layers 222 has a thickness in the range of approximately 5 nm to approximately 10 nm.

[0017] The two types of semiconductor layers 220 and 222 have different compositions. In various embodiments, the semiconductor layers 222 have compositions that exhibit oxidation rates and / or etch selectivities that differ from those of the semiconductor layers 220. In one embodiment, the semiconductor layers 222 contain silicon-germanium (Si₂). 1-x Ge x), while the semiconductor layers 220 contain silicon (Si). In one embodiment, each of the semiconductor layers 220 is undoped or substantially doped silicon (that is, having an external dopant concentration of approximately 0 cm⁻¹). -3 up to approximately 1 × 10 17 cm -3 ), wherein no targeted doping is carried out during the formation of the semiconductor layer 220 (for example, from silicon). Alternatively, each of the semiconductor layers 220 is selectively doped. In one example, the silicon semiconductor layer 220 is produced doped either with a p-type dopant, such as boron (B), aluminum (Al), indium (In), and gallium (Ga), or an n-type dopant, such as phosphorus (P), arsenic (As), and antimony (Sb). In some embodiments, each of the semiconductor layers 222 Si 1-x Ge x , which contains less than 50% Ge by molar ratio (x < 0.5). For example, semiconductor layer 222 made of Si contains1-x Ge x The molar ratio is approximately 15% to approximately 35% Ge. Furthermore, the semiconductor layers 222 can also have different compositions among themselves, and the semiconductor layers 220 can also have different compositions among themselves.

[0018] In various embodiments, the semiconductor layers 220 and / or 222 can contain other materials, such as a composite semiconductor (for example, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide) or an alloy semiconductor (for example, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP), or combinations thereof. The materials of the semiconductor layers 220 and 222 can be selected based on providing different oxidation rates and / or etch selectivities. The semiconductor layers 220 and 222 can be doped or undoped, as discussed above.

[0019] In some embodiments, the semiconductor layers 220 and 222 are grown epitaxially layer by layer from an upper surface of the substrate 208. In one example, each of the semiconductor layers 220 and 222 is grown by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, such as a metal-organic CVD (MOCVD) process, and / or other suitable epitaxial growth processes. During epitaxial growth, the crystal structure of the substrate 208 extends upwards, resulting in the semiconductor layers 220 and 222 having the same crystal orientation as the substrate 208.

[0020] The stacked fins 212a and 212b can be formed by epitaxial growth of the semiconductor layers 220 and 222 over the substrate 208 and subsequently patterned by any suitable method for forming the individual stacked fins 212a and 212b. For example, the stacked fins 212a and 212b can be patterned using one or more photolithographic processes, such as dual-pattern or multiple-pattern processes. Typically, dual-pattern or multiple-pattern processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, smaller spacing dimensions than those achievable using a single, direct photolithography process.In one embodiment, for example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along with the patterned sacrificial layer using a self-aligning process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, can then be used to pattern the fins 212a and 212b by etching the initial semiconductor layers 220, 222 and the substrate 208. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In the illustrated embodiment, the stacked fins 212a and 212b extend longitudinally in the same direction (the longitudinal axes are parallel to each other).

[0021] The dummy gate structure 216 reserves an area for a metal gate stack and includes a dummy interface layer 231, a dummy gate electrode 232, a first gate hard mask layer 234, and a second gate hard mask layer 236. The dummy interface layer 231 is formed over the top and sidewall surfaces of each of the stacked fins 212a and 212b and over the top surface of the insulating structure 210. The dummy interface layer 231 can comprise a dielectric material, such as an oxide layer (e.g., SiO2) or an oxynitride layer (e.g., SiON), and can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods.

[0022] The dummy gate electrode 232 can consist of polycrystalline silicon (poly-Si) and can be formed by suitable deposition processes, such as low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced computed vapor deposition (PECVD). Each of the gate hardmask layers 234 and 236 can consist of one or more layers of dielectric material, such as silicon oxide and / or silicon nitride, and can be formed by CVD or other suitable methods. For example, the first gate hardmask layer 234 can have a silicon oxide layer adjacent to the dummy gate electrode 232, and the second gate hardmask layer 236 can have a silicon nitride layer. The various layers 231, 232, 234, and 236 can be patterned by photolithography and etching processes.

[0023] In process 104, procedure 100 forms ( Fig. 1A) the gate spacer elements 238 above the side walls of the dummy gate structure 216, as in Fig. Figure 3 shows that the gate spacers 238 can comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, other dielectric materials, or combinations thereof, and can include one or more material layers. The gate spacers 238 can be formed by depositing a spacer material, such as a cover layer, over the device 200. The spacer material is then etched by an anisotropic etching process. Sections of the spacer material on the sidewalls of the dummy gate structures 216 become the gate spacers 238.

[0024] In process 106, procedure 100 is further developed ( Fig. 1A) the stacked fins 212a and 212b at the S / D regions by using one or more lithography and etching processes, thereby forming S / D trenches. In some embodiments, the substrate 208 is also partially etched. At this stage, the end sections (also referred to as lateral ends) of the stacked semiconductor layers 220 and 222 are exposed in the S / D trenches. In process 106, method 100 further etches the semiconductor layers 222 laterally in the Y direction through the S / D trenches, thereby forming cavities. In some embodiments, the extent of the etching of the first semiconductor layer 222 is in the range of approximately 2 nm to approximately 5 nm.If the semiconductor layers 222 are Ge or SiGe and the semiconductor layers 220 are Si, the semiconductor layers 222 can be selectively etched using a wet etching agent, such as, but not limited to, solutions of ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH). Lateral etching of the semiconductor layers 222 can also remove a small section of the semiconductor layers 220. Consequently, the thickness T1 of the lateral ends of the semiconductor layers 220 is smaller than the thickness T0 of other sections of the semiconductor layers 220 located beneath the sacrificial gate structure, as in [reference missing]. Fig. Figure 4 shows that internal spacer elements 224 are subsequently formed in the cavities adjacent to the lateral ends of the semiconductor layers 222. In some embodiments, the internal spacer elements 224 contain a dielectric material, such as SiN, SiOC, SiOCN, SiCN, SiO2 and / or another suitable material, such as a dielectric material with a low k-value and a dielectric constant of less than approximately 3.9.

[0025] Process 106 also forms S / D elements 240 in the S / D areas, as shown in Fig. Figure 4 shows that, for example, processes 106 can grow semiconductor materials epitaxially in the S / D trenches. The semiconductor materials can be pulled up over the top surface of the respective stacked fins. Process 106 can form the S / D elements 240 separately for n-devices and p-devices, respectively. For example, process 106 can form the S / D elements 240 for n-devices from n-doped silicon and for p-devices from p-doped silicon germanium. Process 106 can further form a contact etch stop layer (CESL) 242 over the S / D elements 240, and a dielectric intermediate layer (ILD) 244 over the CESL 242. The CESL 242 can contain silicon nitride, silicon oxynitride, silicon nitride with oxygen (O) or carbon (C) elements, and / or other materials. and can be formed by CVD, PVD (physical evaporation), ALD or other suitable methods.The ILD layer 244 can comprise tetraethyl orthosilicate oxide (TEOS oxide), undoped silicate glass, or doped silicon dioxide, such as boron phosphosilicate glass (BPSG), fused silica (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The ILD layer 244 can be formed by PECVD or FCVD (flowable CVD) or other suitable methods. A CMP process can follow process 104 to remove excess dielectric materials. In some embodiments, the CMP process also removes the gate hard masks 234 and 236, exposing the dummy gate electrode 232.

[0026] In process 108, procedure 100 removes ( Fig. 1A) the dummy gate stack 216 to form gate trenches 246, as in Fig. Figure 5 shows that channel regions, such as the n-channel region 230a of the first device structure 206a and the p-channel region 230b of the second device structure 206b, are exposed in the gate grooves 246. Process 108 can comprise one or more etching processes that are selective for the material in the dummy gate structure 216. By selecting an etchant that does not etch the gate spacers 238 and the ILD layer 244, sections of the gate spacers 238 and the ILD layer 244 adjacent to the dummy gate structure 216 are exposed in the gate grooves 246 without significant etching losses. The etching process can include any suitable etching technique, such as wet etching, dry etching, reactive ion etching (RIE), ashing, and / or other etching methods. In one example, the etching process is a dry etching process for which a fluorine-based etchant (for example CF4, CHF3, CH2F2, etc.) is used.

[0027] In process 110, procedure 100 ( Fig. 1A) Floating nanostructures (for example, nanowires or nanosheets) are freely formed in the exposed channel regions. The formation of floating nanostructures involves a selective etching process to selectively remove semiconductor layers 222 from the respective channel region of the FET. Referring to the example of Fig. 6. The semiconductor layers 222 (for example, Si) 1-x Ge x ) from the channel regions of the stacked fins 212a and 212b, while the semiconductor layers 220 (for example, Si) essentially remain as the channel layers. In other words, the semiconductor layers 220 are removed from the channel regions 230a and 230b. Consequently, sections of the semiconductor layers 220 in the channel regions 230a and 230b are suspended in the respective openings. Therefore, after process 110, the semiconductor layers 220 are also referred to as suspended nanostructures 220.

[0028] In one embodiment, the semiconductor layers to be removed are etched by a selective wet etching process, while the remaining semiconductor layers, with a different composition, remain essentially unchanged. In some embodiments, the selective wet etching process includes a hydrofluoride etchant (HF etchant) or an NH4OH etchant. In one embodiment, in which the semiconductor layers 222 contain SiGe and the semiconductor layers 220 contain Si, the selective removal of the SiGe layers 222 comprises a SiGe oxidation process followed by a SiGeO x-removal. In one example, the SiGe oxidation process involves forming and structuring various masking layers so that the oxidation is directed to the SiGe layers 222. In other embodiments, the SiGe oxidation process is a selective oxidation due to the different compositions of the semiconductor layers 220 and 222. In some examples, the SiGe oxidation process is carried out by subjecting the device 200 to a wet oxidation process, a dry oxidation process, or a combination thereof. Subsequently, the oxidized semiconductor layers 222, which are SiGeO xcontained, is removed by an etchant, such as NH4OH or dilute HF. The semiconductor layer can also be removed by a selective wet etching process, while the remaining semiconductor layers with a different composition remain essentially unchanged. In some embodiments, the selective dry etching process includes an etchant based on hydrogen fluoride (HF), fluoride (F2), or carbon fluoride (CF3). x ) or hydrogen (H2).

[0029] The threshold voltage of an n-type FET can be adjusted by metal exit layers. To obtain p-type FETs with the desired threshold voltage, procedure 100 is then continued to adapt the channel area 230b of the second apparatus structure 206b for fine-tuning the threshold voltage of the p-type FET to be formed. The adaptation of the channel area 230b involves various procedures and operations, such as operations 112 and 114, which are described next.

[0030] In process 112, procedure 100 forms ( Fig. 1A) a structured mask on the upper surface of the device 200. As in Fig. As shown in Figure 7, the structured mask covers the first device structure 206a and has an opening that exposes the second device structure 206b. In one embodiment, the structured mask (instead of a soft mask, such as a structured photoresist layer) comprises a hard mask 252 arranged over the first device structure 206a. In some examples, the hard mask 252 contains silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, silicon carbide oxynitride, another semiconductor material, and / or another dielectric material. In one embodiment, the hard mask 252 has a thickness in the range of approximately 1 nm to approximately 40 nm. The hard mask 252 is formed by thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), or any other suitable method.The hard mask 252 is structured using any suitable method, such as a photolithography process, which may include forming a photoresist layer on the hard mask 252, exposing the photoresist by a lithography exposure process, performing a post-exposure baking process, developing the photoresist layer to form the structured photoresist layer that exposes part of the hard mask 252, structuring the hard mask 252, and finally removing the structured photoresist layer. Alternatively, the lithography process can be replaced by other suitable techniques, such as electron beam writing, ion beam writing, maskless structuring, or molecular printing.

[0031] In process 114, the procedure deposits 100 ( Fig. 1A) A threshold-modifying impurity is introduced into the channel region 230b to adjust the threshold voltage of the second device structure 206b. In some embodiments, the threshold-modifying impurity contains germanium. In one example, where the levitating nanostructures 220 are formed from a silicon material, the germanium dopant can form a dipole with the silicon material. The dipole formation can be used to tune a threshold voltage of a FET transistor formed using the levitating nanostructures 220 as channel layers. In one example, the threshold voltage of the FET transistor can be changed by controlling the dosage of the germanium concentration in the levitating nanostructures 220, where the magnitude of the change in the threshold voltage can be proportional to the dosage.If the FET transistor to be formed is, for example, a p-FET, the germanium doping implantation can reduce the threshold voltage of the field-effect transistor to such an extent that a higher dosage results in a greater reduction of the threshold voltage.

[0032] In one embodiment of process 114, the doping with the threshold-modifying impurity comprises a germanium implantation process 254, as described in Fig. Figure 8 shows that the implantation process can be performed at an energy between approximately 0.5 keV and approximately 30 keV. In one embodiment, the implantation process is a substantially vertical implant (for example, perpendicular to a top surface of the substrate). In another embodiment, the implantation process is an inclined implantation. The angle of inclination can be between approximately 0 degrees and approximately 30 degrees. The dosages of implanted germanium vary between approximately 1 × 10⁻⁶ 15 / cm 2 and approximately 5 × 10 15 / cm 2The threshold voltages of the p-FET can be proportionally reduced by approximately 10 mV to approximately 120 mV. Germanium implantation can be performed at an elevated temperature (for example, above 400 °C) to prevent amorphization of the suspended nanostructure 220 during implantation. For example, the atmosphere in which germanium implantation takes place can be heated to a temperature above approximately 450 °C, and the device 200 itself (which, for example, includes the substrate 208) can be heated to a temperature above approximately 400 °C during germanium implantation. In another embodiment, the germanium doping comprises a low-temperature plasma doping process that drives germanium ions into the suspended nanostructures 220.In one example, the plasma doping process is carried out with an RF source of less than approximately 1000 W at approximately 2 MHz and a pulsed DC bias of less than approximately 10 kV at approximately 0.5 - 10 kHz, as well as at a pressure of approximately 0.8 Pa to approximately 26.7 Pa (approximately 6 mTorr to approximately 200 mTorr) and a temperature of less than approximately 100 °C.

[0033] In yet another embodiment of process 114, the method 200 forms a semiconductor layer 258 around each of the floating nanostructures 220, which are arranged in the second device structure 206b (but not those in the first device structure 206a), as shown in Fig. Figure 9 shows that the semiconductor layers 258 contain the threshold-modifying impurity and have compositions that differ from those of the suspended nanostructures 220. In one embodiment, the semiconductor layers 258 contain silicon-germanium (Si₂) 1-x Ge x ), while the floating nanostructures contain 220 silicon (Si). For example, each of the layers contains 258 Si 1-x Ge x comprising approximately 10% to approximately 100% (0.1 ≤ x ≤ 1) of Ge by molar ratio. In a further embodiment, the semiconductor layers contain 258 germanium-tin (Ge x Sn 1-x ), while the floating nanostructures contain 220 silicon (Si). For example, each of the layers contains 258 Ge x Sn 1-xexhibiting approximately 10% to approximately 100% (0.1 ≤ x ≤ 1) of Ge by molar ratio. A sufficient amount of Ge in each of the layers 258 helps to reduce a threshold stress of the channel region 230b in the second device structure 206b. For example, Ge can comprise approximately 60% to approximately 80% of the Si layer 258. 1-x Ge x or Ge x Sn 1-x in the molar ratio. This range of Ge content, in combination with subsequent processing steps, effectively reduces the threshold voltage of the channel region 230b of the second device structure 206b. Furthermore, the semiconductor layers 258 can contain other, differing compositions.

[0034] Further referring to Fig. 9 In some embodiments, the semiconductor layers 258 are grown epitaxially from the faces of the semiconductor layers 220. For example, each of the semiconductor layers 258 is grown by an MBE process, a CVD process such as a MOCVD process, and / or other suitable epitaxial growth processes. The epitaxial growth approach allows materials in the semiconductor layer 258 to form crystal lattices that are consistent with those of the semiconductor layers 220. In some embodiments, each of the semiconductor layers 258 is a conformal layer having a substantially uniform thickness. In one example, each of the semiconductor layers 258 has a thickness of approximately 1 nm to approximately 4 nm. In some embodiments, the thickness ratio between a semiconductor layer 258 and the semiconductor layer 220 surrounding it is approximately 1:4 to approximately 1:2.In other words, semiconductor layer 258 is thinner than its corresponding semiconductor layer 220. Such a thickness ratio provides a suitable amount of germanium, which is required for threshold adjustment.

[0035] As in Fig. As shown in Figure 9, each of the semiconductor layers 220 has a central section exposed in the gate groove 246, as well as two end regions below the gate spacers 238. The central section is suspended in space (and is subsequently enclosed by a metal gate stack), and the end regions are connected to the inner spacers 224 and the gate spacers 238 (for example, encased or surrounded by them). Since only the central sections are exposed, in one embodiment the semiconductor layers 258 are epitaxially grown only in the central sections, but not in the end regions of the suspended nanostructures 220. In other words, the semiconductor layers 258 are formed only in the gate contact region and terminate at the gate spacers 238 and the inner spacers 224.

[0036] Referring to Fig. In process 114, method 100 further removes the structured mask (for example, the hard mask 252) from the device 200 and optionally performs a tempering process to drive the germanium contained in the semiconductor layers 258 into their corresponding semiconductor layers 220. The device 200 is exposed to a gas containing nitrogen (N), phosphorus, or other suitable elements. To prevent oxidation of the semiconductor layers 252 (for example, silicon-germanium or germanium-tin), the gas is oxygen-free in some embodiments. The tempering process conditions are adjusted to control the profile and properties of the resulting channel. In one example, the tempering process is performed at temperatures between approximately 700 °C and approximately 1200 °C.The tempering process can be carried out for a relatively long duration, such as 10 seconds to 100 seconds (so-called "impregnation"), or for a relatively short duration, such as from a few hundred milliseconds to a few seconds (for example, 200 milliseconds to 2 seconds) (so-called "doping").

[0037] The tempering process causes germanium atoms, and possibly silicon or tin atoms, contained in the semiconductor layers 258, to diffuse or migrate into the respective semiconductor layers 220. Conversely, silicon atoms contained in the semiconductor layers 220 can also diffuse or migrate into the respective semiconductor layers 258. As a result of atom migration, the germanium content of the semiconductor layers 258 decreases, and the germanium content of the semiconductor layers 220 increases. In one embodiment, after the tempering process, each of the semiconductor layers 258 contains Si 1-x Ge x or Ge x Sn 1-x, which contains more than 0% but equal to or less than approximately 70% (0.1 < x ≤ 0.7) of Ge by molar ratio. Such a range of Ge content is a result of diluting the original concentration of Ge in semiconductor layer 258 (for example, from approximately 60% to approximately 80%, as described above) and effectively lowers the threshold voltage in channel region 230b. Each of the semiconductor layers 258 and its corresponding semiconductor layer 220 can be effectively combined to form a new floating nanostructure (which, for simplicity, will continue to be designated by the number 220), since the material compositions of semiconductor layers 258 and 220 become the same or at least similar (for example, when germanium is ultimately distributed uniformly in semiconductor layers 258 and 220).

[0038] Since the levitating nanostructures 220 in the second device structure 206b are formed as a combination of two semiconductor layers, the levitating nanostructures 220 in the second device structure 206b can be further referred to Fig. The floating nanostructures 220 in the first apparatus structure 206a are thicker in the Z-direction (and wider in the X-direction). Method 100 can optionally perform a trimming operation during operation 114 to reduce the thickness of the floating nanostructures 220 in the second apparatus structure 206b. The trimming operation uses any suitable etching process, such as dry etching, wet etching, and / or RIE. In one embodiment, the floating nanostructures 220 in the second apparatus structure 206b are trimmed to have approximately the same dimensions (thickness and / or width) as the floating nanostructures 220 in the first apparatus structure 206a.In a particular example, process 100 in step 114 includes a cyclic process of repeating the steps of epitaxial growth of the germanium semiconductor layer 258, annealing to drive in the germanium atoms and trimming floating nanostructures as a way to further increase the germanium content in the floating nanostructures 220 to approximately 80%, such as to 95% or almost 100%.

[0039] In accordance with the embodiments of process 114 disclosed above, the injected germanium atoms are distributed in various ways within the suspended nanostructures 220, which can be tailored by controlling the implantation energy, implantation species, implantation dosage, temperature conditions, etc. As described above and in the Fig. 8 and Fig. As shown in Figure 9, during germanium implantation or epitaxial growth of germanium-containing semiconductor layers, the central sections of the floating nanostructures 220 of the second device structure 206b are affected by this process. Thus, during doping, germanium atoms can be driven mainly into the central sections (and not into the end sections) of the corresponding floating nanostructures 220. Fig. Figure 10 also shows an example concentration profile of germanium in a suspended nanostructure 220 along its longitudinal direction (Y-direction). As in Fig. As shown in Figure 10, the concentration of germanium in the central region of the suspended nanostructure 220 is higher than the concentration of germanium in the two end regions. Any suitable method can be used to determine the concentration (for example, by determining the average or mean concentration). In one embodiment, the concentration of germanium in the central region of each of the suspended nanostructures 220 is essentially uniform, while the concentration of germanium in the end regions exhibits a gradient profile (for example, gradually decreasing from the high concentration in the central region to a concentration of zero). It should be noted that, due to the spreading nature of germanium migration, the concentration of germanium at the Fig. The concentration of germanium at points C and C' shown in Figure 10 can begin to decrease, with these points being located a few nanometers away from the interface between the middle section and an end section (that is, a few nanometers away from a position aligned with a side wall of the gate spacer elements 238). In some embodiments (for example, if the annealing process has a short duration and / or low temperatures), the germanium does not extend far enough under the gate spacer elements 238 to reach the source and drain regions. Instead, the concentration of germanium at points D and D' drops to zero. Thus, at least one section of the two end sections—which is in direct contact with the gate spacer elements 238, the inner spacer elements 224, and the source / drain features 240, respectively—is essentially free of germanium.In one embodiment, the entire end sections of the suspended nanostructures 220 are essentially free of germanium. Likewise, for a cross-section in the XZ plane between points C and C', the concentration of germanium in a core section of each suspended nanostructure 220 can be equal to or lower than the concentration of germanium in an (outer) boundary section of the suspended nanostructure 220. In one example, a uniform germanium concentration of approximately 34% to 38% is achieved in both the core and boundary sections of the suspended nanostructure 220. In yet another example, a germanium concentration of approximately 45% to 50% is achieved in the boundary section of the suspended nanostructure 220, while the core section of the suspended nanostructure 220 is essentially free of germanium atoms.Such a gradient profile can be caused by the relatively short duration of the annealing process (for example, insufficient time for the germanium to migrate all the way to the core). In some embodiments, the edge region of the floating nanostructure 220 exhibits a remnant of the semiconductor layer 258, which contains Ge. x Sn 1-x contains a thin tin-containing outer layer.

[0040] In process 116, procedure 100 continues ( Fig. 1A) proceed to form gate stacks 260a and 260b across channel regions 230a and 230b of the first device structure 206a and the second device structure 206b, respectively. Gate stack 260a engages with the n-channel region 230a, thus forming an n-GAA transistor at the first device structure 206a. Gate stack 260b engages with the p-channel region 230b, thus forming a p-GAA transistor at the second device structure 206b. Referring to the example of Fig. 11. Gate stacks 230a and 230b fill the openings in the channel regions and enclose each of the suspended nanostructures 220. Gate stacks 260a and 260b have similar structures, but in some embodiments use different metals and / or different layer thicknesses. In the present embodiment, gate stacks 260a and 260b have a dielectric gate layer 262, which may have one or more layers of dielectric materials on the inner surfaces of the opening and directly encloses each of the suspended nanostructures 220. The dielectric gate layer 262 contains a dielectric material, such as silicon oxide or silicon oxynitride, and is formed by chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable methods.In some embodiments, the dielectric gate layer 262 also comprises a high k-value dielectric layer, such as hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, yttrium oxide, strontium titanate, other suitable metal oxides, or combinations thereof; and is formed by ALD and / or other suitable processes. The gate stacks 260a and 260b further comprise a gate metal layer 264, which may include one or more metal exit working layers above the dielectric gate layer 262, and a metal filler layer above the metal exit working layers. In some embodiments, the metal exit working layer is an n-metal exit working layer or a p-metal exit working layer. The n-metal exit working layer contains a metal selected from, but not limited to, the group comprising titanium, aluminum, tantalum carbide, tantalum carbide nitride, tantalum silicon nitride, or combinations thereof.The p-metal exit layer contains a metal selected from, but not limited to, the group comprising titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. In some embodiments, the p- or n-metal exit layer comprises multiple layers deposited by CVD, PVD, and / or another suitable process. By doping the channel layers of the p-FET with threshold-modifying impurities, the threshold voltages can be fine-tuned without the need for complex metal exit function control in the p-FET. The metal fill layer contains aluminum, tungsten, cobalt, copper, and / or other suitable materials and is formed by CVD, PVD, plating, and / or other suitable processes. In some embodiments, the gate stacks 260a and 260b enclose the vertically stacked, horizontally oriented channel semiconductor layers.Thus, the device 200 is a stacked, horizontal wraparound gate device (S-HGAA device). In one embodiment, after the gate stacks have been applied, a CMP process is performed to planarize an upper surface of the device 200.

[0041] In various embodiments, the method 100 can optionally skip the trimming process in process 114 without reducing the thickness and / or width of the floating nanostructures 220 in the p-channels of the second device structure 206b. Consequently, the cross-sectional area of ​​the floating nanostructures 220 in the p-GAA transistor can be larger than that in the n-GAA transistor. Since the p-channel relies on holes for conduction, which have a slower mobility than electrons in the n-channel, a larger cross-sectional area in the p-channel helps to increase the effective width of the channel, resulting in higher current and improved transistor performance.

[0042] In the above discussion, the procedure can be 100 ( Fig. 1A) In process 114, the threshold-modifying impurity (for example, germanium) is globally doped into all p-regions of the device 200. Alternatively, in process 114, the method 100 can dope the threshold-modifying impurity into selected p-regions to create threshold voltage differences between different p-FETs. The device 200 can have two or more regions with different threshold voltages, such as at least one standard threshold voltage region (SVt region) and one low threshold voltage region (LVt region). In the example of Fig. Figure 12 shows the first device structure 206a for forming an n-FET and the second device structure 206b for forming a first p-FET in the SVt region. Also in Fig. Figure 12 shows a third device structure 206c for forming a second p-FET in the LVt region. Compared to transistors arranged in an SVt region, the transistor arranged in an LVt region has a lower threshold voltage and operates faster. Therefore, transistors in an LVt region can be suitable for high-speed applications. Method 100 ( Fig. 1A) In process 112, the hard mask 252 can accordingly form, which covers both the first device structure 206a and the second device structure 206b, but has an opening that exposes the third device structure 206c. Consequently, the doping process (for example, germanium implantation, low-temperature plasma doping, or growth of a germanium-containing epitaxial layer and induction by annealing) is limited to the channel region 230c of the third device structure 206c. This results in the threshold voltage of the first p-FET formed on the second device structure 206b not being matched, while the second p-FET formed on the third device structure 206c has a lower threshold voltage than the first p-FET formed on the second device structure 206b.

[0043] Further referring to Fig. 12 can in yet another embodiment the method 100 ( Fig. 1A) In process 114, two impurity doping processes are included. The hard mask 252 can initially cover the first device 206a, with an opening exposing the channel area 230b of the second device structure 206b and the channel area 230c of the third device structure 206c. In process 114, the method 100 performs a first impurity doping process, which dopes a portion of the total dose into both channel area 230b and channel area 230c. Subsequently, a new hard mask is formed, which covers the first device 206a and the second device 206b, with an opening exposing the third device structure 206c. In process 114, the method 100 performs a second impurity doping process, which dopes the remainder of the total dose into channel area 230c. For example, if the total dosage to be administered is 2 × 10 15 / cm 2 If the amount is [missing value], the first impurity doping process can be used to add a germanium dose of 1 × 10 15 / cm 2 globally into all p-FET areas on the device 200, and the second impurity doping process can be used to introduce a germanium dose of 1 × 10 15 / cm 2 only to be introduced into LVt regions. In this way, all of the formed p-FETs will have a reduced threshold voltage, while the p-FETs in LVt regions will have a lower Vt due to the higher received dose.

[0044] Reference is now made to procedure 300. Fig. Figure 1B presents a flowchart of process 300 in accordance with various aspects of the present disclosure. Throughout this disclosure, the same reference numerals denote the same features with respect to composition and formation. Some details of operations in process 300 may be simplified or omitted if similar details have already been described in connection with process 100. Process 300 is only an example. Additional operations may be provided before, during, and after process 300, and some of the described operations may be substituted, omitted, or postponed for additional embodiments of the process. Some embodiments of process 300 are shown below in conjunction with the figures. 13 - 22 described. Fig. Figure 13 is a perspective view of device 200. Fig. Figures 14-22 are (side-by-side) cross-sectional views of the device 200 along sections BB and CC, which are shown in Fig. Figure 13 shows cross-sectional views that cut through the respective channel region along the longitudinal direction of the p-transistors (in the Y-Z plane). A cross-sectional view that cuts through a channel region along the longitudinal direction of an additional p-transistor of the device 200 is also shown in Figure 13. Fig. 22 shown.

[0045] In process 302, procedure 300 ( Fig. 1B) The device 200 provides two or more regions with different threshold voltages, such as at least one standard threshold voltage region (SVt region) and one low threshold voltage region (LVt region). In the example of Fig. Figure 13 shows the first device structure 206a for forming an n-FET and the second device structure 206b for forming a first p-FET in the SVt region. Also in Fig. Figure 13 shows a third device structure 206c for forming a second p-FET in the LVt region. As in Fig. As shown in Figure 13, each of the device structures 206a-c comprises the substrate 208, the insulation structure 210, the fins 212b-c, which have alternately and vertically stacked semiconductor layers 220 and 222 (also referred to as stacked fins 212a-c), and dummy gate structures 216, which engage with the stacked fins 212a-c. Since the substrate 202, the insulation structure 210, the semiconductor layers 220 and 222, and the dummy gate structure 216 have each been described above, detailed descriptions of them are omitted here.

[0046] In process 304, procedure 300 forms ( Fig. 1B) the gate spacer elements 238 above the side walls of the dummy gate structures 216, as in Fig. Figure 14 shows (section AA of the first device structure 206a for forming an n-FET is omitted here for simplification). Since process 304 is similar to process 104 described above, detailed descriptions of it are omitted here for the sake of brevity.

[0047] In process 306, procedure 300 forms ( Fig. 1B) the inner spacer elements 224 and the S / D elements 240, as in Fig. Figure 15 shows that, due to a lateral etching process during the formation of cavities for the application of the internal spacer elements 224, the lateral etching can also remove a small section of the semiconductor layers 220. Consequently, the thickness T1 of the end sections of the semiconductor layers 220 is smaller than the thickness To of other sections of the semiconductor layers 220 located beneath the sacrificial gate structure. Since process 306 is similar to process 106 described above, detailed descriptions of it are omitted here for the sake of brevity.

[0048] In process 308, procedure 300 removes ( Fig. 1B) the dummy gate stacks 216 to form gate trenches 246, as in Fig. Figure 16 shows that since process 308 is similar to process 108 described above, detailed descriptions of it are omitted here for the sake of brevity.

[0049] In process 310, procedure 300 ( Fig. 1B) Floating nanostructures 220 in the exposed channel regions freely, as in Fig. Figure 17 shows that since process 310 is similar to process 110 described above, detailed descriptions of it are omitted here for the sake of brevity.

[0050] In process 312, procedure 300 ( Fig. 1B) a trimming process 270 to reduce the thicknesses of the floating nanostructures 202 in the two channel regions 230b and 230c (but not in channel region 230a for the n-FET), as in Fig. Figure 18 shows that after the trimming process 270, the floating nanostructures 220 in the two channel regions 212b and 212c have essentially the same dimensions (thickness and / or width). The trimming process uses any suitable etching process, such as dry etching, wet etching, and / or RIE. During the trimming process 270, the gate spacers 238 protect the floating nanostructures 202 located beneath them from being etched. The trimming process 270 selectively removes sections of the floating nanostructures 202 that are vertically aligned with the gate grooves 246, while leaving the two end sections of the floating nanostructures 202 essentially unetched. The trimmed thickness of the middle section of the floating nanostructure 202 is designated T2.In the illustrated embodiment, a small section of the floating nanostructure 202, which is located directly below the gate spacer element 238 but not between the inner spacer elements 224, can still retain its original thickness To, which is, for example, approximately 1 nm to approximately 3 nm greater than the thickness T1 of the two end sections and the trimmed thickness T2 of the middle section. In various embodiments, the trimmed thickness T2 can be smaller or larger than the thickness T1 of the two end sections. In one embodiment, the trimmed thickness T2 is essentially equal to the thickness T1. A reduced thickness of the floating nanostructures 220 increases the threshold voltage in the relevant channel regions such that a smaller trimmed thickness T2 of the floating nanostructures results in a greater increase in the threshold voltage.In some embodiments, an increase in a range of approximately 20 mv to approximately 100 mv can be achieved by proportionally trimming middle sections of the floating nanostructures by approximately 1 nm to approximately 3 nm (To - T2).

[0051] In process 314, procedure 300 forms ( Fig. 1B) a structured mask, such as a hard mask 252 as described above, on the upper surface of the device 200, as in Fig. Figure 19 shows that the structured mask covers the third device structure 206c and has an opening that exposes the second device structure 206b. Since process 314 is similar to process 112 described above, detailed descriptions of it are omitted here for the sake of brevity.

[0052] In process 316, procedure 300 ( Fig. 1B) a second trimming process 272 to reduce the thickness of the floating nanostructures 202 in the channel regions 230b of the second device structure 206b, as shown in Fig. Figure 20 shows the trimming process. The trimming process uses any suitable etching process, such as dry etching, wet etching, and / or RIE. During the trimming process 272, the hard mask 252 protects the floating nanostructures 202 in the third device structure 206c from being etched. The trimming process 272 selectively removes additional sections of the floating nanostructures 202 in the second device structure 206b, which are vertically aligned with the gate grooves 246, while leaving the two end sections of the floating nanostructure 202 essentially unetched. As a result of the trimming process 272, the trimmed thickness of the middle section of the floating nanostructure 202 in the channel region 230b has been further reduced and is now designated T3.In the illustrated embodiment, a small section of the floating nanostructure 202, which is located directly below the gate spacer element 238 but not between the inner spacer elements 224, can still retain its original thickness T0, which is, for example, approximately 1 nm to approximately 4 nm greater than the thickness T1 of the two end sections and the trimmed thickness T3 of the middle section. The trimmed thickness T3 in channel region 230b is approximately 1 nm to approximately 3 nm smaller than the trimmed thickness T2 in channel region 230c. In various embodiments, the trimmed thickness T3 can be smaller or larger than the thickness T1 of the two end sections. In one embodiment, the trimmed thickness T3 is essentially equal to the thickness T1.In a particular example, the trimmed thickness T3 of the middle section in channel region 230b is smaller than the thickness T1 of the end sections, while the trimmed thickness T2 of the middle section in channel region 230c is larger than the thickness T1 of the end sections. Since a reduced thickness of the floating nanostructures further increases the threshold voltage in the relevant channel region, the p-FET in the SVt region formed on the second device structure 230b exhibits a higher threshold voltage than the p-FET in the LVt region formed on the third device structure 230c. After process 316, the hard mask 252 is removed in a suitable etching process.

[0053] In process 318, procedure 300 ( Fig. 1A) continued to form gate stacks over corresponding channel ranges, as in Fig. Figure 21 shows that since process 318 is similar to process 116 described above, detailed descriptions of it are omitted here for the sake of brevity. It should be noted that, due to the removal of additional sections of the floating nanostructure 220 of the second device structure 206b, the gate metal layer 264 in gate stack 260b has a larger volume than the gate metal layer 264 in gate stack 230c. By trimming the channel layers of the p-FET, the threshold voltages can be fine-tuned in the gate stacks of the p-FET without the need for a complicated metal output function control.

[0054] Referring to Fig. 22 Alternatively, in addition to the SVt region and the LVt region, the device 200 can also have a high threshold voltage region (HVt region) and a fourth device structure 206d for forming a third p-FET in the HVt region. Since a reduced thickness of the levitating nanostructures further increases the threshold voltage of the field-effect transistor in question, the method 300 can perform the first trimming process 270 on all three device structures 206b-206d, then the second trimming process 272 on device structures 206b and 206d (by covering device structure 206c with a structured mask), and subsequently a third trimming process 274 only on the fourth device structure 206d in the HVt region (by forming another structured mask that covers device structures 206b-c).Consequently, the fourth device structure 206d undergoes three trimming processes and has the smallest thickness, designated T4. The thicknesses T0, T2, T3, and T4 follow the relationship T0 > T2 > T3 > T4. Thus, all p-FETs in three regions will exhibit an increased Vt because they are subjected to at least one trimming process. The p-FETs in SVt regions have a higher threshold voltage than the p-FETs in LVt regions because they undergo an additional trimming process and therefore have a correspondingly smaller channel thickness. The p-FETs in HVt regions have the highest threshold voltage because they undergo two additional trimming processes and therefore have the correspondingly smallest channel thickness. In one embodiment, T1 is larger than T3 and T4, but smaller than T2.

[0055] Reference is now made to procedure 500. Fig. Figure 1C presents a flowchart of Process 500 in accordance with various aspects of the present disclosure. Throughout the present disclosure, the same reference numerals denote the same features with respect to composition and formation. Some details of operations in Process 500 may be simplified or omitted if similar details have already been described in connection with Processes 100 and 300. Process 500 is only an example. Additional operations may be provided before, during, and after Process 500, and some of the described operations may be substituted, omitted, or postponed for additional embodiments of the Process. Some embodiments of Process 500 are described below in connection with the Fig. 23 - 32 described. Fig. Figure 23 is a perspective view of device 200. Fig. Figures 24-32 are (side-by-side) cross-sectional views of the device 200 along sections BB, CC and DD, which are shown in Fig. Figure 23 shows which intersect the respective channel area along the longitudinal direction of the p-transistors (in the YZ plane).

[0056] In process 502, procedure 500 ( Fig. 1C) The device 200 is provided, which has three different threshold voltage ranges, namely a standard threshold voltage range (SVt range), a low threshold voltage range (LVt range), and a high threshold voltage range (HVt range). In the example of Fig. Figure 23 shows that the first device structure 206a for forming an n-FET and the second device structure 206b for forming a first p-FET are arranged in the SVt region. The third device structure 206c for forming a second p-FET is arranged in the LVt region. The fourth device structure 206d for forming a third p-FET is arranged in the HVt region. As shown in Fig. As shown in Figure 23, each of the device structures 206a-d comprises the substrate 208, the insulating structure 210, the fins 212a-d, which have alternating and vertically stacked semiconductor layers 220 and 222 (also referred to as stacked fins 212a-d), and dummy gate structures 216, which engage with the stacked fins 212a-d. Since the substrate 202, the insulating structure 210, the semiconductor layers 220 and 222, and the dummy gate structure 216 have each been described above, detailed descriptions of them are omitted here.

[0057] In process 504, procedure 500 forms ( Fig. 1C) the gate spacer elements 238 above the side walls of the dummy gate structures 216, as in Fig. Figure 24 shows (section AA of the first device structure 206a for forming an n-FET is omitted here for simplification). Since process 504 is similar to process 104 described above, detailed descriptions of it are omitted here for the sake of brevity.

[0058] In process 506, procedure 500 forms ( Fig. 1C) the inner spacer elements 224 and the S / D elements 240, as in Fig. Figure 25 shows that, due to a lateral etching process during the formation of depressions for the application of the internal spacer elements 224, the lateral etching can also remove a small section of the semiconductor layers 220. Consequently, the thickness T1 of the lateral ends of the semiconductor layers 220 is smaller than the thickness T0 of other sections of the semiconductor layers 220 located beneath the sacrificial gate structure. Since process 506 is similar to process 104 described above, detailed descriptions of it are omitted here for the sake of brevity.

[0059] In process 508, procedure 500 removes ( Fig. 1C) the dummy gate stack 216 to form gate trenches 246, as in Fig. Figure 26 shows that since process 508 is similar to process 108 described above, detailed descriptions of it are omitted here for the sake of brevity.

[0060] In process 510, procedure 500 ( Fig. 1C) Floating nanostructures 220 in the exposed channel regions freely, as in Fig. Figure 27 shows that since process 510 is similar to process 108 described above, detailed descriptions of it are omitted here for the sake of brevity.

[0061] In process 512, procedure 500 ( Fig. 1C) a trimming process 270 to reduce the thicknesses of the floating nanostructures 220 in all three channel regions 230b - d (but not in channel region 230a for n-FET), as in Fig. Figure 28 shows that after the trimming process 270, the floating nanostructures 220 in the channel regions 212b–212d have essentially the same dimensions (thickness and / or width). The trimming process uses any suitable etching process, such as dry etching, wet etching, and / or RIE. During the trimming process 270, the gate spacers 238 protect the floating nanostructures 202 located beneath them from being etched. The trimming process 270 selectively removes sections of the floating nanostructure 202 that are vertically aligned with the gate grooves 246, while leaving the two end sections of the floating nanostructure 202 essentially unetched. The trimmed thickness of the middle section of the floating nanostructure 202 is designated T2.In the illustrated embodiment, a small section of the floating nanostructure 202, located directly below the gate spacer 238 but not between the inner spacers 224, can still retain its original thickness T0, which is, for example, approximately 1 nm to approximately 3 nm greater than the thickness T1 of the two end sections and the trimmed thickness T2 of the middle section. In various embodiments, the trimmed thickness T2 can be smaller or larger than the thickness T1 of the two end sections. In one embodiment, the trimmed thickness T2 is essentially equal to the thickness T1. A reduced thickness of the floating nanostructures can increase the threshold voltage of the field-effect transistor such that a smaller thickness of the floating nanostructures results in a greater increase in the threshold voltage.In some embodiments, an increase in a range of approximately 20 mv to approximately 100 mv can be achieved by proportionally trimming middle sections of the floating nanostructures by approximately 1 nm to approximately 3 nm (To - T2).

[0062] In process 514, procedure 500 forms ( Fig. 1C) a structured mask, such as a hard mask 252, on the upper surface of the device 200, as in Fig. Figure 29 shows that the structured mask covers the second and fourth device structures 206b and 206d and has an opening that exposes the third device structure 206c. Since process 514 is similar to process 112 described above, detailed descriptions of it are omitted here for the sake of brevity.

[0063] In process 516, the procedure 500 is used ( Fig. 1C) a threshold-modifying impurity into the channel area 230c to adjust the threshold voltage of the third device structure 206c, as shown in Fig. Figure 30 shows that doping with the threshold-modifying impurity (for example, germanium implantation, low-temperature plasma doping, or growth of a germanium-containing epitaxial layer and annealing) is limited to channel region 230c of the third device structure 206c. This results in the threshold voltage of the first p-FET formed at the second device structure 206b in the SVt region and of the third p-FET formed at the fourth device structure 206d in the HVt region not being further adjusted, while the second p-FET formed at the third device structure 206c in the LVt region now has the lowest threshold voltage. Since process 516 is similar to process 114 described above, detailed descriptions of it are omitted here for the sake of brevity.As discussed above in connection with Process 114, the middle sections of the suspended nanostructures doped with the threshold-modifying impurity can increase in thickness. The thickness of the middle section of the suspended nanostructure in channel region 230c (designated T2') can therefore be greater than the thickness T2 in other channel regions 230b and 230d. Process 500 can optionally perform a trimming operation in Process 516 to reduce the thickness T2' to the thickness T2, so that the suspended nanostructures 220 have essentially the same dimensions in all three regions.

[0064] In process 518, procedure 500 ( Fig. 1C) a second trimming process 272 to reduce the thickness of the suspended nanostructures 220 in the channel region 230d in the HVt region, as in Fig. Figure 31 shows that in step 518, method 500 first forms a structured mask to cover the second device structure 206b and the third device structure 206c, with an opening to expose the fourth device structure 206d. In step 518, method 500 then performs a suitable etching process, such as dry etching, wet etching, and / or RIE, to remove additional sections from the central portions of the floating nanostructures 220 in the channel region 230d. Since step 518 is similar to step 316 described above, detailed descriptions of it are omitted here for brevity. As a result of the trimming process 272, the trimmed thickness of the central portion of the floating nanostructure 202 has been further reduced and is now designated T3. T3 is smaller than T2 and smaller than T2'. Compared to the thickness T4 in the HVt transistor in Fig. 22, which in connection with procedure 300 ( Fig. 1B) undergoes three trimming processes, the thickness T3 in the HVt transistor in Fig. 31 is a result of two trimming processes performed on it, making it larger than T4 and giving it higher mechanical strength for levitated nanostructures. Since a reduced thickness of the levitated nanostructures further increases the threshold voltage in the relevant channel regions, the p-transistor in the HVt region formed on the fourth device structure 230d thus has a higher threshold voltage than the p-transistor formed on the second device structure 230b in the SVt region, as well as than the p-transistor formed on the third device structure 230c in the LVt region.

[0065] In process 520, procedure 500 ( Fig. 1C) continued to form gate stacks over the respective channel ranges, as in Fig.Figure 32 shows that since process 520 is similar to process 116 described above, detailed descriptions of it are omitted here for the sake of brevity. It should be noted that, due to the removal of additional sections of the floating nanostructure 220 of the fourth device structure 206d, the gate metal layer 264 in gate stack 260d has a larger volume than the gate metal layer 264 in gate stack 230b and the gate metal layer 264 in gate stack 230c. Furthermore, the channel layers of the third device structure 206c also contain a threshold-modifying impurity. By doping with the threshold-modifying impurity and trimming the respective channel layers, the threshold voltages can be fine-tuned in the gate stacks of the p-FET without the need for a complex metal work function control.

[0066] In each of the processes 100, 300, or 500, further steps can be performed to complete the fabrication of the device 200. For example, the process can be continued to form contact openings, contact metal, and various contacts, vias, wires, and multilayer interconnect features (for example, metal layers and interlayer dielectrics) across the GAA transistors, which are configured to connect the various features to form a functional circuit that may include one or more multi-gate devices.

[0067] One or more embodiments of the present disclosure provide numerous advantages for a semiconductor device or its fabrication process. In accordance with some embodiments, threshold voltages of p-GAA-FETs are achieved with a simplified fabrication process. In some embodiments, different threshold voltages of p-GAA-FETs can be fine-tuned separately in different ranges to fabricate SVt, LVt, and / or HVt-FETs based on considerations of device performance. Furthermore, embodiments of the present disclosure can be integrated into an existing CMOS fabrication flow, thereby providing an improved process window.

[0068] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims.

Claims

[1] Method for forming a semiconductor device (200), comprising: Providing a substrate (208) comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers arranged over the substrate (208), wherein the first and second semiconductor layers (222, 220) have different material compositions and are arranged alternately with each other; Structuring the first semiconductor layers (222) and the second semiconductor layers (220) to form a first fin (212c) and a second fin (212b, 212d); Removing the first semiconductor layers (222) from the first fin (212c) and the second fin (212b), such that a first section of the structured second semiconductor layers (220) becomes first floating nanostructures (220) in the first fin (212c), and a second section of the structured second semiconductor layers (220) becomes second floating nanostructures (220) in the second fin (212b); Doping a threshold-modifying impurity into the first suspended nanostructures (220) in the first fin (212c), wherein the doping of the threshold-modifying impurity includes the application of a plasma-assisted low-temperature doping process; Forming a first gate stack (260c) over the first fin (212c), wherein a section of the first gate stack (260c) envelops the first floating nanostructures (220), thereby forming a first transistor with a first threshold voltage; and Forming a second gate stack (260b) over the second fin (212b), wherein a section of the second gate stack (260b, 260d) envelops the second floating nanostructures (220), thereby forming a second transistor with a second threshold voltage which is higher than the first threshold voltage. [2] Method according to claim 1, wherein the impurity modifying the threshold is Ge. [3] Method according to claim 1 or 2, wherein doping with the impurity modifying the threshold further comprises: Forming a plurality of third semiconductor layers (258) on the first floating nanostructures (220) in the first fin (212c); and Performing a tempering process to drive the threshold-modifying impurity contained in the third semiconductor layers (258) into the first floating nanostructures (220) in the first fin (212c). [4] Method according to claim 3, wherein the formation of the third semiconductor layers (258) comprises an epitaxial growth of each of the third semiconductor layers (258) such that it encloses a corresponding first floating nanostructure (220) in the first fin (212c), and wherein the third semiconductor layers (258) have different material compositions than the second semiconductor layers (220). [5] Method according to claim 3 or 4, wherein the third semiconductor layers (258) contain either SiGe or GeSn. [6] Method according to any of the preceding claims, wherein the plasma-assisted low-temperature doping process is carried out with an RF source of less than 1000 W at 2 MHz and a pulsed DC bias of less than 10 kV at 0.5 - 10 kHz, and at a pressure of 0.8 Pa to 26.7 Pa and a temperature of less than 100 °C. [7] Method according to any of the foregoing claims, further comprising: Doping the threshold-modifying impurity into the second suspended nanostructures (220) in the second fin (212b), wherein the threshold-modifying impurity in the first suspended nanostructures (220) in the first fin (212c) has a higher concentration than in the second suspended nanostructures (220) in the second fin (212b). [8] Method according to any of the preceding claims, wherein doping the threshold-modifying impurity into the first suspended nanostructures (220) in the first fin (212c) comprises a first doping of the threshold-modifying impurity simultaneously into both the first suspended nanostructures (220) in the first fin (212c) and the second suspended nanostructures (220) in the second fin (212b), and a second doping of the threshold-modifying impurity into the first suspended nanostructures (220) in the first fin (212c), but not into the second suspended nanostructures (220) in the second fin (212b). [9] Method according to any of the foregoing claims, further comprising: Trimming the first and second suspended nanostructures (220) to reduce their thicknesses prior to doping the threshold-modifying impurity into the first suspended nanostructures (220). [10] Method according to any of the foregoing claims, further comprising: Trimming the second suspended nanostructures (220) to further reduce their thickness after doping the threshold-modifying impurity into the first suspended nanostructures (220). [11] Procedure, encompassing: Forming a plurality of first floating layers (220) in a first fin (212c) and a plurality of second floating layers (220) in a second fin (212d), wherein the first and second floating layers (220) contain the same first semiconductor material; Performing a first etching process (270) to simultaneously remove sections of the first and second floating layers (220), thereby reducing the thicknesses of the first and second floating layers (220); doping (254) an impurity into the first suspended layers (220), wherein the second suspended layers (220) are substantially free of the impurity, wherein the doping of the impurity comprises applying a plasma-assisted low-temperature doping process; Performing a second etching process (272) to remove additional sections of the second floating layers (220) without etching the first floating layers (220), thereby further reducing the thickness of the second floating layers (220); and Forming a first gate stack (260c) and a second gate stack (260d) which engage with the first and second floating layers (220) respectively. [12] Method according to claim 11, wherein the first gate stack (260c) and the first floating layers (220) are arranged in a low threshold voltage region, and the second gate stack (260b) and the second floating layers (220) are arranged in a standard threshold voltage region. [13] Method according to claim 11, wherein the first gate stack (260c) and the first floating layers (220) are arranged in a low threshold voltage region, and the second gate stack (260d) and the second floating layers (220) are arranged in a high threshold voltage region. [14] Method according to any one of the preceding claims 11 to 13, wherein the plasma-assisted low-temperature doping process is carried out with an RF source of less than 1000 W at 2 MHz and a pulsed DC bias of less than 10 kV at 0.5 - 10 kHz, and at a pressure of 0.8 Pa to 26.7 Pa and a temperature of less than 100 °C. [15] Method according to any one of claims 11 to 14 above, wherein the impurity is Ge. [16] Method according to claim 15, wherein the concentration of germanium in the middle sections of the first suspended layers (220) is higher than a concentration of germanium in two end sections of the first suspended layers (220). [17] Method according to any one of the preceding claims 11 to 16, wherein when forming the first gate stack (260c) a first transistor with a first threshold voltage is formed and when forming the second gate stack (260d) a second transistor with a second threshold voltage is formed, wherein the first transistor is formed as a p-FET and the second transistor is formed as a p-FET. [18] Method according to any one of the preceding claims 11 to 17, wherein after carrying out the first etching process and prior to doping an impurity into the first floating layers (220) a hard mask (252) is formed which covers the second floating layers (220) and leaves the first floating layers (220) free. [19] Method according to any one of claims 11 and 13 to 18 above, further comprising: Forming a plurality of third floating layers (220) in a third fin (212b), wherein the third floating layers (220) contain the first semiconductor material; wherein during the execution of the first etching process sections of the third suspended layers (220) are removed, thereby reducing the thickness of the third suspended layers (220); wherein when an impurity is introduced into the first suspended layers (220), the third suspended layers (220) are essentially free of the impurity; and where, during the execution of the second etching process, the third suspended layers (220) are not etched.

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