Semiconductor package and method for its manufacture

Abstract

Package includes: an integrated circuit die (50), wherein a side wall of the integrated circuit die (50) has a first slope (72A) and a second slope (72B), wherein the first slope (72A) and the second slope (72B) have different gradients; an encapsulation material (120) that surrounds the integrated circuit die (50) and is in physical contact with the first slope (72A) and the second slope (72B), wherein a top surface of the integrated circuit die (50) is lower than a top surface of the encapsulation material (120); and an insulating layer (124) over the integrated circuit die (50) and the encapsulation material (120), wherein one side wall of the insulating layer (124) is coplanar with the first slope (72A).

Description

background

[0001] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density is largely due to repeated reductions in the minimum feature size, allowing more components to be integrated in a given area. As the demand for smaller electronic devices has increased, a need has arisen for methods for smaller and more creative packaging of semiconductor dies. One example of such packaging technology is package-on-package (PoP) technology. In a PoP device, an upper semiconductor package is stacked on top of a lower semiconductor package to achieve a high level of integration and high component density.PoP technology generally enables the manufacture of semiconductor devices with enhanced functionalities and small footprints on a printed circuit board (PCB).

[0002] Packages and manufacturing processes for such are known, for example, from US 2002 / 0027257 A1, US 2017 / 0186655 A1 or US 2004 / 113283 A1. Short description of the drawings

[0003] Aspects of the present invention can best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Rather, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. The Fig. 1, Fig. 2, Fig. 3, Fig. 4A and Fig. 4B show cross-sectional views of intermediate steps in a method of manufacturing an integrated circuit die according to some embodiments. The Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11A, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17A and Fig. 17B show cross-sectional views of intermediate stages in a method of manufacturing a package component according to some embodiments. The Fig. 11B and Fig. 11C illustrate possible chemical mechanisms for an intermediate in a method of manufacturing a package component according to some embodiments. Fig. 18 shows a cross-sectional view of the fabrication of a semiconductor package according to some embodiments. Detailed description

[0004] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to facilitate the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numerals and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0006] In various embodiments, methods are provided for manufacturing a semiconductor package having a plurality of package components. An integrated circuit die (e.g., a sensor die) may include an insulating layer with a desired strength, durability, and flexibility, while also having a specific chemical composition so that the insulating layer can be quickly and efficiently removed in a later step. The integrated circuit die may be attached to a substrate having a backside redistribution structure and vias, and an encapsulation material may be formed around the integrated circuit die and the vias. The dielectric layer may then be removed to form a frontside redistribution structure that is electrically connected to the integrated circuit die and the vias.This package component can then be attached to another package component to create the semiconductor package.

[0007] The Fig. 1, Fig. 2, Fig. 3, Fig. 4A and Fig. 4B show cross-sectional views of intermediate stages in a method of manufacturing an integrated circuit die 50 according to some embodiments. The integrated circuit die 50 is packaged into an integrated circuit package during later processing. The integrated circuit die 50 may be: a sensor die (e.g., an ultrasonic sensor); a logic die, e.g., a CPU die (CPU: main processor), a GPU die (GPU: graphics processing unit), a SoC die (SoC: system-on-a-chip), an application processor (AP die), a microcontroller die, etc.); a memory die, e.g., a DRAM die (Dynamic Random Access Memory), an SRAM die (SRAM: static random access memory), a power management die, e.g., an integrated power management die (PMIC), a radio frequency (RF) die; a MEMS die (MEMS: microelectromechanical system). a signal processing die, e.g. a DSP die (DSP: digital signal processing); a front-end die, e.g.an analog front-end die (AFE die), or the like; or a combination thereof. As shown, in some embodiments, the integrated circuit die 50 is a sensor die, such as an ultrasonic sensor (e.g., an ultrasonic fingerprint sensor). In other embodiments, the integrated circuit die 50 may be a light sensor, an image sensor, or another suitable type of sensor, if desired.

[0008] In Fig. 1, the integrated circuit die 50 includes a substrate 52. In some embodiments, the substrate 52 may be a wafer-level structure, such as a wafer, having different device regions that will be singulated into a plurality of integrated circuit dies 50 in later steps. In some embodiments, the substrate 52 includes a semiconductor substrate 52A, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52A may also include other semiconductor materials, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used.The semiconductor substrate 52A has an active side (e.g., the side shown in . Fig. 1 facing up), which is sometimes referred to as a front side, and an inactive side (e.g. the side that is in Fig. 1 facing down), which is sometimes referred to as a backside. The semiconductor substrate 52A may have a thickness of about 130 µm to about 150 µm. The substrate 52 may have a thickness of about 170 µm to about 190 µm.

[0009] In some embodiments, the substrate 52 further includes devices 52B fabricated in and / or on the active side of the semiconductor substrate 52A, and an interconnect structure 52C having a plurality of metallization structures (not shown) disposed over and electrically connected to the devices 52B. The devices 52B may be active devices (e.g., transistors, diodes, etc.), passive devices (e.g., capacitors, resistors, etc.), combinations thereof, or the like. The devices 52B may be fabricated using any methods suitable for fabricating such devices. The interconnect structure 52C connects the devices 52B to one another to form an integrated circuit.The metallization structures of the interconnect structure 52C include metal lines and vias (not shown) formed in one or more low-k dielectric layers (not shown) and may be formed using any suitable process (such as deposition, single damascene process, dual damascene process, or the like).

[0010] The interconnect structure 52C is electrically connected to structural elements disposed on or along a top surface of the substrate 52. As shown, in embodiments where the integrated circuit die 50 is a sensor, such as an ultrasonic sensor, the integrated circuit die 50 may include sensor elements 54 and / or dummy elements 56 (e.g., dummy pads) on or along the top surface of the substrate 52. Each sensor element 54 may be a sensor element suitable, for example, for generating and / or transmitting a signal or a pulse depending on the type of sensor desired. For example, in an embodiment where the sensor is an ultrasonic sensor, each sensor element 54 may include a piezoelectric transducer responsive to ultrasonic forces and electrically connected to the integrated circuit fabricated in the substrate 52.

[0011] The integrated circuit die 50 further includes pads 62 (e.g., aluminum pads), such as input / output (I / O) regions, for establishing external connections. The pads 62 are disposed on the active side of the substrate 52 of the integrated circuit die 50, such as on a top surface of the interconnect structure 52C. The pads 62 may be separated from the sensor elements 54 and the dummy elements 56 by an isolation region 58 to reduce any undesirable electrical influence that the pads 62 may have on the sensor elements 54. One or more passivation layers 64 are disposed on the integrated circuit die 50, e.g., on portions of the pads 62, the sensor elements 54, and the dummy elements 56. As shown, openings extend through the passivation layers 64 to the pads 62.The passivation layers 64 may comprise silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination thereof, and may be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or the like, or a combination thereof.

[0012] In Fig. 2, an insulating layer 68 may be provided over the structure of Fig. 1. The insulating layer 68 can be selected for stability, tensile strength, and flexibility so that it remains stable during subsequent processing steps, during storage or transport, and / or during packaging in a semiconductor device. In some embodiments, a material for the insulating layer 68 is selected to have a high glass transition temperature T g , a high decomposition temperature T das well as high tensile strength and a high modulus of elasticity. As will be explained in more detail later, the insulating layer 68 is removed in subsequent processing steps. Accordingly, the insulating layer 68 can also be referred to as a sacrificial layer.

[0013] The insulating layer 68 may comprise a polymer such as a polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), or the like; or the like, or a combination thereof. The insulating layer 68 may be formed, for example, by spin coating, lamination, ALD, CVD, or the like. For example, the insulating layer 68 may be formed by applying a polymer blend to the structure, e.g., by spin coating.

[0014] In some embodiments, the polymer base comprises a polyimide repeating unit. The polyimide repeating unit may, in turn, comprise an electrophilic functional group FG, which can attract a larger portion of an electron cloud in a molecule. Therefore, the electrophilic functional group FG can attract electrons away from a portion of the repeating unit at or near the imide group. The electrophilic functional group FG can attach in series with the imide group, as shown in the following exemplary chemical structure:

[0015] Exemplary chemical structures for the electrophilic functional group FG may contain highly electronegative atoms (e.g., oxygen atoms), such as a carbonyl group containing an ester group, as discussed later. Variants of the chemical structure below may be carbon chains (with one or more carbon atoms) instead of one or two oxygen atoms in each part of the chain. Alternatively, the electrophilic functional group FG may contain an anhydride or the like, or other suitable functional groups in series with the imide group.

[0016] As solvents, organic solvents such as ketones, alcohols, polyalcohols, ethers, glycol ethers, cyclic ethers, aromatic hydrocarbons, esters, propionates, lactates, lactic acid esters, alkylene glycol monoalkyl ethers, alkyl lactates, alkyl alkoxypropionates, cyclic lactones, monoketone compounds containing a ring, alkylene carbonates, alkyl alkoxy acetate, alkyl pyruvates, ethylene glycol alkyl ether acetates, diethylene glycols, propylene glycol alkyl ether acetates, alkylene glycol alkyl ether esters, alkylene glycol monoalkyl esters, or the like can be used.

[0017] After applying the polymer mixture, a pre-curing process may be performed to evaporate all or part of the solvent. The pre-curing process may be performed at a temperature of about 90°C to about 100°C for a duration of about 3 minutes to about 10 minutes. After the pre-curing process, a curing process to crosslink the polymer base may be performed at a temperature of about 225°C to about 230°C for a duration of about 60 minutes to about 65 minutes. The insulating layer 68 may, for example, be manufactured with a thickness of about 15 µm to about 30 µm.

[0018] Several advantages are achieved with the polymer base and the method for producing the insulating layer 68 described above. First, by using a glass transition temperature T g from about 243 °C to about 255 °C and a decomposition temperature T dfrom about 340°C to about 370°C, the insulating layer 68 is stable at higher processing temperatures that may be required in later steps. Second, due to its tensile strength of about 120 MPa to about 150 MPa and its elastic modulus of about 3.0 GPa to about 4.5 GPa, the insulating layer 68 is also reliable during later processing. Third, the insulating layer 68 can be efficiently removed in a later processing step, for example, with a wet etchant containing a base, as will be explained in more detail later. In particular, the electrophilic functional group enables a rapid and productive reaction with other parts of the polymer structure, such as parts with a stronger positive charge near the imide group.

[0019] In Fig. 3, a grooving process, such as a laser grooving process, may be performed to prepare each integrated circuit die 50 for singulation from the wafer. In one embodiment, the insulating layer 68, the passivation layers 64, and portions of the substrate 52 (such as portions of dielectric layers of the interconnect structure 52C of the substrate 52) may be patterned, for example, using a laser grooving or laser drilling process in which a laser is directed at the portions of the insulating layer 68 to be removed to expose the underlying substrate 52. An advantage of the insulating layer 68 is that it maintains its strong adhesion to the substrate 52 and the passivation layers 64 during the grooving process. For example, the polyimide portions (e.g.,the cyclic imide moieties) of the molecules of the insulating layer 68 form multiple hydrogen bonds with the passivation layers 64 to enable strong adhesion between the layers.

[0020] During the laser grooving process, a drilling energy may be about 500 mJ to about 1000 mJ, and a drilling angle may be about 0° (perpendicular to a major surface of the insulating layer 68) to about 90° to the normal of the major surface (i.e., a top surface) of the insulating layer 68. The grooving process may be performed to create openings 70 above the substrate 52 to identify scribe trench regions of the substrate 52 to be severed during later singulation. In some embodiments, the openings 70 extend into the substrate 52, such as into the interconnect structure 52C of the substrate 52. In other embodiments, the openings 70 may extend through the interconnect structure 52C of the substrate 52 and into the semiconductor substrate 52A of the substrate 52.

[0021] In some embodiments, the openings 70 have widths that decrease as the openings 70 extend from a top surface of the insulating layer 68 to the substrate 52. The openings 70 may have a width W1 at or near their bottom surfaces of about 50 μm to about 60 μm and a width W2 at or near the top surface of the insulating layer 68 of about 70 μm to about 100 μm. In some embodiments, the width W1 may be about 65% of the width W2. In some embodiments, sidewalls of the insulating layer 68, the passivation layers 64, and the substrate 52 exposed by the openings 70 have non-vertical slopes that form non-zero angles with the normal of the major surface (i.e., a top surface) of the substrate 52. The angle of the non-vertical slopes may be substantially equal to the drilling angle used in the laser grooving process.In the illustrated embodiment, the bottom surfaces of the openings 70 are planar surfaces. In other embodiments, the bottom surfaces of the openings 70 may be curved surfaces with one or more convex portions, one or more concave portions, or a combination thereof.

[0022] In Fig. 4A, the integrated circuit dies 50 are separated from the wafer. In one embodiment, the dicing process may be performed using a saw blade (not individually shown) to create the scribe trench regions of the substrate 52 between adjacent portions of the insulating layer 68 and at the openings 70 (see Fig. 3). However, as one of ordinary skill in the art would appreciate, using a saw blade for the singulation process is merely an illustrative embodiment and is not intended to be limiting. Any method for performing the singulation process, such as using one or more etches, may be used. These and other suitable methods may be used to singulate the structure. In some embodiments, the integrated circuit dies 50 have a width of about 198 mm to about 202 mm.

[0023] In some embodiments, sidewalls of the substrate 52 of the integrated circuit die 50 have chamfered structures with first chamfers 72A and second chamfers 72B. The first chamfers 72A are created during the laser grooving process described above with reference to Fig. 3. The first bevels 72A have non-vertical slopes that form non-zero angles with the normal of the main surface (i.e., the top surface) of the substrate 52. The second bevels 72B are created during the dicing process described above. In some embodiments where the dicing process is a sawing process, the second bevels 72B have substantially vertical slopes that form substantially non-zero angles with the normal of the main surface (i.e., the top surface) of the substrate 52, within process variations of the sawing process. In some embodiments, the bevels 72A are created in the interconnect structure 52C of the substrate 52, but not in the semiconductor substrate 52A of the substrate 52. In other embodiments, the bevels 72A may be created in the interconnect structure 52C and the semiconductor substrate 52A of the substrate 52.

[0024] Fig. Figure 4B shows an enlarged sectional view of a portion 74 of the integrated circuit die 50 (see Fig. 4A) according to some embodiments. In some embodiments, the slope 72A of the substrate 52, a sidewall of the passivation layers 64, and a sidewall of the insulating layer 68 are within process variations of the laser grooving process described above with reference to Fig. 3, is substantially coplanar. In some embodiments, an imaginary plane 76 (depicted by a dashed line in Fig. 4B) extending along the slope 72A forms an angle θ with the major surface (i.e., the top surface) of the substrate 52. In some embodiments, the angle θ is about 50° to about 70°. As will be explained in more detail later, the insulating layer 68 is removed in later processing steps. By fabricating the integrated circuit die 50 with sloped sidewalls having the angle θ in the range specified above, a volume of the insulating layer 68 is reduced. By reducing the volume of the insulating layer 68, a removal speed of the insulating layer 68 is increased in the later removal process.

[0025] The Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11A, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17A and Fig. 17B show cross-sectional views of intermediate stages in a method of manufacturing a first package component 100 according to some embodiments. The first package component 100 includes a first package region 100A and a second package region 100B, and in each of the package regions 100A and 100B, one or more of the integrated circuit dies 50 are packaged into an integrated circuit package. The integrated circuit packages may also be referred to as integrated fan-out packages (InFO packages).

[0026] In Fig. 5, a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 102 may be a wafer, so that multiple packages can be formed simultaneously on the carrier substrate 102.

[0027] The release layer 104 may be made of a polymer-based material that can later be removed along with the carrier substrate 102 from overlying structures fabricated in later steps. In some embodiments, the release layer 104 is a heat-removable, epoxy-based material that loses its adhesiveness when heated, such as an LTHC (light-to-heat conversion) release liner. In other embodiments, the release layer 104 may be an ultraviolet (UV) adhesive that loses its adhesiveness when exposed to UV light. The release layer 104 may be dispensed as a liquid and cured, or it may be a laminate layer coated onto the carrier substrate 102, or the like. A top surface of the release layer 104 may be leveled and may have a high degree of planarity.

[0028] In Fig. 6, a redistribution structure 106 may be formed on the release layer 104. The redistribution structure 106 may also be referred to as a backside redistribution structure. In the illustrated embodiment, the redistribution structure 106 includes an insulating layer 108, a metallization structure 110 (sometimes referred to as a redistribution layer or a redistribution line) over the insulating layer 108, and an insulating layer 112 over the metallization structure 110. The redistribution structure 106 is optional and may be omitted in some embodiments. In some embodiments, an insulating layer without metallization structures is formed on the release layer 104 instead of the redistribution structure 106.

[0029] The insulating layer 108 may be formed on the release layer 104. A bottom surface of the insulating layer 108 may be in contact with a top surface of the release layer 104. In some embodiments, the insulating layer 108 is formed from a polymer, such as polybenzoxazole (PBO), a polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the insulating layer 108 is formed from a nitride, such as silicon nitride; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), or the like; or the like. The insulating layer 108 may be formed using any suitable deposition method, such as spin coating, ALD, CVD, lamination, or the like, or a combination thereof.

[0030] The metallization structure 110 can be formed on the insulating layer 108. For example, the metallization structure 110 can be formed by first forming a seed layer (not individually shown) over the insulating layer 108. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising a plurality of sublayers made of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer can be formed, for example, by physical vapor deposition (PVD) or the like. A photoresist (not individually shown) is then formed on the seed layer, which is subsequently patterned. The photoresist can be formed by spin coating or the like and can be exposed for patterning.The structure of the photoresist corresponds to the metallization structure 110. Patterning creates openings through the photoresist to expose the seed layer. A conductive material is deposited in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be deposited by plating, such as electroplating or electroless plating, or the like. The conductive material can be a metal such as copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and the portions of the seed layer on which the conductive material has not been deposited are removed. The photoresist can be removed using a suitable stripping or detachment process, for example, using an oxygen plasma or the like.After the photoresist has been removed, exposed portions of the seed layer are removed, for example, using a suitable etching process, such as wet or dry etching. The remaining portions of the seed layer and the conductive material form the metallization structure 110.

[0031] The insulating layer 112 may be formed on the metallization structure 110 and the insulating layer 108. In some embodiments, the insulating layer 112 may be formed using similar materials and methods as the insulating layer 108, and the description will not be repeated here. In some embodiments, the insulating layer 108 and the insulating layer 112 comprise the same material. In other embodiments, the insulating layer 108 and the insulating layer 112 comprise different materials. Subsequently, the insulating layer 112 is patterned to create openings 114 that expose portions of the metallization structure 110. The patterning may be performed using any suitable method, such as by exposing the insulating layer 112 if it is a photosensitive material, or by etching, for example, by anisotropic etching, if the insulating layer 112 is not a photosensitive material.If the insulating layer 112 is a photosensitive material, it can be developed after exposure.

[0032] Fig. 6 shows a redistribution structure 106 with only one metallization structure 110 for illustration. In some embodiments, the redistribution structure 106 may include any number of insulating layers and metallization structures. If more insulating layers and metallization structures are to be formed, steps and processes discussed above may be repeated. The metallization structures may include one or more conductive elements. The conductive elements may be formed during the formation of the metallization structure by depositing the seed layer and the conductive material of the metallization structure over a surface of the underlying insulating layer and into openings of the underlying insulating layer, thereby physically and electrically connecting various conductive lines.

[0033] In Fig. 7 are placed in the openings 114 (see Fig. 6) Vias 116 are formed extending away from the topmost insulating layer (e.g., insulating layer 112) of redistribution structure 106. As an example for forming vias 116, a seed layer (not individually shown) is formed over redistribution structure 106, e.g., on insulating layer 112 and on portions of metallization structure 110 exposed by openings 114. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sublayers made of different materials. In a specific embodiment, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed, for example, by PVD or the like.A photoresist (not shown individually) is then formed on the seed layer, which is subsequently patterned. The photoresist may be formed by spin coating or the like and may be exposed for patterning. The pattern of the photoresist corresponds to the layout of the vias 116. Patterning creates openings through the photoresist to expose the seed layer. A conductive material is deposited in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be deposited by plating, such as electroplating or electroless plating, or the like. The conductive material may be a metal such as copper, titanium, tungsten, aluminum, or the like. The photoresist and the portions of the seed layer on which the conductive material has not been deposited are then removed.The photoresist can be removed using a suitable stripping process, for example, using an oxygen plasma or the like. After the photoresist has been removed, exposed portions of the seed layer are removed, for example, using a suitable etching process, such as wet or dry etching. The remaining portions of the seed layer and the conductive material form the vias 116. The vias 116 can each have a height of about 245 µm to about 255 µm and a width of about 270 µm to about 290 µm.

[0034] In Fig. 8, the integrated circuit dies 50 ( Fig. 4A) is adhered to the insulating layer 112 with an adhesive 118. In the illustrated embodiments, only one integrated circuit die 50 is adhered in each of the package regions 100A and 100B. In other embodiments, multiple integrated circuit dies 50 may be adhered adjacent to each other in each of the package regions 100A and 100B. The adhesive 118 is located on backsides of the integrated circuit dies 50 and adheres the integrated circuit dies 50 to the redistribution structure 106, such as to the insulating layer 112. The adhesive 118 may be any suitable adhesive, an epoxy, a die attach layer (DAF), or the like.The adhesive 118 may be applied to the backsides of the integrated circuit dies 50; it may be applied over the surface of the carrier substrate 102 if no redistribution structure 106 is used; or it may be applied to a top surface of the redistribution structure 106, if desired. For example, the adhesive 118 may be applied prior to the process described above with reference to FIG. Fig. 4A discussed singulation for separating the integrated circuit dies 50 may be applied to the backsides of the integrated circuit dies 50.

[0035] In Fig. 9, an encapsulation material 120 is formed on and around the various components. Once formed, the encapsulation material 120 encapsulates the vias 116 and the integrated circuit dies 50. The encapsulation material 120 may be a molding compound, such as an epoxy, a resin, a moldable polymer, a combination thereof, or the like, with fillers dispersed therein. The fillers may be insulating fibers, insulating particles (e.g., silicon dioxide particles, glass particles, micrite particles, or the like), other suitable elements, a combination thereof, or the like. The encapsulation material 120 may be applied over the carrier substrate 102 by compression molding, transfer molding, or the like such that the vias 116 and / or the integrated circuit dies 50 are buried or concealed.Encapsulation material 120 is also applied in gap regions between integrated circuit dies 50 and follows the contours of the sidewalls of insulating layer 68. Encapsulation material 120 may be applied in a liquid or semi-liquid form and subsequently cured. If insulating layer 68 is selected to be a polyimide polymer having an ester group and is fabricated as described above with reference to FIG. Fig. 2, this can offer several advantages. For example, the compression molding process for forming the encapsulation material 120 can be performed in such a way that the insulating layer 68 is not deformed. This avoids deformation and damage to the integrated circuit die 50.

[0036] In Fig. 10, a planarization process is performed on the encapsulation material 120 to expose the vias 116 and the integrated circuit dies 50 (e.g., the insulating layer 68). The planarization process may also remove material of the vias 116 and the insulating layer 68 until all of the vias 116 and the insulating layer 68 are exposed. After the planarization process, top surfaces of the vias 116, the insulating layer 68, and the encapsulation material 120 are coplanar within process variations. The planarization process may, for example, be a chemical mechanical polishing (CMP), a grinding process, or the like. In some embodiments, planarization may be omitted, for example, if the vias 116 and / or the insulating layer 68 are already exposed.If the insulating layer 68 is chosen to be a polyimide polymer having an ester group and is prepared as described above with reference to . Fig. 2, this can provide several advantages. For example, the advantages of ensuring that the insulating layer 68 has a desired hardness and maintains its strong adhesion to the substrate 52 and the passivation layer 64 during the planarization process can be achieved to prevent damage to the insulating layer 68 and detachment of the insulating layer 68 from the passivation layer 64. Thus, damage to the integrated circuit die 50 can be avoided.

[0037] In Fig. 11A, the insulating layer 68 (see Fig. 10) is removed from each of the integrated circuit dies 50 to create openings 121 exposing the pads 62 and the passivation layers 64. The insulating layer 68 may be removed, for example, with an isotropic or anisotropic etching process using a dry or wet etchant. As shown, after removing the insulating layer 68, the encapsulant 120 may substantially retain its shape in which the integrated circuit dies 50 overhang due to the sloped sidewalls of the insulating layer 68. The opening 121 may have a width W3 near the substrate 52 of about 30.5 mm to about 30.7 mm and a width W4 at or near the top of the encapsulant 120 of about 30.49 mm to about 30.5 mm. In some embodiments, the width W4 may be about 0.7% to about 0.13% smaller than the width W3 (or about 99.93% to about 99.87% of the width W3).As a result, the encapsulation material 120 can overhang the opening 121 by a distance D1 of approximately 10 µm to approximately 20 µm.

[0038] In some embodiments, a wet etching process uses a wet etchant containing a stripping agent, such as SPR920 or the like. In some embodiments, SPR920 is a solution containing a base such as tetramethylammonium hydroxide (TMAH), dimethyl sulfoxide (DMSO), and water, where the TMAH has a mass fraction of about 1% to about 2%, the DMSO has a mass fraction of about 96% to about 98%, and the water has a mass fraction of about 1% to about 2%. The wet etching process can be performed at a temperature of 48°C to about 52°C and for a duration of about 3 minutes to about 10 minutes.

[0039] Fig. Figure 11B shows a possible generic mechanism, and Fig. Figure 11C shows a possible specific mechanism for how the main component of the wet etchant (e.g., TMAH in SPR920) can interact with and remove the insulating layer 68. The main component of the wet etchant (e.g., the negatively charged portions of the base, such as the hydroxyl groups in TMAH) can attract positively charged portions of the insulating layer 68. The electrophilic functional group FG attracts electrons from the molecules of the insulating layer 68 away from other portions of the molecules. For example, by attracting electrons to the electrophilic functional group FG, the carbon atoms in the cyclic imide group can have a slightly positive charge. Therefore, the TMAH can break apart the molecules of the insulating layer 68 to be removed in the wet etching process.

[0040] In Fig. 11C, in which the molecules of insulating layer 68 may include an ester group as the electrophilic functional group FG, additional sites on the molecule may attract the wet etchant. For example, in addition to the carbon atoms of the cyclic imide group, the carbon atom of the ester group may also have a slightly positive charge because electrons are attracted to the oxygen atoms of the ester group. Therefore, the molecules of insulating layer 68, which comprise a polyimide with an ester chemical structure, may provide additional sites for the negatively charged portions of the base (e.g., TMAH) to efficiently disrupt insulating layer 68.

[0041] Alternatively, in embodiments using a dry etching process, the dry etchant may contain oxygen (O2), nitrogen (N2), or the like, or combinations thereof. The dry etching process may be performed at a temperature of about 23°C to about 26°C, at a pressure of about 45 Pa to about 55 Pa, and for a duration of about 24 minutes to about 30 minutes.

[0042] If the insulating layer 68 is chosen to be a polyimide polymer having an ester group and is prepared as described above with reference to Fig. 2, this has the advantage of improving efficiency and yield in the isotropic wet etching process described above, which uses, for example, SPR920 containing TMAH. As a result, unlike the dry etching process described above, which can process approximately 9 wafers per hour, the wet etching process can process up to approximately 167 wafers per hour. Furthermore, the wet etching process can be approximately three or four times cheaper than the dry etching process.

[0043] Let’s get to Fig. 11A. In some embodiments, the process for removing the insulating layer 68 (see Fig. 10) roughening the top surface of the encapsulation material 120 such that the encapsulation material 120 has a roughened top surface 120t. In some embodiments, a roughness of the top surface of the encapsulation material 120 after performing the above-described wet etching process is greater than a roughness of the top surface of the encapsulation material 120 after performing the above-described dry etching process. In embodiments using the above-described wet etching process, the roughened top surface 120t of the encapsulation material 120 has a roughness of about 0.5 μm to about 0.7 μm. In embodiments using the above-described dry etching process, the roughened top surface 120t of the encapsulation material 120 has a roughness of about 0.1 μm to about 0.2 μm.

[0044] In some embodiments, in the process of removing the insulating layer 68 (see Fig. 10) Furthermore, the top surfaces of the vias 116 are roughened, and the vias 116 have roughened top surfaces 116t. In some embodiments, a roughness of the top surfaces of the vias 116 after performing the above-described wet etching process is greater than a roughness of the top surfaces of the vias 116 after performing the above-described dry etching process because a conductive material (such as copper) of the vias 116 corrodes in the wet etching process. In embodiments using the above-described wet etching process, the roughened top surfaces 116t of the vias 116 have a roughness of about 0.02 μm to about 0.2 μm. In embodiments using the dry etching process described above, the roughened top surfaces 116t of the vias 116 have a roughness of about 0.01 µm to about 0.05 µm.

[0045] In the Fig. 12 to 15, a redistribution structure 122 (see Fig. 15) is formed over the encapsulation material 120, the vias 116, and the integrated circuit dies 50. The redistribution structure 122 may also be referred to as a front-side redistribution structure. The redistribution structure 122 includes insulating layers 124 and 128 and a metallization structure 126. More insulating layers and metallization structures may also be formed in the redistribution structure 122. The metallization structures may be referred to as redistribution layers or redistribution lines. The redistribution structure 122 is shown as an example with only one metallization structure. If more insulating layers and metallization structures are to be formed, the steps and processes described below may be repeated.

[0046] In Fig. 12, the insulating layer 124 is deposited on the encapsulation material 120, on the vias 116 and in the openings 121 (see Fig. 11A) are deposited over the substrates 52 of the integrated circuit dies 50. As shown, the insulating layer 124 may substantially fill the openings 121. In some embodiments, the insulating layer 124 may be formed using similar materials and methods as the insulating layer 108 described above with reference to Fig. 6, and the description will not be repeated here. In some embodiments, a planarization process is performed to impart a substantially planar top surface to the insulating layer 124. In some embodiments, portions of the insulating layer 124 that are directly above the integrated circuit dies 50 and below the top surface of the encapsulation material 120 have substantially the same profile as the portions shown in Fig. 10, since these parts of the insulating layer 124 cover the openings 121 ( Fig. 11A) that were created after removing the insulating layer 68. The insulating layer 124 may have a thickness directly above the encapsulation material 120 of about 9 µm to about 11 µm.

[0047] In some embodiments, the roughened top surface 120t of the encapsulation material 120 improves the adhesion between the encapsulation material 120 and the insulating layer 124. In embodiments in which the roughened top surface 120t described above with reference to Fig. 11A is used, the higher roughness of the roughened top surface 120t of the encapsulation material 120 improves the adhesion between the encapsulation material 120 and the insulating layer 124 compared to embodiments in which the wet etching process described above with reference to Fig. 11A is used.

[0048] In some embodiments, the roughened top surfaces 116t of the vias 116 improve the adhesion between the vias 116 and the insulating layer 124. In embodiments in which the method described above with reference to Fig. 11A is used, the higher roughness of the roughened top surfaces 116t of the vias 116 improves the adhesion between the vias 116 and the insulating layer 124 compared to embodiments in which the wet etching process described above with reference to Fig. 11A is used.

[0049] In Fig. 13, the insulating layer 124 is then patterned. The patterning creates openings 130 that expose portions of the vias 116; openings 132 that expose portions of the pads 62; and openings 134 that expose the passivation layer 64 directly above the sensor elements 54. The patterning can be performed using a suitable method, such as by exposing and developing the insulating layer 124 if it is a photosensitive material. In other embodiments where the insulating layer 124 is not a photosensitive material, a mask layer (not individually shown) can be formed and patterned over the insulating layer 124, and exposed portions of the insulating layer 124 can be removed, for example, by etching. The opening 134 can have a width W5 of approximately 29.3 mm to approximately 29.4 mm.

[0050] In Fig. 14, the metallization structure 126 is then formed. The metallization structure 126 comprises conductive elements that extend along the main surface of the insulating layer 124 and through the insulating layer 124 to be physically and electrically connected to the vias 116 and the pads 62 of the integrated circuit dies 50. For example, the metallization structure 126 may be formed by depositing a seed layer (not individually shown) over the insulating layer 124 and in the openings (e.g., the openings 130, the openings 132, and the openings 134 shown in Fig. 13) extending through the insulating layer 124. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sublayers made of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed, for example, by PVD or the like. A photoresist (not individually shown) is then formed on the seed layer, which is subsequently patterned. The photoresist may be formed by spin coating or the like and may be exposed for patterning. The pattern of the photoresist corresponds to the metallization pattern 126.Patterning creates openings through the photoresist to expose the seed layer (which includes portions in openings 130 above vias 116 and in openings 132 above pads 62). A conductive material is then deposited in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be deposited by plating, such as electroplating or electroless plating, or the like. The conductive material may be a metal such as copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and underlying portions of the seed layer forms the metallization structure 126. The photoresist and the portions of the seed layer (which include portions of the photoresist and seed layer in openings 134 above sensor elements 54) on which the conductive material has not been deposited are then removed.The photoresist may be removed using a suitable stripping process, for example, using an oxygen plasma or the like. After the photoresist has been removed, exposed portions of the seed layer are removed, for example, using a suitable etching process, such as wet or dry etching. The metallization structure 126 may have a thickness of about 4 µm to about 5 µm.

[0051] In Fig. 15, the insulating layer 128 is deposited on the metallization structure 126 and the insulating layer 124. In some embodiments, the insulating layer 128 may be formed using similar materials and methods as those described above with reference to Fig. 6, and the description will not be repeated here. In some embodiments, the insulating layer 124 and the insulating layer 128 comprise the same material. In other embodiments, the insulating layer 124 and the insulating layer 128 comprise different materials. The insulating layer 128 may be patterned in a similar manner to the insulating layer 124 to create openings 136. The patterning may be performed, for example, using a suitable method, such as by exposing and developing the insulating layer 128 if it is a photosensitive material, or by etching, for example, anisotropic etching, if the insulating layer 128 is not a photosensitive material. The openings 136 may have a width W6 in the insulating layer 124 and a width W7 in the insulating layer 128.In some embodiments, the width W6 of the openings 136 may be substantially equal to the width W5 of the openings 134 (see . Fig. 14), and the width W7 of the openings 136 may be greater than the width W6 of the openings 136. For example, the width W6 may be about 29.25 mm to about 29.35 mm, and the width W7 may be about 29.35 mm to about 29.39 mm. In other embodiments, the openings 134 may not be created during patterning of the insulating layer 124, as described above with reference to Fig. 13. In these embodiments, the openings 136 may be created by simultaneously patterning the insulating layer 124 and the insulating layer 128. The insulating layer 128 may have a thickness directly above the encapsulation material 120 of about 8.5 µm to about 11 µm.

[0052] Although not individually illustrated, in embodiments where the integrated circuit dies 50 are to be connected through the insulating layer 128, under-bump metallizations (UBMs) for external connection to the redistribution structure 122 may be formed, for example, for integrated circuit dies 50 that are logic devices or memory devices. In some embodiments, and as discussed above, the integrated circuit dies 50 that are logic devices or memory devices may have external connections via the metallization structure 126, the vias 116, and the redistribution structure 106. In some embodiments, the package regions (e.g., the first package region 100A and / or the second package region 100B) that include integrated circuit dies that are sensor dies may not include UBMs.

[0053] In Fig. 16, a carrier substrate detachment for detaching the carrier substrate 102 (see Fig. 15) from the redistribution structure 106 (e.g., the dielectric layer 108). In some embodiments, the release comprises projecting light, such as laser light or UV light, onto the release layer 104 so that the heat of the light decomposes the release layer 104 and the carrier substrate 102 can be removed. The structure is then flipped and placed on a belt (not individually shown) to fabricate additional structures, such as conductive interconnect elements 152 described below.

[0054] In addition, Fig. 16 conductive interconnects 152 are formed to extend through the insulating layer 108 to contact the metallization structure 110. Openings are formed through the insulating layer 108 to expose portions of the metallization structure 110. The openings may be formed, for example, by laser drilling, etching, or the like. The conductive interconnects 152 are formed in the openings. In some embodiments, the conductive interconnects 152 comprise a flux and are formed using a flux dipping process. In some embodiments, the conductive interconnects 152 comprise a conductive paste, such as solder paste, silver paste, or the like, and are applied using a printing process.The conductive interconnects 152 may be BGA (Ball Grid Array) interconnects, solder balls, metal pillars, C4 (Controlled Collapse Chip Interconnect), microbumps, ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) bumps, or the like. The conductive interconnects 152 may comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive interconnects 152 are formed by first forming a layer of solder by evaporation, electroplating, printing, solder transfer, ball placement, or the like. After the layer of solder is formed on the structure, a reflow process may be performed to form the material into the desired bump shapes.In another embodiment, the conductive interconnect elements 152 are metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal capping layer is formed on the metal pillars. The metal capping layer may comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like, or a combination thereof, and may be formed using a plating process.

[0055] In Fig. 17, a singulation process is carried out by sawing along scribe trench areas (not shown individually), for example, between the first package area 100A and the second package area 100B (see Fig. 16). By sawing, the first package region 100A is separated from the second package region 100B to produce individual first package components 100. The illustrated individual first package component 100 originates either from the first package region 100A or the second package region 100B.

[0056] In some embodiments, a first roughness of a first portion of the roughened top surface 120t of the encapsulation material 120 on an inclined sidewall of the encapsulation material 120 inside the first package component 100 is different from a second roughness of a second portion of the roughened top surface 120t of the encapsulation material 120 at an edge of the first package component 100. In some embodiments, the first roughness of the roughened top surface 120t of the encapsulation material 120 is greater than the second roughness of the roughened top surface 120t of the encapsulation material 120. A difference between the first roughness of the roughened top surface 120t of the encapsulation material 120 and the second roughness of the roughened top surface 120t of the encapsulation material 120 may also be referred to as a uniformity of the roughened top surface 120t of the encapsulation material 120. In embodiments in which the above-mentioned with reference to Fig. 11A is used, the roughened top surface 120t of the encapsulation material 120 has a uniformity of less than about 0.1 µm. In embodiments in which the wet etching process described above with reference to Fig. 11A is used, the roughened top surface 120t of the encapsulation material 120 has a uniformity of greater than about 0.5 µm.

[0057] Fig. 17B shows an enlarged sectional view of a portion 138 of the first package component 100 (see Fig. 17A) according to some embodiments. In some embodiments, the slope 72A of the substrate 52, a sidewall of the passivation layer 64, and a sidewall of the insulating layer 124 are substantially coplanar. In some embodiments, an imaginary plane 140 (shown in Fig. 17B) extending along the slope 72A, forms an angle θ with the major surface (i.e., the top surface) of the substrate 52. In some embodiments, the angle θ is about 50° to about 70°. In some embodiments, an interface between the encapsulation material 120 and the integrated circuit die 50 includes a first portion (such as an interface between the encapsulation material 120 and the slope 72A) having a first slope and a second portion (such as an interface between the encapsulation material 120 and the slope 72B) having a second slope different from the first slope. The first slope is equal to a slope of the slope 72A. The second slope is equal to a slope of the slope 72B.

[0058] Fig.18 illustrates fabrication and implementation of device stacks according to some embodiments. The device stacks are fabricated from the integrated circuit packages fabricated in the first package component 100. The device stacks may also be referred to as package-on-package (PoP) structures. The first package component 100 is connected to a second package component 200 via conductive interconnects 152. In some embodiments (not shown), more than one first package component 100 may be connected to the second package component 200 via conductive interconnects 152.

[0059] In some embodiments, the second package component 200 may include an interposer or a package substrate, including a substrate 202, an upper redistribution structure 204, and a lower redistribution structure 206 such that the substrate 202 is sandwiched between the upper redistribution structure 204 and the lower redistribution structure 206. The substrate 202 may include vias 208 to electrically connect the upper redistribution structure 204 to the lower redistribution structure 206. The substrate 202 may not include active and passive devices.

[0060] The substrate 202 may be fabricated using any suitable method and may, for example, comprise a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, composite materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like may also be used. Furthermore, the substrate 202 may be a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. In an alternative embodiment, the substrate 202 is based on an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is glass fiber resin, such as FR4.Alternatives for the core material include bismaleimide triazine (BT) resin or, alternatively, other printed circuit board (PCB) materials or layers. Build-up layers, such as an Ajinomoto build-up layer (ABF), or other laminates can also be used for the substrate 202.

[0061] In an alternative embodiment, the second package component 200 may be a process controller, such as a digital processing chip, e.g., a multilayer digital processing chip or controller (ML-DPC). In these embodiments, the second package component 200 is fabricated on a wafer, which is then singulated into individual components. The process controller monitors the output signals of the sensor elements 54 of the first package component 100 and controls the function of the sensor elements 54 in coordination with other devices that comprise the overall sensor device. Although not individually illustrated, in some embodiments, the substrate 202 (e.g., a silicon substrate) may include active and passive devices.To meet the structural and functional design requirements for the second package component 200, a wide variety of devices may be used, such as transistors, capacitors, resistors, combinations thereof, or the like. The devices may be manufactured using any suitable method.

[0062] Although not individually illustrated, the substrate 202 may also include an interconnect structure above the active and passive devices, designed to connect the active and passive devices into a functional circuit. The interconnect structure may be formed from alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper), with vias connecting the layers of conductive materials and may be formed using a suitable process such as deposition, single-damascene process, dual-damascene process, or the like. In addition, the vias 208 may extend through the substrate 202 to electrically connect portions of the upper redistribution structure 204 to portions of the lower redistribution structure 206.

[0063] The second package component 200 may further include bond pads 210 on a top surface of the upper redistribution structure 204 for electrically and mechanically connecting to the conductive connection elements 152 of the first package component 100. In some embodiments, the bond pads 210 are formed by creating recesses (not shown) in dielectric layers on the top surface of the redistribution structure 204. The recesses may be created such that the bond pads 210 can be embedded in the dielectric layers. In other embodiments, the recesses are omitted, as the bond pads 210 can be formed on the dielectric layer.

[0064] After the second package component 200 has been manufactured, the first package component 100 is mechanically and electrically bonded to the second package component 200 by means of the conductive connecting elements 152 of the first package component 100 and the upper redistribution structure 204 of the second package component 200.

[0065] In some embodiments, a solder resist (not shown) is formed on the upper redistribution structure 204. The conductive interconnects 152 may be disposed in openings in the solder resist to electrically and mechanically connect to conductive interconnects (e.g., the bond pads 210) in the second package component 200. The solder resist may be used to protect portions of the second package component 200 (e.g., the upper redistribution structure 204) from external damage. In some embodiments, an epoxy flux (not shown) is applied to the conductive interconnects 152 before they are reflowed, with at least the epoxy portion of the epoxy flux remaining after the first package component 100 has been attached to the second package component 200.

[0066] In some embodiments, an underfill (not shown) is formed between the first package component 100 and the second package component to enclose the conductive interconnects 152. The underfill may reduce mechanical stress and protect interconnects resulting from reflow of the conductive interconnects 152. The underfill may be formed using a capillary flow process after the first package component 100 has been attached to the second package component 200, or it may be formed using a suitable deposition process before the first package component 100 is attached to the second package component 200. In embodiments where the epoxy flux is applied, it may function as the underfill.

[0067] In some embodiments, additional functional components, such as one or more surface mount devices (SMDs) 212 (e.g., capacitors, resistors, inductors, or the like) and an interconnect structure 214 (e.g., a connector), are electrically and mechanically connected to the second package component 200. In some embodiments, when the second package component 200 is a process controller, it is fabricated on a wafer, which is then diced into individual components. The one or more SMDs 212 and the interconnect structure 214 may be attached to the lower redistribution structure 206 before or after the dicing process to fabricate the second package component 200.In some embodiments, the one or more SMDs 212 and the interconnect structure 214 are attached to the lower redistribution structure 206 after the first package component 100 has been attached to the upper redistribution structure 204. In the illustrated embodiment, the one or more SMDs 212 and the interconnect structure 214 are attached to the lower redistribution structure 206. In other embodiments, some or all of the SMDs 212 and the interconnect structure 214 are attached to the upper redistribution structure 204. Although not individually illustrated, the interconnect structure 214 may also be connected to other packages or devices.

[0068] The first package component 100 can also be implemented in other devices. As an example, a PoP structure is shown, but the first package component 100 can also be implemented in an FCBGA (Flip Chip Ball Grid Array) package. Other elements and processes can also be used. For example, test structures can be used to assist in the verification testing of a 3D package or 3DIC devices. The test structures can include, for example, test pads fabricated in a redistribution layer or on a substrate that enable testing of the 3D package or 3DIC devices, the use of probes and / or probe cards, and the like. The verification testing can be performed on intermediate structures as well as on the final structure.In addition, the structures and methods disclosed herein may be used in conjunction with test methodologies that include intermediate verification of proven good dies to increase yield and reduce cost.

[0069] Embodiments may achieve advantages. For example, by forming the insulating layer 68 as described above, the efficiency and yield of the overall manufacturing process may be improved. In particular, the insulating layer 68 is formed to be stable during later processing. For example, the insulating layer 68 has a high glass transition temperature and decomposition temperature, so that the insulating layer 68 can maintain a substantially uniform composition and robust adhesion to the substrate 52 and the passivation layer 64 and can prevent deformation during later steps for which, for example, elevated temperatures may be used (e.g., forming the encapsulation material 120). The high tensile strength and high elastic modulus improve the lifetime and adhesion to the substrate 52 and the passivation layers 64 during later planarization (e.g.,Grinding) of the encapsulation material 120 is further improved. Furthermore, the special composition of the insulating layer 68 (e.g., a polyimide with an ester group) facilitates quick and efficient removal using a wet etching process.

[0070] According to one embodiment, a package includes an integrated circuit die. A sidewall of the integrated circuit die has a first slope and a second slope. The first slope and the second slope have different gradients. The package further includes an encapsulation material surrounding the integrated circuit die and in physical contact with the first slope and the second slope; and an insulating layer over the integrated circuit die and the encapsulation material. A top surface of the integrated circuit die is lower than a top surface of the encapsulation material. A sidewall of the insulating layer is coplanar with the first slope.

[0071] Embodiments may have one or more of the following features. The package further includes a via extending through the encapsulation material adjacent to the integrated circuit die. In the package, a width of the insulating layer increases as the insulating layer extends from the top surface of the encapsulation material to the top surface of the integrated circuit die. The package further includes a redistribution layer over the insulating layer, wherein a portion of the redistribution layer extends through the insulating layer and is electrically connected to the integrated circuit die. In the package, the top surface of the encapsulation material has a roughness of about 0.5 µm to about 0.7 µm. In the package, the first slope and the top surface of the integrated circuit die form a first angle, wherein the first angle is about 50° to about 70°.In the package, the second slope is substantially perpendicular to the top surface of the integrated circuit die.

[0072] According to another embodiment, a package comprises an integrated circuit die; an encapsulation material in physical contact with sidewalls of the integrated circuit die; and a first redistribution structure over the integrated circuit die and the encapsulation material. A first interface between the encapsulation material and the integrated circuit die comprises a first portion having a first slope and a second portion having a second slope different from the first slope. The first redistribution structure comprises an insulating layer having a first portion extending along a top surface of the encapsulation material and a second portion extending from the top surface of the encapsulation material to the integrated circuit die. A second interface between the second portion of the insulating layer and the encapsulation material is coplanar with the first portion of the first interface.

[0073] Embodiments may have one or more of the following features. The package further comprises a second redistribution structure, wherein the integrated circuit die is sandwiched between the first redistribution structure and the second redistribution structure. The package further comprises a via extending through the encapsulation material adjacent to the integrated circuit die, the via electrically connecting the first redistribution structure to the second redistribution structure. In the package, a roughness of a top surface of the via is about 0.02 µm to about 0.2 µm. In the package, a roughness of a third interface between the first portion of the insulating layer and the encapsulation material is about 0.5 µm to about 0.7 µm.In the package, the first portion of the first interface and a top surface of the integrated circuit die form a first angle, the first angle being about 50° to about 70°. In the package, the second portion of the first interface is substantially perpendicular to the top surface of the integrated circuit die.

[0074] According to yet another embodiment, a method comprises attaching an integrated circuit die to a first insulating layer. The integrated circuit die comprises: a substrate; a pad over the substrate; and a second insulating layer over the pad and the substrate. A sidewall of the substrate has a first slope and a second slope. The first slope and the second slope have different gradients. A sidewall of the second insulating layer is coplanar with the first slope. The method further comprises forming an encapsulation material around the integrated circuit die; and removing the second insulating layer to create a first opening in the encapsulation material.

[0075] Embodiments may have one or more of the following features. In the method, the second insulating layer comprises a polyimide having an ester group. In the method, removing the second insulating layer comprises performing a wet etching process. In the method, the wet etching process is performed using a solution containing tetramethylammonium hydroxide (TMAH), dimethyl sulfoxide (DMSO), and water. The method further comprises forming a redistribution structure over the integrated circuit die and the encapsulation material, wherein a third insulating layer of the redistribution structure fills the first opening. The method further comprises creating a second opening in the redistribution structure, wherein the second opening exposes the integrated circuit die.

Claims

[1] Package with: an integrated circuit die (50), wherein a sidewall of the integrated circuit die (50) has a first slope (72A) and a second slope (72B), the first slope (72A) and the second slope (72B) having different gradients; an encapsulation material (120) surrounding the integrated circuit die (50) and in physical contact with the first slope (72A) and the second slope (72B), wherein a top surface of the integrated circuit die (50) is lower than a top surface of the encapsulation material (120); and an insulating layer (124) over the integrated circuit die (50) and the encapsulation material (120), wherein a sidewall of the insulating layer (124) is coplanar with the first slope (72A). [2] The package of claim 1, further comprising a via (116) extending through the encapsulation material (120) adjacent the integrated circuit die (50). [3] The package of claim 1 or 2, wherein a width of the insulating layer (124) increases as the insulating layer (124) extends from the top surface of the encapsulation material (120) to the top surface of the integrated circuit die (50). [4] The package of any preceding claim, further comprising a redistribution layer (126) over the insulating layer (124), a portion of the redistribution layer (126) extending through the insulating layer (124) and being electrically connected to the integrated circuit die (50). [5] Package according to one of the preceding claims, wherein a roughness of the top surface (120t) of the encapsulation material (120) is about 0.5 µm to about 0.7 µm. [6] The package of any preceding claim, wherein the first slope (72A) and the top surface of the integrated circuit die (50) enclose a first angle, the first angle being about 50° to about 70°. [7] A package according to any preceding claim, wherein the second slope (72B) is perpendicular to the top surface of the integrated circuit die (50). [8] Package with: an integrated circuit die (50); an encapsulation material (120) in physical contact with sidewalls of the integrated circuit die (50), wherein a first interface between the encapsulation material (120) and the integrated circuit die (50) has a first portion with a first slope and a second portion with a second slope different from the first slope; and a first redistribution structure (122) over the integrated circuit die (50) and the encapsulation material (120), the first redistribution structure (122) comprising an insulating layer (124) having a first portion extending along a top surface of the encapsulation material (120) and a second portion extending from the top surface of the encapsulation material (120) to the integrated circuit die (50), a second interface between the second portion of the insulating layer (124) and the encapsulation material (120) being coplanar with the first portion of the first interface. [9] The package of claim 8, further comprising a second redistribution structure (122), wherein the integrated circuit die (50) is sandwiched between the first redistribution structure (122) and the second redistribution structure (122). [10] The package of claim 9, further comprising a via (116) extending through the encapsulation material (120) adjacent to the integrated circuit die (50), the via (116) electrically connecting the first redistribution structure (122) to the second redistribution structure (122). [11] The package of claim 10, wherein a roughness of a top surface (116t) of the via (116) is about 0.02 µm to about 0.2 µm. [12] Package according to one of claims 8 to 11, wherein a roughness of a third interface between the first part of the insulating layer (124) and the encapsulation material (120) is about 0.5 µm to about 0.7 µm. [13] The package of any one of claims 8 to 12, wherein the first portion of the first interface and a top surface of the integrated circuit die (50) enclose a first angle, the first angle being about 50° to about 70°. [14] The package of claim 13, wherein the second portion of the first interface is perpendicular to the top surface of the integrated circuit die (50). [15] Procedure with the following steps: Attaching an integrated circuit die (50) to a first insulating layer (112), the integrated circuit die (50) comprising: a substrate (52), wherein a side wall of the substrate (52) has a first slope (72A) and a second slope (72B), wherein the first slope (72A) and the second slope (72B) have different gradients, a pad (62) above the substrate (52), and a second insulating layer (68) over the pad (62) and the substrate (52), wherein a sidewall of the second insulating layer (68) is coplanar with the first slope (72A); Producing an encapsulation material (120) around the integrated circuit die (50); and Removing the second insulating layer (68) to create a first opening (121) in the encapsulation material (120). [16] The method of claim 15, wherein the second insulating layer (68) comprises a polyimide having an ester group. [17] The method of claim 15 or 16, wherein removing the second insulating layer (68) comprises performing a wet etching process. [18] The method of claim 17, wherein the wet etching process is performed using a solution containing tetramethylammonium hydroxide (TMAH), dimethyl sulfoxide (DMSO) and water. [19] The method of any one of claims 15 to 18, further comprising forming a redistribution structure (122) over the integrated circuit die (50) and the encapsulation material (120), wherein a third insulating layer (124) of the redistribution structure (122) fills the first opening (121). [20] The method of claim 19, further comprising creating a second opening (134) in the redistribution structure (122), the second opening (134) exposing the integrated circuit die (50).

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