ERROR DETECTION SCHEMES FOR ANALOGUE CONTENT ADDRESSABLE MEMORY

Abstract

Circuit (600) which has the following features: an analog content-addressable memory aCAM array (610) comprising a row of aCAM cells (610 (A) - (Y)) electrically connected along a matching line, each aCAM cell from the row of aCAM cells being programmed to store an analog voltage threshold representing an entry of a word programmed representatively across the row of aCAM cells, wherein: the row of aCAM cells contains a redundancy aCAM cell (610(A)(n-1) - 610(Y)(n-1)) which is programmed to store a calculated redundancy analog voltage threshold, and The redundancy analog voltage threshold is calculated such that each row of a binary array representing the word in binary digits contains a sequence of ones and zeros specified by a binary parity check matrix.

Description

background

[0001] Content-addressable memory ("CAM") is a type of computer memory in which stored data is searched for by its content rather than its location. When a "word" is entered into a CAM, the CAM searches for that word in its contents. If the CAM finds the word (i.e., "returns a match"), it returns the address of the location where the found word is located.

[0002] Analog CAMs (“aCAMs”) are special types of CAMs that can store and search ranges of values ​​(unlike more traditional digital-based CAMs that can only store / search zeros and ones) using the programmable conductance of memristors.

[0003] Individual aCAM cells can be arranged in aCAM arrays consisting of rows and columns of aCAM cells. Words can be stored along the rows of the aCAM array (the rows of an aCAM array can be referred to as "match lines"), with each aCAM cell of a particular row storing one entry of the stored word. When the aCAM array receives an input word (e.g., a series of analog voltage signals, each representing one entry of the input word), the aCAM array can search for the input word along the columns of the aCAM array (i.e., a first entry of the input word can be searched for in a first column of the aCAM array, a second entry of the input word can be searched for in a second column of the aCAM array, etc.). The aCAM array "finds" the input word in a given row if all aCAM cells of the given row provide a match for their respective entries of the input word. ROTH, RM: Analog Error-Correcting Codes. In: IEEE Transactions on Information Theory, Vol. 66, No. 7, July 2020, pages 4075–4088, describes techniques for detecting errors in analog memories. Brief description of the drawings

[0004] The present disclosure will be described in detail in accordance with one or more various examples with reference to the following figures. The figures are for illustrative purposes only and show examples only. Fig. Figure 1 shows an example of an aCAM array consistent with the technology disclosed herein. Fig. Figure 2 shows an example circuit consistent with the technology disclosed herein. Fig. 3 shows an example table according to examples of the technology disclosed herein. Fig. Figure 4 shows another example table consistent with the technology disclosed herein. Fig. Figure 5 shows another example table consistent with the examples of the technology disclosed herein. Fig. Figure 6 shows an example circuit consistent with the technology disclosed herein. Fig. Figure 7 shows an example circuit consistent with the technology disclosed herein. Fig. Figure 8 shows an example circuit consistent with examples of the technology disclosed herein. Fig. 9 shows a block diagram of an example computer system in which various of the examples described herein may be implemented.

[0005] The figures are not exhaustive and do not limit the present disclosure to the precise form disclosed. Detailed description

[0006] Content-addressable memories (CAMs) are powerful, efficient, and fast. However, traditional CAMs (i.e., digital / non-analog CAMs) are also relatively large, consume high power, and are relatively expensive. These disadvantages have historically limited the applicability of CAMs to select applications where their performance, efficiency, and speed are so desirable that they outweigh their size, cost, and power consumption.

[0007] However, recent advances in analog CAMs (aCAMs) have led to significant reductions in size, cost, and power consumption (an aCAM can be considered a special type of CAM here). Accordingly, aCAMs have recently been introduced as valuable accelerators for various computational tasks, including matrix multiplication, machine learning tasks such as tree-based inference, analog signal processing, scientific computing, and so on.

[0008] Although aCAMs are generally more powerful, efficient, and faster than other non-CAM memory / memory processing circuits, they can be prone to errors from several sources, including: (1) inaccurate programming of conductances for memristors (e.g., the conductance a memristor is actually programmed to may differ from the intended value); (2) drift of stored conductances over time (e.g., the conductance a memristor was originally programmed to may drift over time, so that the conductance the memristor actually stores differs from the originally programmed value); (3) manufacturing defects (e.g., short cells or open cells), etc.If one or more aCAM cells of an aCAM row contain an error, the aCAM row may (a) erroneously return a match for an input word that the aCAM row was not programmed / intended to store, or (b) erroneously return a mismatch for an input word that the aCAM row was actually programmed / intended to store. These erroneous match outputs can degrade the performance of an aCAM array. For example, the aCAM array may not correctly / effectively perform a particular computational task. For this reason, the ability to detect errors in aCAM arrays can be very important.

[0009] However, error detection techniques are currently lacking in this emerging technology area (this is partly because error detection techniques in other memory devices are not suitable for aCAMs due to differences in functionality). Furthermore, existing (and immature) approaches to detecting errors in aCAM arrays are generally inefficient and can consume significant computational resources. For example, errors in an aCAM array can be detected by sequentially reading the conductance values ​​stored in each cell of the aCAM array using the aCAM array's read circuitry. However, this approach can require a tremendous number of read operations for larger aCAM arrays. For an aCAM array with 512 rows and 50 columns, for example, error detection by sequentially reading the conductance values ​​using the aCAM array's read circuitry would require 25.600 read operations, which, as already mentioned, would consume significant computing resources. Accordingly, there is a need for more efficient error detection methods in this emerging and valuable technology area.

[0010] With this in mind, examples of the technology disclosed herein provide new circuits for detecting errors in aCAMs with improved efficiency. These circuits, specifically designed for the structure and operation of aCAM arrays, include counter subcircuits (e.g., modulo-2 counter subcircuits) electrically connected to match lines of aCAM rows such that the counter subcircuits receive match-related signals output by aCAM rows (i.e., a given counter subcircuit receives match-related signals output by an aCAM row that is electrically connected to the same match line as the given counter subcircuit).The match-related signals output by an aCAM row may include a match signal when each aCAM cell of the aCAM row returns a match in response to an input vector applied to the circuit, and a mismatch signal when at least one of the aCAM cells of the aCAM row returns a mismatch in response to the input vector applied to the circuit (such an input vector may include a plurality of analog voltage signals, each analog voltage signal being applied to a different column of the aCAM array, or a digital signal / series of digital signals that are converted to analog voltage signals before being applied to the columns of the aCAM array).The value stored by a counter subcircuit can change in response to receiving a match signal and can remain the same in response to receiving a mismatch signal. As described in more detail below, the stored value of the counter subcircuit can be used to detect / identify a fault in the associated aCAM row after a set of (specially calculated) fault detection input vectors have been sequentially applied to the circuit.

[0011] In certain implementations, the circuit may also include "redundancy aCAM cells" programmed to store (specially calculated) redundancy values ​​used for error detection purposes (as described below, in other implementations these redundancy values ​​may instead be stored in memory external to the aCAM array and then imposed on the circuit by strategically initializing and reinitializing the values ​​stored by the counter subcircuits before and / or during the application of error detection input vectors).For example, redundancy values ​​can be programmed into an aCAM row by programming the conductance of memristors in one or more redundancy aCAM cells added to the aCAM row (these redundancy aCAM cells, along with the non-redundancy aCAM cells, are electrically connected to a match line and can therefore be considered part of the aCAM row). Here, the non-redundant aCAM cells (i.e., the "task-driven aCAM cells") of the aCAM row can be freely programmed as required by a computational task for which the aCAM array is used.As described in more detail below, the redundancy values ​​can be calculated using a parity check matrix (H) (as used here, a parity check matrix can refer to a matrix or similar representation that describes conditions that a codeword of a code must satisfy - the parity check matrix (H) can be calculated based on a number of columns in the aCAM array and a maximum number of errors (τ) that can be detected per aCAM row). Using the parity check matrix (H), the redundancy values ​​can be calculated such that each row of the aCAM array is programmed to "representatively" store at least one codeword of a code (C) (an aCAM cell effectively stores an analog voltage threshold - the value of this analog voltage threshold can be programmed by programming the conductance of the memristor that makes up the aCAM cell).Here, a codeword (representative) can be programmed for all aCAM cells of an aCAM row or for a subset of aCAM cells of the aCAM row. The code (C) can refer to the number of programmable levels of the aCAM cells of the aCAM array (as described in more detail below, the number of programmable levels for an aCAM cell can be proportional to the number of unique / discrete conductance values ​​to which the memristor forming the aCAM cell is reliably programmable). In certain implementations (e.g.the internal redundancy implementation for the "bit interleaving" scheme described below), the calculation of redundancy values ​​such that each row of the aCAM array is programmed to store at least one codeword of the code (C) (representatively) may correspond to the calculation of redundancy values ​​such that each row of a binary array representing the word programmed over a given aCAM row (representatively) in binary digits (i.e., ones and zeros) contains a sequence of ones and zeros predetermined by the parity check matrix (H).These sequences - imposed on the given aCAM row by programming redundancy analog voltage thresholds in the redundancy aCAM cells of the given aCAM row - ensure that each row in the binary matrix representing the word (representatively programmed over the given aCAM row) in binary digits contains at least one codeword of the code (C) with respect to the binary parity check matrix (H).

[0012] As already indicated, circuits of the technology disclosed herein, using imposed redundancy values ​​(imposed, for example, by "internal redundancy," where redundant aCAM cells are added to aCAM arrays, or by "external redundancy," where redundancy values ​​are stored in an external memory and imposed on the circuits by strategically initializing / reinitializing the stored values ​​of the counter subcircuits), detect faults in an aCAM row based on the stored value of a counter subcircuit associated with the aCAM row,after a set of (specially calculated) error detection input vectors has been sequentially applied to the circuit. Like the redundancy values ​​described above, the set of error detection input vectors can also be calculated based on the parity check matrix (H). In certain implementations (e.g., internal redundancy implementations for the bit interleaving scheme), a circuit detects an error in the aCAM row if: (a) when the binary parity matrix (H) dictates even parity, the value stored by a counter subcircuit (electrically connected to the match line of the aCAM row) after the sequential application of the set of error detection input vectors differs from the value stored by the counter subcircuit before the sequential application of the set of error detection input vectors (as indicated above,this may correspond to the reception of an even number of match signals by the counter subcircuit); and (b) if the binary parity matrix (H) prescribes odd parity, the value stored by the counter subcircuit after the sequential application of the set of error detection input vectors is the same as the value of the counter subcircuit before the sequential application of the set of error detection input vectors (as indicated above, this may correspond to the reception of an odd number of match signals by the counter subcircuit).

[0013] Returning to the error detection input vectors: Each error detection input vector may comprise a plurality of analog voltage input signals, each analog voltage input signal being applied to one of the columns of the aCAM array (when an error detection input vector is initially received by the circuit, it may comprise one or more digital input signals that are converted by the circuit into the plurality of analog voltage signals before being applied to the aCAM columns). Each error detection input vector may contain only one "non-wildcard" analog voltage input signal, a "wildcard" analog voltage input signal, calculated such that each aCAM cell of the aCAM array always returns a match when the wildcard analog voltage input signal is applied to it (by this construction, each error detection input vector effectively checks one column of the aCAM array).In part through its relationship to the parity check matrix (H)—which in turn is calculated based on the number of columns of the aCAM array and a maximum number of errors (τ) to be detected per aCAM row—the set of error detection input vectors can be calculated based on: (a) a number of columns of the aCAM array, where a number of error detection vectors in a set of error detection vectors is an integer multiple of the number of columns in the aCAM array; (b) a number of programmable levels that each aCAM cell of the aCAM array can be programmed to store; and (c) a maximum number of errors (τ) to be detected across a single row of aCAM cells.

[0014] As already indicated, the circuits of the presently disclosed technology can detect errors in aCAM arrays more efficiently than existing / conventional techniques. For example, and as described above, detecting errors by sequentially reading conductances using the read circuitry of a 512x50 aCAM array (i.e., an aCAM array with 512 rows and 50 columns) would require 25,600 reads. In contrast, the circuits of the presently disclosed technology can detect up to one error per row of the 512x50 aCAM array with only 357 reads (i.e., applying 357 error detection input vectors distributed across a plurality of sets of error detection input vectors), where the aCAM cells each have 8 programmable levels, or 765 reads (i.e.,Application of 765 error detection input vectors distributed across a plurality of sets of error detection input vectors) when the aCAM cells each have 16 programmable levels (in "internal redundancy" implementations, such a circuit may include adding a redundancy column to the aCAM array). Similarly, circuits of the technology disclosed herein can detect up to 3 errors per row of the 512x50 aCAM array with only 1,309 reads (i.e., application of 1,309 error detection input vectors distributed across a plurality of sets of error detection input vectors) when the aCAM cells each have 8 programmable levels, or 2,805 reads (i.e., application of 2,805805 error detection input vectors distributed across a plurality of sets of error detection input vectors) when the aCAM cells each have 16 programmable levels (in "internal redundancy" implementations, such a circuit may include the addition of 3 redundancy columns to the aCAM array). As these two exemplary comparisons demonstrate, circuits of the technology disclosed herein can detect errors in aCAM arrays significantly more efficiently than existing / conventional techniques. This improved efficiency can reduce the time, power consumption, computational resources, costs, etc. associated with detecting errors in aCAM arrays.

[0015] It is also noted how the circuits of the technology disclosed herein exploit the unique design / operation of aCAM circuits in their error detection schemes. In particular, example circuits exploit the parallel operation of aCAM arrays (i.e., the fact that a given error detection input vector can be applied to all aCAM rows of an aCAM array simultaneously—and that, by extension, each aCAM row of the aCAM array generates its match line output simultaneously), such that the time complexity of an error detection cycle does not depend on the number of rows of the aCAM. Accordingly, examples can significantly reduce the time complexity associated with detecting errors in very large aCAM arrays with, for example, thousands of aCAM rows.

[0016] Before describing examples of the technology disclosed herein in more detail, a brief introduction to (1) certain terms used in the following descriptions and (2) the basic operation of aCAMs is instructive.

[0017] For integers a ≤ b, where [a : b] is the integer subset {z∈ℤ:a≤z≤b} and [a : b〉 denotes the set [a : b - 1]. In this document, the shorthand notation [b] and [b) is used for [1 : b] and [0 : b).

[0018] q ≥ 2 can be a positive integer representing the alphabet size (as indicated above, q can also refer to the number of programmable levels of each aCAM cell of an aCAM array). Here, a q-comparator (e.g., an aCAM cell of the technology disclosed here) can be a circuit that computes the bivariate function Γ q : [q〉 2 → {0,1}, which is defined by equation (1) below. Γ(x,ϑ)=Γq(x,ϑ)={1if x≤ϑ0else

[0019] The argument x may represent an input signal applied to the q-comparator (e.g., a single signal component of an input signal), and ϑ may represent the threshold value stored (or representatively stored) by the q-comparator (i.e., a q-comparator is synonymous here with an aCAM cell of the technology disclosed herein).

[0020] As already indicated, recent designs of nanoscale aCAMs use q-comparator blocks arranged in m × n arrays (i.e., aCAM arrays with m rows n columns), where each entry (i,j) ∈ [m〉 × [n〉] represents the function x ↦ Γ q (x,ϑ i,j ) for a given threshold ϑ i,j implemented. An input vector (e.g., an error detection input vector) applied to the aCAM array can be represented as a vector x = (x j ) j∈[n〉 ∈ [q〉 n , where x jserves as the input for all comparators along column j. Each row (“match line”) in the aCAM array computes the conjunction (“and”, “Λ”) of the outputs of the comparators along the row, and the m results from the output vector, v ∈ {0, 1} m , of the aCAM array. The non-zero entries in v are called “matches,” and in practice, one may be interested in finding all matches (i.e., knowing the entire vector v), or only in whether there is at least one match, or only in the number of matches. Each aCAM cell (i,j) may contain a memristor whose conductance is set to the threshold ϑ i,j (a value proportional to it) is set / programmed. It is assumed that these conductances change much less frequently than the input vector x.

[0021] Fig. Figure 1 shows a schematic diagram of an aCAM array 100. The aCAM array 100 consists of an m × n array of aCAM cells. Each aCAM cell acts as a comparator (represented by the triangular shape). Each comparator has two q-ary input terminals and one binary output terminal. For a given comparator / aCAM cell, one input terminal is associated with an analog threshold voltage stored by the aCAM cell and is fed by the aCAM cell's memristor (here, the aCAM cell's memristor stores a conductance proportional to the analog voltage threshold stored by the aCAM cell). The comparator's second input terminal is connected via a column conductor to an entry of the input vector x (i.e., it is connected to an analog input voltage signal).The output terminals of the n comparators along each row i ∈ [m〉 are ANDed together to produce the value of the match line, ML. i . During normal operation of the aCAM array 100, the output value v i row i equals ML i .

[0022] As indicated above, the operation of an aCAM (e.g., aCAM array 100) may be susceptible to errors from various sources, including: (1) incorrect programming of conductances for memristors (e.g., the conductance a memristor is actually programmed to may be different than intended); (2) drift of stored conductances over time (e.g., the conductance a memristor was originally programmed to may drift over time, such that the conductance the memristor actually stores differs from the originally programmed value); (3) manufacturing defects (e.g., short cells or open cells), etc.If one or more aCAM cells of an aCAM row contain an error, the aCAM row may (a) erroneously return a match for an input word that the aCAM row was not programmed / intended to store, or (b) erroneously return a mismatch for an input word that the aCAM row was actually programmed / intended to store. These erroneous match line outputs can negatively impact the performance of an aCAM array. For example, the aCAM array may be unable to correctly / effectively perform a particular computational task. For this reason, the ability to detect errors in an aCAM array can be very important.Since available / less sophisticated fault detection techniques for aCAMs are generally not efficient, the examples of the technology disclosed here fulfill an important need for efficient fault detection in this emerging and valuable technology area.

[0023] As indicated above, examples of the technology disclosed herein provide several schemes (and circuits for implementing the schemes) for detecting faults in aCAM arrays. These schemes generally include: (1) circuit hardware additions (e.g., counter subcircuits, redundancy aCAM cells for internal redundancy schemes, etc.); (2) redundancy coding (which, in certain examples, may be performed during programming of the non-redundant / task-driven aCAM cells of the aCAM array); and (3) fault detection (which may be performed periodically), which consists of applying one or more sets of specially calculated fault detection input vectors to the aCAM array—where a fault in a particular aCAM row of the aCAM array may be detected after applying the last fault detection input vector of a set.For example: (1) after applying the last error detection input vector of a first set of error detection input vectors, a circuit disclosed herein may detect a fault in a first aCAM row; (2) after applying the last error detection input vector of a second set of error detection input vectors, the circuit disclosed herein may detect a fault in a second aCAM row; (3) after applying the last error detection input vector of a third set of error detection input vectors, the circuit disclosed herein may detect a fault in a third aCAM row; and so on.

[0024] As indicated above, in order for the schemes disclosed here to function, redundancy values ​​are imposed on an aCAM array in addition to the task-related thresholds (i.e., the aCAM array thresholds programmed according to the aCAM array's intended computational task). These calculated redundancy values ​​can be stored in two ways: (1) through "internal redundancy" - where the calculated redundancy values ​​are programmed as thresholds in redundancy columns of the aCAM array (as indicated above, this may involve programming conductance values ​​of memristors of redundancy aCAM cells so that the redundancy aCAM cells effectively store an analog threshold voltage value representing a calculated redundancy value); and (2) "external redundancy" - where the calculated redundancy values ​​are stored in a memory (e.g.an SRAM) outside the aCAM array - and the redundancy values ​​are imposed on the aCAM array by initializing (and in certain cases strategically reinitializing) the values ​​stored in the counter subcircuits described above.

[0025] During fault detection (i.e., the application of fault detection input vectors to the aCAM array), aCAM rows containing faults (i.e., aCAM rows providing erroneous / unintended match-related signals) can be detected / identified based on values ​​stored by the counter subcircuits described above. The individual disclosed schemes may differ in the tradeoffs they offer between the following attributes: (a) extent of changes and additions to the circuit hardware; (b) number of redundancy columns; and (c) time complexity (or latency) of the detection cycle.

[0026] As already mentioned, these methods generally exploit the parallel operation of aCAMs by feeding all aCAM rows of an aCAM array with the error detection input vectors and simultaneously generating their respective match line outputs. Accordingly, the time complexity of the detection cycle in these methods may not depend on the number of aCAM rows in the aCAM array.

[0027] Here it may be useful to use the threshold values ​​ϑ i,j to be considered as elements in the ring, ℤq of the integers modulo q. An aCAM array (e.g. aCAM array 100) can then be written as an m × n array over ℤq be considered, where ϑ i = (ϑ i,j ) j,∈[n〉 represents the vector of thresholds along i ∈ [m〉. As indicated above, the coding can generally be performed such that each ϑ i a codeword of a code (subset) Cvon ℤqn For a given k (which depends on the code C), the first k entries in ϑ i contain the task-related thresholds, which can be freely chosen (during a programming phase) according to a desired computational task for the aCAM array. The remaining r = n - k entries can form the redundancy part of the aCAM array (i.e., the redundancy columns that store computed redundancy values ​​as thresholds or store them representatively) and can be used by an encoder for C (again, during the programming phase). In this case, examples can attempt to minimize r depending on the specified number of errors to be detected per aCAM line.

[0028] Regarding errors, this document has so far (implicitly) assumed the Hamming metric, where an error event means that a threshold is incorrect, regardless of the (integer) difference between the correct and the erroneous value. The Hamming metric can be conservative because it can model multiple error sources, such as comparator malfunctions or drift in the programmed thresholds. If only drift errors are expected, it may be useful to consider an L1 metric instead, resulting in detection schemes that require less redundancy. Under an L1 metric, an error event can be defined as a change in a threshold by ±1 (larger changes are interpreted as multiple errors at the same threshold).

[0029] The following description of examples of the technology disclosed herein is structured as follows. Section I summarizes the definitions and properties of codes. Section II describes "internal redundancy" implementations for two Hamming metric detection schemes: the bit interleaving scheme (Construction A in Section II-A) and the shift-and-count scheme (Construction B in Section II-B). The "external redundancy" implementations for these two methods are described in Section II-C. Section III describes example circuits constructed according to Sections I-II.

[0030] In all detection methods disclosed here, the number of test vectors grows linearly with the alphabet size q and superlinearly with the number of columns of an aCAM array, but does not depend on the number of rows of the aCAM array. As already indicated, this feature enables the examples of the present technology to reduce the time complexity for fault detection in large aCAM arrays with many rows. I. Definitions and Notation

[0031] Examples can be codes C ⊆ ℤqn use linear and systematic methods across ℤq This means that there exists a k×n matrix G over ℤq which is called the generator matrix, such that: • (the linear property) C={c = uG : u ∈ℤqk} where operations in ℤq be executed, and • (the systematic property) G is an invertible k×n-submatrix over ℤq contains.

[0032] In such a code, the rows of G form a basis of C, that is, they are linearly independent over ℤq and each codeword in C can be represented as a (unique) linear combination of the rows of G; thus |C| = q k . The parameters n, k and r=nk are called the length, the dimension and the redundancy of C. By permuting the columns of G and applying invertible linear operations to the rows of G, examples can obtain a generator matrix of the form: (lk|A), where I k is the k×k identity matrix. In this case, the encoding can be performed by the mapping: u↦uG=(u|uA), where u is part of a codeword. For this reason, examples may require the systematic condition (in addition to linearity, which is also useful for the recognition process). To utilize the full functionality of aCAM, the coding scheme must not impose any restrictions on the first, e.g., k, task-related thresholds in each aCAM row. Note that when q is a prime number, linearity always implies the systematic property.

[0033] The minimum (Hamming) distance of C, usually denoted by d, is the smallest number of positions at which two distinct codewords differ. Equivalently, d is the smallest Hamming weight of any nonzero codeword in C. If a codeword is subject to any pattern of no more than τ = d - 1 errors, then such an event can always be detected (since the errors cannot convert one codeword into another). Furthermore, if a codeword is subject to any pattern of no more than [(d - 1) / 2] errors, then the codeword can always be recovered. The length n, dimension k, and minimum distance d of a systematic linear code are usually written as triples [n, k, d].

[0034] A parity check matrix of a code C⊆ℤqn is an r×n matrix over ℤq such that C forms its right core: C={c∈ℤqn:Hc⊤=0r} (where 0 r for the column with zeros in ℤqr and the superscript τ denotes the transposition of a vector or matrix). Every systematic linear [n, k = n - r, d] code has an r×n parity check matrix containing an invertible r×r submatrix; in particular, if G has the form (2), then (−A⊤|Ir) such a matrix. Conversely, every r×n-matrix over ℤq, which contains an invertible r×r submatrix, a parity check matrix of a systematic linear [n, k = n - r, d] code over ℤq. The minimum distance of such a code can be characterized by each of its parity check matrices H as follows: It is the largest integer d such that each d - 1 columns in H is linearly independent over ℤq are.

[0035] For a row vector y∈ℤn is the syndrome vector of y with respect to an r×n parity check matrix H of a code C⊆ℤqn the column r-vector σ=Hy⊤.

[0036] Thus, the codewords of C are all vectors in ℤqn, whose syndrome is completely zero.

[0037] The concept of systematic linear codes can be easily extended to codes over the integer ring No. (except that in this case the code is infinitely large). In fact, any linear code over No. also systematic (similar to the prime numbers q). II. Coding and recognition schemes

[0038] This section introduces two error detection coding schemes for aCAM arrays using the Hamming metric. In this section, m and n represent the number of rows and columns in the array, respectively, and τ is the largest number of errors that can be detected in a given row. Each scheme uses a specific systematic linear [n, k = n - r, d = τ + 1] code C. In construction A (Section II-A), the code is binary, while in construction B (Section II-B), it is ℤq. In each coding scheme, the coding algorithm can be identical for all rows and executed by an encoder of the form of equation (3). Furthermore, the examples can exploit the operation of aCAM, in that the detection process applies the same set of (specially calculated) error detection input vectors—in parallel—to all aCAM rows (in particular, the latency of the process does not depend on the number of aCAM rows). This section first describes schemes that utilize the implementation of internal redundancy, where r (out of n) columns in an aCAM array are reserved for storing the redundancy values ​​as thresholds (as suggested above, these redundancy values ​​can be programmed / stored by programming the conductance of memristors in redundant aCAM cells). Here, r can be referred to as the column redundancy of an aCAM array.The implementation of external redundancy is discussed in Section III-C.

[0039] Since both the encoding and recognition processes can be uniform across aCAM lines, this document uses the notation ϑ = (ϑ j ) j∈[n〉 for the vector of thresholds along a generic aCAM row in the aCAM array, omitting the index i of the aCAM row. A. Construction A: Bit interleaving scheme

[0040] The coding scheme presented in this section, called the bit interleaving scheme or Construction A, applies to cases where the alphabet size q is a power of 2. Assuming that τ is much smaller than n, C be a [n, k = n - r, d = τ + 1] binary alternating code (in particular a BCH code) whose redundancy is given by the following equation (4): r(τ,n)={τ2⋅⌈log2(n+1)⌉ if τ is evenτ−12⋅⌈log2n⌉+1 if τ is odd Writing b = log2 q (which is a positive integer), the row vector ϑ can be represented as a binary b×n array (i.e., a binary array representing the vector ϑ in binary digits) Φ=Φ(ϑ)=(ϕs,j)(s,j)∈[b〉×[n〉, where column j in Φ is the b-vector in {0,1} b is the (integer) ϑ j to base 2 represents: ϑj=∑s∈[b〉2s⋅ϕs,j,j∈[n〉.

[0041] The coding can be done such that for each s ∈ [b〉, row s in Φ, namely ϕ s = (ϕ s,j ) j∈[n〉, is a codeword of C (hence the name bit interleaving). Thus, for r = r(τ, n) as in (4), the first k = n - r entries in ϑ can be freely chosen (depending on the computational task). The remaining r entries can be determined by encoding / calculating redundancy values. In other words (and as will be described in more detail below), examples can determine a sequence of ones and zeros for each row s in Φ such that each s in Φ is a codeword of C. Examples can effect this sequence by encoding / calculating redundancy values ​​that are stored (or representatively stored) in redundancy cells of an aCAM array.

[0042] The recognition procedure is based on the following principle: For a binary b×n parity check matrix H = (H ℓ,j ) (ℓ,j)∈[r〉×[n〉 of C, error detection is achieved by checking whether the following equality holds for each s ∈ [b〉: Hϕs⊤=0 (where the equality over No. 2 To this end, example circuits constructed according to the bit interleaving scheme add a modulo-2 counter subcircuit (i.e., a toggle bit) to each match line of an aCAM array (i.e., the modulo-2 counter subcircuit may be electrically connected to a match line of an aCAM row so that the modulo-2 counter receives match-related signals output by the aCAM row). The modulo-2 counter subcircuit may be synchronized with the clock of the n-vectors input to the aCAM and may invert its value each time its input is a 1 (e.g., each time it receives a match signal output by the aCAM row with which it shares a match line).

[0043] Fig. Figure 2 shows an example of an aCAM array 200 with additional counter subcircuits (these counter subcircuits can be modulo-2 counter subcircuits or other types of counter subcircuits). In certain examples, the "REG" can represent a one-bit memory, and the circled "+" can represent addition modulo 2. In other words, each modulo-2 counter subcircuit can have one input bit and one output bit and can contain a one-bit memory element (REG). During each clock cycle, the contents of REG can be updated by exclusive-ORing (XORing) with the input. The output can be the contents of REG (here, XORing is equivalent to addition modulo 2).

[0044] As already indicated, during a recognition cycle a sentence X⊆[q〉n of error detection input vectors are applied to the aCAM array 200. This set of error detection input vectors is described in more detail below after the introduction of some notations.

[0045] For j ∈ [n〉 let e j the standard unit vector, which has its (only) “one” at position j, and for each ℓ ∈ [r) we denote by J ℓ the support of the line ℓ in H: Jl={j∈[n〉:Hl,j≠0} For (ℓ, s) ∈ [r〉 × [b〉, let XL,s the following subset of [q〉 n : Xl,s={(2a+1)⋅2s⋅ej:a∈[2b−s−1〉,j∈Jl} (which is size 2 b-s-1 · |J ℓ | has). The set X is now defined as the union: X=∪(l,s)∈[r〉×[b〉Xl,s⋅

[0046] Thus |X|=(∑s∈[b〉2b−s−1)⋅∑lε[r〉|Jl|=(q−1)⋅‖H‖, where ||H|| denotes the total number of ones in the matrix H. This number is at most r · n, and for r > 1 it is typically close to r · n / 2.

[0047] The following algorithm (9) represents a detection cycle in which the elements of X are applied as error detection input vectors to the aCAM array 200.

[0048] As shown, ML i and MODC i for the (binary) content of the match line or the modulo-2 counter subcircuit of row i. In each iteration over (ℓ,s), the error detection input vectors in XL,s the entry ℓ in the vector Hϕs⊤ (see equation (7)). If the vector Hϕs⊤ in an aCAM line is not equal to zero, an error can be marked in this aCAM line (see Fig. 2, during the detection cycle, examples can output v ithe line i on MODC i instead of ML i It can be observed that MODC i = 0 is an invariant at the beginning of each iteration of the loop over s and therefore the value of MODC i at the end of each of these iterations is the same as if XL,s for the larger quantity XL,s would be kept (in other words, for a given (ℓ, s), algorithm (9) reuses the previously performed calculation for (f, s' > s)).

[0049] In summary, a detection process according to examples of the technology disclosed herein may consist of applying at most (q - 1) · r · n test vectors to the aCAM array 200 (and typically half this number). The required column redundancy is determined by equation (4).

[0050] Example 1: As an illustrative example, an aCAM array with m = 512 rows and k = 50 columns may be prone to errors. As already indicated, an existing / conventional approach to error detection would be to periodically read the thresholds directly across the entire aCAM array—which would mean m · k = 25,600 reads. In comparison, Table 300 shows Fig. 3 the column redundancy r and the error detection input vectors used in construction A for q = 8, 16 and τ = 1, 2, 3. As described above, equation (8) can be used to calculate the error detection input vectors |X| (which, as indicated above, may include multiple sets of error-detection input vectors). For τ = 1, the matrix H is the 1 × 51 all-ones vector (11 ... 1). For τ = 2, it is a 6 × 56 parity-check matrix of a truncated binary Hamming code, with columns spanning the lightest (in terms of Hamming weight) non-zero binary 6-vectors. And for τ = 3, it is a 7 × 57 parity-check matrix of a truncated extended binary Hamming code, with columns spanning the lightest binary 7-vectors with odd Hamming weight.

[0051] The construction A can be generalized by changing the radix 2 to any radix with ρ ≥ 2, where q = ρ b for any positive integer b. Accordingly, the counter subcircuit in each aCAM line is now modulo ρ and the code C becomes ℤρ. In this example, C has a 0-1 parity check matrix, that is, a matrix whose entries point to the subset {0,1} of Zq are limited. Otherwise, an implementation testing equation (7) requires a different (and possibly much larger) set X of test vectors.

[0052] In this more general framework, the quantities XL,s be defined by: B. Construction B: Shift-and-Count Scheme

[0053] The design presented in this section, referred to as the shift-and-count scheme or Design B, can have less column redundancy than Design A, but at the cost of using more complex counter subcircuits that are electrically connected to the match lines of the aCAM rows. Design B may require that q is a prime number, namely that ℤq is the finite field GF(q) (as indicated above, q represents the alphabet size of the code and, associated with it, the number of programmable levels of the aCAM cells of an aCAM array). To clarify that q is prime in construction B, this section uses the notation p instead of q. In contrast to construction A, which used a base-2 representation (i.e., a binary array) to represent the threshold vector ϑ, construction B uses the base-2 representation of the entries of the parity check matrix of the underlying code that defines the scheme. The threshold vectors are codewords of C.

[0054] Let C be a linear [n, k = n - r, d = τ + 1] code over ℤp and H = (H ℓ,j ) (ℓ,j)∈[r〉x[n〉 be an r×n parity check matrix of C over ℤp. Let b = [log2p] be written, and for ℓ ∈ [r〉 let b ℓ the smallest positive integers such that H ℓ,j∈ [2 bℓ 〉 (for this purpose, the examples consider the entries H ℓ,j as if they were integers in [p〉). So b ℓ ≤ b for all ℓ ∈ [r]. For each (ℓ,j) ∈ [r〉 × [n〉 let h ℓ,f = (h s,l,j ) s∈[bℓ〉 ∈ {0,1} bℓ the base-2 representation of (the integer) H ℓ,j : Hl,J=∑S∈[bl〉2s⋅hs,l,j

[0055] Then for each ϑ=(ϑj)j∈[n〉∈ℤpn: Hϑ⊤=0 (above ℤp if and only if the following equality holds for every ℓ ∈ [r〉: ∑s∈[bl〉2s∑j∈[n〉hl,s,j⋅ϑj=0 (above ℤp The shift-and-count scheme involves the calculation of redundancy values ​​such that equation (11) holds, and a detection cycle that verifies equation (12) by applying to an aCAM array (as before) a set of error detection input vectors X∗⊆[p〉n As already indicated, detection may require counter subcircuits of modulo p (as opposed to modulo 2 counter subcircuits) that can also multiply by 2 (modulo p).

[0056] In this section, we now describe the theorem X*. For this purpose, it may be convenient to define an r* × n 0-1 matrix H*, which is obtained from H by replacing each entry, H ℓ,j , through the column b ℓ - Vector h ℓ,f ∈ {0,1} bℓ More precisely: H* has r* = ∑ ℓ∈[r〉 b ℓ Rows indexed by pairs (ℓ, s), where ℓ ∈ [r〉 and s ∈ [b ℓ 〉, and n columns indexed by j ∈ [n〉, and (H*)( ℓ,s ) ,j = (h ℓ,s,j ). If with Jl,s∗ the support of the row (ℓ,s) in H*, the set X* can be defined as the union: X∗=∪l∈[r〉∪s∈[bl〉Xl,s∗, where for each ℓ ∈ [r〉 and s ∈ [bℓ 〉, Xl,s∗={a⋅ej:a∈[q〉,j∈Jl,s∗}

[0057] Therefore: |X∗|=(q−1)⋅∑l∈[r〉∑s∈[bl〉|Jl,s∗|=(q−1)⋅‖H∗‖.

[0058] The following algorithm (14) represents the detection cycle that solves equation (12) for each ℓ ∈ [r〉 and s ∈ [b ℓ 〉 verified. The notation MODSC i stands for the stored value of a counter subcircuit that can also multiply by 2 modulo p. (Note that the loop over s can be unified over all ℓ ∈ [r) by b ℓ is replaced by b and each Xl,s∗ for s ∈ [b ℓ + 1,b〉 is used.)

[0059] Example 2: Reusing the aCAM array from Example 1, Table 400 shows Fig. 4 the parameters for construction B. The values ​​q = 8,16 were converted to the prime numbers p = 11,17 (as indicated above, the values ​​of q can represent the number of programmable levels of the aCAM cells of the aCAM array, which in this case may have to be prime numbers). For τ = 1, the matrix H is again the all-one vector. For τ = 2, it is a 3×53 parity check matrix of a truncated Hamming code over ℤp where the easiest columns are selected), and for τ = 3 it is a 4×54 parity check matrix of a (truncated) code (presented in Problem 3.44 in RM Roth, “Fault-tolerant dot-product engines,” IEEE Trans. Inf. Theory, 65 (2019), 2046–2057), while ||H*|| is minimized over all possible choices for the irreducible polynomial f(·,·) in it and for the entries in the second and third rows, and in the fourth row all possible linear combinations of the first three rows are added.

[0060] If C has a normalized alternating code over ℤp represents, then (assuming that τ≤n r=1+⌈p−1p⋅(τ−1)⌉⋅⌈logpn⌉

[0061] For large p, this expression is approximately (1 / 2) log2 p smaller than the column redundancy, represented by equation (4), of construction A. The number r* of rows in H* is bounded from above by: r⋅b=r⋅⌈log2p⌉≈(13)p−1p⋅τ⋅log2n Thus, if ||H*|| is estimated as r · b / n / 2 and ||H|| in equation (8) is correspondingly estimated as r · n / 2, then the size of X* in equation (13) is twice the size of X in construction A. It should be noted that these estimates are somewhat conservative: e.g., for τ = 4, the size of X* for p = 17 is actually smaller than the corresponding size of X for q = 16 in Table 300 of Fig. 3.

[0062] In Table 500 of Fig. Figure 5 summarizes the (approximate) values ​​of column redundancy and the number of error-detection input vectors for constructions A and B (note the different bases of the logarithms). The estimates for ||H|| and ||H*|| for τ ∈ {2, 3} are based on the assumption that half of the entries are in H and H*1. These estimates may be somewhat conservative. C. External redundancy

[0063] As illustrated in Sections III-A and III-B, respectively, designs A and B use columns of the aCAM array (i.e., redundancy columns containing redundant aCAM cells) to store calculated redundancy values ​​in each row of the aCAM array. These redundancy values ​​are programmed as thresholds similar to the task-controlled thresholds of the aCAM array (i.e., the redundancy values ​​are effectively stored as analog voltage thresholds for individual redundancy aCAM cells, with the analog (redundancy) voltage thresholds being programmed / tuned by programming the conductances of memristors in the redundancy aCAM cells).

[0064] In contrast, in the external redundancy implementation, the redundancy values ​​are stored in a separate memory (e.g., random access memory (RAM), static RAM (SRAM), etc.) outside the aCAM array. This approach is applicable to both designs A and B. For simplicity, this section describes the external redundancy implementation for design A (i.e., the bit interleaving scheme), but the same / similar principles would also apply to an external redundancy implementation for design B (i.e., the shift-and-count scheme).

[0065] Various implementations that use external memory can pre-compute the contribution of the redundancy values ​​to the left-hand side of equation (7) in the external memory, thus eliminating the need for redundancy columns in the aCAM array. However, such an external redundancy scheme assumes that the redundancy values ​​are arranged in columns (similar to the aCAM array) and that they are susceptible to errors like any aCAM cell. However, these assumptions do not always hold. For example, redundancy values ​​in the external memory can be arranged in various ways, and thus different error correction and error detection techniques can be used to protect these stored redundancy values ​​from errors. For the purposes of error detection of an aCAM, the stored redundancy values ​​can therefore be assumed to be error-free.

[0066] In this way (with the same parity check matrix H), examples can use the entire m×n aCAM array (instead of just an m-×-k array) for the task-related thresholds (i.e., for the thresholds used to perform a specific computational task on the aCAM array), where each row is (freely) labeled with a threshold vector v∈ℤqn Instead of requiring equation (7), the coding can consist in determining for each s ∈ [b) the syndrome vector of ϕ s with respect to the r×n parity check matrix H: σs=(σl,s)l∈[r〉=Hϕs⊤ Each syndrome vector σ s be a ρ-ary r-vector, as well as any difference Δs,i=(Δl,s,i)l∈[r〉=σs+1−σs,s∈[b〉, where examples σ b = 0 and the notation Δ s,iits dependence on the row index i in the a-CAM becomes clear. These differences, which amount to br symbols, can be stored in external memory. The task of the recognition cycle is now to check equation (16) (instead of equation (7)). This is achieved by changing the initialization of the modulo-p counter MODC i in: MODCi←Δl,s,i, for every i ∈ [m〉 and for every (ℓ, s) ∈ [r〉 × [b〉.

[0067] Using external memory for redundancy has several advantages. First, the length of the code used by examples does not need to exceed the number of aCAM columns used for a computational task (i.e., all programmed thresholds of the aCAM array can be "task-specific" thresholds). This, in turn, reduces the number of error detection input vectors that need to be applied for detection, since there are no redundancy columns to check. Furthermore, a shorter code sometimes also means less redundancy, as shown in Example 3 below. Second, by using external memory, the alphabet of redundancy can be larger than the aCAM's native alphabet. For example, if the original alphabet is 8 and we want to use construction B, we must use p = 11.The task-related thresholds, which are freely chosen, can still be restricted to [8], but the redundancy (or syndrome) values ​​can also take values ​​in [8 : 11], i.e., outside the range of thresholds that can be programmed into individual cells of the aCAM. In other words, in examples, construction B can be applied where the number of programmable levels of the individual cells of an aCAM array is not a prime number.

[0068] When using design A, the use of external memory offers the additional advantage of allowing unequal error protection for low- and high-order bits. For example, low-order bits can be less (or not at all) protected if they do not affect the result, or they may need more protection because they are more susceptible to drift in the programmed thresholds. This flexibility can be achieved by selecting different codes C s can be achieved (all with length n), with corresponding (binary) parity check matrices H s and redundancies r s for different indices s ∈ [b) of the radix-ρ representation of the thresholds. Under this scenario, equality (16) becomes σ=Hsϕs⊤. Since the syndrome of each row ϕ sin Φ is now calculated with respect to a different parity check matrix, an iteration for a particular pair (ℓ, s) in Algorithm (14) cannot reuse calculations previously performed for (ℓ, s' > s). Therefore, the definition of XL,s in (9) be amended as follows: Xl,s={α⋅ps⋅ej:α∈[1:pb−s〉,j∈Jl,s}, where J ℓ,s the support of the line ℓ in H s The expression (8) for |X| changes in each case |X|=∑s∈[b〉(αb−s−1)⋅‖Hs‖ =∑s∈[b〉(qαs−1)⋅‖Hs‖. Using different codes, examples can reduce the total number of redundancy / syndrome values.

[0069] Storing the (error-free) syndrome in external memory can also allow the use of codes C with (the same minimum spacing, but with) less redundancy in examples. The following example 3 can demonstrate this.

[0070] Example 3: Example 3 can use the 512x50 aCAM array of Example 1, but with an alphabet size q = 7, and can consider construction B with τ = 3. With internal redundancy, in Example C, a linear [n, k = 50, d = 4] code over No. 7 and the shortest currently known code of this type has length n = 55 corresponding to redundancy r = 5. On the other hand, examples with external redundancy / syndromes can have redundancy r = 4 by defining H as a 4×50 parity check matrix of the linear [n = 50,k = 46,d = 4] code over No. 7 is taken. III. Example circuits

[0071] Fig. Figure 6 shows an example circuit 600 for detecting errors in an aCAM array, in accordance with various examples of the technology disclosed herein. Circuit 600 may be an example circuit implementing an internal redundancy implementation for the bit interleaving scheme described above (i.e., Design A).

[0072] As shown, the circuit 600 includes an aCAM array 610. The aCAM array 610 includes multiple rows (e.g., aCAM rows 610(A), 610(B)... 610(X), 610(Y), etc.) and multiple columns (e.g., aCAM columns 610(0), 610(1), 610(2)... 610(n-1), etc.) of aCAM cells.

[0073] aCAM column 610(n-1) may be a redundancy column, and aCAM cell 610(A)(n-1) may comprise a redundant aCAM cell of aCAM row 610(A). In various examples, aCAM array 610 may comprise additional redundancy columns. In other words, aCAM row 610(A) may include additional redundancy aCAM cells.

[0074] As previously mentioned, each aCAM cell of aCAM row 610(A) (including redundant aCAM cell 610(A)(n-1)) can be programmed to store an analog voltage threshold representing one entry of a word representatively programmed across aCAM row 610(A). As described above, each aCAM cell of aCAM row 610(A) can include a memristor. An aCAM cell of aCAM row 610(A) can be programmed to store its associated analog voltage threshold by programming the conductance of its associated memristor. The number of programmable levels that an aCAM cell of aCAM array 610 can store can be proportional to a number of conductances to which the associated memristor is reliably programmable.

[0075] The memristor of the redundancy aCAM cell 610(A)(n-1) can be programmed so that the aCAM cell 610(A)(n-1) stores a calculated redundancy analog voltage threshold (i.e., an analog voltage threshold representing a calculated redundancy value). As described above, the redundancy analog voltage threshold / redundancy value can be calculated such that each row of a binary array representing the word (representatively programmed via the aCAM row 610(A)) in binary digits contains a sequence of ones and zeros specified by a binary parity check matrix (H) (i.e., a parity check matrix consisting of ones and zeros). As described above, a parity check matrix can refer to a matrix or similar representation that describes conditions that a codeword of a code must satisfy.The sequences of ones and zeros specified by the binary parity check matrix (H) - imposed on a CAM row 610(A) by programming analog redundancy voltage thresholds in aCAM cells of the aCAM row 610(A) - thus ensure that each row in the binary array representing the word (representatively programmed via aCAM row 610(A)) in binary digits contains at least one codeword of a code (C) related to the binary parity check matrix (H). In certain cases (e.g., when a maximum number of errors (τ) to be detected per aCAM row is equal to one), this may mean that the redundancy analog voltage threshold for an aCAM cell 610(A)(n-1) is calculated such that each column of a given row of the binary array is an entry of a codeword (i.e., the codeword is programmed representatively across all aCAM cells of the aCAM row 610(A)). In other cases (e.g.,However, if the maximum number of errors (τ) to be detected per aCAM row is greater than one, this may mean that only a subset of columns of the given row of the binary array are entries of a codeword (i.e., the codeword is representatively programmed across a subset of the aCAM cells of aCAM row 610(A)). For example, a codeword may be representatively programmed across aCAM cells 610(A)(0), 610(A)(2), and 610(A)(n-1) (i.e., the columns of the binary array representing the analog voltage thresholds stored by aCAM cells 610(A)(0), 610(A)(2), and 610(A)(n-1) may comprise a stack of codewords).

[0076] The parity check matrix (H) may be calculated based on a number of columns of the aCAM array 610 (including redundancy columns) and a maximum number of errors (τ) to be detected per aCAM row. For example, if (τ=1), the parity check matrix (H) may be an "all-one" vector of length (n) (i.e., the number of columns of the aCAM array 610; it may also be the case that for τ=1, the aCAM array 610 contains only one redundancy column). Thus, if the parity check matrix (H) specifies even parity, the redundancy analog voltage threshold for the aCAM cell 610(A)(n-1) can be calculated such that each row of the binary array representing the word (representatively programmed via the aCAM row 610(A)) in binary digits contains an even number of ones.Accordingly, if the parity check matrix (H) specifies odd parity, the redundancy analog voltage threshold for the redundancy cell aCAM 610(A)(n-1) can be calculated such that each row of the binary array representing the word (representatively programmed via the aCAM row 610(A)) in binary digits contains an odd number of ones. A simplified example to illustrate the concept: If the "word" representatively stored via the aCAM row 610(A) includes the following sequence of thresholds / entries: 2 3 4 6 [Bit of the redundancy value, calculation pending] A binary array representing the thresholds / entries in binary digits would include: 0 0 1 1 [Bit of the redundancy value, calculation pending]1 1 1 0 [Bit of the redundancy value, calculation pending]0 1 0 0 [Bit of the redundancy value, calculation pending]

[0077] If the parity check matrix (H) specifies even parity, each row of the binary array representing the threshold values ​​in binary digits should contain an even number of ones. The calculated redundancy value for the aCAM cell 610(A)(n-1) would therefore be 3 (and the redundancy analog voltage threshold would be an analog voltage threshold representing the calculated redundancy value of 3) to ensure that each row of the binary array representing the word in binary digits contains an even number of ones, i.e.: 001101110101001

[0078] On the other hand, if the parity check matrix (H) specifies odd parity, each row of the binary array representing the word in binary digits should contain an odd number of ones. Thus, the calculated redundancy value for the aCAM cell 610(A)(n-1) would be 4 (and the redundancy analog voltage threshold would be an analog voltage threshold representing the calculated redundancy value of 4) to ensure that each row of the binary array representing the word in binary digits contains an odd number of ones, i.e.: 001111110001000

[0079] Note that in cases where the binary parity check matrix (H) is a single-row "all-one" vector, the parity constraint (i.e., even or odd) applies to all columns of the binary array. However, if the binary parity check matrix (H) is more complex (e.g., if the maximum number of errors to be detected per aCAM row (τ) is greater than one), the binary parity check matrix (H) may have multiple rows. In this context, (1) a first row of the binary parity check matrix (H) may impose a parity constraint (i.e., even or odd) for a first subset of columns of the binary array—including at least one column representing a redundancy value (in the example where (τ) is greater than one, there may be multiple redundancy columns, and therefore multiple columns of the binary array may represent redundancy values / thresholds); (2) a second row of the binary parity check matrix (H) may contain the same parity condition (ieeven or odd) for a second subset of columns of the binary array - including at least one column representing a redundancy value; (3) a third row of the binary parity check matrix (H) may prescribe the same parity condition (i.e., even or odd) for a third subset of columns of the binary array - including at least one column representing a redundancy value; and so on. Furthermore, in certain examples, a first row of the binary parity check matrix (H) may prescribe a first parity condition (e.g., even parity) and a second row of the binary parity check matrix (H) may prescribe a second (different) parity condition (e.g., odd parity).For these reasons, the redundancy analog voltage threshold for the redundancy aCAM cell 610(A)(n-1)) is more generally calculated such that each row of the binary array representing the word (representatively programmed via aCAM row 610(A)) in binary digits contains a sequence of ones and zeros specified by the binary parity check matrix (H).

[0080] As shown, circuit 600 also includes a counter subcircuit associated with each aCAM row of aCAM array 610. For example, counter subcircuit 620 is electrically connected to the match line of aCAM row 610(A) such that counter subcircuit 620 receives match-related signals output by aCAM row 610(A). As indicated above, the match-related signals output by aCAM row 610(A) may include a match signal when each aCAM cell of aCAM row 610(A) returns a match in response to an input vector applied to circuit 600, and a mismatch signal when at least one of the aCAM cells of aCAM row 610(A) returns a mismatch in response to the input vector applied to circuit 600.

[0081] As previously mentioned, counter subcircuit 620 may be a modulo-2 counter subcircuit that stores either a first value or a second value (e.g., a 0 or a 1). The value stored by counter subcircuit 620 may change when counter subcircuit 620 receives a match signal and may remain the same when counter subcircuit 620 receives a mismatch signal.

[0082] As indicated above, in response to a first set of error detection input vectors sequentially applied to circuit 600, circuit 600 may detect an error in aCAM row 610(A) if: (a) when the binary parity matrix (H) dictates even parity, the value stored by counter subcircuit 620 after sequential application of the first set of error detection input vectors is different from the value stored by counter subcircuit 620 before sequential application of the first set of error detection input vectors (as indicated above, this may correspond to counter subcircuit 620 receiving an even number of match signals);and (b) if the binary parity matrix (H) specifies odd parity, the value stored by the counter subcircuit 620 after the sequential application of the first set of error detection input vectors is the same as the value stored by the counter subcircuit 620 before the sequential application of the first set of error detection input vectors (as indicated above, this may correspond to the receipt of an odd number of match signals by the counter subcircuit 620).

[0083] Like the redundancy values ​​described above, the first set of error detection input vectors may also be calculated based on the parity check matrix (H). When applied to the aCAM array 610, each error detection input vector may comprise a plurality of analog voltage input signals, with each analog voltage input signal being applied to one of the columns of the aCAM array 610 (when an error detection input vector is initially received by the circuit 600, it may comprise a digital input signal(s) that are converted by the circuit 600—e.g., using digital-to-analog converter circuit components—into the plurality of analog voltage signals before being applied to the columns of the aCAM array 610).When applied to the aCAM array 610, each error detection input vector can only contain one "non-wildcard" analog voltage input signal, where a "wildcard" analog voltage input signal is calculated such that each aCAM cell of the aCAM array 610 always returns a match when the wildcard analog voltage input signal is applied to it (by this construction, each error detection vector effectively checks one column of the aCAM array 610).In part through their relationship to the parity check matrix (H) - which in turn is calculated based on the number of columns of the aCAM array 610 and a maximum number of errors (τ) detectable in a single aCAM row - the first set of error detection input vectors can be calculated based on: (a) a number of columns of the aCAM array 610, where a number of error detection vectors in the first set of error detection vectors is an integer multiple of the number of columns in the aCAM array; (b) a number of programmable levels that each aCAM cell of the aCAM array 610 can be programmed to store; and (c) a maximum number of errors (τ) detectable across a single aCAM row.

[0084] As indicated above, in certain examples, fault detection in aCAM array 610 may include applying multiple sets of fault detection input vectors to circuit 600, where a fault in a particular aCAM row of aCAM array 610 is detected after applying the last fault detection input vector of a set. For example, circuit 600 may detect a fault in aCAM row 610(A) after applying the final fault detection input vector of the first set of fault detection input vectors; after applying the final fault detection input vector of a second set of fault detection input vectors, circuit 600 may detect a fault in aCAM row 610(C); after applying the final error detection input vector of a third set of error detection input vectors, circuit 600 may detect an error in aCAM row 610(B); and so on.Here, each set of error detection input vectors can be calculated in the same / similar way using the binary parity check matrix (H).

[0085] Fig. Figure 7 shows an example circuit 700 for detecting errors in an aCAM array, in accordance with various examples of the technology disclosed herein. Circuit 700 may be an example circuit implementing an external redundancy implementation for the bit interleaving scheme described above (i.e., Design A).

[0086] As shown, the circuit 700 includes an aCAM array 710. The aCAM array 710 includes multiple rows (e.g., aCAM rows 710(A), 710(B)... 710(X), 710(Y), etc.) and multiple columns (e.g., aCAM columns 710(0), 710(1), 710(2)... 710(n-1), etc.) of aCAM cells.

[0087] In contrast to the aCAM array 610 from Fig. 6, the aCAM array 710 may not contain redundant columns / redundant aCAM cells. Accordingly, each column / each aCAM cell of the aCAM array 710 may be programmed for / dedicated to a computation task. In other words, all programmed thresholds of the aCAM array 710 may be "task-related" thresholds.

[0088] Similar to the aCAM cells of the aCAM line 610(A) used in conjunction with Fig. 6, each aCAM cell of aCAM row 710(A) can be programmed to store an analog voltage threshold value representing one entry of a word representatively programmed across aCAM row 710(A). Each aCAM cell of aCAM row 710(A) can include a memristor. An aCAM cell of aCAM row 710(A) can be programmed to store its analog voltage threshold value by programming the conductance of its memristor. The number of programmable levels that an aCAM cell of aCAM row 710 can store can be proportional to the number of conductance values ​​to which its memristor is reliably programmable.

[0089] As already indicated, in external redundancy implementations, the calculated redundancy values ​​are stored in a memory (e.g., a RAM) external to an aCAM array. Accordingly, the redundancy values ​​for the circuit 700 may be stored in a memory (not shown) external to the aCAM array 710. In certain examples, this memory may be part of the circuit 700, but in other examples, the memory may be external to the circuit 700. In this case, the redundancy values ​​stored in the (external) memory may be calculated in the same / similar manner as in connection with Fig. 6 and sections I-III.

[0090] Like circuit 600, circuit 700 includes a counter subcircuit connected to each aCAM row of aCAM array 710. For example, counter subcircuit 720 is electrically connected to the match line of aCAM row 710(A) such that counter subcircuit 720 receives match-related signals output by aCAM row 710(A). As previously mentioned, the match-related signals output by aCAM row 710(A) may include a match signal when each aCAM cell of aCAM row 710(A) provides a match in response to an input vector applied to circuit 700, and a mismatch signal when at least one of the aCAM cells of aCAM row 710(A) provides a mismatch in response to the input vector applied to circuit 700.

[0091] As previously mentioned, counter subcircuit 720 may be a modulo-2 counter subcircuit that stores a value of either one or zero. The value stored by counter subcircuit 720 may change when counter subcircuit 720 receives a match signal and may remain the same when counter subcircuit 720 receives a mismatch signal.

[0092] As described in connection with Section II-C, in the external redundancy implementation, redundancy values ​​stored in external memory may be imposed on circuit 700 by strategically initializing (and in certain cases reinitializing) the values ​​stored by the counter subcircuits of circuit 700.

[0093] For example, before a first set of error detection input vectors is sequentially applied to the circuit 700 (this first set of error detection input vectors may be calculated in the same / similar manner as described in connection with Fig. 6 and Sections I-II), the value stored by the counter subcircuit 720 may be initialized in accordance with at least one calculated syndrome vector (σ) for a binary array representing the word (representatively programmed via a CAM line 710(A)) in binary digits. In certain of these examples (and as indicated above), this value may be set to the value of one bit of a stored syndrome comparison vector (Δ), where the stored syndrome comparison vector (Δ) is generated by performing an exclusive "OR" operation between two calculated syndrome vectors (e.g., σ s and σ s-1) is calculated for the binary array, wherein the two calculated syndrome vectors are assigned to adjacent rows of the binary array. As already indicated, the at least one calculated syndrome vector (σ) can be calculated based on the binary array and a binary parity check matrix (H).

[0094] As indicated above, in response to the sequential application of the first set of error detection input vectors to the circuit 700, the circuit 700 detects an error in the aCAM row 710(A): (a) if the binary parity check matrix (H) prescribes a first type of parity (e.g., even or odd), the value stored by the counter subcircuit 720 after sequential application of the first set of error detection input vectors is zero, and (b) if the binary parity check matrix prescribes a second type of parity (e.g., the other of even or odd), the value stored by the counter subcircuit 720 after sequential application of the first set of error detection input vectors is one.

[0095] Fig. Figure 8 shows an example circuit 800 for detecting faults in an aCAM array in accordance with various examples of the technology disclosed herein. Circuit 800 may be an example circuit implementing the shift-and-count scheme described above (i.e., Design B).

[0096] As shown, the circuit 800 includes an aCAM array 810. The aCAM array 810 includes multiple rows (e.g., aCAM rows 810(A), 810(B)...810(X), 810(Y), etc.) and multiple columns (e.g., aCAM columns 810(0), 810(1), 810(2)...810(n-1), etc.) of aCAM cells.

[0097] Similar to the aCAM cells of the aCAM lines 610(A) and 710(A), which in conjunction with the Fig. 6 and 7, respectively, each aCAM cell of aCAM row 810(A) can be programmed to store an analog voltage threshold representing an entry of a word representatively programmed across aCAM row 810(A). Each aCAM cell of aCAM row 810(A) can include a memristor. An aCAM cell of aCAM row 810(A) can be programmed to store its analog voltage threshold by programming the conductance of its memristor. The number of programmable levels that an aCAM cell of aCAM row 810 can store can be proportional to a number of conductances to which its memristor is reliably programmable.

[0098] In examples where circuit 800 implements an internal redundancy implementation, one or more of the columns of aCAM array 810 may include redundancy columns. In other words, one or more of the aCAM cells of aCAM row 810(A) may be redundant aCAM cells. As described above, a redundancy aCAM cell may be programmed to store a calculated redundancy analog voltage threshold. As described above, the redundancy analog voltage threshold (or more precisely, a redundancy value represented by the redundancy analog voltage threshold) may be calculated using a parity check matrix (H) such that the word includes at least one codeword of a code (C) related to the parity check matrix (H) (as described above, the codewords of the code (C) may span an alphabet size w).Accordingly, circuit 800 differs from certain implementations of circuits 600 and 700 (i.e., the circuits implementing construction A) in which each row of a binary array representing the word (representatively stored via an aCAM row) contains at least one codeword.

[0099] In other examples, circuitry 800 may implement an external redundancy implementation, and all aCAM cells of aCAM array 810 may be programmed as task-related thresholds (i.e., thresholds / ACAM cells associated with a particular computation task).

[0100] Like circuits 600 and 700, circuit 800 includes a counter subcircuit associated with each aCAM row of aCAM array 810. However, instead of using modulo-2 counter subcircuits, the counter subcircuits of circuit 800 may be modulo-q counter subcircuits capable of multiplying by 2 modulo q. In particular, unlike the modulo-2 counter subcircuits of Fig. 6-7, the modulo-q counter subcircuits can be capable of storing "q" unique values. Multiplication by 2, in turn, is performed by a bit shift operation in the modulo-q counter subcircuits (described in more detail in the following section). For this reason, the modulo-q counter subcircuits are denoted by "MODSC" and can be referred to as "modulo-q shift counter subcircuits" or "modulo-q shift + counter subcircuits."

[0101] A modulo-q counter subcircuit may comprise an input data bit, an input control bit, an output bit and a cascade of b single-bit memories whose content is stored as a binary representation of an integer between 0 and 2 b-1The number b can be chosen to be the smallest possible number to represent the q stages 0, 1,..., q-1. The input control bit can determine whether the modulo q counter subcircuit is in either a "counting mode" or a "shifting mode". In "counting mode", during each clock cycle, the input data bit is added (using standard adding circuitry) to the integer represented in the b memory bits. If the result is q, the contents of all memory bits are reset. Otherwise, the result is written to the memory bits. In "shifting mode", the contents of each memory bit are shifted to the next (higher-order) bit in the cascade, with the most significant bit becoming a "carry" bit and 0 being inserted into the least significant bit.If the resulting content of the b+1 bits (= b memory bits plus the carry bit) represents a number at least q, q is subtracted (using a standard subtraction circuit) from the number represented by these b+1 bits. The output bit is the inclusive OR of all b memory bits.

[0102] As already indicated, q can correspond to the number of programmable levels for the aCAM cells of the aCAM array 810. The number of programmable levels, q, that an aCAM cell of the aCAM array 810 can store can be proportional to the number of conductances to which its memristor can be reliably programmed. The value of q can also be the alphabet size of the code (C).

[0103] As shown, counter subcircuit 820 is electrically connected to the match line of aCAM row 810(A) such that counter subcircuit 820 receives match-related signals output by aCAM row 810(A). The match-related signals output by aCAM row 810(A) may include a match signal when each aCAM cell of aCAM row 810(A) provides a match in response to an input vector applied to circuit 800, and a mismatch signal when at least one of the aCAM cells of aCAM row 810(A) provides a mismatch in response to the input vector applied to circuit 800.

[0104] The value stored by the counter subcircuit 820 may change when the counter subcircuit 820 receives a match signal and remain the same when the counter subcircuit 820 receives a mismatch signal.

[0105] Circuit 800 can detect an error if the value stored by counter subcircuit 820 after sequentially applying a set of error detection input vectors is nonzero. In other words, the value stored by counter subcircuit 820 after sequentially applying a set of error detection input vectors is nonzero if and only if all b bits are zero, so that a zero output bit is equivalent to the b storage bits representing the integer 0.

[0106] Fig.9 shows a block diagram of an example computer system 1100 in which various of the examples described herein may be implemented. For example, computer system 900 may be used to program threshold values ​​for circuits 600, 700, and 800. Computer system 900 may also be used to calculate redundancy values ​​and input vectors for error detection. Computer system 900 may also be used to initialize and reinitialize values ​​stored by counter subcircuits.

[0107] Computer system 900 includes a bus 912 or other communication mechanism for conveying information, and one or more hardware processors 904 connected to bus 912 for processing information. For example, hardware processor(s) 904 may be one or more general-purpose microprocessors.

[0108] Computer system 900 also includes main memory 906, such as random access memory (RAM), a cache, and / or other dynamic storage devices connected to bus 912, for storing information and instructions to be executed by processor 904. Main memory 906 may also be used to store temporary variables or other intermediate information during the execution of instructions to be executed by processor 904. When instructions are stored in storage media accessible to processor 904, computer system 900 becomes a special-purpose machine adapted to perform the operations specified in the instructions.

[0109] Computer system 900 also includes a read-only memory (ROM) 908 or other static storage device connected to bus 912 for storing static information and instructions for processor 904. A storage device 910, such as a magnetic disk, an optical disk, or a USB stick (flash drive), etc., is provided and connected to bus 912 for storing information and instructions.

[0110] Computer system 900 may be coupled to a display 912, e.g., a liquid crystal display (LCD) (or a touchscreen), via bus 912 for displaying information to a computer user. An input device 914, including alphanumeric and other keys, is coupled to bus 912 for communicating information and command selections to processor 904. Another type of user input device is cursor control 916, such as a mouse, trackball, or cursor direction keys for communicating direction information and command selections to processor 904 and controlling cursor movement on display 912. In some embodiments, the same direction information and command selections as with cursor control may be implemented via receiving touches on a touchscreen without a cursor.

[0111] Computer system 900 may include a user interface module for implementing a graphical user interface, which may be stored on a mass storage device as executable software code executed by the computing device(s). This and other modules may include, for example, components such as software components, object-oriented software components, class components and task components, processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables.

[0112] In general, the word "component," "engine," "system," "database," "data store," and the like, as used herein, may refer to logic embodied in hardware or firmware, or to a collection of software instructions that may have entry and exit points and be written in a programming language such as Java, C, or C++. A software component may be compiled and linked into an executable program, installed in a dynamic link library, or written in an interpreted programming language such as BASIC, Perl, or Python. It is understood that software components may be called by other components or by themselves, and / or may be called in response to detected events or interrupts. Software components configured to run on computing devices may be embodied on a computer-readable medium, such asa compact disc, digital video disc, flash drive, magnetic disk, or other tangible medium, or as a digital download (and may be originally stored in a compressed or installable format that must be installed, decompressed, or decrypted before execution). Such software code may be stored partially or entirely in a memory of the executing computing device so that it can be executed by the computing device. Software instructions may be embedded in firmware, such as an EPROM. In addition, the hardware components may consist of interconnected logic units such as gates and flip-flops and / or programmable units such as programmable gate arrays or processors.

[0113] Computer system 900 may implement the techniques described herein using custom hard-wired logic, one or more ASICs or FPGAs, firmware, and / or program logic that, in combination with the computer system, makes or programs computer system 900 into a special-purpose machine. According to one embodiment, the techniques described herein are performed by computer system 900 in response to processor(s) 904 executing one or more sequences of one or more instructions contained in main memory 906. Such instructions may be read into main memory 906 from another storage medium, such as storage device 910. Execution of the instruction sequences contained in main memory 906 causes processor(s) 904 to perform the method steps described herein.In alternative embodiments, hard-wired circuits may be used instead of or in combination with software instructions.

[0114] The term "non-transitory media" and similar terms as used herein refer to any media that stores data and / or instructions that cause a machine to operate in a particular manner. Such non-transitory media may include non-volatile media and / or volatile media. Non-volatile media includes, for example, optical or magnetic disks, such as storage device 190. Volatile media includes dynamic memory, such as main memory 906. Common forms of non-transitory media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tape or other magnetic data storage media, CD-ROMs, other optical data storage media, physical media with hole patterns, RAM, PROM and EPROM, FLASH EPROM, NVRAM, other memory chips or cartridges, and networked versions thereof.

[0115] Non-transitory media are distinct from transmission media but can be used in conjunction with them. Transmission media are involved in the transfer of information between non-transitory media. Transmission media include, for example, coaxial cables, copper and fiber optic cables, including the wires that make up the 912 bus. Transmission media can also take the form of acoustic or light waves, such as those generated in data communications via radio and infrared.

[0116] Computer system 900 also includes a communications interface 918 connected to bus 912. Network interface 918 establishes a bidirectional data communications connection to one or more network connections connected to one or more local area networks. For example, communications interface 918 may be an Integrated Services Digital Network (ISDN) card, a cable modem, a satellite modem, or a modem for establishing a data communications connection to a corresponding type of telephone line. As another example, network interface 918 may be a Local Area Network (LAN) card for establishing a data communications connection to a compatible LAN (or a WAN component for communicating with a WAN). Wireless connections may also be implemented.In each of these implementations, the network interface 918 sends and receives electrical, electromagnetic, or optical indicators that carry digital data streams representing various types of information.

[0117] A network connection typically enables data communication over one or more networks to other data devices. For example, a network connection may establish a connection over a local area network to a host computer or data devices operated by an Internet service provider (ISP). The ISP, in turn, provides data communication services over the worldwide packet data communication network, now commonly referred to as the "Internet." Both the local area network and the Internet use electrical, electromagnetic, or optical indicators that transmit digital data streams. The indicators in the various networks and the indicators in the network connection and in the communication interface 918 that transmit the digital data to and from the computer system 900 are examples of transmission media.

[0118] Computer system 900 can send messages and receive data, including program code, over the network(s), the network connection, and the communications interface 918. In the Internet example, a server could transmit requested code for an application program over the Internet, the ISP, the local network, and the communications interface 918.

[0119] The received code may be executed by processor 904 upon receipt and / or stored in storage device 910 or other non-volatile memory for later execution.

[0120] Each of the processes, methods, and algorithms described in the preceding sections may be embodied in, and fully or partially automated by, code components executed by one or more computer systems or computer processors comprising computer hardware. The one or more computer systems or computer processors may also operate to support the performance of the corresponding operations in a cloud computing environment or as software as a service (SaaS). The processes and algorithms may be partially or fully implemented in application-specific circuitry. The various features and methods described above may be used independently or combined in various ways.Various combinations and subcombinations are intended to be within the scope of this disclosure, and certain method or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular order, and the associated blocks or states may be performed in other suitable orders, in parallel, or otherwise. Blocks or states may be added to or removed from the disclosed examples. The execution of certain operations or processes may be distributed among computer systems or computer processors located not only in a single machine, but distributed across a number of machines.

[0121] As used herein, a circuit may be implemented in any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, ASICs, PLAs, PALs, CPLDs, FPGAs, logic components, software routines, or other mechanisms may be implemented to form a circuit. In implementation, the various circuits described herein may be implemented as discrete circuits, or the described functions and features may be distributed, in part or in whole, among one or more circuits.Although various features or functional elements are individually described or claimed as separate circuits, these features and functions may be shared by one or more common circuits, and such description is not intended to assume or imply that separate circuits are required to implement these features or functions. If a circuit is implemented in whole or in part with software, that software may be implemented to operate with a computer or processing system capable of performing the functionality described with respect to it, such as computer system 900.

Claims

[1] Circuit (600) comprising: an analog content-addressable memory aCAM array (610) comprising a row of aCAM cells (610 (A) - (Y)) electrically connected along a match line, each aCAM cell of the row of aCAM cells being programmed to store an analog voltage threshold representing an entry of a word representatively programmed across the row of aCAM cells, wherein: the row of aCAM cells contains a redundancy aCAM cell (610(A)(n-1) - 610(Y)(n-1)) programmed to store a calculated redundancy analog voltage threshold, and the redundancy analog voltage threshold is calculated such that each row of a binary array representing the word in binary digits contains a sequence of ones and zeros specified by a binary parity check matrix. [2] The circuit of claim 1, further comprising: a counter subcircuit (620-626) electrically connected to the match line such that the counter subcircuit receives match-related signals output from the row of aCAM cells, the match-related signals output from the row of aCAM cells comprising a match signal when each aCAM cell in the row of aCAM cells returns a match in response to an input vector applied to the circuit, and a mismatch signal when at least one of the aCAM cells in the row of aCAM cells returns a mismatch in response to the input vector applied to the circuit. [3] A circuit according to claim 2, wherein: the counter subcircuit stores either a first or a second value; the value stored by the counter subcircuit toggles in response to the counter subcircuit receiving a match signal and remains the same in response to the counter subcircuit receiving a mismatch signal; and the circuit detects a fault in the row of aCAM cells in response to a set of fault detection input vectors applied sequentially to the circuit if: if the binary parity matrix (H) prescribes an even parity, the value stored by the counter subcircuit after sequential application of the set of error detection input vectors differs from the value of the counter subcircuit before the sequential application of the set of error detection input vectors, and if the binary parity matrix (H) specifies odd parity, the value stored by the counter subcircuit after sequential application of the set of error detection input vectors is equal to the value of the counter subcircuit before sequential application of the set of error detection input vectors. [4] The circuit of claim 3, wherein each error detection input vector, when applied to the row of aCAM cells, comprises a plurality of analog voltage input signals, each analog voltage input signal of the plurality of analog voltage signals being applied to one of the aCAM cells of the row of aCAM cells. [5] The circuit of claim 4, wherein each error detection input vector, when applied to the row of aCAM cells, includes only a non-wildcard analog voltage input signal, a wildcard analog voltage input signal being calculated such that each aCAM cell of the aCAM array always returns a match when the wildcard analog voltage input signal is applied to it. [6] A circuit according to claim 5, wherein the set of error detection input vectors is calculated based on: a number of aCAM cells in the row of aCAM cells, wherein a number of error detection vectors in the set of error detection vectors is an integer multiple of the number of aCAM cells in the row of aCAM cells; a number of programmable levels that each aCAM cell in the row of aCAM cells can store; and a maximum number of errors to be detected in the row of aCAM cells. [7] A circuit according to claim 6, wherein: each row of the binary array representing the representative programmed word in binary digits contains a codeword of a code; the binary parity check matrix refers to the code and the code is selected based on the number of aCAM cells in the row of aCAM cells and the maximum number of errors to be detected; and the set of error detection input vectors is calculated from rows of the binary parity check matrix. [8] The circuit of claim 7, wherein the set of error detection input vectors is a first set of a plurality of sets of error detection input vectors calculated to detect errors stored by the aCAM array. [9] A circuit according to claim 5, wherein: each aCAM cell of the row of aCAM cells has a memristor and an aCAM cell from the row of aCAM cells is programmed to store its analog voltage threshold by programming the conductance of its memristor. [10] A circuit according to claim 9, wherein: the number of programmable levels that an aCAM cell from the row of aCAM cells can store is proportional to a number of conductances to which its memristor can be reliably programmed. [11] Circuit (700) comprising: an analog content-addressable memory aCAM array (710) comprising a row of aCAM cells (710(A) - 710(Y)) electrically connected along a match line, each aCAM cell of the row of aCAM cells being programmed to store an analog voltage threshold representing an entry of a word representatively programmed across the row of aCAM cells; and a counter subcircuit (720 - 726) electrically connected to the match line such that the counter subcircuit receives match-related signals output from the row of aCAM cells, wherein the match-related signals output from the row of aCAM cells include a match signal when each aCAM cell in the row of aCAM cells returns a match in response to an input vector applied to the circuit, and a mismatch signal when at least one of the aCAM cells in the row of aCAM cells returns a mismatch in response to the input vector applied to the circuit, wherein the counter subcircuit stores either the value zero or one; the value stored by the counter subcircuit toggles in response to the counter subcircuit receiving a match signal and remains the same in response to the counter subcircuit receiving a mismatch signal. [12] A circuit according to claim 11, wherein: before a set of error detection input vectors is sequentially applied to the circuit, the value stored by the counter subcircuit is initialized in accordance with at least one calculated syndrome vector for a binary array representing the word in binary digits. [13] A circuit according to claim 12, wherein: the value stored by the counter subcircuit, initialized according to the at least one calculated syndrome vector, is set to the value of a bit of a stored syndrome comparison vector, wherein the stored syndrome comparison vector is calculated by performing an exclusive "OR" operation between two calculated syndrome vectors for the binary array, the two calculated syndrome vectors being associated with adjacent rows of the binary array. [14] A circuit according to claim 12, wherein: the at least one calculated syndrome vector is calculated based on the binary array and a binary parity check matrix. [15] A circuit according to claim 14, wherein: the circuit detects a fault in the row of aCAM cells in response to the set of fault detection input vectors sequentially applied to the circuit if: if the binary parity check matrix prescribes a first type of parity, the value stored by the counter subcircuit after sequential application of the set of error detection input vectors is zero, and if the binary parity check matrix prescribes a second type of parity, the value stored by the counter subcircuit after sequential application of the set of error detection input vectors is one. [16] A circuit according to claim 11, wherein: each aCAM cell in the row of aCAM cells has a memristor; and an aCAM cell from the row of aCAM cells is programmed to store its analog voltage threshold by programming the conductance of its memristor. [17] Circuit (800) comprising: an analog content-addressable memory aCAM array (810) comprising a row of aCAM cells (810(A)-(Y)) electrically connected along a match line, each aCAM cell of the row of aCAM cells being programmed to store an analog voltage threshold representing an entry of a word representatively programmed across the row of aCAM cells; and a modulo-q counter subcircuit (820-826) electrically connected to the match line such that the modulo-q counter subcircuit receives match-related signals output from the row of aCAM cells, the match-related signals output from the row of aCAM cells comprising a match signal when each aCAM cell in the row of aCAM cells returns a match in response to an input vector applied to the circuit, and a mismatch signal when at least one of the aCAM cells in the row of aCAM cells returns a mismatch in response to the input vector applied to the circuit, wherein: q is a number of programmable levels of a particular aCAM cell from the row of aCAM cells and is also a prime number, and the value stored by the modulo-q counter subcircuit changes in response to the counter subcircuit receiving a match signal and remains the same in response to the counter subcircuit receiving a mismatch signal. [18] A circuit according to claim 17, wherein: the row of aCAM cells includes a redundancy aCAM cell programmed to store a calculated redundancy analog voltage threshold; the redundancy analog voltage threshold is calculated using a parity check matrix, so that the word contains at least one codeword of a code that refers to the parity check matrix; and the code has an alphabet size of q. [19] A circuit according to claim 18, wherein: each aCAM cell in the row of aCAM cells has a memristor; and an aCAM cell from the row of aCAM cells is programmed to store its analog voltage threshold by programming the conductance of its memristor. [20] A circuit according to claim 19, wherein: the number of programmable levels, q, that an aCAM cell from the row of aCAM cells can store is proportional to a number of conductances to which its memristor is reliably programmable.

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