Methods for analyzing modules

Abstract

The invention relates to a method (100) for analyzing modules (30) comprising at least two electronic components (50), taking into account at least one correlation between the electrical properties of the components (50) and their position on a wafer (40) on which the components (50) are provided for the assembly of the modules (30), comprising the following steps: - Providing (101) measurement data for the respective components (50), which result from a measurement of at least one characteristic of the components (50) taking into account the position on the wafer (40), - Providing (102) at least one component representation based on the provided measurement data, whereby a model of the respective component is parameterized depending on the measurement data in order to take into account the correlation of the electrical properties of the components (50) and the position for the component representation, - Evaluate (103) with regard to the operation of the module (30) with the components (50) on the basis of at least one component representation.

Description

[0001] The invention relates to a method for analyzing modules. Furthermore, the invention relates to a computer program, a device, and a storage medium for this purpose. State of the art

[0002] It is known in the art that semiconductor components are typically manufactured on a wafer and subsequently assembled into a functional structure, such as a power semiconductor. It should be noted that the properties of individual components can vary depending on their position on the wafer. Even though these differences are often small, they can still have a significant impact on the functionality and performance of the entire module. Therefore, controlling and minimizing these positional dependencies represents an ongoing challenge. Disclosure of the invention

[0003] The subject matter of the invention is a method having the features of claim 1, a computer program having the features of claim 8, a device having the features of claim 9, and a computer-readable storage medium having the features of claim 10. Further features and details of the invention emerge from the respective subclaims, the description, and the drawings. Features and details described in connection with the method according to the invention naturally also apply in connection with the computer program according to the invention, the device according to the invention, and the computer-readable storage medium according to the invention, and vice versa, so that with regard to the disclosure of the individual aspects of the invention, reference is or can always be made to each other.

[0004] The subject matter of the invention is in particular a method for analyzing modules which have at least two electronic components, in particular semiconductor components, preferably power semiconductors, in particular taking into account at least one correlation of electrical properties of the components and / or with a position on a wafer on which the components are manufactured and / or provided for constructing the modules, in particular for taking into account adjacent components.

[0005] The method according to the invention can comprise, according to a first method step, providing measurement data for the respective components. This providing can comprise, for example, receiving the measurement data and / or retrieving the measurement data from a storage medium. For this purpose, the measurement data can be in digital form. Furthermore, the measurement data can result from a measurement of at least one characteristic of the components, taking into account the position on the wafer. This can include, for example, the measurement data also containing information about the position on the wafer at which the measured component was located.

[0006] According to a further method step, the method according to the invention can comprise providing at least one component representation, in particular a digital twin, based on the provided measurement data. For this purpose, a model of the respective component can be parameterized depending on the measurement data, i.e., the parameters of the model can be changed, for example, such that the measurement data are fitted. By parameterizing the model, the correlation of the electrical properties of the components and / or their position can be taken into account for the component representation.

[0007] According to a further method step for analysis, the method according to the invention can comprise evaluating the operation of the module with the components based on the at least one component representation, wherein the evaluation can further comprise simulating the operation of the module. In other words, the component representation, e.g., the digital twin, can be used to estimate and / or predict the characteristics of the operation of the module with these components, taking into account the position on the wafer. This makes it possible to determine an optimal design for the modules.

[0008] Preferably, the evaluation can include determining the performance of the components, for which purpose parameters such as temperature and / or power dissipation are calculated, which result from switching losses and / or conduction losses of the components. The performance of the components can be further characterized by parameters such as threshold voltage, conductivity, capacitance, resistance, current density, thermal resistance, breakdown voltage, frequency response, and noise behavior. An evaluation of such parameters can further optimize the manufacturing process.

[0009] In a further embodiment, the component representation may comprise a digital twin of the respective component. To provide the component representation, the parameterization of the model of the respective component depending on the measurement data may include changing at least one or more parameters of the model such that an output of the model is adjusted to the measurement data (“fitting”) in order to obtain a realistic image of the respective component from the digital twin. A digital twin can be understood as a digital representation of the material component from the real world in the digital world. The digital twin thus enables a realistic simulation of the component and thus also a reliable assessment of the effect of its position on the wafer on the functionality of the module.

[0010] A further advantage can be achieved within the scope of the invention if the measurement data result from the measurement of at least one characteristic of those components that are arranged adjacently on the wafer. In other words, neighboring components can be specifically evaluated using the method according to the invention. This provides insights into how the module structure can be further optimized during the manufacturing process.

[0011] Furthermore, it can be provided that the model includes at least one of the following parameters, which is adjusted depending on the measurement data, for the respective component: tolerance of a threshold voltage of the component, tolerance of an epiresistance, tolerance for a channel mobility, tolerance of a gate-source capacitance, tolerance of a gate-drain capacitance, tolerance of a channel-to-drain short, tolerance of a series resistance of a body diode, tolerance of a breakdown voltage, tolerance of a lifetime in the reverse direction. The at least one characteristic can include a voltage and / or a capacitance of the components. This enables a realistic evaluation.

[0012] It is also advantageous if the components are embodied as semiconductor components, whereby a plurality of components can be provided on the wafer, with the respective module being equipped with at least three components. Thus, these can be modules in which not only the characteristics of an individual component, but also the interaction of the components on the module influences the operation of the module. This can be specifically assessed during the evaluation. For example, depending on the position of various components on the wafer, the effect on the operation of the module can be evaluated.

[0013] Advantageously, the invention can provide for simulating the switching on and off of the components during the evaluation. This allows for further improvement of the evaluation.

[0014] The invention also relates to a computer program, in particular a computer program product, comprising instructions that, when executed by a computer, cause the computer to execute the method according to the invention. Thus, the computer program according to the invention provides the same advantages as those described in detail with reference to a method according to the invention.

[0015] The invention also relates to a data processing device configured to carry out the method according to the invention. The device can be, for example, a computer that executes the computer program according to the invention. The computer can have at least one processor for executing the computer program. A non-volatile data memory can also be provided, in which the computer program is stored and from which the computer program can be read by the processor for execution.

[0016] The invention may also provide a computer-readable storage medium that contains the computer program according to the invention and / or includes instructions that, when executed by a computer, cause the computer to carry out the method according to the invention. The storage medium is designed, for example, as a data storage device such as a hard disk and / or a non-volatile memory and / or a memory card. The storage medium can, for example, be integrated into the computer.

[0017] Furthermore, the method according to the invention can also be implemented as a computer-implemented method.

[0018] Further advantages, features, and details of the invention will become apparent from the following description, which describes embodiments of the invention in detail with reference to the drawings. The features mentioned in the claims and in the description may be essential to the invention individually or in any combination. They show: Fig. 1 a schematic visualization of a method, a device, a storage medium and a computer program according to embodiments of the invention. Fig. 2-3 schematic comparisons of conventional methods and the method according to embodiments of the invention. Fig. 4 Schematic representations for visualizing methods according to embodiments of the invention.

[0019] In Fig. 1 schematically illustrates a method 100, a device 10, a storage medium 15, and a computer program 20 according to exemplary embodiments of the invention. The method 100 can be used to analyze modules 30 that have at least two electronic components 50, such as semiconductor components, preferably power semiconductors. The analysis can be carried out taking into account at least one correlation between electrical properties of the components 50 and a position of the components 50 on a wafer 40 on which the components 50 are manufactured and provided for constructing the modules 30. In particular, the analysis can be carried out taking into account the adjacent components 50 on the wafer.

[0020] According to a first method step 101, the measurement data for the respective components 50 can be provided. This can be measurement data resulting from a measurement of at least one characteristic of the components 50, taking into account their position on the wafer 40. For example, a component 50 can have a capacitance between certain terminals, known as CGD, as a characteristic, which influences its switching speed and its high-frequency behavior. A semiconductor component can transition from the non-conductive to the conductive state at a further characteristic, a specific voltage, the so-called breakdown voltage (VBR). For certain components 50, such as MOSFETs, the threshold voltage (VTH) can be a characteristic that determines the voltage at which it begins to conduct.A component 50 may exhibit a specific resistance, the on-resistance (RON), in the conducting state, with a lower value resulting in lower power losses. Measuring these characteristics can be beneficial for understanding the performance of semiconductor components 50.

[0021] Subsequently, according to a second method step 102, at least one component representation can be provided, in particular in the form of a digital twin, based on the provided measurement data. For this purpose, a model of the respective component can be used and parameterized depending on the measurement data. For example, the parameters of the model are changed such that the measurement data are fitted in order to take into account the correlation between the electrical properties of the components 50 and the position for the component representation through the parameterization of the model.

[0022] Then, according to a third method step 103, an evaluation 103 and, in particular, a simulation of the operation of the module 30 with the components 50 can be carried out for analysis based on the at least one component representation. The evaluation 103 can include determining a performance of the components 50, for which purpose a temperature and / or power loss resulting from switching losses and / or conduction losses of the components 50 is calculated.

[0023] It is known that manufacturing processes have statistical tolerances. Thus, even a key parameter of a component (chip) cannot be constant. It is often necessary that all produced modules meet the performance requirements, since the worst performing components determine the technical effort and limit performance. It must also be considered that a broad statistical distribution would be very expensive. Fig. Figure 2 shows that conventional solutions often rely on a randomized approach, such as a Monte Carlo approach. Here, the product limits (see 201) are first defined, and then random chip parameters (see 202) are used as model parameters (see 203). From this, a defined number of random models are obtained. This can be achieved, for example, by defining random chip properties, in which the components 50 are randomly parameterized according to a distribution.

[0024] An approach according to embodiments of the invention using a digital twin, however, can first use tests 211 at the wafer level to then obtain a digital twin for each component 50 based on the test results (see 212). This digital twin can then provide the model parameters (see 213) to obtain a defined number of realistic models.

[0025] The product limits are, for example, lower and upper limits from the measurements of parameters such as CGD, VBR, VTH, and / or RON. All components 50 for which the measurements lie outside the limits can be discarded.

[0026] The component representation and / or the evaluation 103 regarding the operation of the module 30 can be performed, for example, using a PSpice simulation. The module can be simulated with the components 50, in particular, the switching on and off of the components 50. This yields, for example, a result for the switching energies (E on / off) of the components, from which the losses can be calculated.

[0027] It may be an advantage of embodiments of the invention that a reduction in effort and thus in costs is possible by designing smaller chip sizes with the same performance. For this purpose, consideration of correlations in the properties of the components 50, ie, the chip properties, e.g., C GS , V TH , in predicting component performance. In particular, the creation of virtual worst-case models, which are not available, can be avoided by using wafer-level measurements. Furthermore, a digital twin can pave the way for further performance optimization.

[0028] In Fig. Figure 3 shows various approaches for taking statistics into account. According to a conventional Monte Carlo approach, the product limits are defined (see 301), then random chip properties are used (see 302) and inserted as model parameters (see 303). Power dissipation can then be randomly generated (see 304), and a chip temperature calculation can be performed (see 305). An approach according to embodiments of the invention, however, can include first conducting tests at wafer level (see 311), then using the test results to create a digital twin for each chip (i.e., component 50) (see 312), determining the model parameters from these (see 313), and calculating the power dissipation on this basis (see 314). This can then also be used to calculate the chip temperature (see 315).The temperatures Tj can depend on losses, such as Psw (switching loss) and Pcond (conduction loss), and thermal resistance.

[0029] It is in Fig. Figure 3 shows another conventional variant in which the product limitations 321 are used to determine random chip properties (see 322) in order to parameterize a model in this way (see 323). A power loss calculation 324 and a chip temperature calculation can then also be performed here (see 325). In the conventional method, the model, in particular the chip model, receives, for example, tolerance parameters for the chip power (e.g., DVTH, DRON). Disadvantages here are that it is assumed that a Gaussian distribution exists and that all chip properties and all chips are statistically independent.

[0030] Another in Fig. The approach illustrated in Figure 3 according to embodiments of the invention may include wafer-level tests 331 to obtain a digital twin of the respective component 50 (i.e., chips) (see 332). A simulation may then be performed on this basis (see 333) to perform a power loss calculation 334 and a chip temperature calculation (see 335). The model, in particular the chip model, receives tolerance parameters for the chip power (e.g., DVTH, DRON), and an individual set of tolerance parameters can be extracted for each measured chip. Advantages are that the approach covers the differences between chips within a module 30, the low probability of the worst case of all chip properties, the correlation of the chip properties, and the correlation of neighboring chips.

[0031] The model used for the method according to embodiments of the invention can be a PSpice semiconductor model. In particular, the model represents a key component for predicting component performance. The model topology can be implemented, for example, as a PSpice subcircuit comprising a standard Spice component.

[0032] The model may further include at least one of the following parameters: dvt (threshold voltage tolerance VTH), drd (epi-resistance tolerance), dbet (channel mobility tolerance), dcgs (gate-source capacitance tolerance CGS), dcgd (gate-drain capacitance tolerance CGD), dcds (CDS tolerance), drdio (body diode series resistance tolerance), dbv (breakdown voltage tolerance), dtt (reverse bias lifetime tolerance). The parameters are preferably chip performance tolerance parameters, with the range of each parameter preferably being between -1 and +1. The + / -1 refers to the maximum / minimum value of the parameter (e.g., 6σ), while 0 is the nominal value.

[0033] In Fig. 4 shows a schematic flow diagram for further optimization. The model, preferably a PSpice model, can have at least one of the following tolerance parameters for the chip performance: dvt, ie the tolerance of the threshold voltage, drd, ie the tolerance of the epi-resistance, dbet, ie the tolerance of the channel mobility, dcgs, ie the tolerance of the CGS, and dcgd, ie the tolerance of the CGD. Fig.The steps illustrated in Figure 4 can serve to extract chip parameters, which are determined, for example, based on the provided measurement data. According to a first step 401, dvt can be extracted, in particular from a measurement of the parameter VTH. Subsequently, according to a second step 402, dbet can be extracted, in particular from a measurement of RDSON. RDS(ON) stands in particular for "drain-source on-resistance" and can denote the resistance between drain and source of a metal-oxide-semiconductor field-effect transistor (MOSFET) in the on state. According to a third step 403, drd can be extracted from this measurement according to step 402. According to a fourth step 404, dcgs can be extracted from a measurement of Qgs.In particular, Qgs stands for "gate-source charge" and can refer to the electrical charge required to bring the gate of a metal-oxide-semiconductor field-effect transistor (MOSFET) or a similar transistor type to a specific voltage level. According to a fifth step 405, dcgd can be extracted from a Qgd measurement. In particular, Qgd stands for "gate-drain charge" and can refer to the electrical charge that is transferred between the gate and drain of a metal-oxide-semiconductor field-effect transistor (MOSFET) or a similar transistor type during the switching process. Furthermore, according to a sixth step 406, dcds and drdio can be randomly generated, and dbv and dtt can be assumed to be 0.

[0034] In summary and more generally, the measurement of the at least one characteristic of the components 50 according to a method according to embodiments of the invention can thus also include at least one of the following characteristics: VTH, RDSON, Qgs, Qgd. From this, for example, at least one of the following parameters for the model can be derived: dvt, dbet, drd, dcgs, dcgd, dcds, drdio, dbv, dtt.

[0035] The above explanation of the embodiments describes the present invention exclusively by way of examples. Of course, individual features of the embodiments can be freely combined with one another, provided they are technically feasible, without departing from the scope of the present invention.

Claims

[1] Method (100) for analyzing modules (30) having at least two electronic components (50), taking into account at least one correlation of electrical properties of the components (50) and a position on a wafer (40) on which the components (50) are provided for constructing the modules (30), comprising the following steps: - Providing (101) measurement data for the respective components (50) which result from a measurement of at least one characteristic of the components (50) taking into account the position on the wafer (40), - Providing (102) at least one component representation on the basis of the provided measurement data, wherein for this purpose a model of the respective component (50) is parameterized as a function of the measurement data in order to take into account the correlation of the electrical properties of the components (50) and the position for the component representation, - Evaluating (103) with regard to an operation of the module (30) with the components (50) on the basis of the at least one component representation. [2] Method (100) according to claim 1, characterized by that the evaluation (103) comprises determining a performance of the components (50), wherein for this purpose a temperature and / or power loss is calculated which results from switching losses and / or conduction losses of the components (50). [3] Method (100) according to one of the preceding claims, characterized bythat the component representation comprises a digital twin of the respective component (50), wherein, in order to provide the component representation, the parameterization of the model of the respective component (50) as a function of the measurement data comprises changing at least one or more parameters of the model such that an output of the model is adjusted to the measurement data in order to obtain a realistic image of the respective component (50) by means of the digital twin. [4] Method (100) according to one of the preceding claims, characterized by that the measurement data result from the measurement of at least one characteristic of those components (50) which are arranged adjacently on the wafer (40). [5] Method (100) according to one of the preceding claims, characterized byin that the model comprises at least one of the following parameters, which is set as a function of the measurement data, for the respective component (50): tolerance of a threshold voltage of the component, tolerance of an epi-resistance, tolerance for a channel mobility, tolerance of a gate-source capacitance, tolerance of a gate-drain capacitance, tolerance of a channel-to-drain short, tolerance of a series resistance of a body diode, tolerance of a breakdown voltage, tolerance of a lifetime in the reverse direction, wherein the at least one characteristic variable comprises a voltage and / or a capacitance of the components (50). [6] Method (100) according to one of the preceding claims, characterized by that the components (50) are designed as semiconductor components, wherein a plurality of components (50) is provided on the wafer (40), wherein the respective module is equipped with at least three components (50). [7] Method (100) according to one of the preceding claims, characterized by that during the evaluation (103) switching on and off of the components (50) is simulated. [8] Computer program (20) comprising instructions which, when the computer program (20) is executed by a computer (10), cause the computer (10) to carry out the method (100) according to one of the preceding claims. [9] Device (10) for data processing, which is arranged to carry out the method (100) according to one of claims 1 to 7. [10] A computer-readable storage medium (15) comprising instructions which, when executed by a computer (10), cause the computer (10) to carry out the steps of the method (100) according to any one of claims 1 to 7.

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