High-performance output drivers with low bias current in a high-voltage environment

Abstract

Integrated circuit (10) for data processing, the integrated circuit comprising: a central processing unit that is trained to process data; an output pin (2) of the integrated circuit (10) to supply processed data (D) at output pin (2) to an external device connected to output pin (2); a driver (7) for the output pin (2) with an output MOSFET (MPo) of the driver (7) connected to the output pin (2) to supply the processed data (D) with the power specified for the output pin (2), the driver (7) comprises: a dynamic driver stage (8) configured to switch the output MOSFET (MPo) between its conducting and non-conducting states, and a static driver stage (9) configured to maintain the state of the output MOSFET (MPo) until the dynamic driver stage (8) switches the state, wherein the dynamic driver stage (8) comprises a dynamic turn-on stage (11) with a first MOSFET (MP1) of the same technology as the output MOSFET (MPo) and a dynamic turn-off stage (12) and wherein the charge stored in the capacitance of the first MOSFET (MP1) at the turn-on time (T1) is used to charge the capacitance of the output MOSFET (MPo) at its gate contact in order to switch the output MOSFET (MPo) into its conducting state.

Description

AREA OF INVENTION

[0001] The present invention relates to an integrated circuit for processing data, wherein the integrated circuit comprises: a central processing unit that is trained to process data; an output pin of the integrated circuit to deliver processed data at the output pin to an external device connected to the output pin; a driver for the output pin with an output MOSFET of the driver connected to the output pin to supply the processed data with the power specified for the output pin. BACKGROUND OF THE INVENTION

[0002] Well-known integrated circuits for data processing include those used in audio, video, or computer applications, to name just a few. A central processing unit within the integrated circuit is used to process data, and one or more output pins are used for wired communication with other integrated circuits in the same device or with other devices to transmit the processed digital data as a data signal. A driver for one or more of these output pins is used to supply the processed data signal with the power specified for that pin. For example, a general-purpose output pin might provide a processed data signal with an output voltage of 5 volts and a maximum output current of 10 mA.These drivers often include a driver output MOSFET that is connected to the output pin to deliver the specified power.

[0003] Fig. Figure 1 shows a circuit and timing diagram of a state-of-the-art driver 1 for an output pin 2 of an integrated circuit 3, which is supplied with voltage V BAT is supplied. A high-side ground generation stage 4 is used to generate a high-side ground voltage V. HSGND of, for example, 1.8 volts in relation to V BAT based on a reference voltage V REFto generate as an input voltage for a driver stage 5. A level shifter 6 is used to shift the voltage level of the digitally processed data signal D (internally in the integrated circuit 3) to the input voltage level of the driver stage 5. Based on the processed data signal D, the output PMOS MPo is switched on at a turn-on time T1 or switched off at a turn-off time T2. The high-side ground voltage V generated by the high-side ground generation stage 4 HSGND It supplies the drive energy for the gate control of the output PMOS MPo. When the processed data signal D goes high at the turn-on time T1 and the output PMOS MPo is switched on, HSGND (gate capacitance of the output PMOS MPo) is charged in a stepwise manner. This stepwise charge causes a rapid discharge of capacitor C. HSGNDAs the arrow from the circuit to the timing diagram shows, once the output PMOS MPo is fully switched on, the charge at HSGND decreases, and the high-side ground generation stage 4 finally establishes the high-side ground voltage VGS. HSGND The severity of the discharge of the high-side ground voltage V HSGND and the time required to restore the high-side ground voltage V HSGND The required amount is determined by the size of the capacitor C. HSGND and determines the bias current of the High-Side-Ground generation stage 4.

[0004] It is important to note that the high-side ground voltage V HSGND must be restored before the next data cycle of the processed data signal D can be initiated, which directly affects the maximum data rate that can be supported.

[0005] Data transmission rates between integrated circuits continue to increase. At the same time, increasing integration is driving up the demands for energy-efficient circuits that require less chip area. Unfortunately, current state-of-the-art solutions, such as those described in Fig. The driver shown represents a compromise between data rate (speed), power consumption and chip area.

[0006] Fig. Figure 2 illustrates the constructive compromise of driver 1 according to the state of the art. Since the high-side ground voltage V HSGND The need to fully restore the system before the next data cycle is initiated requires that the support for higher data rates increases the high-side ground voltage (V) recovery time. HSGND This is minimized, which requires a higher power consumption from the high-side ground generation stage 4. To increase the high-side ground voltage V HSGND To restore, a higher bias current I is required. Brequired. A larger capacitance of capacitor C HSGND This is required to quickly turn on the output PMOS MPo, as shown in the upper part of the timing diagram in Fig. 2 can be seen, compared to the lower part of the time diagram with a smaller capacity C. HSGND Unfortunately, with current designs, operating at higher speeds results in a larger area on the silicon chip and higher power consumption.

[0007] Fig. Figure 3 illustrates the limitations of the state of the art and highlights the conflict between high-frequency operation, power consumption, and the chip area of ​​the integrated circuit. This becomes increasingly problematic as the number of parallel-operated drivers grows.

[0008] US 2004 / 0169543A1 and US7,683,672B2 also disclose integrated circuits in CMOS technology with a driver for the output pin of the integrated circuits to deliver processed data with specified power to an external device, with the aforementioned problems also occurring at least partially in these circuits. SUMMARY OF THE INVENTION

[0009] It is an object of the invention to provide an integrated circuit with an output driver that supports high data rates while minimizing power consumption and chip area. This object is achieved with an integrated circuit according to claim 1 and with a method according to claim 6.

[0010] Fig. Figure 4 shows the fundamental difference between the one in Fig. Figure 1 shows a driver 1 for controlling the output PMOS MPo and an integrated circuit according to the invention with a driver 7 for controlling the output PMOS MPo. The driver 7 comprises a dynamic driver stage 8 configured to switch the output PMOS MPo between its conducting and non-conducting states, and a static driver stage 9 configured to maintain the state of the output PMOS MPo until the dynamic driver stage 8 switches the state. The detailed function of the driver 7 is described in Figure 1. Fig. Sections 5 to 7 are explained. The major advantage of this driver 7 is that, even at higher operating frequencies of the integrated circuit, it requires a lower supply current (lower power) and a smaller chip area, as shown in Fig. 8 can be seen.

[0011] These and other aspects of the invention will become apparent from and be clarified by the embodiments described below. Those skilled in the art will understand that different embodiments can be combined with one another. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 shows a circuit and timing diagram of a state-of-the-art driver for an output pin of an integrated circuit. Fig. Figure 2 shows a timing diagram of a driver from Fig. 1 with a larger and a smaller capacity in the high-side mass generation stage. Fig. 3 shows the compromise of the design of the in Fig. 1 of the driver shown with regard to data rates, power consumption and chip area. Fig. Figure 4 shows the fundamental difference between the state-of-the-art driver and the driver. Fig. 1 and the driver according to the invention Fig. 5. Fig. Figure 5 shows an integrated circuit with a driver according to the invention. Fig. Figure 6 shows the sequence of events that occur in a dynamic power-on stage of the dynamic driver stage. Fig. Expires in 5 days. Fig. Figure 7 shows the sequence of events that occur in a dynamic shutdown stage of the dynamic driver stage. Fig. Expires in 5 days. Fig. 8 shows the advantages of the in Fig. 5 shown in the invention compared to the driver shown in Fig. 1 driver shown according to the state of the art. DETAILED DESCRIPTION OF THE EXECUTION FORMS

[0012] Fig. Figure 5 shows an integrated circuit 10 according to an embodiment of the invention for processing a data signal representing digital data with the bits “0” and “1”, wherein the integrated circuit 10 could be used in any type of technology field, such as for processing audio or video data. The integrated circuit 10 comprises a Fig. 5. A central processing unit (not shown) configured to process data, which may include internal or external memory for storing the processed digital data. The integrated circuit 10 also includes one or more output pins 2 to deliver the processed digital data as a processed data signal D at output pin 2 to an external device connected to output pin 2. The external device could, for example, be another integrated circuit of the same audio player or a computer that receives the processed data signal D via a wired bus such as the Universal Serial Bus.

[0013] The integrated circuit 10 further comprises a driver 7 for output pin 2 with a p-channel MOSFET, referred to as the output PMOS MPo of driver 7, which is connected with its drain contact to output pin 2 to supply the processed data signal D with the power specified for output pin 2. For example, a general-purpose output pin provides the processed data signal D with an output voltage of 5 volts and a maximum output current of 10 mA.

[0014] In general, the driver 7 of the integrated circuit 10 combines both a dynamic energy source, which quickly provides gate drive to the output PMOS MPo when the processed data signal D goes HIGH, and a static energy source, which supplies a regulated voltage to maintain the ON state of the PMOS MPo output transistor. This enables fast turn-on of the PMOS MPo output transistor without the need for a capacitor C. HSGND a large capacity is required.

[0015] To achieve this, the driver 7 of the integrated circuit 10 comprises a dynamic driver stage 8 configured to switch the output PMOS MPo between its conducting and non-conducting states, and a static driver stage 9 configured to maintain the state of the output PMOS MPo until the dynamic driver stage 8 switches the state. The dynamic driver stage 8 includes a dynamic turn-on stage 11 to switch the output PMOS MPo from its non-conducting state to its conducting state at a turn-on time T1 upon the occurrence of a rising edge of the processed data D, as shown in the Fig. 6 and Fig. Figure 7 shows that the dynamic driver stage 8 also includes a dynamic turn-off stage 12 to switch the output PMOS MPo from its conducting state to its non-conducting state at a turn-off time T2 when a negative edge of the processed data D occurs, as shown in the Fig. 6 and Fig. Figure 7 shows these two dedicated circuits of the dynamic driver stage 8, ensuring precise and energy-saving switching of the output PMOS MPo, as explained below.

[0016] The dynamic power-on stage 11 comprises a first PMOS MP1 of the same technology as the output PMOS MPo, wherein the source and drain contacts of the first PMOS MP1 are connected to the output of a first inverter 13 of the dynamic power-on stage 11. The first inverter 13 receives at its input the processed data signal D from the central processing unit or another processing stage of the integrated circuit 10 and is supplied with a voltage V. DDsupplied. This structure of the dynamic turn-on stage 11 allows the charge stored in the capacitance of the first PMOS MP1 at turn-on time T1 to be used to charge the capacitance of the output PMOS MPo at its gate contact in order to switch the output PMOS MPo into its conducting state, as shown by Fig. Section 6 is explained.

[0017] Fig. Figure 6 shows the waveforms of the operating time of the dynamic switch-on stage 11 of the in Fig. The integrated circuit 10 shown in Figure 5. The processed data signal D is represented as the first waveform with the positive edge at the switch-on time T1 and the negative edge at the switch-off time T2. The function of the dynamic switch-on stage 11 is explained by a sequence of six steps, which are also shown in the operating time curves of the Fig. The 6 are numbered. The rising edge of the processed data signal D at the switch-on time T1 causes the following sequence: Step 1: The first PMOS MP1, whose source and drain contacts are connected, holds a charge in its gate capacitance of QP = VDD * CG,MP1, which is the same charge needed to charge the capacitance of the output PMOS MPo at its gate contact in order to switch the output PMOS MPo into its conducting state, since both transistors are built with the same technology. Step 2: The voltage V M The output of the first inverter 13 goes to 0 V. Step 3: The voltage V N The gate contact of the first PMOS MP1 is pulled below ground (GND; 0 V). Step 4: The n-channel NMOS MNo connected to the gate contact of the first PMOS MP1 is switched on by the falling edge of the voltage V M at the output of the first inverter 13, it is switched on at its gate contact and conducts until V N = 0 V, which causes the charge QP to be dissipated by the voltage V GPAt the gate contact of the output PMOS MPo, current flows via an n-channel first MMOS MN1. Step 5: The voltage V at the gate contact of the output PMOS MPo drops to V BAT - V DD and switches the output PMOS MPo to the conducting state. Step 6: The static driver stage 9 holds the output PMOS MPo in its conducting state with a weak latch to the high-side ground voltage V. HSGND , which will be explained below.

[0018] The static driver stage 9 comprises a second inverter 14, whose input is connected to the gate contact of the output PMOS MPo and whose output is connected to the input of a third inverter 15, the output of which is connected to the gate contact of the output PMOS MPo via a resistor 16. The second inverter 14 and the third inverter 15 switch between a positive supply voltage level V BATfor example 5 volts and a high-side ground voltage V HSGND in order to, where V HSGND more or less V BAT minus the reference voltage level V DD is and smaller than the positive supply voltage level V BAT is. The high-side ground voltage V HSGND can be, for example, reduced to 1.8 volts below V BAT be determined. This circuit of the static driver stage 9 ensures a weak connection to the high-side ground voltage V. HSGND This operation requires no additional bias current as with prior art drivers. Once the output PMOS MPo is switched to the conducting state, the static driver stage 9 maintains the conducting state. In comparison to prior art, the high-side ground voltage source V provides HSGND not the energy to bring the output PMOS MPo into the conducting state. The high-side ground generation stage, which generates the high-side ground voltage V HSGNDIt only needs to provide a very small current source on the order of ~6 nA per driver 7, which can be supplied by a voltage reference circuit. Therefore, no large capacitor C is required. HSGND required to ensure a fast response of the high-side ground voltage V HSGND to enable this. In state-of-the-art drivers, the capacitor C had to be HSGND generally be significantly larger than the gate capacitance of both the output PMOS MPo and the first PMOS MP1 to absorb current transients, which required a large chip area, especially considering that each driver might require 7 individual high-side ground stages.

[0019] To enable high-frequency operation, it is equally important to enable rapid turn-off of the output PMOS MPo, meaning that the output PMOS MPo is switched from its conducting to its non-conducting state. To achieve this, the dynamic driver stage 8 of the integrated circuit 10 includes a dynamic turn-off stage 12, which is configured to control a second p-channel PMOS MP2 of the driver stage 7, connected to the gate contact of the output PMOS MPo, into its conducting state in order to discharge the capacitance of the output PMOS MPo at its gate contact and switch the output PMOS MPo into its non-conducting state.

[0020] Fig. Figure 7 shows the waveforms of the operating time of the dynamic shutdown stage 12 of the in Fig. The integrated circuit 10 shown in Figure 5. The processed data signal D is represented as the first waveform with the positive edge at the switch-on time T1 and the negative edge at the switch-off time T2. The function of the dynamic switch-off stage 12 is explained by means of a sequence of eight steps, which are also shown in the operating time curves of the Fig. The 7 are numbered. The negative edge of the processed data signal D at the switch-off time T2 causes the following sequence: Step 1: A third p-channel PMOS MP3 with connected source and drain contacts holds a charge in its gate capacitance QP = VDD * CG,MP3. This is the same charge that the second PMOS MP2 needs to switch to its conducting state QD = VDD * CG,MP2, since both transistors are built using the same technology. Step 2: The processed data signal D switches to 0 V at the switch-off time T2, which is the input of a fourth inverter 18 that is connected to a fifth inverter 17. Step 3: The voltage V P The gate contact of the third PMOS MP3 is pulled below ground (GND; 0 V). Step 4: A third n-channel NMOS MN3 conducts until the voltage V P = 0 V, which means that the charge QP is independent of the voltage V GP,D flows to the gate contact of the PMOS MP2. Step 5: The voltage V GP,D The voltage drops to V at the gate contact of the second PMOS MP2. BAT - V DD . Step 6: The voltage V GP At the gate contact of the output PMOS, MPo discharges to V BAT and switches the output PMOS MPo to the non-conducting state. Step 7: The static driver stage 9 holds the output PMOS MPo in its non-conducting state with a weak latch to the high-side ground voltage V. HSGND , voltage V GPn = V HSGND . Step 8: The voltage V GP,D At the gate contact of the second PMOS MP2, a discharge occurs onto the supply voltage V. BAT .

[0021] The following summarizes the improvements of the invention compared to the prior art: The driver 7 according to the invention requires significantly less power in both high-frequency and low-frequency operation and does not require large energy storage devices that occupy a large chip area. State-of-the-art drivers as shown in Fig. 1 • The high-side mass generation stage must drive and restore the charge at the output PMOS MPo. At higher speeds, the power required for this increases significantly. • If the high-speed implementation is used at low speed, operation is inefficient (high power consumption of the controller of the high-side mass generation stage) • Requires a large capacity C HSGND for a rapid restoration of the high-side ground voltage V HSGND which results in a large chip area per driver. INVENTIONAL DRIVER AS SHOWN IN FIG. 5 • The high-side ground voltage V HSGND This is a reference signal that is practically discharged. The high-side ground generation stage typically requires only a few nanoamperes and is independent of the operating frequency. • The invention supports a wide range of operating frequencies without any loss of performance. • Does not require a large capacitance C capacitor.

[0022] Fig. 8 shows the advantages of the in Fig. 5 of the inventive driver 7 compared to the one shown in Fig. 1 driver shown according to the state of the art.

[0023] With the above explanation of driver 7, a method is disclosed to provide a processed data signal D, which is processed by the integrated circuit 10, at the output pin 2 of the integrated circuit 10 with the power specified for the output pin 2 of the integrated circuit 10, wherein the method comprises the following steps: Using the charge stored in the capacitance of a first PMOS MP1 of a dynamic turn-on stage 11 to charge the capacitance of an output PMOS MPo at its gate contact in order to switch the output PMOS MPo at output pin 2 from its non-conducting state to its conducting state at a turn-on time T1 when a positive edge of the processed data signal D occurs; Maintaining the state of the output PMOS MPo with a static driver stage 9 until the dynamic driver stage 8 switches the state again; Using a dynamic turn-off stage 12 to discharge the capacitance of the output PMOS MPo at its gate contact, in order to switch the output PMOS MPo at output pin 2 from its conducting state to its non-conducting state at turn-off time T2 when a negative edge of the processed data signal D occurs.

[0024] In another embodiment of the invention, n-channel MOSFETs and p-channel MOSFETs as well as the polarities of the voltages can be exchanged to achieve equivalent functionality of the driver 7.

[0025] Furthermore, the invention can be used in (switching) power conversion or in audio amplification or in haptic drivers or in any other similar application that is implemented with an integrated circuit and in which the person skilled in the art wishes to achieve the advantages of the invention.

Claims

[1] Integrated circuit (10) for processing data, wherein the integrated circuit comprises: a central processing unit that is trained to process data; an output pin (2) of the integrated circuit (10) to supply processed data (D) at output pin (2) to an external device connected to output pin (2); a driver (7) for the output pin (2) with an output MOSFET (MPo) of the driver (7) connected to the output pin (2) to supply the processed data (D) with the power specified for the output pin (2), characterized by , that the driver (7) includes: a dynamic driver stage (8) configured to switch the output MOSFET (MPo) between its conducting and non-conducting states, and a static driver stage (9) configured to maintain the state of the output MOSFET (MPo) until the dynamic driver stage (8) switches the state, wherein the dynamic driver stage (8) comprises a dynamic turn-on stage (11) to switch the output MOSFET (MPo) from its non-conducting state to its conducting state at a turn-on time (T1) upon the occurrence of a positive edge of the processed data (D), and wherein the dynamic driver stage (8) comprises a dynamic turn-off stage (12) to switch the output MOSFET (MPo) from its conducting state to its non-conducting state at a turn-off time (T2) upon the occurrence of a negative edge of the processed data (D), wherein the dynamic turn-on stage (11) comprises a first MOSFET (MP1) of the same technology as the output MOSFET (MPo), wherein the source contact and the drain contact of the first MOSFET (MP1) are connected to the output of a first inverter (13) of the dynamic turn-on stage (11),wherein the first inverter (13) receives the processed data (D) at its input and wherein the charge stored in the capacitance of the first MOSFET (MP1) at the turn-on time (T1) is used to charge the capacitance of the output MOSFET (MPo) at its gate contact in order to switch the output MOSFET (MPo) into its conducting state. [2] Integrated circuit (10) according to claim 1, wherein the dynamic turn-off stage (12) is configured to control a second MOSFET (MP2) of the driver stage (7), which is connected to the gate contact of the output MOSFET (MPo), into its conducting state in order to discharge the capacitance of the output MOSFET (MPo) at its gate contact in order to switch the output MOSFET (MPo) into its non-conducting state. [3] Integrated circuit (10) according to claim 1 or 2, wherein the static driver stage (9) comprises a second inverter (14) which is connected at its input to the gate contact of the output MOSFET (MPo) and at its output to the input of a third inverter (15), wherein the third inverter (15) is connected at its output to the gate contact of the output MOSFET (MPo) via a resistor (16), wherein the second inverter (14) and the third inverter (15) are connected between a positive supply voltage level (V BAT ) and a reference voltage level (V HSGND ), which is smaller than the positive supply voltage level (V BAT ) is, switch. [4] Method for providing processed data at an output pin (2) by an integrated circuit (10) according to any one of claims 1 to 3 with the power specified for the output pin (2) of the integrated circuit (10), wherein the method comprises the following steps: Using the charge stored in the capacitance of a first MOSFET (MP1) of a dynamic turn-on stage (11) to charge the capacitance of an output MOSFET (MPo) at its gate contact in order to switch the output MOSFET (MPo) at the output pin (2) from its non-conducting state to its conducting state at a turn-on time (T1) when a positive edge of the processed data (D) occurs; Maintaining the state of the output MOSFET (MPo) with a static driver stage (9) until the dynamic driver stage (8) switches the state; Using a dynamic turn-off stage (12) to discharge the capacitance of the output MOSFET (MPo) at its gate contact in order to switch the output MOSFET (MPo) at the output pin (2) from its conducting state to its non-conducting state at turn-off time (T2) when a negative edge of the processed data (D) occurs.

Images