SELF-ADJUSTING CORE STRUCTURE

Abstract

A device comprises a glass plate that includes a first surface, a trench in the first surface, and a routing structure above the first surface. A conductor track includes a first section within the trench and a second section above the first surface. The conductor track extends laterally over a length greater than the width of the conductor track. The first section extends a depth below the first surface, and the second section extends a height above the first surface, with the depth being at least 10 percent or at least 20 percent of the height. The second section includes a sidewall with a concave or planar profile. The glass plate includes a second surface opposite the first surface. A through-glass via (TGV) extends between the first and second surfaces. The TGV is coupled to the conductor track.

Description

BACKGROUND In electronics manufacturing, integrated circuit (IC) encapsulation is a phase of semiconductor device manufacturing in which an IC, monolithically fabricated on a chip (or die), is enclosed in a package that protects the IC chip from physical damage. The package connects the IC chip to other encapsulated IC chips and / or a scaled host component, such as a package substrate or printed circuit board. Multiple IC chips can be assembled into a multi-die package (MCP). Some IC packages incorporate interposers, which are substrates used to connect multiple chips or dies within a single integrated circuit (IC) package. Traditionally, package substrates and interposers were made from organic materials. More recently, package substrates and interposers with a glass core sandwiched between layers of organic materials have been introduced. A substrate with a glass core offers advantages over conventional substrates with an organic core, including low total thickness variation (TTV), high via density (PTH density), high dimensional stability, and high strength. The layers of organic materials over the surfaces of a glass-core package substrate or interposer generally feature redistribution structures with one or more redistribution layers (RDLs) and interconnection features on the upper and lower surfaces of the redistribution structures. Glass-core package substrates and interposers also generally feature through-glass vias (TGVs). The redistribution structures and the TGVs couple the upper and lower interconnection features, allowing the package substrate or interposer to couple IC dies to each other and to a printed circuit board. The object described here is illustrated in the accompanying figures as an example and not as a limitation. For the sake of simplicity and clarity of illustration, elements depicted in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Views labeled "cross-section," "profile," and "top view" correspond to orthogonal planes within a Cartesian coordinate system. Thus, cross-section and profile views are drawn in the xz-plane, and top views in the xy-plane. Profile views in the xz-plane are usually cross-section views. Where appropriate, drawings are labeled with axes to indicate the orientation of the figure. Furthermore, where deemed appropriate, reference symbols have been repeated between figures to indicate corresponding or analogous elements.In the figures: Fig. 1 illustrates a flowchart of methods for forming an IC device structure with a glass core substrate or an interposer according to some embodiments, wherein the glass core has a conductor track with a section within a trench on a surface of the glass and a section above the surface; Fig. 2 is a cross-sectional view of a glass plate according to some embodiments, received in an initial stage of manufacturing; Figs. 3A-3M illustrate cross-sectional views of a glass plate according to some embodiments, developed during the execution of operations of the methods illustrated in Fig. 1; Fig. 4 is a cross-sectional view of a glass core package substrate or interposer in a manufacturing stage of the methods illustrated in Fig. 1 according to some embodiments; Fig. 5 illustrates a system in a manufacturing stage of the methods illustrated in Fig.Figure 1 illustrates the process after attaching one or more IC dies and a host component to the package substrate of Figure 4 according to some embodiments; Figures 6A-6H illustrate cross-sectional views of a glass plate according to some alternative embodiments, which evolves during the execution of operations of the process illustrated in Figure 1; Figure 7 illustrates a mobile computing platform and a data server machine employing one or more devices comprising an IC package with a substrate or an interposer with a glass core, the glass core having a conductor with a section within a trench in the glass and a section above the surface of the glass according to some embodiments; and Figure 8 is a functional block diagram of an electronic computing device according to some embodiments. DETAILED DESCRIPTION Embodiments are described with reference to the accompanying figures. Although specific configurations and arrangements are shown and discussed in detail, this serves only illustrative purposes. Those skilled in the relevant field will recognize that other configurations and arrangements are possible without deviating from the essence and scope of protection of the description. It is obvious to those skilled in the relevant field that the techniques and / or arrangements described here can be used in a variety of systems and applications other than those described in detail here. The following detailed description refers to the accompanying drawings, which form part thereof and illustrate exemplary embodiments. It is further understood that other embodiments may be used and structural and / or logical modifications may be made without deviating from the scope of protection of the claimed subject matter. It should also be noted that directions and references, e.g., upward, downward, above, below, and so on, are used only to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be understood in a restrictive sense, and the scope of protection of the claimed subject matter is defined exclusively by the attached claims and their equivalents. Numerous details are set forth in the following description. However, it is obvious to those skilled in the art that embodiments can also be implemented in practice without these specific details. In some cases, well-known methods and devices are shown in the form of a block diagram instead of in detail to avoid making the embodiments unclear. Throughout the entire description, a reference to "any embodiment," "a specific embodiment," or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment.Thus, the appearance of the expression "in any embodiment," "in a specific embodiment," or "in some embodiments" at various points throughout the entire description does not necessarily refer to the same embodiment. Furthermore, the specific features, structures, functions, or characteristics in one or more embodiments may be combined in any suitable manner. For example, a first embodiment may be combined with a second embodiment wherever the specific features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive. As used in the description and the accompanying claims, the singular forms "ein", "eine", and "der / die / das" are intended to include the plural forms unless the context clearly indicates otherwise. It is further understood that the term "and / or", as used here, refers to and includes all possible combinations of one or more of the associated listed elements. The terms "coupled" and "connected," along with their derivatives, can be used here to describe functional or structural relationships between components. These terms are not synonymous. Instead, in certain embodiments, "connected" can be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" can be used to indicate that two or more elements are in either direct or indirect (with other intervening elements) physical or electrical contact with each other, and / or that the two or more elements work together or interact with each other (e.g., as in a cause-and-effect relationship). The terms "above," "below," "between," and "on," as used here, refer to the relative position of a component or material with respect to other components or materials, where such physical relationships are noteworthy. A "vertical" orientation refers to the z-direction. A "lateral" orientation refers to the x- or y-direction. In the context of materials, for example, a material or layer above or below another may be in direct contact with it, or it may have one or more materials or layers in between. Furthermore, a material between two materials or layers may be in direct contact with both materials / layers, or it may have one or more materials / layers in between.In contrast, a first material or layer is located "on" a second material or layer, in direct physical contact with that second material / layer. Similar distinctions must be made in the context of component arrangements. As used throughout this description and in the claims, a list of elements joined by the phrase "at least one of" or "one or more of" can mean any combination of the listed terms. For example, the phrase "at least one of A, B, or C" can mean A; B; C; A and B; A and C; B and C; or A, B, and C. Unless otherwise specified in the specific context of use, the term "predominantly" means more than 50% or more than half. For example, a compound that is predominantly a first constituent means that more than half of the compound is the first constituent (e.g., < 50%). The term "mainly" means the largest part or majority. For example, a compound that is mainly composed of a first constituent means that the compound has more of the first constituent than of any other constituent. A compound that is primarily composed of first and second constituents means that the compound contains more of the first and second constituents than of any other constituent. The term "essentially" means that there is only a slight variation.For example, a composition that is essentially a first component means that the composition further contains < 1% of any other component. A composition that is essentially a first and second component means that the composition may further contain < 1% of any component that replaces one of the first or second components. With the increasing miniaturization of circuit arrangements in IC dies coupled to a package substrate or interposer, the desired number of connections between the IC dies and the package substrate or interposer may increase. It may be desirable to provide a large number of traces on the surface of a glass core. Additionally, there may be a need to supply the IC dies with a significant amount of power, which may require connections capable of carrying relatively high currents. Electrical resistance is inversely proportional to the cross-sectional area of ​​a wire. A trace with a specific cross-sectional area will have a lower resistance than another trace with a smaller cross-sectional area. It may therefore be desirable to provide traces with relatively large cross-sectional areas. More conductor tracks can be placed on the surface of a glass core, and they can be made wider and larger. However, a challenge with this approach is that, due to design rules, conductor tracks on the surface of a glass core must be spaced a certain distance apart. As the height above the surface increases, these design rules may require larger spacing. Another challenge is that widening conductor tracks limits the number of conductor tracks that can be placed on the surface of a glass core. Embodiments relate to an IC device structure with a glass core substrate or an interposer, wherein the glass core has a conductor track with a section within a trench on a surface of the glass and a section above the surface. Embodiments also relate to a self-aligning core structuring process. Advantages of the embodiments described here are that conductor tracks with a section within a trench and a section above the glass can have a higher aspect ratio than other conductor tracks that are located only on the glass surface.A further advantage of the conductor tracks described here is that they can have a larger cross-sectional area than conductor tracks located solely on the glass surface. The increased thickness provided by the section of the conductor track within the trench gives these conductor tracks a lower electrical resistance than those located solely on the glass surface. Another advantage of the embodiments described here is that package substrates or interposers with a glass core are stiffer and can accommodate more IC dies than substrates made of organic materials. As illustrated in Fig. 1, a variety of manufacturing processes can be implemented to form IC device housing structures with one or more of the features described herein. Fig. 1 illustrates a flowchart of processes for forming an IC device structure with a glass core substrate or interposer according to some embodiments, wherein the glass core has a conductor track with a section within a trench on a glass surface and a section above the surface. The processes 101 begin at an input 110, at which a workpiece having a glass thickness is received. The workpiece may be prepared upstream of the processes 101 and may be in a large plate format, a wafer format, or the like. The workpiece received at the input 110 may be structured with a plurality of holes and trenches, or the workpiece may be unstructured, as shown, for example, in Fig. 2. Fig. 2 is a cross-sectional view of a glass plate 204 according to some embodiments, received in an initial stage of the manufacturing process 202. The advantages of fabricating IC device housing structures on glass are that the flatness and / or thickness control for a glass preform is better than that of starting substrates based on organic materials (e.g., epoxy), and the costs can be considerably lower than for monocrystalline materials (e.g., silicon). The glass 204 is a solid bulk material layer that may have been previously formed into any shape suitable for an encapsulation workpiece, such as rectangular. The glass 204 has a first surface 206 and a second surface 208 opposite the first surface.The glass 204 has a thickness T1, which can vary depending on the implementation, for example to limit curvature, while remaining thin enough to allow the formation of vias and grooves with spacings as small as the surface flatness of the glass 204 permits. In exemplary embodiments, the thickness T1 is advantageously 0.1 µm to 3.0 µm. Although not shown, one or more material layers can coat either the first surface 206 or the second surface 208 of the glass 204, or both, such that the glass 204 forms a bulk or core layer of a multilayer substrate. Exemplary coating materials include inorganic materials such as silicon nitride (SiNx) or silicon oxynitride (SiOxNy). In other embodiments, a silicon layer (polycrystalline or monocrystalline) can coat one or both sides of the glass 204. Organic material layers, such as dielectric polymer materials, can also coat one or more sides of the glass 204. Although the glass 204 is advantageously essentially free of organic materials (e.g., without adhesives, etc.), a workpiece in the manufacturing stage 202 may therefore contain organic material within a substrate stack comprising the glass 204. The glass 204 advantageously consists predominantly of silicon and oxygen. In some embodiments, the glass 204 comprises at least 23 percent silicon and at least 26 percent oxygen by weight (i.e., wt.%). The glass 204 may further comprise one or more additives, such as aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, or zinc. In some embodiments, in which the glass 204 comprises at least 23 wt.% Si and at least 26 wt.% O, the glass 204 further comprises at least 5 wt.% Al. Additives within the glass 204 may form suboxides (A₂O), monoxides (AO), binary oxides (AO₂), ternary oxides (ABO₃), and mixtures thereof. For example, the glass 204 can be AlOx (e.g. Al2O3), BOx (e.g. B2O3), MgOx (e.g. MgO), CaOx (e.g. CaO), SrOx (e.g. SrO), BaOx (e.g. BaO), SnOx (e.g. SnO2), NaOx (e.g. Na2O), KOx (e.g. K2O), POx (e.g. P2O3), ZrOx (e.g. ZrO2), LiOx (e.g. Li2O), TiOx (e.g.The glass may contain TiO2) or ZnOx (e.g., ZnO2). Depending on its chemical composition, glass 204 can therefore be described, for example, as silicon dioxide, quartz glass, aluminosilicate, borosilicate, or aluminoborosilicate. The glass 204 is advantageously a bulk material with a substantially homogeneous composition, in contrast to a composite material that may only comprise glass fillers and / or fibers. Although the glass 204 is substantially amorphous in some embodiments, it may also have a different morphology or microstructure, such as polycrystalline (e.g., nanocrystalline). Returning to Fig. 1, the process 101 is continued at block 115, in which features are formed in the unstructured glass 204. Exemplary features include through holes or openings in the glass and grooves or channels on one or both surfaces of the glass. The features can be produced by any process known to be suitable for bulk glass. In some embodiments, block 115 comprises laser ablation, a glass etching process (laser-assisted or otherwise), or any other technique known to be suitable for forming features within or through a thickness of the glass with a desired xy size (diameter or width and length), a desired z size (depth), and a desired feature spacing. Figures 3A and 3B are cross-sectional views of the glass plate 204 in a manufacturing stage 210 after features have been written into the glass plate with laser radiation according to some embodiments. Figure 3C is a top view of the glass plate 204 in the manufacturing stage 210. The cross-sectional view in Figure 3A is along line AA' (shown in Figure 3C). The cross-sectional view in Figure 3B is along line BB' (in Figure 3A). In the example illustrated in Figures 3A-3C, positions 211 for grooves 212 and positions 213 for through holes 214 were written with laser radiation that modifies one or more properties of the glass 204. In some embodiments, the laser radiation is pulsed (e.g., at a femtosecond rate), which makes the sections of the glass 204 exposed to the radiation more susceptible to etching by chemical etchants.The laser structuring process at 210 can therefore define both positions and dimensions of trenches 212 as well as through holes 214. Figures 3D and 3E are cross-sectional views of the glass plate 204 in a manufacturing stage 216 after features have been etched into the glass plate according to some embodiments. Figure 3F is a top view of the glass plate 204 in a manufacturing stage 216. As illustrated in Figures 3D, 3E, and 3F, the etching process forms trenches 212 and through-holes 214. Although in the illustrated example the trenches 212 are formed on both the first surface 206 and the second surface 208, in other examples the trenches 212 may be formed on only one of the surfaces. The dimensions of the through-holes 214 and the trenches 212 can vary with the implementation, as described below. In the manufacturing stage 216, any suitable wet or dry etching process known in the field can be used. The trenches 212 have side walls 218. In some embodiments, the side walls 218 are essentially straight or planar. In some examples, the side walls 218 are essentially orthogonal to the surfaces 206, 208, as illustrated in Fig. 3E. In other examples, the side walls 218 may have a positive taper with respect to one of the surfaces 206, 208, e.g., the trench is wider at the surface than at a bottom surface 219 of the trench. In further examples, the side walls 218 may have a negative taper with respect to one of the surfaces 206, 208, e.g., the trench is narrower at the surface than at the bottom of the trench. Returning to Fig. 1, the process 101 is continued at block 120, in which conductive features are formed on one or both surfaces of the glass plate and TGVs are formed. Conductive features have conductive traces or lines. Conductive features and TGVs can be formed using a subtractive etching process, a semi-additive process, or any other suitable process. Figs. 3G-3L illustrate a subtractive etching process for producing conductive features and TGVs according to some embodiments. Figs. 6A-6H illustrate a semi-additive process for producing conductive features and TGVs according to some embodiments. Figures 3G and 3H are cross-sectional views of the glass plate 204 in a manufacturing stage 220 after the deposition of a conductive material 222 and after the application of a photoresist 224 over the conductive material 222 according to some embodiments. Figure 31 is a top view of the glass plate 204 in a manufacturing stage 220. As illustrated in Figure 3G-31, the conductive material 222 covers both surfaces 206, 208 and fills the through-holes 214 and the grooves 212. The conductive material 222 can be any conductive material containing metals, such as copper, aluminum, gold, titanium, nickel, tungsten, silver, zirconium, cobalt, and alloys thereof, without limitation. The conductive material 222 can be deposited by any suitable process known in the field.In some examples, the conductive material 222 is formed by sputtering copper or another suitable metal over the surfaces 206, 208. In Figures 3G-3I, the photoresist 224 was applied at selected positions over the conductive material 222 on surfaces 206 and 208. Any suitable photoresist can be used. In some embodiments, the photoresist 224 is a dry-film resist. The photoresist 224 can be formed using any suitable technique. For example, the photoresist 224 can be applied using vacuum lamination or hot lamination techniques. Furthermore, in Figures 3G-3I, the photoresist 224 can be applied over entire surfaces and then patterned by a photolithographic process to form openings, with the conductive material 222 being removed in a subsequent process to form conductive features, e.g., conductor tracks 228, at specific positions on surfaces 206 and 208. Figures 3J, 3K, and 3M are cross-sectional views of the glass plate 204 in a manufacturing stage 226 after the removal of unmasked sections of the conductive material 222 and the photoresist 224 according to some embodiments, thereby exposing conductive traces 228 and conductive features 230. Figure 3L is a top view of the glass plate 204 in the manufacturing stage 226. Cross-sections of TGVs 229 are shown in Figure 3J. The conductive traces 228 comprise a first section 236 within the trench 212 and a second section 234 above the surface of the glass 204, e.g., B. the first surface 206 or the second surface 208. The conductor tracks 228 and the conductive features 230 have upper surfaces 231 and side walls 232 that extend over the surface 206. In the one shown in Fig.In the example illustrated in 2J-L, the conductive traces 228 and the conductive features 230 were formed using a subtractive etching process that etches the conductive material 222 through a lithographically defined etch mask of photoresist. In alternative embodiments, the conductive traces 228 and the conductive features 230 can be formed using a semi-additive process, as described, for example, elsewhere herein. Although the conductor tracks 228 are generally located within the trenches 212, a segment 233 (also called a section) of a conductor track 228 can extend a lateral length L3 away from a trench 212 or TGV 229. For example, the segment 233 is located above the first surface 206, but not above a trench or TGV. Accordingly, a conductor track 228 can have a first thickness T2 away from the trench and a second thickness T3 above the trench 212. The first thickness T2 is between the surface 206 and the upper surface 231 of the conductor track 228. The second thickness T3 is between the bottom surface 219 of the trench and the upper surface 231. The second thickness T3 is greater than the first thickness T2. In some examples, the length L3 is greater than the width W1 of a conductor track or a width W2 of a trench, but this is not essential. The conductor tracks 228 have a length L1 extending laterally, a width W1 at the upper surface 231 of the conductor track 228, and a width W2. The width W2 can be located either near the glass surface, e.g., the first surface 206, or at the bottom surface 219 of the trench 212. The width W1 can be located at the upper surface 231 of the conductor track 228. In embodiments, the width W1 can be between 30 and 50 micrometers. In some examples, the widths W1 and W2 are approximately equal. In some examples, the width W1 can be slightly narrower than W2, e.g., five to ten percent narrower. In some examples, the width W1 can be slightly wider than W2, e.g., five to ten percent wider. In embodiments, a conductor track 228 extends over a lateral length L1, where L1 is greater than a width W1 or W2 of the conductor track. In some examples, the conductor tracks 228 have lateral dimensions L1 of 40 micrometers to 10 mm or more. As illustrated in Fig. 3J and Fig. 3L, one section of a conductor track 228 may be located over a TGV, and another section may not be located over a TGV. For example, the conductor track 228 extends over a lateral length L2 that does not extend over a TGV. In some examples, the length L2 of a conductor track extends between first and second TGVs. In some examples, the length L2 of a conductor track extends between a TGV and a conductive feature that is not a TGV (not illustrated in Fig. 3J) within a routing structure over a surface of the glass 204, e.g. B. the first surface 206 or the second surface 208.In some examples, a conductor 228 extends without bridging a position where a TGV (or another conductive feature within the glass 204) meets the first surface 206. For example, a conductor 228 can extend between first and second features (not illustrated in Fig. 3J or Fig. 3L) on the first surface 206. As another example, a conductor 228 can extend between first and second features in a routing structure across a first surface 206. As mentioned, a conductor 228 can also extend over a length L3 that is neither within nor above a trench 212. As illustrated in Fig. 3K, a conductor track 228 can have a height H1 (e.g., z-height) above the first surface 206 (or the second surface 208) of 5 to 75 micrometers. A conductor track 228 can extend to a depth D1 (e.g., z-height) below the first surface 206. The depth D1 can be between 5 micrometers and 40–50 percent of the glass thickness T1. In some examples, the conductor tracks 228 can extend over a depth D1 between 0.05 mm and 1.5 mm. As mentioned, the conductor track 228 can have a width W1 or W2. When two conductor tracks 228 are adjacent to each other, a minimum distance S1 between the conductor tracks is required. The minimum distance S1 required between adjacent conductor tracks 228 also applies to conventional conductor tracks.For example, two or more adjacent conventional conductor tracks on the surface of a glass core or within a dielectric in a redistribution structure may be required to maintain a minimum spacing S1 between conductor tracks. An advantage of the embodiments described herein is that, due to the additional depth within the glass plate, adjacent conductor tracks 228 of a specific width can be thicker than adjacent conventional conductor tracks of the same width. Accordingly, the conductor tracks 228 can provide a lower electrical resistance than conventional conductor tracks. A lower electrical resistance is particularly advantageous for conductor tracks 228 carrying power signals. In embodiments where a subtractive etching process is used, the minimum distance S1 between adjacent conductor tracks 228 can be 1-2 times the height H1. Accordingly, in some examples, the height H1 is in the range of 15-25 micrometers and S1 in the range of 30-50 micrometers. Depending on the process used, the sidewalls 232 can have a profile with a concave curvature or a convex shape, indicating a subtractive etching process. The conductor tracks 228 can have a first corner C1 between the upper surface 231 and a sidewall 232. There can also be a second corner C2 where the sidewall 232 meets the first surface 206 (or the second surface 208). The conductor tracks 228a illustrated in Fig. 3K have a first corner C1 without significant undercut or overhang at the first corner C1 according to some embodiments. The second corner C2 of the conductor track 228a curves to meet the first surface 206. Fig. 3M illustrates additional examples of the sidewall profiles 232 of conductor tracks produced by a subtractive etching process, according to some embodiments. The conductor tracks 228b illustrated in Fig. 3M have a first corner C1 with an undercut or overhang at the first corner C1. The second corner C2 of the conductor track 228b meets the first surface 206 with a vertically straight or planar profile. The conductor tracks 228c illustrate sidewalls 232 with a concave curved profile defined by a radius of curvature R1. In some examples, a sidewall may be more curved, as illustrated by a radius of curvature R3, or less so, as illustrated by a radius of curvature R2. In Fig. 3M, dashed lines show sidewall profiles with varying degrees of curvature. The conductor tracks 228c have different degrees of undercut at the first corner C1. The conductive traces 228d have a width W4 at the first surface 206, where the first section 236 meets the second section 234. The width W4 is smaller than the width W2 of the trench 212 at either the first surface 206 or the lower surface 219. The second corner C2 of the conductive traces 228d may have a depression or trough between the vertical extension of the side wall 232 and the first surface 206, indicating the removal of a small section of the conductive material 222 within the trench 212, i.e., a removal of the conductive material within the first cut 236. The conductor tracks 228e have a width W5 at the first surface 206, where the width W5 is greater than the width W2 of the trench 212. The second corner C2 of the conductor tracks 228d may have a section that extends laterally and overlaps the width W2 of the trench 212. Referring again to Fig. 1, the process 101 is continued at block 130, in which redistribution structures are formed over a surface of the glass plate 204. Fig. 4 is a cross-sectional view of the glass plate 204 in a manufacturing stage after the formation of the redistribution structures 404 and 406 according to some embodiments. The structure illustrated in Fig. 4 can be a housing substrate 402 according to some embodiments. In other embodiments, the structure illustrated in Fig. 4 can be an interposer. The housing substrate 402 has a glass plate 204 with conductive traces 228 and conductive features 230, similar to the example illustrated in Figs. 3J-3L. (The orientation of the glass plate 204 is reversed compared to Fig. 3J.)The redistribution structure 404 is located above the first surface 206 and comprises one or more layers of a housing metallization, which has multiple front-side conduction metallizations 408 and front-side via metallizations 410 between the conduction metallization layers. The redistribution structure 406 is located above the second surface 208 and comprises one or more layers of a housing metallization, which has multiple back-side conduction metallizations 412 and back-side via metallizations 414 between the conduction metallization layers. The via metallization can connect the conduction metallization vertically to the conductor tracks 228 and the conductive features 230. In some examples, the housing substrate 402 may have only one redistribution structure on one surface. The redistribution structures 404 and 406 comprise first surfaces 405a, 405b near the glass plate 204 and second surfaces 407a, 407b opposite the first surfaces, which can be referred to as the "outer" surface. As shown in Fig. 4, intermediate connections 416, 418 (also referred to as contact pads) were formed on the outer surfaces of the redistribution structures 404 and 406. The intermediate connections 416, 418 can be separated by the solder resist material 420. The via metallization connects the conductor metallization, the conductor tracks 228, and the conductive features 230 vertically to the intermediate connections 416, 418 on the outer surfaces. The conductor tracks 228 and the conductive features 230, together with metallization features in the redistribution structures, can be used to conduct electrical signals between the intermediate connections 416, 418.For example, the conductive traces 228 can be used as part of a network for conducting electrical power signals from intermediate connections on one surface to intermediate connections on an opposite surface, or to and from an electrical component within the glass plate 204. The via metallization 410, 414 and the conduction metallization 408, 412 within the housing substrate 402 can, for example, be formed by an additive or semi-additive process. The via metallization 410, 414 and the conduction metallization 408, 412 can include copper. However, other conductive materials are also possible. The housing substrate metallization is embedded in one or more layers of a housing substrate insulator 422. In exemplary embodiments, the housing substrate insulator 422 comprises an organic dielectric material (e.g., a polymer). The housing substrate insulator 422 may comprise an epoxy resin, a phenolic glass, or a resin film, such as the commercially available GX series films from Ajinomoto Fine-Techno Co., Inc. Exemplary epoxy resins include a novolac acrylate, such as epoxy phenol novolacs (EPN) or epoxy cresol novolacs (ECN). In some specific examples, the housing substrate insulator 422 is a bisphenol-A epoxy resin containing, for example, epichlorohydrin. In other examples, the housing substrate insulator 422 comprises a bisphenol-F epoxy resin (containing epichlorohydrin). In other examples, the housing substrate insulator 422 features aliphatic epoxy resin that is monofunctional (e.g.The housing substrate insulator 422 can be difunctional (e.g., butanediol diglycidyl ether) or of higher functionality (e.g., trimethylolpropane triglycidyl ether). In other examples, the housing substrate insulator 422 features glycidylamine epoxy resin, such as triglycidyl p-aminophenol (functionality 3) and N,N,N,N-tetraglycidyl bis-(4-aminophenyl)methane (functionality 4). Returning to Fig. 1, the procedures of 101 are continued at block 140, in which an IC device package 502 is completed according to some embodiments. Fig. 5 is a cross-sectional view of an IC device package 502 in a manufacturing stage after the attachment of one or more IC dies and a host component to a package substrate according to some embodiments. As illustrated in Fig. 5, the IC dies 504a and 504b have been attached to a surface of the package substrate 402, and the package substrate 402 has been attached to a host component 506. In some embodiments, the IC dies 504a and 504b can be attached to intermediate connections 416 of the package substrate 402 by solder features 512. In some embodiments, the intermediate connections 416 are bonded directly to conductive features (not shown) of the IC dies 504a and 504b using a hybrid bonding technique. When hybrid bonding is used, surface metal features embedded in an insulator of one IC die are directly fused to surface metal features embedded in an insulator of another die (or, in this case, the redistribution structure 404). The hybrid-bonded interface between the dies can include both metallurgically interdiffused metals and chemically bonded insulators. Dies 504a and 504b can incorporate a circuit arrangement to perform any desired functionality. For example, either IC die 504a or 504b can be a logic circuit, an integrated power management circuit, a transmitter, a receiver, a memory controller, a communication controller, a controller, a processor, an application-specific integrated circuit (ASIC), or a memory. Either IC die 504a or 504b can be a photonic integrated circuit (PIC) or incorporate optical or photonic elements. The IC fixture package 502 can be coupled to a power supply 530. The power supply 530 can be coupled to the IC die 504a and 504b via the host component 506 and the package substrate 402 with a glass core.Power can be provided to the IC dies 504a and 504b from the power supply 530 through a network comprising conductive structures within the package substrate 402, e.g. conductor tracks 228, conductive features 230 and metallization features within the redistribution structures 404, 406. The package substrate 402 can be attached to the host component 506 by fusing first-level interposers (FLIs) 511. In exemplary embodiments, the FLIs 511 are solder (e.g., SAC) micro-contact mounds, although other interposer features are possible. In some embodiments, the host component 506 consists predominantly of silicon. The host component 506 can also comprise one or more alternative materials known to be suitable as interposers or package substrates (e.g., an epoxy preform, a laminate sheet with or without a core, etc.). The host component 506 can have one or more metallized redistribution layers (not shown) embedded in a dielectric material. The host component 506 can also have one or more IC dies embedded therein.In embodiments in which the housing substrate 402 is an interposer, the interposer can be attached to one or more IC dies instead of the host component 506 via the redistribution structure 406. In other embodiments, the host component 506 has second-level interconnects (SLI) 520. The SLI 520 can comprise any solder (ball, contact bump, etc.) suitable for a given host board architecture (e.g., a surface-mount FR4, etc.). As illustrated in the dashed lines, one or more heat spreaders and / or heat sinks 550 can further be coupled to the IC dies 504a and 504b, which may be advantageous, for example, if the IC dies 504a, 504b comprise one or more CPU cores or another circuit arrangement with similar power density. The IC device package 502 comprises a package substrate 402. The package substrate 402 includes a glass plate with a trench on one surface and conductive traces that have a first section within the trench and a second section above the surface. In the examples presented above, the conductive traces 228 of the package substrate 402 are fabricated by a subtractive etching process. In these examples, the sidewall profiles of the conductive traces 228 have a concave curvature, indicative of the subtractive etching process. However, in other examples, the conductive traces 228 may not have sidewalls 232 with inwardly curved profiles. In other examples described below, the sidewalls 232 may have an essentially straight or planar profile, indicative of a semi-additive process. Returning to Fig. 1, in block 120 of process 101, conductive features are formed on one or both surfaces of the glass plate, and TGVs are formed. Figs. 6A-6H illustrate a semi-additive process for forming conductive traces on one or both surfaces of a glass plate and forming TGVs according to some embodiments. Figs. 6A and 6B illustrate a manufacturing stage 602 following the deposition of a nucleation layer 604 on surfaces of the glass plate 204. The manufacturing stage 602 can be performed after the formation of features in a glass plate. For example, the manufacturing stage 602 illustrated in Figs. 6A and 6B can be performed following the manufacturing stage 216 illustrated in Figs. 3D and 3E. In some examples, the nucleation layer 604 is a thin film of conductive material comprising copper, gold, silver, or another suitable metal.The germ layer 604 is deposited on surfaces 206, 208, on surfaces of passage holes 214 and on surfaces of trenches 212, including the side walls 218 and the bottom surfaces 219 of the trenches 212. Figures 6C and 6D are cross-sectional views of the glass plate 204 in a manufacturing stage 606 after the deposition and structuring of the photoresist 608 over the surface of the glass plate 204. The structured photoresist serves as a plating mask for a subsequent manufacturing step. The photoresist 608 can be structured by a photolithographic process and has openings at positions intended for conductive traces and other conductive features. The photoresist 608 can be any suitable resist material known in the field. Similarly, the photolithographic process can be any suitable photolithographic process known in the field. Figs. 6E and 6F are cross-sectional views of the glass plate 204 in a manufacturing stage 610 after electroplating of the conductive material 222 over exposed surfaces of the glass plate 204, including surfaces 206, 208 and the surfaces of through holes 214 of the trenches 212. The conductive material 222 is plated onto the nucleation layer 604 in openings in the plating mask made of photoresist 608. Figures 6G and 6H are cross-sectional views of the glass plate 204 in a manufacturing stage 612 after performing the photoresist removal and nucleation layer etching processes to expose conductive traces 628 and conductive features 630 according to some embodiments. Figures 6G and 6H illustrate a glass core structure 614 comprising the conductive traces 628, which have a section within a trench, the conductive features 630, and the conductive features 630. The photoresist 608 and the exposed sections of the nucleation layer 604 can be removed using any suitable process known in the field. The conductive traces 628 comprise a first section 636 within the trench 212 and a second section 634 above the surface of the glass 204, e.g., B. the surface 206, 208. The conductor tracks 628 and the conductive features 630 have upper surfaces 631 and side walls 632 extending over the surface 206.The second sections 634 comprise the sidewalls 632. The sidewalls 632 have a profile that is substantially vertical or inclined at less than 10° to the vertical, indicating a semi-additive structuring process. The conductor tracks 228 comprise a top corner C3 between the top surface 631 and a sidewall 632. In some examples, the top corner C3 may be rounded (not illustrated in Fig. 6H), indicating a semi-additive structuring process. Similar to the conductor tracks 228, the conductor tracks 628 may extend laterally over a length greater than the width of the conductor track. Cross-sections of TGVs 629 are shown in Fig. 6G. As illustrated in Fig. 6H, a conductor track 628 can have a height H2 (e.g., z-height) above the first surface 206 (or the second surface 208) of 5 to 75 micrometers. A conductor track 628 can extend to a depth D2 (e.g., z-height) below the first surface 206. The depth D2 can be between 5 micrometers and 40–50 percent of the glass thickness T1. In some examples, the conductor tracks 628 can extend over a depth D2 between 0.05 mm and 1.5 mm. The conductor track can have a width W3. When two conductor tracks 628 are adjacent to each other, a minimum spacing S2 between the conductor tracks is required. The same minimum spacing S2 required between adjacent conductor tracks 628 can also apply to conventional conductor tracks.An advantage of the embodiments described herein is that, due to the additional depth within the glass plate, adjacent conductor tracks 628 of a specific width W3 can be thicker than adjacent conventional conductor tracks of the same width W3. Accordingly, the conductor tracks 628 can provide a lower electrical resistance than conventional conductor tracks. A lower electrical resistance is particularly advantageous for conductor tracks 628 carrying power signals. In embodiments using a semi-additive process, the minimum spacing S2 between adjacent conductor tracks 628 can be 0.25–0.50 times the height H2. Accordingly, in some examples, the height H2 is in the range of 15–25 micrometers, and S2 is in the range of 3.50–13 micrometers. A redistribution structure can be formed over one or both of the surfaces 206, 208 of the glass core structure 614 to form a package substrate or an interposer in a manner similar to that described with reference to Fig. 4 and the package substrate 402. According to some embodiments, a package substrate comprising a glass core structure 614 can be contained within an IC device package, such as the IC device package 502, as described with reference to Fig. 5. Similarly, according to some embodiments, an IC device package can comprise one or more IC dies and a host component attached to a package substrate comprising a glass core structure 614 that includes redistribution structures. In some embodiments, an IC device package can comprise one or more IC dies attached to an interposer that comprises a glass core structure 614 that includes redistribution structures. Fig. 7 illustrates a mobile computing platform and a data server machine employing one or more devices comprising an IC device package 750 (or an interposer) with a substrate having a glass core, the glass core having a conductor with a portion within a trench in the glass and a portion above the surface of the glass, as described, for example, elsewhere herein. A server machine 706, for example, can be any commercial server, including any number of high-performance computing platforms arranged within a rack and networked together for electronic data processing. The mobile computing platform 705 can be any portable device configured for electronic data display, electronic data processing, wireless transmission of electronic data, or the like.For example, the mobile computing platform 705 can be a tablet, a smartphone, a laptop, etc., and can include a display screen (for example, a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system 710, and a battery 715. Whether arranged within the integrated system 710 illustrated in extended view 720 or as a standalone enclosure within the server machine 706, the IC device enclosure 750 (or an interposer) with a substrate has a glass core, the glass core having a conductor with a portion within a trench in the glass and a portion above the surface of the glass, as described elsewhere herein. The IC device enclosure 750 can further be combined with one or more integrated power management circuits (PMICs) 730, (wireless) integrated RF circuits (RFICs) 725 with a wireless broadband RF transmitter and / or receiver (TX / RX) (e.g.,with a digital baseband and an analog front-end module, which further includes a power amplifier on a transmit path and a low-noise amplifier on a receive path) and a controller 735 coupled to a host substrate 760. The PMIC 730 can perform battery power regulation, DC-DC conversion, etc., and thus has an input coupled to the battery 715 and an output that provides power to other functional modules. As further illustrated, the RFIC 725 in the exemplary embodiment has an output coupled to an antenna (not shown) to implement any number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.11, and others.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth and their derivatives, as well as all other wireless protocols referred to as 3G, 4G, 4G and beyond. Fig. 8 is a functional block diagram of an electronic computing device 800 according to an embodiment of the present invention. The computing device may be located within the mobile computing platform 705 or the server machine 706, as described elsewhere herein. The device 800 further comprises a housing substrate 802 which accommodates a number of components, such as, among others, a processor 804 (e.g., an application processor). The processor 804 may be physically and / or electrically coupled to the housing substrate 802. In general, the term "processor" or "microprocessor" may refer to any device or any section of a device that processes electronic data from registers and / or a memory in order to transform such electronic data into other electronic data, which may further be stored in registers and / or a memory.In some embodiments, the housing substrate 802 can be an IC device housing comprising a substrate with a glass core, wherein the glass core has a conductive trace with a portion within a trench in the glass and a portion above the surface of the glass, as described elsewhere herein. In some examples, one or more of the components of the computing device 800 comprise an interposer comprising a substrate with a glass core, wherein the glass core has a conductive trace with a portion within a trench in the glass and a portion above the surface of the glass, as described elsewhere herein. In various examples, one or more 806 communication chips may also be physically and / or electrically coupled to the 802 package substrate. In other implementations, the 806 communication chips may be part of the 804 processor. Depending on its applications, the 800 computing device may include other components that may not be physically and electrically coupled to the 802 package substrate.These other components include, among others, volatile memory (for example, DRAM 832), non-volatile memory (for example, ROM 835), flash memory (for example, NAND or NOR), magnetic memory (MRAM 830), graphics processor 822, digital signal processor, cryptoprocessor, chipset 812, antenna 825, touchscreen display 815, touchscreen control 865, battery 816, audio codec, video codec, power amplifier 821, global positioning system (GPS) device 840, compass 845, accelerometer, gyroscope, loudspeaker 820, camera 841, and a mass storage device (such as a hard disk drive, a solid-state drive (SSD), a compact disk (CD), a digital versatile disk (DVD), and so on) or the like. The 806 communication chips enable wireless communication for the transmission of data to and from the 800 computing device. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through a non-solid medium by using modulated electromagnetic radiation. The term does not imply that the associated devices contain no wires whatsoever, although in some embodiments they may not. The 806 communication chip can implement any of a number of wireless or optical standards or protocols. As discussed, the 800 computing device can incorporate multiple 806 communication chips.For example, a first communication chip can be dedicated to shorter-range wireless communication, such as WiFi and Bluetooth, and a second communication chip can be dedicated to longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and others. Although certain features set forth herein have been described with reference to various implementations, this description should not be interpreted in a restrictive sense. Thus, various modifications of the implementations described herein, and other implementations that are apparent to a person skilled in the art in the field to which this disclosure belongs, are considered to be inherent in the nature and scope of protection of this disclosure. It is understood that the invention is not limited to the embodiments described above, but can also be implemented with modifications and variations without deviating from the scope of the appended claims. For example, the above embodiments can have specific combinations of features, as detailed below. Example 1: Device comprising: a glass plate comprising a surface, a trench in the surface and a routing structure above the surface; and a conductor comprising a first section within the trench and a second section above the surface, the conductor extending laterally over a length, the length being greater than a width of the conductor. Example 2: Setup according to Example 1, wherein the first section extends a depth below the surface, the second section extends a height above the surface, and the depth is at least twenty percent of the height. Example 3: Setup according to Example 1 or 2, wherein the second section includes a side wall with a concave profile. Example 4: Setup according to Example 1 or 2, wherein the second section includes a side wall with a planar profile. Example 5: Setup according to one of Examples 1 to 3, wherein the conductor track includes a third section above the surface and extending laterally away from the trench. Example 6: Setup according to one of Examples 1 to 3 or 5, wherein the routing structure comprises a first side near the surface, a second side opposite the first side, and a metallization feature that couples the conductor track to an intermediate connection feature on the second side. Example 7: Setup according to Example 6, wherein the surface is a first surface, the trench is a first trench, the conductor track is a first conductor track, the length is a first length, and the width is a first width, wherein the glass plate further comprises: a second surface opposite the first surface, the second surface comprising a second trench; and a second conductor track extending laterally over a second length within the second trench, the second conductor track comprising a second width, the second conductor track comprising a third section within the second trench and a fourth section above the second surface, and the second length being greater than the second width. Example 8: Setup according to Example 7, wherein the routing structure is a first routing structure, the metallization feature is a first metallization feature, and the interconnect feature is a first interconnect feature, further comprising: a second routing structure over the second surface, wherein the second routing structure comprises a third side near the second surface, a fourth side opposite the third side, and a second metallization feature coupling the second conductor track to a second interconnect feature on the fourth side. Example 9: Setup according to Example 8, wherein the glass plate further comprises a through-glass via extending between the first conductor track and the second conductor track. Example 10: Setup from Example 8, further comprising an integrated circuit die (IC die) coupled to the first interconnect feature. Example 11: Device comprising: a glass plate comprising a first surface, a second surface opposite the first surface and a trench in the first surface; a conductor comprising a first section within the trench and a second section above the first surface, the conductor extending laterally over a length between a first and a second position on the first surface, the second position being spaced apart from the first position; and a through-glass via (TGV) extending between the first and second surfaces, the TGV being coupled to the conductor at the first position. Example 12: Setup according to Example 11, further comprising: a first routing structure over the first surface, wherein the first routing structure comprises a first side near the first surface, a second side opposite the first side, and a first metallization feature that couples the conductor at the second position to a first intermediate connection feature on the second side; and a second routing structure over the second surface, wherein the second routing structure comprises a third side near the second surface, a fourth side opposite the third side, and a second metallization feature that couples the TGV to a second intermediate connection feature on the fourth side. Example 13: Setup according to Example 12, further comprising an integrated circuit die (IC die) coupled to the first interconnect feature and a host component coupled to the second interconnect feature. Example 14: Establishment according to Example 12, further comprising a service provision that is coupled with the second intermediate connection feature. Example 15: Setup according to Example 11 or 12, wherein the first section extends a depth below the first surface, the second section extends a height above the first surface, and the depth is at least ten percent of the height. Example 16: Setup according to Example 11, 12 or 15, wherein the conductor track includes a third surface away from the first surface, a side wall and a corner where the third surface and the side wall meet, the side wall comprising a profile with an overhang at the corner. Example 17: Setup according to Example 11 or 12, wherein the first section includes a first width on the first surface; the second section includes a second width on the first surface; and the second width is greater or less than the first width. Example 18: Method comprising: forming a trench on a first surface of a glass plate; forming a conductive track, wherein the forming of the conductive track comprises depositing a conductive material onto the first surface and onto second surfaces within the trench; and forming a first routing structure over the first surface. Example 19: The method of claim 18, wherein the formation of the conductive track further comprises: applying a mask comprising a photoresist material over the conductive material; and etching sections of the conductive material within openings in the mask. Example 20: The method of claim 18, wherein the formation of the conductive track further comprises: applying a seed layer to the first surface and the second surfaces; applying a mask comprising a photoresist material over the seed layer; and wherein the deposition of the conductive material further comprises electroplating the conductive material at positions defined by openings in the mask.

Claims

Device comprising: a glass plate comprising a surface, a trench in the surface and a routing structure above the surface; and a conductor comprising a first section within the trench and a second section above the surface, the conductor extending laterally over a length, the length being greater than a width of the conductor. Device according to claim 1, wherein the first section extends a depth below the surface, the second section extends a height above the surface, and the depth is at least twenty percent of the height. Device according to claim 1 or 2, wherein the second section comprises a side wall with a concave profile. Device according to claim 1 or 2, wherein the second section comprises a side wall with a planar profile. Device according to one of claims 1 to 3, wherein the conductor track comprises a third section above the surface and extending laterally away from the trench. Device according to one of claims 1 to 3 or 5, wherein the routing structure comprises a first side near the surface, a second side opposite the first side and a metallization feature that couples the conductor track to an intermediate connection feature on the second side. The device according to claim 6, wherein the surface is a first surface, the trench is a first trench, the conductor track is a first conductor track, the length is a first length, and the width is a first width, wherein the glass plate further comprises: a second surface opposite the first surface, wherein the second surface comprises a second trench; and a second conductor track extending laterally over a second length within the second trench, wherein the second conductor track comprises a second width, wherein the second conductor track comprises a third section within the second trench and a fourth section above the second surface, and the second length is greater than the second width. Device according to claim 7, wherein the routing structure is a first routing structure, the metallization feature is a first metallization feature and the intermediate connection feature is a first intermediate connection feature, further comprising: a second routing structure over the second surface, wherein the second routing structure comprises a third side near the second surface, a fourth side opposite the third side and a second metallization feature that couples the second conductor track to a second intermediate connection feature on the fourth side. Device according to claim 8, wherein the glass plate further comprises a through-glass via extending between the first conductor track and the second conductor track. Device according to claim 8, further comprising an integrated circuit die (IC die) coupled to the first interconnect feature. Device according to one of claims 1 or 3 to 10, wherein the first section extends a depth below the surface and the depth below the surface is in a range of 0.5 to 1.5 millimeters; and the second section extends a height above the surface and the height above the surface is in a range of 5 to 75 micrometers. Device according to one of claims 1 or 3 to 10, wherein the first section extends a depth below the surface and the depth below the surface is in a range of 5 micrometers to 50% of the thickness of the glass plate; and the second section extends a height above the surface, and the height above the surface is in a range of 5 to 75 micrometers. Device according to one of claims 1 or 2 or 4 to 12, wherein the second section comprises a side wall comprising: a first corner near the surface and a second corner away from the surface, wherein: a first section of the side wall near the first corner is substantially perpendicular to the surface; and a second section of the side wall near the second corner overhangs the surface. A device comprising: a glass plate comprising a first surface, a second surface opposite the first surface, and a trench in the first surface; a conductor comprising a first section within the trench and a second section above the first surface, the conductor extending laterally over a length between a first and a second position on the first surface, the second position being spaced apart from the first position; and a through-glass via (TGV) extending between the first and second surfaces, the TGV being coupled to the conductor at the first position. The device according to claim 14, further comprising: a first routing structure over the first surface, wherein the first routing structure comprises a first side near the first surface, a second side opposite the first side, and a first metallization feature that couples the conductor track at the second position to a first intermediate connection feature on the second side; and a second routing structure over the second surface, wherein the second routing structure comprises a third side near the second surface, a fourth side opposite the third side, and a second metallization feature that couples the TGV to a second intermediate connection feature on the fourth side. The device according to claim 15, further comprising an integrated circuit die (IC die) coupled to the first interconnect feature and a host component coupled to the second interconnect feature. Device according to claim 15, further comprising a power supply coupled to the second intermediate connection feature. Device according to claim 14 or 15, wherein the first section extends a depth below the first surface, the second section extends a height above the first surface, and the depth is at least ten percent of the height. Device according to one of claims 14, 15 or 18, wherein the conductor track comprises a third surface located away from the first surface, a side wall and a corner where the third surface and the side wall meet, wherein the side wall comprises a profile with an overhang at the corner. Device according to claim 14 or 15, wherein the first section comprises a first width on the first surface; the second section comprises a second width on the first surface; and the second width is greater than the first width;

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