Hybrid address mapping

Abstract

Computer program product (700) for implementing a hybrid address translation, wherein the computer program product comprises: a physically tangible non-volatile storage medium (702) that is readable by a processing circuit and stores instructions (704) for execution by the processing circuit to carry out a procedure comprising: Receiving a first address, wherein the first address has an effective address that refers to a memory location in a first address space in a computer system having a first and a second page table, wherein the first page table has a Hashed Page Table (HPT) (107) and the second page table has a Radix Tree (108); Searching a segment conversion buffer (SLB) (105) for an SLB entry (110) corresponding to the first address; wherein the SLB has a plurality of SLB entries, each having a corresponding type field (111B) and a corresponding address field (111A), wherein the plurality of SLB entries has a first and a second entry, wherein the first entry has a first type field corresponding to a search in the first page table, and the second entry has a second type field corresponding to a search in the second table; Determine whether a value of the type field in the SLB entry corresponding to the first address matches a search in the first or second page table; Searching the first or second page table to determine an address mapping for the first address based on the type field in the SLB entry that corresponds to the first address, by: Based on the finding that the value of the type field corresponds to the search in the first page table, searching the first page table to determine a second address, where the second address is a mapping of the first address into a second address space; and Based on the finding that the value of the type field matches the search in the second page table, search the second page table to find the second address.

Description

BACKGROUND

[0001] The present invention relates generally to data processing systems and, more particularly, to computer addressing methods.

[0002] In today's computer systems, system memory is managed by the operating system and allocated to various software applications as needed. The various software applications can run in one or more partitions, and the one or more partitions can run different operating systems (OSs). Virtual memory techniques can be used in such a computer system to divide the physical memory of the computing system among many processes and applications. The software applications therefore deal with effective addresses in a virtual memory space, which allows the applications to read, write, and execute as needed without having to deal with the actual physical memory locations where the operations take place.Applications rely on the operating system on which each application sits to map the effective address used by the application to a physical address in computer memory. Address translation is the mechanism by which effective addresses pointing to virtual memory are translated into real memory addresses. Address translation is a complex process that, if not performed well, can end up on the critical path that determines the processor's clock cycle.

[0003] When the CPU requests an effective address, the system first checks an effective-to-real address translation (ERAT) cache to determine a real address that corresponds to the effective address. If the effective address is not located in the ERAT cache, various other caches, including a segment lookaside buffer (SLB) and a translation lookaside buffer (TLB), may be checked to determine the real address that corresponds to the effective address. The ERAT cache, SLB, and TLB store data related to translations for recently used effective addresses, and they are searched to provide information necessary for the address translation process.However, if the effective address is not located in any of these caches, an additional page table lookup must be performed to determine the correct translation of the effective address.

[0004] The document US 2010 / 0 030 997 A1 relates to a method for managing a virtual memory system configured to allow multiple page sizes. Each page size has at least one table associated with it. The method involves maintaining entries in the tables to track the page size for which the effective address is mapped. When a new effective address-to-physical address mapping needs to be made for a page size, the method accesses the corresponding tables to determine previous mappings for a different page size in the same segment. If no such conflicting mapping exists, a new mapping is created in the corresponding table. A formula is used to create an index for accessing a mapping in a table.US Pat. No. 5,946,679 A relates to a method that searches for table information using keys of different lengths. Based on criteria, the method selects one of three processes to perform the search. The first routine is a reverse hash search routine, useful for searching for information with few key lengths. The second process is a hierarchical search routine, suitable for searching for information with many key lengths. The third process is a compressed radix tree search, suitable for searching for information that presents significant time constraints for the first two routines.

[0005] The document US 2009 / 0 094 430 A1 relates to a method comprising: receiving a request for a memory address in a memory device from a requesting process; granting a lock for the requested memory address to the requesting process; providing exclusive access to a page containing the requested memory address to the requesting process for a page access time period; and releasing exclusive access to the page provided to the requesting process in response to an expiration of the page access time period. SUMMARY OF THE INVENTION

[0006] The invention relates to a computer program product, a system, and a method for hybrid address translation, the features of which are specified in the corresponding claims. Embodiments are specified in the dependent claims. One aspect includes receiving a first address, the first address pointing to a memory location in a first address space. The computer searches a segment translation buffer (SLB) for an SLB entry corresponding to the first address; the SLB entry has a type field and an address field, and determines whether a value of the type field in the SLB entry indicates a hashed page table (HPT) lookup or a radix tree lookup.Based on the determination that the value of the type field indicates HPT search, an HPT is searched to determine a second address, the second address comprising a translation of the first address to a second address space; and based on the determination that the value of the type field indicates radix tree search, a radix tree is searched to determine the second address.

[0007] Additional features and advantages are realized by the methods of the present invention. Further embodiments and aspects of the invention are described in detail herein and are considered part of the claimed invention. For a better understanding of the invention, including its advantages and features, reference is made to the description and drawings. BRIEF DESCRIPTION OF THE VARIOUS VIEWS OF THE DRAWINGS

[0008] The subject matter considered as the invention is particularly pointed out and distinctly claimed in the claims at the end of the specification. The foregoing and other features and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, in which: the Fig. 1A to 1B show a system for hybrid address translation according to one embodiment; Fig. 2 shows a process flow of a method for hybrid address translation according to an embodiment; the Fig. 3 to 5 show a process flow of a method for searching a radix tree according to one embodiment; Fig. 6 shows a process flow of a method for searching a hashed page table according to one embodiment; and Fig. 7 illustrates a computer program product according to an embodiment. DETAILED DESCRIPTION

[0009] Embodiments of systems and methods for hybrid address translation are provided, with example embodiments discussed in detail below. Hybrid address translation enables different types of page tables, particularly a hashed page table (HPT) and a radix tree, to be used in a single data processing system to achieve a translation of a first address to a second address. The type of page table used for a particular address translation is based on the type of request and / or the operating system (OS) running the application that issued the address to be translated. HPT is preferred for a few random accesses over relatively large data sets, while a radix tree is preferred for accesses with a high degree of spatial locality.Therefore, for example, data-side accesses in a memory-intensive application such as the DB2 database can be directed to a HPT, while statement-side accesses can use a radix tree. Thanks to the hybrid address translation scheme, the performance of different software applications running on a single data processing system can be increased by using the type of address translation appropriate for each type of software application or each type of memory access. Furthermore, address translation can also be performed across multiple non-contiguous memory areas, and when searching a radix tree, multiple roots of the radix tree can be used if necessary, reducing the time required to perform a translation using a radix tree.

[0010] To determine the type of page table lookup to use for a particular address translation, the SLB entries for each address contain a type field that specifies whether an HPT lookup or a radix tree lookup should be used for that address. The type field is a single bit and can be placed in any suitable location within an SLB entry. Any suitable type value can be used to specify a radix tree or HPT lookup. In the discussion below, a type value of 0 specifies an HPT lookup and a type value of 1 specifies a radix tree lookup; however, this is for illustrative purposes only.

[0011] The SLB entries may also contain radix tree pointers, which are used to specify the root of a radix tree search. The virtual space identifier (VSID) of the SLB can be repurposed as a pointer to the root of a radix tree search. A radix tree pointer may contain an address space identifier (address space ID) that specifies a block of entries in the radix tree to search for the address. The size of the block of entries determines the number of levels of the radix tree to search; a larger block of entries is located higher up in the radix tree. Valid leaf entries in the radix tree specify a page size corresponding to the level in the tree. The address space ID associated with an address can be stored in the SLB entry using any mechanism that expands an effective address beyond its natural size.Depending on the software requirements, such an address extension may be as few as zero bits. The address space ID may include a process identifier (PID), which may be an external PID associated with the address in some embodiments. Since an effective address of a radix tree is defined as a 48-bit address, effective addresses whose first 16 bits are set to a value other than zero can be considered an implicit identifier of an address space. Using the address space ID in the SLB entry to specify a root of the search in a radix tree enables searches across multiple non-contiguous memory regions without providing a radix tree that covers the entire address space.Tree traversals can be shorter (e.g., less than 4 steps) than a fully specified radix tree, which uses pointers to the root of the page table when multiple high-order bits of the effective address match. For example, software can explicitly specify more bits for frequently encountered implementations, or hardware can maintain a certain number of SLB entries as a page-walk cache, which uses a greedy algorithm to select the SLB containing the largest number of matching high-order bits. To reduce the number of levels traversed, the smallest segment size corresponding to the SLB entry is used to initiate a radix tree traversal. The address space ID can also prevent unnecessary flushes of the TLB contents, for example, by assigning different contexts to different address space IDs.

[0012] A hybrid address translation as described below with reference to the Fig. 1A to 1B and 2 to 6 can be used for any type of address translation in a data processing system, for example, input / output, partition level, or partition level to physical level. While the Fig. 1A to 1B and 2 to 6 are discussed below with reference to the translation of an effective address into a real address indicating a physical location in a computer memory, the Fig. 2 to 6 may be used in various embodiments for any address translation level to translate any type of first address in a first address space into any type of second address in a second address space.

[0013] Fig. 1A shows an exemplary data processing system 100A including a hybrid address translation and Fig. 1B shows an embodiment of a system 100B for hybrid address translation including an SLB entry, an HPT, and a radix tree that can be implemented in a data processing system such as data processing system 100A. Fig. Data processing system 100A shown in Figure 1A includes a processor 101 and a main memory 109. Address translation logic 103, an ERAT cache 104, an SLB 105, and a TLB 106 are stored in the processor 101. A plurality of software applications 102A through 102N, an HPT 107, and a radix tree 108 are stored in the main memory 109. Each of the software applications 102A through 102N accesses specific memory locations in the main memory 109 via the address translation logic 103. Effective addresses are output by the software applications 102A through 102N, and the address translation logic 103 converts the effective address into a real address that can be used to access memory locations in the main memory 109. The address translation logic 103 searches various caches, including the ERAT cache 104, the SLB 105, and the TLB 106, in addition to the HPT 107 and the radix tree 108, to perform address translations.ERAT cache 104 may, in some embodiments, comprise content addressable memory (CAM). SLB 105 contains a plurality of SLB entries, each corresponding to an effective address. TLB 106 stores a plurality of real address translations corresponding to virtual addresses.

[0014] Let us now turn Fig. 1B, which shows an exemplary SLB entry 110 that includes an address field 111A and a type field 111B. The SLB entry 110 may be located in the SLB 105 of Fig. 1A. The type field 111B indicates whether the effective address stored in address field 111A in the SLB entry 110 should be searched for in the HPT 107 (e.g., type = 0) or in the radix tree 108 (e.g., type = 1), and it can be based on the type of application or the type of memory access that issued the effective address. For an SLB entry where the type field 111B has the value "0," indicating a search in the HPT 107, the address field 111A contains a virtual address corresponding to the matching effective address; the virtual address is searched for in the TLB 106 and in the HPT 107. For an SLB entry where the type field 111B has the value "1", indicating a lookup in the radix tree 108, the address field 111A contains an effective address and information about the ID of the address space to be looked up in the TLB 106 and the radix tree 108.In various embodiments, the address space ID in address field 111A may include a PID, and it may be an external PID. The radix tree 108 includes various levels, each of which specifies differently sized memory segments in the data processing system. The top-level 256-terabyte (TB) segment 112 has various 512-gigabyte (GB) sub-segments 113A through 113N; the 512-GB sub-segment 113A has various 1-GB sub-segments 114A through 114N; and the 1-GB sub-segment 114A has the 2-megabyte (MB) sub-segment 115. The effective address and address space ID information in address field 111A for a type 1 SLB entry are used to determine a level at which to begin searching the radix tree 108.Segments 112, 113A to 113N, 114A to 114N, and 115A are shown for illustrative purposes only; a radix tree such as radix tree 108 may have any suitable number, size, and structure of segments and sub-segments.

[0015] Fig. 2 shows a process flow of a method 200 for hybrid address translation according to one embodiment. Fig. 2 is made with reference to the Fig. 1A to 1B and may be implemented in address translation logic 103. In block 210, the ERAT cache 104 is first searched for an effective address to be translated, which was issued by one of the applications 102A to 102N. In block 202, it is then determined whether the effective address was found in the ERAT cache 104. If the effective address is in the ERAT cache 104, the translation from the ERAT cache 104 is used to access the main memory 109 in block 203, and the flow of method 200 ends. However, if the effective address is not in the ERAT cache 104, the SLB 105 is searched for the address in block 204, and in block 205, it is determined whether an SLB entry for the effective address exists in the SLB 105.If an SLB entry 110 for the effective address is found in the SLB 105, it is then determined whether the type field 111B corresponding to that effective address specifies a radix tree search or an HPT search. If the type field 111B specifies a radix tree search, flow proceeds from block 205 to block 206, and the TLB 106 and the radix tree 108 are searched for the effective address and the address space ID corresponding to the effective address specified by the address field 111A; this is determined with reference to the . Fig. 3 to 5. If the effective address type field 111B specifies an HPT search, the flow switches from block 205 to block 207 and the TLB 106 and the HPT 107 are searched for the virtual address corresponding to the effective address specified by the address field 111A; this will be explained with reference to Fig. 6. If it is determined in block 205 that no SLB entry for the effective address exists in the SLB 105, an SLB miss error is output in block 208, and the flow of method 200 ends.

[0016] Fig. 3 shows a process flow of a method 300 for a radix tree search according to one embodiment. The method 300 is executed by the address translation logic 103 during block 206 of the method 200 of Fig. 2 is performed if the type field in type field 111B in SLB entry 110 corresponding to the effective address specifies a radix tree lookup. In block 301, the address space ID for the effective address is first extracted from address field 111A in SLB entry 110. Then, in block 302, TLB 106 is searched for the effective address and the address space ID corresponding to the effective address. It is then determined in block 303 whether the effective address and the address space ID are located in TLB 106. If the effective address and the address space IB are located in TLB 106, the real address translation specified for the effective address in TLB 106 is inserted into ERAT cache 104 and used in block 304 to access main memory 109.However, if it is determined in block 303 that the effective address and address space ID are not in the TLB, flow proceeds to block 305 where the radix tree 108 is searched for the effective address, and the address space ID is used to determine a root of the radix tree search.

[0017] The search of the radix tree 108, which takes place in block 306 of the method 300, is performed with reference to Fig. 4, which is performed by the address translation logic 103 and shows a process flow of a method 400 for a radix tree search for an effective address using an address space ID as a root of the search according to one embodiment. First, in block 401, a size of the block of entries corresponding to the address space ID is determined. The size of the block of entries, also referred to as the segment size, which is specified by the address space ID, indicates the level at which the search in the radix tree 108 should begin. A larger segment size indicates a higher level and a radix tree search having a larger number of steps, while a smaller segment size indicates a lower level and a radix tree search having a smaller number of steps. As in Fig. 4, a segment size of 256 TB indicates a 4-level radix tree search in block 402A; a segment size of 512 GB indicates a 3-level radix tree search in block 402B; a segment size of 1 GB indicates a 2-level radix tree search in block 402B; and a segment size of 2 MB indicates a 1-level radix tree search in block 402D; the segment sizes and the number of levels used in Fig. 4 are for illustrative purposes only and may differ from one another based on the structure of the radix tree being searched.

[0018] The radix tree 108 is searched for the effective address, starting at the level indicated by the determined segment size in blocks 402A to 402D; this is done with reference to Fig. 5 is discussed in more detail. Fig. 5 shows a process flow of a method 500 for a radix tree search according to one embodiment. The radix tree search illustrated by the method 500 may be performed at any of blocks 501, 504, 507, or 510 depending on the segment size determined in block 401 of Fig. 4. A 4-level search in the radix tree, as determined by block 402A of Fig. 4, begins at block 501; this corresponds to a start of the search at the level of segment 112 of the radix tree 108 of Fig. 1B. A 3-level search in the radix tree, as described by block 402B of Fig. 4, begins at block 504; this corresponds to a start of the search at the level of segments 113A to 113N of the radix tree 108 of Fig. 1B. A 2-level search in the radix tree, as described by block 402C of Fig. 4, begins at block 507; this corresponds to a start of the search at the level of segments 114A to 114N of the radix tree 108 of Fig. 1B. A 1-level search in the radix tree, as described by block 402D of Fig. 4, begins at block 510; this corresponds to a start of the search at the level of segment 115 of the radix tree 108 of Fig. 1B. Starting the search at the lowest level in the radix tree, which is specified by the segment size corresponding to the address space ID of the effective address, may reduce the number of steps required to search the radix tree, thus speeding up the translation of the effective address.

[0019] The procedure 500 of Fig. 5 will now be discussed. First, in block 501, the fourth (highest) level of the radix tree 108 is searched for the effective address to find a smaller corresponding segment in the third level of the radix tree 108. In block 502, it is then determined whether an SLB entry for the smaller corresponding segment in the third level of the radix tree 108 for the effective address exists in the SLB 105. If the SLB entry for the smaller corresponding segment in the third level exists in the SLB, flow proceeds to block 504; otherwise, in block 503, an SLB entry for the smaller corresponding segment in the third level is added to the SLB, and flow proceeds to block 504. In block 504, the smaller corresponding segment in the third level determined in block 501 is searched for the effective address to find a smaller corresponding segment in the second level.In block 505, it is then determined whether an SLB entry for the smaller corresponding segment in the second level exists in the SLB 105. If the SLB entry for the smaller corresponding segment in the second level exists in the SLB 105, the flow proceeds to block 507; otherwise, in block 506, an SLB entry for the smaller corresponding segment is added to the SLB 105 and the flow proceeds to block 507. In block 507, the smaller corresponding segment in the second level of the radix tree 108, which was determined in block 504, is searched for the effective address to find a smaller corresponding segment in the first level of the radix tree. In block 508, it is then determined whether an SLB entry for the smaller corresponding segment in the first level exists in the SLB 105.If the SLB entry for the smaller corresponding first-level segment is present in the SLB 105, flow proceeds to block 510; otherwise, in block 509, an SLB entry for the smaller corresponding first-level segment is added to the SLB 105 and flow proceeds to block 510. In block 510, the smaller corresponding first-level segment determined in block 507 is searched for the effective address using the search of the radix tree 108 performed by the method 500 of FIG. Fig. 5 is completed at this point, and the flow returns to block 403 of the method 400 of Fig. 4 back.

[0020] Referring again to Fig. 4, the process switches to block 403, in which it is determined whether during the search, which is carried out in the course of the method 500 from Fig. 5 was performed, there was a hit in the radix tree 108. If it is determined in block 403 that there was a hit in the radix tree 108 with respect to the effective address, the flow switches to block 404, and the translation specified for the effective address by the radix tree 108 is inserted into the TLB 106 and the ERAT cache 104 and used in block 404 to access the main memory 109, and the flow of the method 400 ends. If it is determined in block 403 that there is no hit in the radix tree, a radix tree miss error is indicated in block 405, and the flow of the method 400 ends. The radix tree search applied to the effective addresses having a type field 111B indicating a radix tree search is thus completed.

[0021] Fig. 6 shows a process flow of a method 600 for searching an HPT according to one embodiment. The method 600 is executed by the address translation logic 103 during block 207 of the method 200 of Fig. 2 is performed if the type field 111B in the SLB entry 110 specifies an HPT search. In block 601, a virtual address corresponding to the effective address is first extracted from the address field 111A of the SLB entry 110, which corresponds to the effective address in the SLB 105. In block 602, the TLB 106 is then searched for the virtual address. It is then determined in block 603 whether the virtual address was found in the TLB 106. If the virtual address was found in the TLB 106, the translation specified by the TLB 106 for the virtual address is inserted into the ERAT cache 104 and used to access main memory in block 604, and the flow of the method 600 ends. If the virtual address is not in the TLB, flow proceeds to block 605, where the HPT 107 is searched for the virtual address. The HPT 107 may be searched using any suitable method.Then, in block 606, it is determined whether the virtual address was found in the HPT 107. If the virtual address was found in the HPT 107, the translation specified by the HPT 107 for the virtual address is input to the TLB 106 and the ERAT cache 104 and used to access the main memory 109 in block 607, and the flow of the method 600 ends. Otherwise, an error due to a miss in the HPT is output in block 608, and the flow of the method 600 ends.

[0022] As described above, embodiments may be realized in the form of processes executed by a computer and devices for practicing these processes. One embodiment may include a computer program product 700 embodied in Fig.7, on a computer-readable / usable medium 702, wherein computer program code logic 704 includes instructions embodied in tangible media as an article of manufacture. Example articles of manufacture for the computer-readable / usable medium 702 may include floppy disks, CD-ROMs, hard disk drives, Universal Serial Bus (USB) flash drives, or any other computer-readable storage medium, wherein, when the computer program code logic 704 is loaded into and executed by a computer, the computer becomes an apparatus with which the invention may be practiced.Embodiments include, for example, computer program code logic 704, whether stored in a storage medium that is loaded into and / or executed by a computer, or transmitted over a particular transmission medium such as electrical wiring or cabling, fiber optics, or electromagnetic radiation, wherein, when the computer program code logic 704 is loaded into and executed by a computer, the computer becomes a device with which the invention can be practiced. When implemented on a general-purpose microprocessor, segments of the computer program code logic 704 configure the microprocessor to generate particular logic circuits.

[0023] Technical effects and advantages include improved performance for different types of memory accesses and / or applications running on a data processing system by using different address translation lookup schemes where necessary.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not limiting of the invention. The singular forms "a," "an," and "the," "which," as used herein, are intended to include the plural forms, unless the context clearly indicates otherwise. Further, it is to be understood that the terms "comprises" and / or "comprising," when used in this specification, refer to the presence of specified features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0025] The corresponding structures, materials, acts, and equivalents of all means or steps plus functional elements in the following claims are intended to include any structure, material, or act for performing the function in combination with other claimed elements specifically claimed. The description of the present invention has been presented for the purpose of illustration and explanation, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention.The embodiment was chosen and described in order to best explain the principles of the invention and its practical application, and to enable others skilled in the art to understand the invention in terms of various embodiments with various modifications as are suited to the particular use contemplated.

[0026] As will be understood by those skilled in the art, aspects of the present invention may be embodied as a system, a method, or a computer program product. Accordingly, aspects of the present invention may take the form of an embodiment implemented entirely in hardware, an embodiment implemented entirely in software (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, all of which may be generally referred to herein as a "circuit," a "module," or a "system." Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer-readable mediums having computer-readable program code embodied thereon.

[0027] Any combination of one or more computer-readable media may be used. The computer-readable media may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or unit, or any suitable combination of the foregoing.More specific examples (but not limited to) of the computer-readable storage medium would include: an electrical connection with one or more cables, a portable computer diskette, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.For the purposes of this document, a computer-readable storage medium may be any tangible medium that can contain or store a program for use by, or in connection with, an instruction execution system, apparatus, or device.

[0028] A computer-readable signal carrier may contain a propagated data signal having computer-readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination of these forms. A computer-readable signal carrier may be any computer-readable medium other than a computer-readable storage medium that is capable of carrying, relaying, or transmitting a program for use by, or in connection with, an instruction execution system, apparatus, or device.

[0029] Program code embodied on a computer-readable medium may be transmitted via any suitable medium, including, but not limited to, wireless, wired, fiber optic cable, radio frequency (RF), etc., or any suitable combination of the foregoing.

[0030] Computer program code for performing operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object-oriented programming language such as Java, Smalltalk, C++, or the like, as well as conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server.In the latter scenario, the remote computer may be connected to the user's computer over any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, over the Internet using an Internet service provider).

[0031] Aspects of the present invention are described above with reference to flowchart and / or schematic representations of methods, devices (systems), and computer program products according to embodiments of the invention. It is understood that each block of the flowchart and / or block diagram representations, as well as combinations of blocks in the flowchart and / or block diagram representations, may be implemented by computer program instructions.These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that the instructions, executing via the processor of the computer or other programmable data processing apparatus, produce a means for performing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0032] These computer program instructions may also be stored on a computer-readable medium that can instruct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored on the computer-readable medium produce an article of manufacture that includes instructions that perform the function / act specified in the block or blocks of flowchart and / or block diagrams.

[0033] The instructions of the computer program may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operating steps to be performed on the computer, other programmable device, or other devices to produce a computer-executed process such that the instructions executing on the computer or other programmable device enable processes to perform the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0034] As described above, embodiments may be realized in the form of processes executed by a computer and devices for practicing those processes. In embodiments, the invention is realized in computer program code executed by one or more network elements. Embodiments include a computer program product on a computer-usable medium with computer program code logic containing instructions embodied in tangible media as an article of manufacture.Exemplary articles of manufacture for a computer usable medium may include floppy disks, CD-ROMs, hard disk drives, Universal Serial Bus (USB) flash drives, or any other computer-readable storage medium, wherein when the computer program code logic is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention.Embodiments include, for example, computer program code logic, whether stored in a storage medium that is loaded into and / or executed by a computer, or whether transmitted over a particular transmission medium such as electrical wiring or cabling, fiber optic technology, or electromagnetic radiation, wherein when the computer program code logic is loaded into and executed by a computer, the computer becomes an apparatus with which the invention can be practiced.

[0035] The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of code comprising one or more executable instructions for performing the specified logical function(s). It should also be noted that in some alternative implementations, the functions specified in the block may sometimes appear in a different order than that shown in the figures.For example, depending on the functionality associated with them, two blocks shown as consecutive blocks may actually execute substantially concurrently, or the blocks may sometimes execute in reverse order. It will also be appreciated that each block of the block diagrams and / or flowchart illustrations, as well as combinations of blocks in the block diagrams and / or flowchart illustrations, may be executed by systems relying on special-purpose hardware to perform the specified functions or operations, or by combinations of special-purpose hardware and computer instructions.

Claims

[1] Computer program product (700) for implementing a hybrid address translation, the computer program product comprising: a physically tangible non-volatile storage medium (702) readable by a processing circuit and storing instructions (704) for execution by the processing circuit to perform a method comprising: Receiving a first address, the first address comprising an effective address pointing to a memory location in a first address space in a computer system having first and second page tables, the first page table comprising a hashed page table (HPT) (107) and the second page table comprising a radix tree (108); Searching a segment translation buffer (SLB) (105) for an SLB entry (110) corresponding to the first address; wherein the SLB has a plurality of SLB entries, each having a corresponding type field (111B) and a corresponding address field (111A), the plurality of SLB entries having a first and a second entry, the first request having a first type field corresponding to a lookup in the first page table, and the second entry having a second type field corresponding to a lookup in the second table; Determine whether a value of the type field in the SLB entry corresponding to the first address corresponds to a lookup in the first or second page table; Searching the first or second page table to determine an address translation for the first address based on the type field in the SLB entry corresponding to the first address by: based on the determination that the value of the type field corresponds to the search in the first page table, searching the first page table to determine a second address, the second address comprising a translation of the first address into a second address space; and based on the determination that the value of the type field matches the lookup in the second page table, search the second page table to determine the second address. [2] The computer program product of claim 1, wherein the address field of the first entry in the SLB comprises a virtual address corresponding to an effective address, wherein searching the first page table to determine the second address comprises: Extracting the virtual address corresponding to the first address from the address field of the SLB entry corresponding to the first address; and Search the first page table for the virtual address. [3] The computer program product of claim 1, wherein the address field of the second entry in the SLB has an address space identifier (ID) and a segment size corresponding to an effective address, wherein searching the second page table to determine the second address corresponding to the first address comprises: Extracting the address space identifier (ID) and segment size associated with the first address from the address field of the SLB entry corresponding to the first address; Determining a root of the search in the second page table based on the address space ID and the segment size; and Search the second page table for the first address, starting at the root. [4] The computer program product of claim 3, wherein the address space ID comprises a process ID associated with the first address. [5] The computer program product of claim 3, wherein the address space ID and the segment size indicate that the root is a level in the radix tree that is below a top level of the radix tree, and wherein the search of the radix tree for the first address begins at the level that is below the top level of the radix tree, such that the top level of the radix tree is not searched. [6] The computer program product of claim 1, wherein the first address comprises an effective address issued by an application executing on a computer as part of a memory access, the second address comprises a real address, and the second address space comprises a physical computer memory of the computer. [7] The computer program product of claim 1, wherein the value of the type field is based on at least one type of memory access and / or a type of application associated with the first address. [8] The computer program product of claim 1, wherein the first address space comprises a plurality of non-contiguous memory areas. [9] A computer system (100A, 100B) for hybrid address translation, the system comprising: Address translation logic (103); and a segment translation buffer (SLB) (105), the system being configured to perform a method comprising: Receiving a first address, the first address comprising an effective address pointing to a memory location in a first address space comprising a first and a second page table, the first page table comprising a hashed page table (HPT) (107) and the second page table comprising a radix tree (108); Searching the SLB for an SLB entry (110) corresponding to the first address, the SLB having a plurality of SLB entries each having a corresponding type field (111B) and a corresponding address field (111A), the first request having a first type field corresponding to a lookup in the first page table and the second entry having a second type field corresponding to a lookup in the second table; Determine whether a value of the type field in the SLB entry corresponding to the first address corresponds to a lookup in the first or second page table; Searching the first or second page table to determine an address translation for the first address based on the type field in the SLB entry corresponding to the first address by: based on the determination that the value of the type field corresponds to the search in the first page table, searching the first page table to determine a second address, the second address comprising a translation of the first address into a second address space; and based on the determination that the value of the type field matches the lookup in the second page table, search the second page table to determine the second address. [10] The computer system of claim 9, wherein the address field of the first entry in the SLB comprises a virtual address corresponding to an effective address, wherein searching the first page table to determine the second address comprises: Extracting the virtual address corresponding to the first address from the address field of the SLB entry corresponding to the first address; and searching the first page table for the virtual address. [11] The computer system of claim 9, wherein the address field of the second entry in the SLB has an address space identifier (ID) and a segment size corresponding to an effective address, wherein searching the second page table to determine the second address corresponding to the first address comprises: Extracting the address space identifier (ID) and segment size associated with the first address from the address field of the SLB entry corresponding to the first address; Specifying a root of the search in the radix tree based on the address space ID and the segment size; and Search the second page table for the first address, starting at the root. [12] The computer system of claim 11, wherein the address space ID comprises a process ID associated with the first address. [13] The computer system of claim 11, wherein the address space ID and the segment size indicate that the root is a level in the radix tree that is below a top level of the radix tree, and wherein the search of the radix tree for the first address begins at the level that is below the top level of the radix tree, such that the top level of the radix tree is not searched. [14] The computer system of claim 9, wherein the first address comprises an effective address issued by an application (102A, 102B, 102N) running on the computer as part of a memory access, the second address comprises a real address, and the second address space comprises a physical computer memory of the computer. [15] The computer system of claim 9, wherein the value of the type field is based on at least one of a type of memory access and a type of application associated with the first address. [16] A computer-executed method (200) for hybrid address translation in a computer, the method comprising: Receiving a first address, the first address comprising an effective address pointing to a memory location in a first address space in a computer system having first and second page tables, the first page table comprising a hashed page table (HPT) (107) and the second page table comprising a radix tree (108); Searching (204) a segment translation buffer (SLB) (105) for an SLB entry (110) corresponding to the first address, the SLB having a plurality of SLB entries each having a corresponding type field (111B) and a corresponding address field (111A), the plurality of SLB entries having a first and a second entry, the first request having a first type field corresponding to a lookup in the first page table and the second entry having a second type field corresponding to a lookup in the second table; determining (205) whether a value of the type field in the SLB entry corresponding to the first address corresponds to a lookup in the first or second page table; Searching the first or second page table to determine an address translation for the first address based on the type field in the SLB entry corresponding to the first address by: based on determining that the value of the type field corresponds to the search in the first page table, searching (207) the first page table to determine a second address, the second address comprising a translation of the first address to a second address space; and based on the determination that the value of the type field corresponds to the search in the second page table, searching (206) the second page table to determine the second address. [17] The computer-executed method (200, 600) of claim 16, wherein the address field of the first entry in the SLB comprises a virtual address corresponding to an effective address, wherein searching the first page table to determine the second address comprises: Extracting (601) the virtual address corresponding to the first address from the address field of the SLB entry corresponding to the first address; and Search (602) the first page table for the virtual address. [18] The computer-executed method (200, 300, 400) of claim 16, wherein the address field of the second entry in the SLB has an address space identifier (ID) and a segment size corresponding to an effective address, wherein searching the second page table to determine the second address corresponding to the first address comprises: Extracting (301, 401) the address space identifier (ID) and the segment size associated with the first address from the address field of the SLB entry corresponding to the first address; Determining (305) a root of the search in the second page table based on the address space ID and the segment size; and Searching (305) the second page table for the first address, starting at the root. [19] The computer-executed method (200, 300, 400) of claim 18, wherein the address space ID comprises a process ID associated with the first address. [20] The computer-implemented method (200, 300, 400) of claim 18, wherein the address space ID and the segment size indicate that the root is a level in the radix tree that is below a top level of the radix tree, and wherein the searching of the radix tree for the first address begins at the level that is below the top level of the radix tree, such that the top level of the radix tree is not searched.

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