SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD

Abstract

In one embodiment, the semiconductor component (1) comprises: - a gate electrode (33), - a first semiconductor region (21) of a first conductivity type on a top side (20) of a semiconductor body (2), - a plug region (24) of a second conductivity type, - a first electrode (31) which electrically contacts the first semiconductor region (21) and the plug region (24), - a well region (23) of the second conductivity type, and - at least one barrier region (41, 42) comprising a first barrier region (41) in the semiconductor body (2), where - the well region (23) is located between the first barrier region (41) and the first semiconductor region (21), - the first barrier region (41) is a barrier for charge carriers of the second conductivity type, - the first electrode (31) extends in a direction towards the first barrier region (41) deeper than or as deep as the first semiconductor region (21) into the semiconductor body (2).

Description

[0001] A semiconductor component is provided. Furthermore, a method for manufacturing such a semiconductor component is also provided.

[0002] The document M. Takei et al., “DB (Dielectric Barrier) IGBT with extreme injection enhancement”, 2010 22nd International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2010, pages 383-386, refers to injection enhancement.

[0003] One problem to be solved is to provide a semiconductor device that has improved electrical performance.

[0004] This problem is solved, inter alia, by a semiconductor component and a method according to the independent patent claims. Exemplary developments are the subject matter of the dependent claims.

[0005] For example, the semiconductor device described here comprises a first barrier region in a semiconductor body. At least a portion of a well region is located between the first barrier region and a first semiconductor region, wherein the first barrier region is a barrier for charge carriers of at least one conductivity type. At least one of a plug region or a first electrode extends into the semiconductor body in a direction toward the first barrier region deeper than the first semiconductor region. With such a first barrier layer, manufacturing costs can be kept relatively low, while an improved saturation voltage V ce-SAT between a collector and an emitter or between a source and a drain and also better long-term device reliability can be achieved.

[0006] For example, the semiconductor body is made of silicon, Si. However, the semiconductor body can alternatively be made of a semiconductor material with a wide band gap such as SiC, Ga2O3 or GaN

[0007] For example, the semiconductor device is a metal-insulator-semiconductor field-effect transistor, MISFET, a metal-oxide-semiconductor field-effect transistor, MOSFET, an insulated-gate bipolar transistor, IGBT, a reverse-conducting insulated-gate bipolar transistor, RC-IGBT, a bipolar transistor, BJT, a thyristor, a gate-turn-off thyristor, GTO, a gate-commutated thyristor, GCT, or a junction field-effect transistor, JFET.

[0008] For example, the semiconductor component is a power component. For example, the semiconductor component is configured for a maximum voltage between a source or emitter electrode and a drain or collector electrode of at least 0.2 kV, or of at least 0.6 kV, or of at least 1.2 kV. Alternatively or additionally, the semiconductor component is configured for a current between the source or emitter electrode and the drain or collector electrode of at least 0.01 kA, or of at least 0.1 kA, of at least 1 kA, and / or of at most 100 kA, or of at most 10 kA. This means that a current flow through the semiconductor component can be controlled by means of the gate electrode and by the respective voltages between the first and second electrodes, and can in particular be switched on and off by switching a voltage at the gate electrode on and off.

[0009] Thus, it is possible that the semiconductor device is a semiconductor chip or wafer and can be any type of IGBT or MISFET.

[0010] The semiconductor component is, for example, a power module for converting direct current from a battery into alternating current for an electric motor, for example in vehicles such as hybrid vehicles or plug-in electric vehicles or in railways such as commuter trains.

[0011] In at least one embodiment, the semiconductor device comprises: - a gate electrode on a top side of a semiconductor body, - a first semiconductor region of a first conductivity type at the top, wherein the first semiconductor region is a source region or an emitter region, - optionally a plug area of ​​a second conductivity type, - a first electrode which electrically contacts the first semiconductor region and the plug region and can thus be an emitter electrode or a source electrode, - a well region of the second conductivity type in which the first semiconductor region is at least partially embedded, and - at least one barrier region comprising a first barrier region partially or completely in the semiconductor body, wherein - at least a part of the well region is located between the first barrier region and the first semiconductor region, - the first barrier region is a barrier for charge carriers of at least the second conductivity type, and - at least one of the plug region or the first electrode extends in the direction of the first barrier region deeper than or as deep as the first semiconductor region into the semiconductor body.

[0012] The fact that the plug region and / or the first electrode extends into the semiconductor body means, for example, that the plug region and / or the first electrode extends deeper into the semiconductor body in a direction away from the top side. In other words, the plug region and / or the first electrode extends from the top side to a rear side of the semiconductor body, and a second electrode, which may be a drain electrode or a collector electrode, is applied to the rear side, for example. This means that the plug region and / or the first electrode partially penetrates the semiconductor body. A depth of the plug region and / or the first electrode is thus greater than a depth of the first semiconductor region.

[0013] For example, the present device relates to planar IGBT technology. In particular, a planar IGBT design is described in which a vertical hole path at an emitter contact, which is present in reference IGBT designs, is blocked by at least one barrier region. The at least one barrier region could be or comprise a dielectric or a highly doped n-type layer, forcing the holes to flow parallel to an electron channel formed at a gate-oxide interface and exit the device at a side emitter contact, thereby increasing a plasma concentration in this region, resulting in a strong injection enhancement effect, and ultimately leading to a greatly improved technology curve. The design can be considered the functional equivalent of a finely structured trench IGBT rotated by 90° in cross-section.

[0014] Recently, trench IGBTs have been sought after due to their superior turn-on performance and improved technology curve in terms of a trade-off between their turn-off energy, E off , and V ce-SAT considered a preferred design choice over planar IGBTs. The trench IGBT design benefits from its superior plasma profile, which stems from a closely spaced vertical flow of electrons and holes near the emitter, resulting in an injection enhancement effect. The IGBT plasma profile, and thus its turn-on performance in the trench structure, can be further improved by increasing the length of the emitter contact, L pcont , or in other words, by reducing a distance between adjacent trenches.

[0015] In a conventional planar IGBT structure, however, injected electrons from a planar channel force holes to enter the emitter contact laterally near their edge. As a result, the plasma profile and thus V ce-sat The conventional planar IGBT design cannot be improved simply by shortening the emitter contact length as in trench devices. However, planar IGBTs offer other advantages, such as better long-term reliability (i.e., device lifetime) and robust performance in service-oriented architectures compared to trench designs, along with a less complex and therefore more cost-effective manufacturing process.

[0016] It is therefore desirable to engineer the electron and hole flow in the planar design to achieve equal or even improved turn-on performance compared to the trench design, while retaining the original advantages of the planar design. In short, a new IGBT design is desired that combines the best of both worlds—i.e., trench and planar design.

[0017] Previously, DB-IGBTs (dielectric-barrier IGBTs) proposed by Takei et al. partially solved this problem by introducing a dielectric layer as a barrier for the hole path to the emitter contact. However, in their design, holes are formed in the third dimension from p +regions between n-type source regions. This has two disadvantages with respect to the semiconductor device described here, since (i) it significantly reduces the injection enhancement effect and (ii) the minimum achievable emitter contact width required to maximize the injection enhancement effect is limited by lithography.

[0018] In the semiconductor device described here, referred to here as a trench-like planar insulated gate bipolar transistor (TLP-IGBT), it is also proposed to use a barrier layer to block the vertical hole path and instead redirect the holes so that they flow parallel to the electron channel, but the holes are to exit, for example, via a side emitter contact. This feature makes it possible to increase the injection amplification effect by reducing a side emitter contact dimension, such as L pcont, and achieve improved turn-on performance and technology curve like a trench design device.

[0019] In contrast to devices according to the reference trench design, the design described here also allows for a true point contact emitter device without any lithographic constraints by reducing the vertical dimension L pcont In addition, it is proposed to stack several such cells along the vertical dimension for further reinforcement, similar to a lateral stacking of trench cells. Furthermore, the at least one barrier layer is not limited to dielectric materials and can also be a semiconductor layer, such as n + Si, be.

[0020] In short, the introduction of the above feature results in significantly improved turn-on losses and a significantly improved technology curve compared to the planar technology reference platform, making it a potential candidate for the new next-generation planar IGBT technology suitable for both low-voltage and high-voltage platforms.

[0021] According to at least one embodiment, the semiconductor component comprises the plug region, which is of the second conductivity type. The plug region can be used to electrically contact the well region, in particular by means of the first electrode.

[0022] If no dedicated plug region is present, the well region itself can also fulfill the function of the plug region, i.e., it can be electrically connected to the first semiconductor region. This means that the plug region can be integrated into the well region.

[0023] According to at least one embodiment, the plug region, as seen in a top view of the top side, extends, for example, along the first semiconductor region and / or the gate electrode. For example, the plug region extends completely along the first semiconductor region and partially or completely overlaps with the first semiconductor region. In other words, the first semiconductor region may partially or completely cover the plug region, such that the first semiconductor region is located directly between the plug region and the top side. Alternatively or additionally, the plug region, as seen in a top view, may run along the first semiconductor region on a side remote from the gate electrode. In other words, at least a part of the plug region, as seen in a top view of the top side, is located adjacent to the first semiconductor region, and the first semiconductor region is located between the gate electrode and the plug region.In this configuration, the top surface may be partially formed by the plug region.

[0024] According to at least one embodiment, the first electrode is in direct contact with the first barrier region. This means that the first electrode extends into the semiconductor body up to the first barrier region, into the first barrier region, or even through the first barrier region. Otherwise, the first electrode may end away from the first barrier region. For example, a distance between the first barrier region and the first electrode in a direction perpendicular to the top side is at least 0.1 µm and / or at most 0.5 µm.

[0025] It is possible for the first barrier region to run parallel to the top surface. For example, a length of the first barrier region, viewed in cross-section, exceeds a thickness of the first barrier region by at least a factor of five, or by at least a factor of ten, and / or by at most a factor of 50. This can apply from a plane of symmetry of the contact surface with the first electrode.

[0026] According to at least one embodiment, the plug region is in direct contact with the first barrier region. This means that the plug region extends into the semiconductor body up to the first barrier region, into the first barrier region, or even through the first barrier region. Otherwise, the plug region may end away from the first barrier region. For example, a distance between the first barrier region and the plug region in the direction perpendicular to the top side is at least 0.1 µm, or is at least 0.5 µm, and / or is at most 2 µm.

[0027] According to at least one embodiment, the first barrier region is completely covered by the semiconductor body on a side of the first barrier region facing the first semiconductor region. This applies, for example, in at least one cross-section through the semiconductor body perpendicular to the top side. For example, the first barrier region between adjacent first semiconductor regions is completely covered by the well region and / or by the plug region. This means that the first electrode can cover a top side of the plug region exposed from the source region, such that no or no significant area portion of the plug region runs obliquely to the top side and is contacted by the first electrode.

[0028] According to at least one embodiment, the first barrier region consists of or comprises one or more doped barrier layers. The at least one doped barrier layer is, for example, of the first conductivity type.

[0029] According to at least one embodiment, the first barrier region consists of or comprises one or more dielectric layers. It is possible that different dielectric materials can be combined to form the first barrier region.

[0030] For example, the at least one dielectric layer is made of at least one of the following materials: SiO2, Si3N4, Al2O3, Y2O3, ZrO2, HfO2, La2O3, Ta2O5, TiO2. Therefore, the gate insulator can also be referred to as an oxide layer. The same materials can be selected for all other electrically insulating layers in the semiconductor device.

[0031] According to at least one embodiment, the semiconductor body further comprises a drift region of the first conductivity type. For example, the drift region is located directly adjacent to the well region and / or the first barrier region. The drift region can be located directly on a gate insulator layer.

[0032] According to at least one embodiment, the first barrier region extends into the drift region in a direction parallel to the top side. For example, the first barrier region ends in the drift region, in particular beyond the well region.

[0033] According to at least one embodiment, the first barrier region protrudes from the well region into the drift region with a projection length. The drift region can protrude from the well region and thus also from the first semiconductor region along the direction parallel to the top side and / or away from the first electrode. For example, the projection length is at least 10%, or at least 30%, or at least 50% of a width of the well region and / or the source region along a same direction. Alternatively or additionally, the projection length is at most 300%, or at most 200%, or at most 150% of the width of the well region and / or the source region along the same direction.

[0034] According to at least one embodiment, the first barrier region separates the drift region from the well region and / or the plug region along a direction perpendicular to the top surface. Thus, along this direction, there may be no direct connection between the drift region and the well region and / or the plug region.

[0035] According to at least one embodiment, the first barrier region comprises one or more openings. The at least one opening can extend completely through the first barrier region. Thus, in the at least one opening, the semiconductor body, for example, the drift region, can be exposed from the first barrier region.

[0036] According to at least one embodiment, the at least one opening is located adjacent to the first semiconductor region and / or the well region and / or the plug region, as viewed in a top view. Therefore, the at least one opening may be remote from the first semiconductor region and / or the well region and / or the plug region, as viewed in a top view.

[0037] According to at least one embodiment, the semiconductor component further comprises one or more second barrier regions. The at least one second barrier region is located in the semiconductor body between the first barrier region and the first semiconductor region. For example, the at least one second barrier region is remote from both the first barrier region and the first semiconductor region. The at least one second barrier region is a barrier through the semiconductor body for charge carriers of at least the second conductivity type.

[0038] According to at least one embodiment, at least one of the plug region and the first electrode extends along the at least one second barrier region to the first barrier region. Thus, the plug region or the first electrode can extend entirely along the at least one second barrier region in the direction perpendicular to the top side, for example, starting at the top side.

[0039] According to at least one embodiment, the at least one second barrier region comprises an electrically conductive layer that is electrically insulated from the semiconductor body by a further dielectric layer. Thus, the at least one second barrier region can be formed in multiple layers.

[0040] According to at least one embodiment, the number of second barrier regions is at least one and at most ten. For example, the number of second barrier regions is at least two and at most eight, or the number of second barrier regions is at least two and at most five.

[0041] According to at least one embodiment, the electrically conductive layer is in electrical contact with either the gate electrode or the first electrode.

[0042] Thus, the at least one second barrier region can correspond to an active or a dummy MOS cell in a trench design device.

[0043] According to at least one embodiment, at least one further first semiconductor region of the first conductivity type is located on at least one main side of the second barrier layer in direct contact with the at least one second barrier region. The at least one further first semiconductor region and the corresponding main side can be aligned parallel to the top side. It is possible for such a further first semiconductor region to be located directly on both main sides of the corresponding second barrier region.

[0044] It is possible for at least one second barrier region to be present with at least one further first semiconductor region, and for at least one second barrier region to be present without an associated further first semiconductor region or with only one associated further first semiconductor region. For example, the second barrier region without an associated further first semiconductor region or with only one associated further first semiconductor region is a lowermost second barrier region, i.e., the second barrier region furthest from the top side, or is a second intermediate barrier region arranged between the first barrier region and another second barrier region located closer to the top side.

[0045] According to at least one embodiment, the semiconductor body further comprises a second semiconductor region, for example, on a bottom side opposite the top side. The second semiconductor region can be either a drain region of the first conductivity type or a collector region of the second conductivity type. Thus, the semiconductor component can be a field-effect transistor or an insulated-gate bipolar transistor.

[0046] Additionally, a method for producing the semiconductor component is provided. A semiconductor component is produced by means of the method as specified in connection with at least one of the above-mentioned embodiments. Thus, features of the semiconductor component are also disclosed for the method, and vice versa.

[0047] In at least one embodiment, the method is used to manufacture a semiconductor device. The method comprises the following steps, for example, in the order given: A) Providing at least part of the semiconductor body, B) forming the first barrier region on the at least part of the semiconductor body, and C) Applying the first electrode and the gate electrode to the semiconductor body.

[0048] Between process steps B) and C), there may be additional process steps such as overgrowing the first barrier region. Further optional steps may include forming the at least one second barrier region and the electrically insulating layers prior to applying the electrodes.

[0049] According to at least one embodiment, the method further comprises one or some or all of the following steps, for example between steps B) and C), wherein in step A) only a first part of the semiconductor body is provided: B1) forming a second part of the semiconductor body over the first barrier region, for example by using selective Si epitaxy, and / or B2) producing the first semiconductor region and the plug region in the second part, for example either by ion implantation or by in-situ doping during the growth of the second part, and / or B3) forming a gate insulator layer (53) on the second part, and / or B4) etching through the second part to the first barrier region, for example by using a mask layer on the semiconductor body.

[0050] It is possible that steps B1 to B4 are performed in the order given.

[0051] A semiconductor device and method described herein are explained in more detail below using exemplary embodiments with reference to the drawings. In the individual figures, identical elements are designated by the same reference numerals. However, the relationships between the elements are not shown to scale; rather, individual elements may be exaggerated to facilitate understanding.

[0052] The figures show: Fig. 1 is a schematic sectional view of an embodiment of a semiconductor device described here, Fig. 2 and Fig. 3 schematic sectional views of reference components, Fig. 4 to 11 Comparisons of electrical properties between embodiments of semiconductor devices described here and reference devices, Fig. 12 is a schematic perspective view of an embodiment of a semiconductor device described herein, Fig. 13 is a schematic plan view of a semiconductor body for an embodiment of a semiconductor device described here, Fig. 14 and Fig. 15 schematic sectional views of embodiments of semiconductor devices described here, Fig. 16 shows a comparison of electrical properties between embodiments of semiconductor devices described here and a reference device, Fig. 17 to 21 are schematic sectional views of embodiments of semiconductor devices described herein, Fig. 22 and Fig. 23 schematic block diagrams of embodiments of a method for manufacturing semiconductor devices described here, Fig. 24 to 35 are schematic sectional views of process steps for producing semiconductor components described here, and Fig. 36 is a schematic sectional view of an embodiment of a semiconductor device described herein,

[0053] In Fig. 1 illustrates an embodiment of a semiconductor component 1. The semiconductor component 1 comprises a semiconductor body 2, which is based, for example, on Si or SiC. A drift region 25, which is, for example, weakly n-doped, is located in the semiconductor body 2. A well region 23, which is, for example, moderately p-doped, is embedded in the drift region 25. A plug region 24, which is, for example, heavily p-doped, can be located next to the well region 23. A first semiconductor region 21 is located on a top side 20 of the semiconductor body 2 and also embedded in the well region 23. For example, the first semiconductor region 21 is heavily n-doped.

[0054] For example, the semiconductor component (1) is an IGBT. Thus, on a bottom side of the semiconductor body 2 opposite the top side 20, i.e., at a lower end of the drift region 25, there is a second semiconductor region 22, which is a collector region that is, for example, heavily p-doped; consequently, the first semiconductor region 21 is then an emitter region. Additionally, a buffer region 28 may optionally be present. This buffer region 28 is of the same conductivity type as the emitter region, but less heavily doped than the collector region, and possibly with a doping concentration higher than that of the drift region 25. The buffer region 28 may be located directly between the second semiconductor region 22 and the drift region 25, for example, as a continuous, uninterrupted layer of constant thickness, like the second semiconductor region 22 itself.

[0055] Instead, if the semiconductor device 1 is not an IGBT but a MISFET or MOSFET, the first semiconductor region 21 is a source region, and consequently the second semiconductor region 22 is a drain region of the same conductivity type as the source region.

[0056] For example, maximum doping concentrations of the first and second semiconductor regions 21, 22 and of the at least one plug region 24 are at least 1 × 10 18 cm -3 or at least 5 × 10 18 cm -3 or at least 1 × 10 19 cm -3 and / or a maximum of 5 × 10 20 cm -3 or at most 2 × 10 20 cm -3 or at most 1 × 10 20 cm -3 . Furthermore, a maximum doping concentration of the well region 23 and / or the buffer region 28 may be at least 5 × 10 15 cm -3 or at least 1 × 10 17 cm -3 and / or a maximum of 5 × 10 19 cm -3or at most 5 × 10 18 cm -3 be.

[0057] Depending on the voltage class of the semiconductor component 1, a maximum doping concentration of the drift region 25 can be at least 1 × 10 11 cm -3 or at least 1 × 10 12 cm -3 or at least 1 × 10 13 cm -3 and / or at most 1 × 10 17 cm -3 or at most 5 × 10 16 cm -3 or at most 1 × 10 16 cm -3 be.

[0058] Furthermore, the semiconductor component 1 comprises a first barrier region 41. The first barrier region 41 can at least not be penetrated by holes during the intended use of the semiconductor component 1.

[0059] On the top side 20 there is a gate insulator layer 53, such as a gate oxide, and a gate electrode 33. The gate electrode 33 is located on the planar top side 20, mainly on the drift region 25. Next to the well region 23, a thickness of the gate insulator layer 53 is, for example, between 50 nm and 250 nm or between 80 nm and 150 nm. On the gate electrode 33 there is a first electrode insulator layer 51, which separates the gate electrode 33 from a first electrode 31.

[0060] It is possible for the first electrode 31 to directly contact lateral surfaces of the first semiconductor region 21 and the well region 23 or the plug region 24. A contact length between the first electrode 31 and the well region 23 and / or the plug region 24 is referred to as L pcont For example, L pcontat least 50 nm and / or at most 10 µm or at most 0.5 µm or at most 0.2 µm. The first electrode 31 also contacts the first semiconductor region 21. A thickness of the first semiconductor region 21 is, for example, at least 50 nm and / or at most 0.5 µm. For example, the first electrode 31 is in contact with the semiconductor body 2 only at the lateral side surfaces of the regions 21, 23, 24 and not, or not significantly, at the top side 20. The lateral side surfaces can run perpendicular to the top side 20, for example with a tolerance of at most 30° or at most 15°.

[0061] In Fig. 1 only shows a part of the semiconductor component 1. Thus, there may be a plane of symmetry S at which the part of the semiconductor component 1 is mirrored and correspondingly extended. Several such mirrored units may be present in the semiconductor component 1, so that in Fig. 1 essentially only one half of a cell unit can be shown in cross-section.

[0062] The first barrier area 41 runs, for example, parallel to the top side 20. A length L B of the first barrier region 41 of the shown half of the cell unit is, along an x-direction, for example, at least 2 µm or at least 5 µm and / or at most 20 µm or at most 12 µm. Alternatively or additionally, a thickness T B of the first barrier region 41 along a y-direction is at least 0.1 µm or at least 0.3 µm and / or is at most 5 µm or is at most 2 µm or is at most 1 µm. It is possible that 0.2 T B ≤ L pcont ≤ T B or 0.5 T B ≤ L pcont ≤ 2 T B or 0.8 T B ≤ L pcont ≤ 1.2 T B .

[0063] Along the x-direction, the first barrier region 41 protrudes from the well region 23 into the drift region 25 with a protrusion length P. For example, the protrusion length P is at least 25% or at least 50% of a length of the well region 23 together with the plug region 24 along the x-direction. Additionally or alternatively, the protrusion length P is at most 300% or at most 150% of the length of the well region 23 together with the plug region 24 along the x-direction.

[0064] Through the first barrier region 41, a main flow Fe of electrons runs antiparallel to a main flow Fh of holes next to the gate electrode 33 through the well region 23.

[0065] In Fig. 2 shows a reference component 91 with a planar design. This reference component 91 largely corresponds to the semiconductor component 1 of Fig. 1, but there is no first barrier region. Consequently, the first electrode 31 does not extend significantly into the semiconductor body 2 to the drift region 25, but is only applied to the top side 20 or extends only slightly into the semiconductor body 2, for example, up to a maximum of 1.5 times the thickness of the first semiconductor region 21.

[0066] Thus, L pcont larger than in the semiconductor device 1 of Fig. 1 and is approximately 3 µm per half of a cell unit.

[0067] In Fig. Figure 3 illustrates a reference device 92 with a trench design. Thus, the gate electrode 33 is accommodated in a trench, and the first electrode 31 is located on the top side 20 or extends only slightly into the semiconductor body 2.

[0068] As discussed above, the trench IGBT design 92 benefits from its superior plasma profile. The IGBT plasma profile, and thus its turn-on power in the trench structure, can be improved by reducing L pcont In the planar IGBT structure 91, injected electrons and holes follow different paths, as shown in Fig. 2 is shown very schematically. As a result, the plasma profile and thus V ce-sat not simply by reducing L pcont as in the trench component 92. This is in Fig. 4, where the effect of scaling L pcont regarding V ce-sat is illustrated.

[0069] As in Fig. 2, in contrast to the trench device 62, it is not possible to achieve a strong injection enhancement effect in the planar design 91 only by reducing the emitter contact length L pcontFor the work, it is important to have a device structure in which a significant portion of the holes enter the emitter contact vertically. This can be achieved in the planar design by directing the main vertical path of the holes through the first barrier region 41, which can be either a dielectric or highly doped n + -layer is blocked and that the holes are redirected so that they flow laterally along the electron channel and exit vertically from the emitter via the side contact 31, as in Fig. 1 is shown.

[0070] In this way, a strong injection reinforcement effect can be generated, which can be achieved by reducing the thickness L pcontto a point-contact emitter device. The design can be considered the functional equivalent of a 90° rotated finely structured trench IGBT, which can be realized with virtually no lithographic constraints.

[0071] The proposed TLP IGBT design 1 was investigated using TCAD simulations to understand its operation and further compare its performance advantages over the planar reference IGBT cell 91. Fig. 1 shows the schematic cross-sections of the TLP IGBT cell used for the 2D TCAD simulations, and Fig. 2 shows the corresponding planar reference IGBT cell 91. As in Fig. 1, the hole current flows antiparallel to the electron current and leaves the device 1 at a small side emitter contact area, which, as desired, leads to a strong injection enhancement effect.

[0072] Accordingly, in the Fig. 5 and Fig. 6 the output characteristics I ce opposite V ce of the TLP-IGBT 1 of Fig. 1 and its comparison with the planar reference IGBT design 91 for V ce from 0 V to 3 V in Fig. 5 and 0 V to 25 V in Fig. 6. Accordingly, the Fig. 5 and Fig. 6 the turn-on power of the TLP-IGBT 1 with that of the reference component 91. As expected, the TLP-IGBT 1 with L pcont = 750 nm a significantly improved V ce-Sat (by about 580 mV) compared to that of the reference IGBT design 91 at a rated current level, I nom , of 62.5 A. The reinforcement of the V ce-sat improved by ~830 mV when L pcont to 110 nm. This confirms the strong injection gain achieved in the TLP IGBT structure 1 compared to the planar reference IGBT 91.

[0073] It is also evident from the transmission characteristics, see Fig. 7 and Fig. 8, shows that the threshold voltage V th and the sub-threshold characteristics of the TLP IGBT cell 1 remain virtually unaffected compared to the reference device 91.

[0074] Furthermore, Fig. 9 Blocking voltage characteristics I c vs. V ce of the TLP-IGBT 1 using an oxide as the first barrier region and the reference design 91 at 398 K at V ge = -15 V

[0075] Fig. Figure 10 shows the turn-off switching waveforms at 298 K of the TLP-IGBT device 1 and their comparison with the reference device 91. The TLP-IGBT 1 turns off similarly to the planar reference device 91, but with a significantly improved E off vs. V ce-Sat- Compromise, as shown in the technology curve diagrams in Fig. 11. The TLP-IGBT 1 shows an improvement of about 400 mV (~16%) in the on state with the same turn-off losses, E off , or about 90 mJ (~32%) lower E off at the same V ce-sat . The technology curves shift further to the left when L pcont was reduced to 110 nm, ie towards a point-emitter contact IGBT.

[0076] These improvements in the technology curve are mainly due to the fact that the E off -Increase for a given improvement of V ce-sat occurs in relatively low proportionality. This is due to the favorable plasma profile achieved in TLP-IGBT 1 with increased plasma concentration near the emitter, where a strong electric field leads to efficient and timely hole removal during the turn-off transient.

[0077] In Fig. Figure 12 illustrates a further embodiment of the semiconductor device 1 in a perspective view. The first semiconductor region 21 and the regions 23, 24 all extend along a z-direction perpendicular to an xy-plane without any intended variations. It should be noted that the first electrode 31 is shown in a simplified manner to better illustrate the regions 21, 23, 24, but in fact, it covers the side surfaces of these regions 21, 23, 24, as shown, for example, in Fig. 1 or Fig. 14 illustrates.

[0078] The first barrier region 41 consists of a dielectric layer 44. Alternatively, however, a multi-layer design of the first barrier region 41 is also possible.

[0079] As an option, the first semiconductor region 21 could be segmented along the z-direction, see Fig. 13. That is, parallel to the gate electrode 33, which is in Fig. 13 is not shown, blocks of the first semiconductor region 21 may be present alternately with blocks of the well region 23 and / or with blocks of the plug region 24.

[0080] Otherwise, the component 1 of Fig. 1 What has been said also applies to the Fig. 12 and Fig. 13 apply and vice versa.

[0081] According to Fig. 14, the optional plug region 24 and / or the well region 23 protrudes along the lateral x-direction and away from the drain region 25 from the first semiconductor region 21. This means that the optional plug region 24 and / or the well region 23 can be electrically contacted from the top side 20 and not only from the lateral sides as the first semiconductor region 21.

[0082] This design allows for improved coverage of an emitter metal of the first electrode 31 over the p-base / plug region 23, 24, resulting in reduced contact resistance compared to designs with only side contact, especially during a turn-off transient. In the latter case, L pcont determined by a thickness of the p-base 23, 24, and therefore an injection gain can be further increased by reducing L pcont can be achieved.

[0083] Unlike in Fig. 14, the optional plug region 24 and / or the tub region 23 may completely cover the first barrier region 41. This is shown in Fig. 36 illustrates.

[0084] For example, the component is Fig. 36 is created by removing the first semiconductor region 21 from a part of the plug region 24, such that the plug region 24 is exposed on the first barrier region, instead of etching completely through the semiconductor body 2 up to the first barrier region 41. Thus, the plug region 24 and / or the well region 23 may completely cover a portion of the first barrier region 41, wherein, as seen in plan view, the first electrode 31 makes electrical contact with the semiconductor body 2. Thus, the first electrode 31 is separated from the first barrier region 41 by the plug region 24 and / or the well region 23. That is, the first semiconductor region 21 and the first electrode 31 may have an equal depth into the semiconductor body 2.

[0085] Contrary to what is said in Fig. 36, when the first semiconductor region 21 is removed, an etch may easily be performed into the plug region 24 and / or the well region 23. Accordingly, the first electrode 31 may have a depth into the semiconductor body 2 that is slightly greater than the first semiconductor region 21 due to manufacturing issues, but the first electrode 31 is then still separated from the first barrier region 41 by the plug region 24 and / or the well region 23.

[0086] Otherwise, this can be the case for components 1 of the Fig. 1 and Fig. 13 What has been said also applies to the Fig. 14 and Fig. 36 apply and vice versa.

[0087] In Fig. 15 shows that the first barrier region 41 consists of a doped barrier layer 45. For example, a maximum doping concentration of the n-doped layer 45 is at least 1 × 10 16 cm -3 or at least 5 × 10 16 cm -3or at least 1 × 10 17 cm -3 and / or at most 1 × 10 20 cm -3 or at most 5 × 10 19 cm -3 or at most 1 × 10 19 cm -3 In this case, the maximum doping concentration of the drift region 25 can be between 1 × 10 12 cm -3 and 1 × 10 13 cm -3 lay.

[0088] Otherwise, this can be the case for components 1 of the Fig. 1, Fig. 12, Fig. 13, Fig. 14 and Fig. 36 What has been said also applies to Fig. 15 apply and vice versa.

[0089] In Fig. 16 the output characteristics of the TLP-IGBT 1 with the n + -Barrier layer 45 with the TLP-IGBT 1 with the oxide barrier 44 and the planar reference design 91 of Fig. 2. It can be seen that the n +-barrier 45 leads to a similar performance advantage as the oxide barrier 44 during on-state conduction and represents an effective barrier to hole flow. Doping of the n + However, layer 45 may need to be optimized in a manner that does not impair the blocking capability of device 1.

[0090] According to Fig. 17, the first barrier region 41 includes a plurality of openings 46 that extend completely through the first barrier region 41, exposing the drift region 25. This provides an additional path for hole extraction during the turn-off transient. This results in an improved reverse bias safe operating area (RBSOA) and thus a certain trade-off in turn-on losses.

[0091] Otherwise, this can be the case for components 1 of the Fig. 1, Fig. 12, Fig. 13, Fig. 14, Fig. 36 and Fig. 15 What has been said also applies to Fig. 17 apply and vice versa.

[0092] The component of Fig. 18, the first electrode 31 is confined or substantially confined to the top surface 20 and thus does not extend or does not extend significantly to the first barrier region 41. However, the plug region 24 extends from the first electrode 31 at the top surface 20 down to the first barrier region 41.

[0093] Otherwise, this can be the case for components 1 of the Fig. 1, Fig. 12, Fig. 13, Fig. 14, Fig. 36, Fig. 15 and Fig. 17 What has been said also applies to Fig. 18 apply and vice versa.

[0094] The performance of the TLP-IGBT 1 can be further optimized by, for example, introducing second barrier regions 42, which analogously correspond to active or dummy trenches in trench IGBT devices, see Fig. 19 to 21. In these figures, for example, there are two of the second barrier regions 42, but this is not a limitation on the number of the second barrier regions 42. For example, there is at least one and there are at most five of the second barrier regions 42.

[0095] Each of the second barrier regions 42 comprises a core made of an electrically conductive layer 47, such as a poly-Si layer. Surrounding this core is a further dielectric layer 48, which electrically insulates the electrically conductive layer 47 from the semiconductor body 2. The electrically conductive layer 47 can optionally be connected to one of the electrodes 31, 33, so that the respective electrically conductive layer 47 can be at the same electrical potential as the associated electrode 31, 33.

[0096] For example, the second barrier regions 42 extend from the lateral side surface of the semiconductor body 2, which is provided with the first electrode 31, into the semiconductor body 2 up to the first barrier region 41. In principle, however, it is also possible that the second barrier regions 42 protrude from the first barrier region 41 or that otherwise the first barrier region 41 protrudes from the second barrier regions 42 or that the second barrier regions 42, in contrast to what is shown in the Fig. 18 to 20, have different extensions into the drift region 25. The second barrier regions 42 can run parallel to the top side 20.

[0097] The second barrier regions 42 may be arranged in an equidistant manner. That is, a distance between adjacent second barrier regions 42 and to the top side 20 and / or to the first barrier region 41 may be L pcontcorrespond, for example with a tolerance of a factor of 1.5.

[0098] As in Fig. As shown in Figure 19, each of the second barrier regions 42 is provided with two further first semiconductor regions 27, wherein one of the further first semiconductor regions 27 is located directly on each main side of the second barrier regions 42 parallel to the top side 20. Analogous to the first barrier region 41, the second barrier regions 42 protrude from these further first semiconductor regions 27 and the associated well region 23 and / or plug region 24 into the drift region 25.

[0099] As regards the geometry and doping of the further first semiconductor regions 27, these further first semiconductor regions 27 can be configured like the first semiconductor region 21.

[0100] Accordingly, a number of vertically stacked cells may be provided, each cell comprising one of the second barrier regions 42 and the associated further first semiconductor regions 27 and / or the well region 23 and / or the plug region 24.

[0101] Otherwise, this can be the case for components 1 of the Fig. 1, Fig. 12, Fig. 13, Fig. 14, Fig. 36, Fig. 15, Fig. 17 and Fig. 18 What has been said also applies to Fig. 19 apply and vice versa.

[0102] In Fig. 20 shows that the uppermost second barrier region 42 adjacent to the top side 20 is electrically contacted with the first electrode 31 and thus corresponds to a dummy MOS cell analogous to an IGBT 92 with a trench design. The lowermost second barrier region 42 adjacent to the first barrier region 41 is electrically contacted with the gate electrode 33 and thus corresponds to an active MOS cell analogous to an IGBT 92 with a trench design.

[0103] Otherwise, the component 1 of Fig. 19 What has been said also applies to Fig. 20 apply and vice versa.

[0104] According to Fig. 21, all second barrier regions 42 are electrically connected to the gate electrode 33.

[0105] Furthermore, in Fig. 21 illustrates that not all of the second barrier regions 42 need to be provided with the further first semiconductor regions 27. For example, the uppermost second barrier region 42 is free of any further first semiconductor regions.

[0106] Otherwise, for example, for improved RBSOA performance, the further first semiconductor regions 27 can be removed from the lowermost second barrier region 42 while retaining them only in the at least one upper cell. In this way, a parasitic NPN transistor responsible for latch-up can be completely eliminated from the hole extraction path while electrons are injected from upper cells. This enables the separation and / or filtering out of electrons and / or holes near contact with the first electrode 31. Lower cells can thus function as hole extractors, while upper cells can continue to be responsible for electron injection.

[0107] Therefore, the further first semiconductor regions 27 can be added to the second barrier regions 42, if necessary. For example, as in Fig. 19 and Fig. 20, each of the second barrier regions 42 has two of the further first semiconductor regions 27, whereas in Fig. 21 the uppermost second barrier region 42 is free of further first semiconductor regions 27, or, as in the variant to Fig. 21, the lowermost second barrier region 42, in addition to the first barrier region, may alternatively be free of further first semiconductor regions 27. It is also possible for a further first semiconductor region 27 to be applied only to one main side of the respective second barrier region 42.

[0108] Otherwise, the component 1 of the Fig. 19 and Fig. 20 What was said also for Fig. 21 apply and vice versa.

[0109] Stacking n vertical cells on top of each other, as in the Fig. For example, the arrangement shown in Figures 19 to 21 leads to the following technical advantages: First, stacking the n cells along the vertical direction would simply increase the MOS cell density in a given chip. Additional electron injection from n vertical cells leads to increased plasma density and thus lower turn-on losses for a given chip area, analogous to a densely packed fine-structured trench design, in the vertical dimension.

[0110] Second, by selectively arranging the source regions 27 in the vertical cells, i.e., removing / adding them in some cells, it is possible to separate or filter out paths for electron injection and hole extraction. For example, upper cells containing such source regions 27 can be used for electron injection, while lower cells without such source regions 27 can only be used for hole extraction during turn-off. Removing the source regions 27 from the hole extraction path would make it difficult for a parasitic thyristor to turn on, resulting in an improvement in RBSOA capability.

[0111] In the Fig. 22 and Fig. 23, a manufacturing method for the semiconductor devices 1 is schematically illustrated as a block diagram.

[0112] In method steps M1, at least a part of the semiconductor body 2 is provided, for example the entire semiconductor body up to the first barrier region 41.

[0113] In process steps M20, M21, M22, the first barrier region 41 is formed.

[0114] According to step M20, see Fig. 22, the dielectric material for the first barrier region 41 is applied to the previously only partially provided semiconductor body 2, and then, in step M3, the first barrier region 41 is overgrown, so that the complete semiconductor body 2 is produced. Otherwise, in step M20, the doped barrier layer 45 can be formed such that step M3 can be optional.

[0115] According to Fig. 23, the complete semiconductor body 2 may be provided in step M1, and etching is performed in step M21. Then, in step M22, the material for the first barrier region 41 is filled into the etched recess. Therefore, method step M3, i.e., overgrowth, may be optional.

[0116] In step M4, the electrodes 31, 33 and all necessary other components are applied.

[0117] The at least one second barrier region 42 can be produced analogously to the first barrier region 41.

[0118] Otherwise, this can be for the Fig. 1 to 21 and 36 also apply to the Fig. 22 and Fig. 23 apply and vice versa.

[0119] In the Fig. 24 to 31, an exemplary method for manufacturing the semiconductor device is shown. According to Fig. 24, a first part 81 of the semiconductor body is provided. For example, the first part 81 comprises the largest part of the drift region 25. Optionally, the first part 81 comprises the buffer region 28, which n + -doped, and the second semiconductor region 22, which is p + -can be endowed.

[0120] In the next step, see Fig. 25, a continuous starting material layer 4 is applied to the first part 81; for example, the starting material layer 4 is a layer of a grown oxide, such as silicon oxide.

[0121] Next, see Fig. 26, the starting material layer 4 is structured, for example by dry etching, to form the first barrier region 41, which accordingly consists of material from the starting material layer 4.

[0122] Then, see Fig. 27, an overgrowth is carried out such that a second part 82 of the semiconductor body 2 is created. The second part 82 completely covers the first barrier region 41. For example, the second part 82 has an elevation that corresponds or approximately corresponds to the first barrier region 41. It is possible that the step of Fig. 27 by selective epitaxial overgrowth, for example with Si.

[0123] In Fig. 28 illustrates that the second part 82 is planarized to form the planar top surface 20.

[0124] In the process steps as in Fig. 29, the well region 23, the plug region 24 and the first semiconductor region 21 are created. This is done, for example, either by ion implantation or by doping during the growth of the second part 82. Then, as also in Fig. 29, the gate insulator layer 53 is provided on the top side 20.

[0125] According to Fig. 30, the semiconductor body 2 is etched starting from the top side 20 to the first barrier region 41, so that a trench is formed. Subsequently, see Fig. 31, the first electrode 31 is deposited in the trench, so that lateral sides of the first semiconductor region 21 and the plug region 24 are electrically connected by the first electrode 31. As indicated by a dot-dash line in Fig. As symbolically shown in Figure 31, the trench belongs to two cell units. That is, the dotted line from Fig. 31 corresponds to the dotted lines of the Fig. 1, 14, 15 and 18 to 21.

[0126] Otherwise, this can be for the Fig. 22 and Fig. 23 What has been said also applies to the Fig. 24 to 31 apply and vice versa.

[0127] In the Fig. 32 to 35 illustrates another method by which, for example, the semiconductor components 1 of the Fig. 19 to 21. The first steps of this process can be compared to the process steps of Fig. 24 to 29. However, after the gate insulator layer 53 has been applied, see Fig. 32, instead of etching the trench, the electrically conductive layer 47 is applied for a first of the second barrier regions 42. For example, the conductive layer 47 consists of poly-Si.

[0128] According to Fig. 33, the conductive layer 47 is structured to correspond to the second barrier region 42. Then, see Fig. 34, a second portion of the dielectric layer 48 is applied, for example, by oxidation analogous to the gate insulator layer 53. Consequently, the conductive layer 47 is surrounded by the dielectric layer 48. Optional electrical lines between the conductive layer 47 and one of the electrodes 31, 33 are not illustrated.

[0129] Then, see Fig. 35, a third part 83 of the semiconductor body 2 is applied. This is done, for example, by epitaxial overgrowth of, for example, Si. Then, semiconductor regions can be formed according to the Fig. 19 to 21 in the third part 83 as required.

[0130] If more than one second barrier area 42 as in the Fig. 19 to 21 is desired, then the steps of Fig. 28, 29 and 32 to 35 are to be repeated accordingly before the first electrode 31, as in the Fig. 30 and Fig. 31 shown.

[0131] Otherwise, if only a second barrier area 42 is to be formed, the step of Fig. 35 directly the steps of Fig. Connect 28 to 31.

[0132] Unless otherwise stated, the components shown in the figures follow one another directly above the other in the order shown, by way of example. Components that do not touch in the figures are spaced apart by way of example. If lines are drawn parallel to each other, the corresponding surfaces may be aligned parallel to each other. Likewise, unless otherwise stated, the relative positions of the drawn components are correctly represented in the figures.

[0133] The invention described here is not limited by the description based on the exemplary embodiments. Rather, the invention encompasses any novel feature as well as any combination of features, including, in particular, any combination of features in the patent claims, even if this feature or combination itself is not explicitly stated in the patent claims or exemplary embodiments. List of reference symbols 1 semiconductor component 2 semiconductor bodies 20 Top 21 first semiconductor region (source / emitter region) 22 second semiconductor region (drain / collector region) 23 Bath area 24 Plug area 25 Drift area 27 further first semiconductor area 28 Buffer area 31 first electrode (source / emitter electrode) 32 second electrode (drain / collector electrode) 33 Gate electrode 4 Starting material layer 41 first barrier area 42 second barrier area 44 dielectric layer 45 doped barrier layer 46 Opening 47 electrically conductive layer 48 additional dielectric layer 51 first electrode insulator layer 53 Gate insulator layer 81 first part of the semiconductor body 82 second part of the semiconductor body 83 third part of the semiconductor body 91 Reference component with planar design 92 Reference component with trench design E off Energy loss when switching off Fe main flow of electrodes Fn main flow of holes I c Current at the second electrode (collector electrode) I on Current at the second electrode in the switched-on state L BLength of the first barrier area of ​​a unit L pcont Length of the first electrical contact (emitter contact) M.. Process step P projection length S plane of symmetry t time T Temperature in K T B - Thickness of the first barrier area V ce Voltage between second and first electrode (collector and emitter electrode) V ce-SAT- Saturation voltage between second and first electrode (collector and emitter electrode) V ge Voltage between gate electrode and first electrode (emitter electrode) x lateral coordinate in µm y vertical coordinate in µm z third dimension QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited non-patent literature

[0000] M. Takei et al., “DB (Dielectric Barrier) IGBT with extreme injection enhancement”, 2010 22nd International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2010, pages 383-386

[0002]

Claims

[1] Semiconductor component (1), comprising: - a gate electrode (33) on an upper side (20) of a semiconductor body (2), - a first semiconductor region (21) of a first conductivity type on the top side (20), wherein the first semiconductor region (21) is a source region or an emitter region, - a plug region (24) of a second conductivity type, - a first electrode (31) which electrically contacts the first semiconductor region (21) and the plug region (24), - a well region (23) of the second conductivity type, in which the first semiconductor region (21) is at least partially embedded, and - at least one barrier region (41, 42) comprising a first barrier region (41) in the semiconductor body (2), wherein - at least a part of the well region (23) is located between the first barrier region (41) and the first semiconductor region (21), - the first barrier region (41) is a barrier for charge carriers of at least the second conductivity type, and - the first electrode (31) extends in a direction towards the first barrier region (41) deeper than or as deep as the first semiconductor region (21) into the semiconductor body (2). [2] Semiconductor component (1) according to the preceding claim, comprising at least one second barrier region (42) in the semiconductor body (2) between the first barrier region (41) and the first semiconductor region (21), wherein the at least one second barrier region (42) is a barrier for charge carriers of at least the second conductivity type, wherein at least one of the first electrode (31) or the plug region (24) extends along the at least one second barrier region (42) to the first barrier region (41). [3] Semiconductor component (1) according to the preceding claim, wherein the at least one second barrier region (42) comprises an electrically conductive layer (47) which is electrically insulated from the semiconductor body (2) by means of a further dielectric layer (48). [4] Semiconductor component (1) according to the preceding claim, wherein the electrically conductive layer (47) is in electrical contact with either the gate electrode (33) or the first electrode (31), and wherein at least one further first semiconductor region (27) of the first conductivity type is located on at least one main side of the second barrier layer (42) in direct contact with the at least one second barrier region (42) and is aligned parallel to the top side (20). [5] Semiconductor component (1) according to the preceding claim, comprising several of the second barrier areas (42), wherein main sides of a lowermost one of the second barrier regions (42) located adjacent to the first barrier region (41) are in direct contact with the plug region (24) and / or the tub region (23). [6] Semiconductor component (1) according to one of the two preceding claims, wherein at least one of the second barrier regions (42) is free of any further first semiconductor region (27) on at least one main side. [7] Semiconductor component (1) according to one of the preceding claims, wherein, as seen in plan view of the top side (20), the plug region (24) extends along the entire first semiconductor region (21) and / or the first semiconductor region (21) is completely and directly covered by an electrical insulator layer (51, 53), so that the first semiconductor region (21) is in electrical contact with the first electrode (31) only on a side surface of the first semiconductor region (21) which is oriented obliquely to the top side (20). [8] Semiconductor component (1) according to one of the preceding claims, wherein the first electrode (31) is in direct contact with the first barrier region (41). [9] Semiconductor component (1) according to one of claims 1 to 7, wherein the first barrier region (41) is completely covered by the semiconductor body (2) on a side of the first barrier region (41) facing the first semiconductor region (21). [10] Semiconductor component (1) according to one of the preceding claims, wherein the plug region (24) extends in a direction towards the first barrier region (41) deeper than the first semiconductor region (21) into the semiconductor body (2) and is in direct contact with the first barrier region (41). [11] Semiconductor component (1) according to one of the preceding claims, wherein the first barrier region (41) consists of or comprises a doped barrier layer (45) of the first conductivity type. [12] Semiconductor component (1) according to one of the preceding claims, wherein the first barrier region (41) consists of or comprises a dielectric layer (44). [13] Semiconductor component (1) according to one of the two preceding claims, wherein the first barrier layer (41) runs parallel to the top side (20) and is remote from the top side (20). [14] Semiconductor component (1) according to one of the preceding claims, wherein the semiconductor body (2) comprises a drift region (25) of the first conductivity type adjacent to the well region (23), wherein the first barrier region (41) extends into the drift region (23) in a direction parallel to the upper side (20). [15] Semiconductor component (1) according to the preceding claim, wherein the first barrier region (41) protrudes from the well region (23) into the drift region (25) with a protrusion length (P) which is between 30% and 300% of a width of the well region (23) along a same direction. [16] Semiconductor component (1) according to one of the two preceding claims, wherein the first barrier region (41) separates the drift region (25) from the well region (22) along a direction (z) perpendicular to the top side (20). [17] Semiconductor component (1) according to one of the preceding claims, wherein the first barrier region (41) comprises at least one opening (46) extending completely through the first barrier region (41), wherein the at least one opening (46), seen in plan view of the top side (20), is located next to the first semiconductor region (21) and the gate electrode (33). [18] Semiconductor component (1) according to one of the preceding claims, wherein the semiconductor body (2) comprises a second semiconductor region (22) on a bottom side opposite the top side (20), the second semiconductor region (22) is either a drain region of the first conductivity type or a collector region of the second conductivity type, so that the semiconductor component (1) is a field effect transistor or an insulated gate bipolar transistor. [19] A method for producing a semiconductor device (1) according to any one of the preceding claims, the method comprising the following steps in the order given: A) providing at least part of the semiconductor body (2), B) forming the first barrier region (41), and C) Applying the first electrode (31) and the gate electrode (33) to the semiconductor body. [20] Method according to the preceding claim, further comprising the following steps between steps B) and C), wherein in step A) only a first part of the semiconductor body (2) is provided: B1) forming a second part of the semiconductor body (2) over the first barrier region (41), B2) producing the first semiconductor region (21) and the plug region (24) in the second part, B3) forming a gate insulator layer (53) on the second part, and B4) Etching through the second part to the first barrier region (41).

Images