Isolated substrate and semiconductor device

Abstract

One objective is to provide a technology capable of suppressing a reduction in the quality of the external appearance and an insulation fault, such as a short circuit between circuit structures, attributable to residue from the plating of a semiconductor device. An insulating substrate (2) comprises: a ceramic substrate (2b); and a circuit structure (2a) connected to a front surface of the ceramic substrate (2b) and to which a semiconductor element (3) is to be mounted. An outer circumferential region of the circuit structure (2a) has, on one side of its rear surface connected to the ceramic substrate (2b), an excluded region (8) that is not in contact with the front surface of the ceramic substrate (2b).

Description

TECHNICAL AREA

[0001] The present disclosure relates to insulating substrates and semiconductor devices. BACKGROUND TECHNOLOGY

[0002] For example, patent document 1 proposes a semiconductor device with improved reliability of a connection between circuit structures and semiconductor elements.

[0003] An insulating substrate mounted on the semiconductor device undergoes a metallization / plating step to bond the circuit structures and semiconductor elements formed on a front surface of a ceramic substrate of the insulating substrate with a solder metal, followed by a deplating step. In the plating step, the entire insulating substrate is plated. In the deplating step, only the areas required for a solder metal bond are masked with resist materials, the plating in an area that does not require plating is dissolved in a deplating solution, and any remaining plating residue is then removed by blowing with air. DOCUMENTS ACCORDING TO THE STATE OF THE TECHNOLOGY PATENT DOCUMENT

[0004] Patent document 1: Published Japanese patent application no. 2007-311527 SUMMARY: PROBLEM TO BE SOLVED BY THE INVENTION

[0005] During the fabrication of circuit structures, however, these structures sometimes exhibit minute roll-offs on the outer perimeters of their interfaces with the ceramic substrate. These roll-offs are less likely to be exposed to airflow, so even after the deplating step, plating residue is likely to remain on the roll-offs. If the semiconductor device is fabricated with this plating residue remaining, the residue accumulated on the roll-offs could be washed away by thermal stress during a soldering process and by the flow of a sealing resin, thus reducing the quality of the semiconductor device's external appearance.Furthermore, if the plating residue flows in such a way that it crosses between the circuit structures, an insulation fault such as a short circuit between the circuit structures could occur.

[0006] In the technology disclosed in patent document 1, outer circumferential regions of the circuit structures have solder reservoir depressions, but the function of the solder reservoir depressions is limited to accumulating solder materials used to connect the semiconductor elements and the circuit structures, and a problem attributable to plating residue is not taken into account.

[0007] Thus, one objective of the present disclosure is to provide a technology capable of suppressing a reduction in the quality of the external appearance and an insulation fault such as a short circuit between circuit structures, which is attributable to a residue from the plating of a semiconductor device. MEANS TO SOLVE THE PROBLEM

[0008] An insulating substrate according to the present disclosure comprises: a ceramic substrate; and a circuit structure connected to a front surface of the ceramic substrate and to which a semiconductor element is to be mounted, wherein an outer circumferential part of the circuit structure has, on one side of its rear surface connected to the ceramic substrate, an excluded part which is not in contact with the front surface of the ceramic substrate. EFFECTS OF INVENTION

[0009] According to the present disclosure, it is likely that in a deplating step performed prior to connecting the circuit structure and the semiconductor element, a deplating solution penetrates to one side of the rear surface of the outer circumferential region of the circuit structure, and that exposure to air by blowing to remove any plating residue is enhanced, thus enabling more effective removal of any unnecessary plating residue. This can suppress a reduction in the quality of the external appearance and an insulation fault, such as a short circuit between circuit structures of a semiconductor device, which are attributable to plating residue.

[0010] These and other objectives, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description when carried out in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [ Fig. Figure 1] is a cross-sectional view of a semiconductor device according to embodiment 1. [ Fig. Figure 2] is a cross-sectional view of a semiconductor device according to embodiment 2. [ Fig. Figure 3] is a cross-sectional view of a semiconductor device according to embodiment 3. [ Fig. Figure 4] is a cross-sectional view of a semiconductor device according to a modification 1 of embodiment 3. [ Fig. Figure 5] is a cross-sectional view of a semiconductor device according to a modification 2 of embodiment 3. [ Fig. 6] includes a top view from above semiconductor elements, wherein a cross-sectional view along line AA and a cross-sectional view along line BB of a semiconductor device according to embodiment 4 are taken. [ Fig. Figure 7] is a top view from above a semiconductor element of a sub-area of ​​a semiconductor device according to a modification 1 of embodiment 4. [ Fig. Figure 8] is a top view from above of a semiconductor element of a sub-area of ​​a semiconductor device according to a modification 2 of embodiment 4. [ Fig. Figure 9] is a top view from above of a semiconductor element of a sub-area of ​​a semiconductor device according to a modification 3 of embodiment 4. DESCRIPTION OF THE EXECUTION FORMS<Ausführungsform 1>

[0011] With reference to the drawings, embodiment 1 is described below. Fig. Figure 1 is a cross-sectional view of a semiconductor device 100 according to embodiment 1.

[0012] As in Fig. As illustrated in Figure 1, the semiconductor device 100 comprises a base plate 1, an insulating substrate 2, semiconductor elements 3, a main terminal 4, a resin housing 5 and a sealing resin 6.

[0013] The base plate 1 is rectangular in plan view and is made of a material with a relatively high thermal conductivity such as copper, a copper alloy, aluminum and an aluminum alloy.

[0014] The insulating substrate 2 comprises front-side circuit structures 2a, a ceramic substrate 2b, and a back-side circuit structure 2c. The ceramic substrate 2b is made of a ceramic such as Al₂O₃, AlN, and Si₃N₄. The front-side circuit structures 2a and the back-side circuit structure 2c are made of a metal containing, for example, Cu as its main component. The front-side circuit structures 2a and the back-side circuit structure 2c are connected to a front surface and a back surface of the ceramic substrate 2b, respectively, by means of (not illustrated) solder materials and the like. The front-side circuit structures 2a are circuit structures to which the semiconductor elements 3 are to be mounted and have been selectively formed. That is, the number of front-side circuit structures 2a is two or more, and the circuits required for the semiconductor device 100 have been formed within them.

[0015] The rear electrodes (e.g., collector electrodes) of the semiconductor elements 3 are connected to the front circuit structures 2a via connecting materials 7 made of a lead-free solder, such as a Sn-Ag-based solder, to mount the semiconductor elements 3. The semiconductor elements 3 are power semiconductor elements made, for example, of Si, SiC, or GaN, and it is important to ensure high heat dissipation because the power semiconductor elements generate heat at high temperatures during operation. While two semiconductor elements 3 in Fig. As illustrated in Figure 1, the number of semiconductor elements 3 is not limited to two and need only be one or more.

[0016] The main terminal 4, containing Cu as the main component, is connected via connecting materials 7 to front electrodes (e.g. emitter electrodes or gate electrodes) of the semiconductor elements 3 in order to form different types of wiring, in order to form circuits necessary for the semiconductor device 100.

[0017] The resin housing 5 is formed from a highly heat-resistant resin, such as PPS, within a rectangular frame (top view). The resin housing 5 is fixed to an outer circumferential region of the base plate 1 with an adhesive (not illustrated) to surround the circuits, including the semiconductor elements 3. The resin housing 5 is filled with the sealing resin 6, such as an epoxy resin, to protect the circuits, including the semiconductor elements 3.

[0018] Next, a problem encountered during the fabrication of the insulating substrate 2 is described. One step in the fabrication of the insulating substrate 2 comprises a plating step to bond the front-side circuit structures 2a and the semiconductor elements 3 with solder, and a deplating step. In the plating step, the entire insulating substrate 2 is plated. In the deplating step, only the areas necessary for bonding with solder are masked with resist materials, the plating in an area that does not require plating is dissolved in a deplating solution for removal, and any remaining plating is then removed by blowing with air.

[0019] During the fabrication of the front-facing circuit structures 2a, the front-facing circuit structures 2a sometimes exhibit minute curls on the sides of the outer perimeters of their interfaces with the ceramic substrate 2b. It is less likely that the curls will be exposed to airflow by blowing, so it is likely that after the deplating step, plating residue will remain on the curls. If the semiconductor device 100 is fabricated with plating residue remaining, the plating residue accumulated on the curls could flow away due to thermal stress during a soldering operation and a current of the sealing resin 6, thus reducing the quality of the external appearance of the semiconductor device.Furthermore, if the residue of a plating crosses between the front-side circuit structures 2a, an insulation fault such as a short circuit between the front-side circuit structures 2a could occur.

[0020] In contrast, embodiment 1, as shown in Fig. Figure 1 illustrates that the outer circumferential regions of the front circuit structures 2a on the sides of their rear surfaces, which are connected to the ceramic substrate 2b, have excluded regions 8 that are not in contact with the front surface of the ceramic substrate 2b. The excluded regions 8 extend over the entire outer circumferential regions of the front circuit structures 2a.

[0021] The excluded sub-areas 8 are arranged as openings larger than the rolls in the sub-areas where the tiny rolls are formed, so that the deplating solution can sufficiently penetrate to the sides of the rear surfaces of the outer circumferential sub-areas of the front circuit structures 2a and wind exposure can be improved by blowing with air. This reduces the plating residue.

[0022] As described above, the semiconductor device 100 according to embodiment 1 comprises the insulating substrate 2, the semiconductor elements 3 mounted on the front surfaces of the front circuit structures 2a and the base plate 1 connected to one side of the rear surface of the ceramic substrate 2b.

[0023] The insulating substrate 2 comprises the ceramic substrate 2b and the front-side circuit structures 2a, which are connected to the front surface of the ceramic substrate 2b and to which the semiconductor elements 3 are to be mounted. The outer circumferential regions of the front-side circuit structures 2a have, on the sides of their rear surfaces that are connected to the ceramic substrate 2b, the recessed regions 8 that are not in contact with the front surface of the ceramic substrate 2b.

[0024] Consequently, it is likely that in the deplating step, which is performed before connecting the front-side circuit structures 2a and the semiconductor elements 3, the deplating solution penetrates to the sides of the rear surfaces of the outer circumferential regions of the front-side circuit structures 2a, and that exposure to air by blowing to remove the plating residue is enhanced, thus enabling more effective removal of any unnecessary plating residue. This can suppress the reduction of external appearance and insulation faults, such as short circuits between the front-side circuit structures 2a of the semiconductor device 100, which are attributable to plating residue.

[0025] The durability and yield of the insulating substrate 2 and the semiconductor device 100 can be improved as a result. <Ausführungsform 2>

[0026] Next, a semiconductor device 200 according to embodiment 2 is described. Fig. Figure 2 is a cross-sectional view of the semiconductor device 200 according to embodiment 2. In embodiment 2, the same components as those described in embodiment 1 bear the same reference numerals as those of the same components, and their description is omitted.

[0027] As in Fig. As illustrated in Figure 2, in embodiment 2 the front circuit structures 2a do not have the excluded sub-areas 8 and the ceramic substrate 2b has excluded sub-areas 9.

[0028] The excluded sections 9 are formed in sections of the ceramic substrate 2b adjacent to the outer circumferential sections of the front-facing circuit structures 2a, such that they are recessed downwards. Specifically, the excluded sections 9 are formed opposite the entire outer circumferential sections of the front-facing circuit structures 2a in the direction of an outer circumference of the ceramic substrate 2b. The excluded sections 9 are formed such that the outer circumferential sections of the front-facing circuit structures 2a are not in contact with the ceramic substrate 2b.

[0029] The excluded sub-areas 9 are arranged as openings larger than the sub-areas in sub-areas adjacent to those where the tiny rolls are formed, so that the deplating solution can sufficiently penetrate to the sides of the rear surfaces of the outer circumferential sub-areas of the front circuit structures 2a and wind exposure can be improved by blowing with air. This reduces the plating residue.

[0030] As described above, in the semiconductor device 200 according to embodiment 2, the insulating substrate 2 comprises the ceramic substrate 2b and the front-side circuit structures 2a, which are connected to the front surface of the ceramic substrate 2b and to which the semiconductor elements 3 are to be mounted. The portions of the ceramic substrate 2b adjacent to the outer circumferential portions of the front-side circuit structures 2a have the downwardly recessed recessed portions 9.

[0031] Thus, it is likely that in the deplating step performed prior to connecting the front-side circuit structures 2a and the semiconductor elements 3, the deplating solution penetrates to the sides of the rear surfaces of the outer circumferential regions of the front-side circuit structures 2a, and that exposure to air by blowing to remove the plating residue is enhanced, allowing for more effective removal of the residue of unnecessary plating. This can suppress the reduction of external appearance and insulation faults, such as short circuits between the front-side circuit structures 2a of the semiconductor device 200, which are attributable to the plating residue. <Ausführungsform 3>

[0032] Next, a semiconductor device 300 according to embodiment 3 is described. Fig. Figure 3 is a cross-sectional view of the semiconductor device 300 according to embodiment 3. In embodiment 3, the same components as those described in embodiments 1 and 2 bear the same reference numerals as those of the same components, and their description is omitted.

[0033] As in Fig. As illustrated in Figure 3, in embodiment 3 the excluded sub-areas 8 and 9 are not formed, and the outer circumferential sub-areas of the front-side circuit structures 2a have conical or tapered shapes 10, such that the front-side circuit structures 2a taper from their rear surfaces connected to the ceramic substrate 2b to their front surfaces to which the semiconductor elements 3 are mounted. The tapered shapes 10 are formed over the entire outer circumferential sub-areas of the front-side circuit structures 2a.

[0034] The outer circumferential regions of the front circuit structures 2a have the tapered shapes 10, such that the outer circumferential surfaces of the front circuit structures 2a point upwards, it is likely that the deplating solution penetrates to the entire outer circumferential regions of the front circuit structures 2a and that the wind exposure by blowing with air to remove the residue of a plating is improved, so that the residue of an unnecessary plating can be removed more effectively.

[0035] As described above, in the semiconductor device 300 according to embodiment 3, the insulating substrate 2 comprises the ceramic substrate 2b and the front-side circuit structures 2a, which are connected to the front surface of the ceramic substrate 2b and to which the semiconductor elements 3 are to be mounted. The outer circumferential regions of the front-side circuit structures 2a have the tapered shapes 10, such that the front-side circuit structures 2a taper from their rear surfaces connected to the ceramic substrate 2b to their front surfaces, to which the semiconductor elements 3 are to be mounted.

[0036] Thus, it is likely that in the deplating step performed prior to connecting the front-side circuit structures 2a and the semiconductor elements 3, the deplating solution penetrates the entire outer circumferential region of the front-side circuit structures 2a, and that exposure to air by blowing to remove the plating residue is enhanced, allowing for more effective removal of the residue of unnecessary plating. This can suppress the reduction in the quality of the external appearance and insulation faults, such as short circuits between the front-side circuit structures 3a of the semiconductor device 300, which are attributable to the plating residue. <Modifikationen der Ausführungsform 3>

[0037] Next, modifications 1 and 2 of embodiment 3 are described. Fig. Figure 4 is a cross-sectional view of a semiconductor device 400 according to modification 1 of embodiment 3. Fig. Figure 5 is a cross-sectional view of a semiconductor device 500 according to modification 2 of embodiment 3.

[0038] As in Fig. As illustrated in Figure 4, the tapered shapes 11 of the outer circumferential sections of the front-side circuit structures 2a can be curved shapes. As shown in Fig. As illustrated in Figure 5, the tapered shapes 12 of the outer circumferential regions of the front-side circuit structures 2a can be stepped shapes. In each of these cases, an effect similar to that obtained in embodiment 3 is achieved. <Ausführungsform 4>

[0039] Next, a semiconductor device 600 according to embodiment 4 is described. Fig. Figure 6(a) is a top view from above the semiconductor elements 3 of the semiconductor device 600 according to embodiment 4. Fig. 6(b) is a line along the AA line of Fig. 6(a) cross-sectional view taken, and Fig. 6(c) is along line BB of Fig. 6(a) Cross-sectional view. In embodiment 4, the same components as those described in embodiments 1 to 3 bear the same reference numerals as those of the same components, and their description is omitted.

[0040] As in Fig. As illustrated in Figure 6(a), in embodiment 4, cut-out sections 13 are formed instead of the excluded sub-areas 8 and 9 and the tapered shapes 10, 11, and 12. The cut-out sections 13 are a plurality of cut-out sections 13 that are successively formed over the entire outer circumferential sub-areas of the front-facing circuit structures 2a. Specifically, the cut-out sections 13 are rectangular in plan view, and each side of the front-facing circuit structures 2a has two cut-out sections 13.

[0041] As in Fig. 6(a), Fig. 6(b) and Fig. As illustrated in Figure 6(c), the cut-out sections 13 are each designed to have the same thickness as each of the front-facing circuit structures 2a. As shown in Fig. 6(a) and Fig. As illustrated in Figure 6(b), a sub-section of each of the front-side circuit structures 2a without the cut-out sub-sections 13 has the same width d2 as a conventional structure without the cut-out sub-sections 13.

[0042] In the conventional structure without the cut-out sections 13, each side in the outer circumferential sections of the front-side circuit structures 2a has a width d2. During the manufacturing of the semiconductor device, a plating residue with a length corresponding to the width d2 could accumulate and flow in such a way that it crosses between adjacent front-side circuit structures 2a over a length d1, so that the plating residue could cause the insulation fault, such as a short circuit, between the front-side circuit structures 2a. Here, d2 ≥ d1.

[0043] In contrast, in embodiment 4, the width d3 on each side in the outer circumferential regions of the front-side circuit structures 2a is sufficiently shorter than the length d1 between adjacent cut-out sections 13 in the outer circumferential regions of the front-side circuit structures 2a (d3 < d1). Even if, during the manufacture of the semiconductor device 600, a plating residue with a length corresponding to the width d3 accumulates and flows in such a way that it crosses between the front-side circuit structures 2a over the length d1, contact between the plating residue and an adjacent front-side circuit structure 2a can thus be suppressed.

[0044] As described above, in the semiconductor device 600 according to embodiment 4, the insulating substrate 2 comprises the ceramic substrate 2b and the front-side circuit structures 2a, which are connected to the front surface of the ceramic substrate 2b and to which the semiconductor elements 3 are to be mounted. The outer circumferential regions of the front-side circuit structures 2a have a plurality of successively cut-out sub-regions 13. The cut-out sub-regions 13 are each rectangular in plan view.

[0045] Even if, during the manufacturing of the semiconductor device 600, the plating residue flows in such a way that it crosses between the adjacent front-side circuit structures 2a, contact between the plating residue and the adjacent front-side circuit structure 2a can thus be suppressed. A reduction in the quality of the external appearance and insulation defects, such as short circuits between the front-side circuit structures 2a of the semiconductor device 600, which are attributable to the plating residue, can thereby be suppressed. <Modifikationen der Ausführungsform 4>

[0046] Next, modifications 1 to 3 of embodiment 4 are described. Fig. Figure 7 is a top view from above a semiconductor element 3 of a partial area of ​​a semiconductor device 700 according to a modification 1 of embodiment 4. Fig. Figure 8 is a top view from above a semiconductor element 3 of a partial area of ​​a semiconductor device 800 according to a modification 2 of embodiment 4. Fig. Figure 9 is a top view from above a semiconductor element 3 of a partial area of ​​a semiconductor device 900 according to a modification 3 of embodiment 4.

[0047] As in Fig. As illustrated in 7, cut-out sections 14 can each be triangular in top view. As in Fig. As illustrated in Figure 8, cut-out sections 15 can each be stepped in the top view. As shown in Fig. As illustrated in Figure 9, cut-out sections 16 can each be arc-shaped in plan view. A similar effect to that obtained in one instance of embodiment 4 can be obtained in each of these cases.

[0048] Although the present revelation has been described in detail, the preceding description is illustrative in all aspects and not limiting. It is therefore understood that numerous, unillustrated modifications can be conceived.

[0049] The embodiments can be freely combined and can be modified or omitted as necessary. EXPLANATION OF THE REFERENCE SYMBOLS

[0050] 1 Base plate, 2 Insulating substrate, 2a Front-facing circuit structure, 2b Ceramic substrate, 3 Semiconductor element, 8, 9 Cut-out section, 10 Tapered shape, 11 Curved shape, 12 Stepped shape, 13, 14, 15, 16 Cut-out section, 100, 200, 300, 400, 500, 600, 700, 800, 900 Semiconductor device QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2007-311527

[0004]

Claims

[1] Insulating substrate comprising: a ceramic substrate; and a circuit structure that is connected to a front surface of the ceramic substrate and to which a semiconductor element is to be mounted, wherein an outer circumferential part of the circuit structure on one side of its rear surface, which is connected to the ceramic substrate, has an excluded part that is not in contact with the front surface of the ceramic substrate. [2] Insulating substrate comprising: a ceramic substrate; and a circuit structure that is connected to a front surface of the ceramic substrate and to which a semiconductor element is to be mounted, wherein a sub-area of ​​the ceramic substrate, adjacent to an outer circumferential sub-area of ​​the circuit structure, has a downwardly recessed recessed sub-area. [3] Insulating substrate comprising: a ceramic substrate; and a circuit structure that is connected to a front surface of the ceramic substrate and to which a semiconductor element is to be mounted, wherein An outer circumferential part of the circuit structure has a tapered shape, so that the circuit structure tapers from its rear surface connected to the ceramic substrate to its front surface, to which the semiconductor element is to be mounted. [4] Insulating substrate according to claim 3, wherein the tapered shape of the outer circumferential part of the circuit structure is a curved shape. [5] Insulating substrate according to claim 3, wherein the tapered shape of the outer circumferential part of the circuit structure is a stepped shape. [6] Insulating substrate comprising: a ceramic substrate; and a circuit structure connected to a front surface of the ceramic substrate to which a semiconductor element is to be mounted, wherein an outer circumferential part of the circuit structure has a plurality of successively cut-out sub-areas. [7] Insulating substrate according to claim 6, wherein the cut-out sections are rectangular, triangular, stepped or arc-shaped in plan view. [8] Insulating substrate according to claim 6 or 7, wherein The circuit structure exhibits a variety of circuit structures and a length between adjacent cut-out sub-areas of the outer circumferential sub-area of ​​each of the circuit structures is shorter than a length between adjacent circuit structures. [9] Semiconductor device comprising: the insulating substrate according to any one of claims 1 to 8; the semiconductor element that is mounted to a front surface of the circuit structure; and a base plate that is connected to one side of a rear surface of the ceramic substrate.

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