Device, memory, and data structure for determining a measure of accuracy of in-memory computing hardware for determining an output of a neural network

Abstract

Device (100) for determining a measure of the accuracy of in-memory computing hardware for determining an output of a neural network, in particular for designing the computing hardware, wherein the computing hardware comprises memory cells representing weights of the neural network, wherein the computing hardware comprises at least one memory cell for detecting or correcting an error in at least one of the memory cells, wherein the neural network comprises at least one layer, wherein the device (100) is configured to generate an error associated with at least one memory cell representing a weight of the at least one layer, and wherein the device (100) is configured to detect the output of the neural network comprising the error in response to an input to the neural network.is configured to provide a true output for the input and to determine the measure depending on the output and the true output.

Description

State of the art

[0001] The invention relates to a device, a memory and a data structure for determining a measure of accuracy of in-memory computing hardware for determining an output of a neural network.

[0002] In-memory computation is used to accelerate calculations of the output of neural networks. Disclosure of the invention

[0003] A device for determining a measure of accuracy of in-memory computing hardware for determining an output of a neural network, in particular for designing the computing hardware, wherein the computing hardware comprises memory cells representing weights of the neural network, wherein the computing hardware comprises at least one memory cell for detecting or correcting an error in at least one of the memory cells, wherein the neural network comprises at least one layer, wherein the device is configured to generate an error associated with at least one memory cell representing a weight of the at least one layer, wherein the device is configured to detect the output of the neural network comprising the error in response to an input to the neural network, to provide a true output for the input, and to determine the measure as a function of the output and the true output.

[0004] It may be provided that the device is configured to determine as a measure a divergence of pairs of an output and a true output or to determine a divergence of pairs of an output and a true output and to determine the measure as a function of the divergence.

[0005] It can be provided that the device is configured to generate the error in the at least one memory cell of the at least one layer in a first iteration, to determine the measure as a function of the output and the true output in the first iteration, to generate a further error in the at least one memory cell in a second iteration or to generate the error in at least one other memory cell of the at least one layer, to determine the output and the true output in the second iteration as a function of the input or as a function of another input and to determine the measure as a function of the output and the true output in the second iteration.

[0006] It may be provided that the neural network comprises a further layer, wherein the device is configured to generate the error in at least one memory cell of the further layer in a third iteration, to determine the output and the true output in dependence on the input or in dependence on another input in the third iteration, and to determine the measure in dependence on the output and the true output in the third iteration.

[0007] It can be provided that the device is configured to determine the measure for a first design of the computing hardware and to determine the measure for a second design of the computing hardware, wherein the first design and the second design are distinguished by a number of memory cells for detecting or correcting the error or by a number of memory cells that are protected by the at least one memory cell for detecting or correcting the error, or by the selection of memory cells that are protected by the at least one memory cell for detecting or correcting the error, wherein the device is configured to output the measure determined for the first design and the measure determined for the second design.

[0008] It may be provided that the device is configured to determine the first design and the second design.

[0009] It may be provided that the device is configured to link the first design to a first area occupied by the memory cells for detecting or correcting the error in the computing hardware according to the first design, to link the second design to a second area occupied by the memory cells for detecting or correcting the error in the computing hardware according to the second design, and to output the first area and the second area.

[0010] It may be provided that the device is configured to determine a first latency for the first design, output the measure determined for the first design and the first area associated with the first latency, determine a second latency for the second design, and output the measure determined for the second design and the second area associated with the second latency.

[0011] Non-volatile memory, wherein the non-volatile memory stores computer-readable instructions that, when executed by a computer, cause the computer to perform a method for determining a measure of accuracy of in-memory computing hardware for determining an output of a neural network, in particular for designing the computing hardware, wherein the computing hardware comprises memory cells representing weights of the neural network, wherein the computing hardware comprises at least one memory cell for detecting or correcting an error in at least one of the memory cells, wherein the neural network comprises at least one layer, the method comprising: generating an error associated with at least one memory cell representing a weight of the at least one layer, detecting the output of the neural network comprising the error in response to an input to the neural network,Providing a true output for the input and determining the measure as a function of the output and the true output.,

[0012] It may be provided that the method comprises: determining a divergence of pairs of an output and a true output as the measure or determining a divergence of pairs of an output and a true output and determining the measure as a function of the divergence.

[0013] It can be provided that the method comprises: generating the error in the at least one memory cell of the at least one layer in a first iteration, determining the measure as a function of the output and the true output in the first iteration, generating a further error in the at least one memory cell or generating the error in at least one other memory cell of the at least one layer in a second iteration, determining the output and the true output in the second iteration as a function of the input or as a function of another input and determining the measure as a function of the output and the true output in the second iteration.

[0014] It can be provided that the neural network comprises a further layer, wherein the method comprises generating the error in at least one memory cell of the further layer in a third iteration, determining the output and the true output in the third iteration as a function of the input or as a function of another input, and determining the measure as a function of the output and the true output in the third iteration.

[0015] It can be provided that the method comprises determining the measure for a first design of the computing hardware and determining the measure for a second design of the computing hardware, wherein the first design and the second design are distinguished by a number of memory cells for detecting or correcting the error or by a number of memory cells protected by the at least one memory cell for detecting or correcting the error, or by the selection of memory cells protected by the at least one memory cell for detecting or correcting the error, and outputting the measure determined for the first design and the measure determined for the second design.

[0016] It may be provided that the method comprises determining the first design and the second design.

[0017] It may be provided that the method comprises assigning the first design to a first area which the memory cells consume to detect or correct the error in the computing hardware according to the first design, assigning the second design to a second area which the memory cells consume to detect or correct the error in the computing hardware according to the second design, and outputting the first area and the second area.

[0018] It may be provided that the method comprises: determining a first latency for the first design, outputting the measure determined for the first design and the first area associated with the first latency, determining a second latency for the second design, and outputting the measure determined for the second design and the second area associated with the second latency.

[0019] Data structure for determining a measure of accuracy of in-memory computing hardware for determining an output of a neural network, in particular for designing the computing hardware, wherein the computing hardware comprises memory cells representing weights of the neural network, wherein the computing hardware comprises at least one memory cell for detecting or correcting an error in at least one of the memory cells, wherein the neural network comprises at least one layer, wherein the data structure comprises at least one data field for generating an error associated with at least one memory cell representing a weight of the at least one layer, wherein the data structure comprises at least one data field for the output of the neural network comprising the error detected in response to an input to the neural network,for a true output for the input and for the measure determined depending on the output and the true output.,

[0020] It can be provided that the data structure comprises at least one data field in order to determine, as a measure, a divergence of pairs of an output and a true output or in order to determine a divergence of pairs of an output and a true output and to determine the measure as a function of the divergence.

[0021] It can be provided that the data structure comprises at least one data field in order to generate the error in the at least one memory cell of the at least one layer in a first iteration, to determine the measure as a function of the output and the true output in the first iteration, to generate a further error in the at least one memory cell in a second iteration or to generate the error in at least one other memory cell of the at least one layer, to determine the output and the true output in the second iteration as a function of the input or as a function of another input and to determine the measure as a function of the output and the true output in the second iteration.

[0022] It can be provided that the neural network comprises a further layer, wherein the data structure comprises at least one data field in order to generate the error in at least one memory cell of the further layer in a third iteration, to determine the output and the true output in the third iteration as a function of the input or as a function of another input and to determine the measure as a function of the output and the true output in the third iteration.

[0023] It can be provided that the data structure comprises at least one data field for determining the measure for a first design of the computing hardware and for determining the measure for a second design of the computing hardware, wherein the first design and the second design are separated by a number of memory cells for detecting or correcting the error or by a number of memory cells that are protected by the at least one memory cell for detecting or correcting the error, or by the selection of memory cells that are protected by the at least one memory cell for detecting or correcting the error, wherein the data structure comprises at least one data field for outputting the measure determined for the first design and the measure determined for the second design.

[0024] It may be provided that the data structure comprises at least one data field for determining the first design and the second design.

[0025] It can be provided that the data structure comprises at least one data field for linking the first design to a first area occupied by the memory cells for detecting or correcting the error in the computing hardware according to the first design, for linking the second design to a second area occupied by the memory cells for detecting or correcting the error in the computing hardware according to the second design, and for outputting the first area and the second area.

[0026] It can be provided that the data structure has at least one data field for determining a first latency for the first design, for outputting the measure determined for the first design and the first area associated with the first latency, for determining a second latency for the second design, and for outputting the measure determined for the second design and the second area associated with the second latency.

[0027] Further embodiments can be found in the following description and the drawing. The drawing shows: Fig. 1 is a schematic representation of an apparatus for determining a measure of accuracy of in-memory computing hardware for determining an output of a neural network, Fig. 2 a schematic representation of an output of the device, Fig. 3 a data structure for determining the measure.

[0028] In Fig. 1 is an apparatus 100 for determining a measure of accuracy of in-memory computing hardware for determining an output f (x i ) of a neural network f for an input x i shown schematically.

[0029] The neural network f comprises at least one layer. In the example, the neural network f comprises an input layer, an output layer, and a hidden layer between the input layer and the output layer. Each layer contains neurons. In the example, the neurons of the input layer are connected to the neurons of the hidden layer via weighted connections. In the example, the neurons of the hidden layer are connected to the neurons of the output layer via weighted connections.

[0030] The neural network f can have fewer than three or more than three layers. The neurons of interconnected layers can be partially or completely connected by the connections.

[0031] In the example, the output of an exemplary neuron is the weighted sum of the input at the connections leading to the exemplary neuron.

[0032] The computing hardware includes memory cells that represent the weights of the neural network. The memory cells that represent the weights each contain, for example, a resistor that represents a weight of the neural network.

[0033] For example, the computing hardware is configured to capture the weighted sum for the exemplary neuron by measuring a sum current. For example, the sum current is captured by the memory cells containing the resistors representing the weights of the weighted sum.

[0034] The computing hardware comprises at least one memory cell for detecting or correcting an error in at least one of the memory cells. The at least one memory cell for detecting or correcting the error comprises, for example, a resistor which is the sum of the resistances of several memory cells monitored by the at least one memory cell. The computing hardware is designed, for example, to detect the current through this memory cell when one memory cell is used to detect or correct the error. The computing hardware is designed, for example, to detect the total current through these memory cells when several memory cells are used to detect or correct the error.

[0035] The computing hardware is configured to perform in-memory calculations depending on the resistances in the memory cells. The computing hardware includes, for example, digital-to-analog converters for generating the input and analog-to-digital converters for capturing the output. The output represents a result of the in-memory calculation. The computing hardware includes, for example, registers for storing the output digitized by the analog-to-digital converters as the result.

[0036] The register contains bits, for example, for binary storage of the result.

[0037] The computing hardware is designed to detect and correct the result depending on an output of the at least one memory cell for detecting or correcting the error.

[0038] The at least one memory cell for detecting or correcting the error protects, for example, one bit of the result. The at least one memory cell for detecting or correcting the error protects, for example, multiple bits of the result.

[0039] The device 100 comprises at least one processor 102 and at least one memory 104. The at least one memory 104 comprises a non-volatile memory. The device 100 comprises a human-machine interface 106. The human-machine interface 106 comprises, for example, a display for displaying the measurement. The human-machine interface 106 comprises, for example, an input device for detecting an input from a user.

[0040] The non-volatile memory includes computer-readable instructions that, when executed by a computer, cause the computer to perform a method for determining a measure of accuracy of in-memory computing hardware for determining an output of a neural network.

[0041] The device 100 is designed to carry out the method.

[0042] The method is carried out in particular for designing a design of the computing hardware.

[0043] The procedure includes the following steps: - Generating an error associated with at least one memory cell representing a weight of the layer. - Capture the output f'(x i ) of the neural network that includes the error in response to an input x i into the neural network. - Providing a true output f (x i ) for the input x i . - Determine the measure depending on the output f'(x i ) and the true output f(x i ).

[0044] The measure is determined repeatedly in iterations, for example, where different inputs x i given, different errors are generated, the error is generated in different memory cells of the same layer or, in the case of a multi-layer neural network, in different layers.

[0045] The measure is determined, for example, for a layer l of the neural network.

[0046] The measure is determined, for example, for different designs k of the computing hardware.

[0047] For example, the measure for layer l for design k is a divergence. In the example, the measure is the Kullback-Leibler divergence KL l of pairs from an output f'(x i ) and a true outcome f (x i ): KLl(k)=∑if(xi)logf(xi)f'(xi)k

[0048] The following description uses the Kullback-Leibler divergence as an example. Instead of the Kullback-Leibler divergence of pairs, the measure can also be another divergence, e.g., the Jensen-Shannon divergence. It can also be specified that the measure is determined depending on the divergence.

[0049] The designs differ, for example, in - a number of memory cells for detecting or correcting the error, - by a number of memory cells protected by the at least one memory cell for detecting or correcting the error, - by selecting memory cells protected by the at least one memory cell for detecting or correcting the error.

[0050] The method may include outputting the dimensions determined for the designs.

[0051] The method may include associating the respective design with a respective area that the memory cells consume to detect or correct the error in the computing hardware according to the respective design.

[0052] The method may provide for the output of the respective area.

[0053] The method includes, for example, outputting the measurement determined for the respective design and the respective area in a respective display area of ​​the display that corresponds to the size of the area required for the respective design.

[0054] The device 100 is configured, for example, to execute the method by means of a simulation of the computing hardware. This means that the computing hardware is simulated in the method. The device 100 is configured, for example, to execute the method by means of the computing hardware. This means that the computing hardware is used in the method.

[0055] In Fig. Figure 2 schematically illustrates an output 200 of the device 100 for the computing hardware, wherein the computing hardware implements a Resnet20 with FeFET memory cells. The output 200 represents the accuracy 202 on the x-axis, the latency 204 on the right y-axis, and the area 206 on the left y-axis.

[0056] The accuracy 202 is proportional to the Kullback-Leibler divergence. In the example, the measure is represented as accuracy 202.

[0057] The latency 204 for a given accuracy value is caused by the number of additional computation cycles performed to correct the error in order to achieve the accuracy value.

[0058] The area 206 is the area required for the at least one memory cell to detect or correct the error in the computing hardware according to the respective design.

[0059] The output 200 represents the area 208 and the latency 210 for two protected bits of the result, the area 212 and the latency 214 for three protected bits of the result, the area 216 and the latency 218 for four protected bits and a Pareto value 220 for the area and a Pareto value 22 for the latency.

[0060] The output determination is not limited to computing hardware with FeFET memory cells. The output is determined accordingly for computing hardware with other memory cells, such as RRAM memory cells.

[0061] The determination of the output is not limited to a specific neural network architecture. The output is determined accordingly for Rasnet32 or NiN, for example.

[0062] For example, layer-by-layer optimization is provided to improve the throughput of the neural network architecture by selecting appropriate approximation levels for each layer. For example, dynamic programming is provided to generate the Pareto front of accuracy and area for different configurations. The cost of the Pareto front is defined as the area for the different designs. The optimization, for example, requires that at least one configuration is searched for and found that minimizes the cumulative latency and requires the least area.

[0063] In Fig. 3, a data structure 300 for determining the measure is shown schematically.

[0064] The data structure 300 includes at least one data field 302 for generating an error associated with at least one memory cell representing a weight of the layer.

[0065] The data structure 300 includes at least one data field 302 for the output of the neural network, which includes the error detected in response to an input to the neural network.

[0066] The data structure 300 includes at least one data field 302 for the true output for the input.

[0067] The data structure 300 includes at least one data field 302 for the measure determined as a function of the output and the true output.

[0068] For the Kullback-Leibler divergence, the data structure 300 comprises at least one data field 302 to determine as a measure the Kullback-Leibler divergence of pairs of an output and a true output, or to determine the Kullback-Leibler divergence of pairs of an output and a true output and to determine the measure as a function of the Kullback-Leibler divergence.

[0069] The data structure 300 comprises, for example, at least one data field 302 to generate the error in the at least one memory cell of the layer in a first iteration, to determine the measure as a function of the output and the true output in the first iteration.

[0070] The data structure 300 comprises, for example, at least one data field 302 to generate a further error in the at least one memory cell in a second iteration or to generate the error in at least one other memory cell of the layer.

[0071] The data structure 300 comprises, for example, at least one data field 302 for determining the output and the true output in the second iteration depending on the input or depending on another input and determining the measure depending on the output and the true output in the second iteration.

[0072] In the event that the neural network comprises a further layer, the data structure 300 comprises, for example, at least one data field to generate the error in at least one memory cell of the further layer in a third iteration, to determine the output and the true output in the third iteration as a function of the input or as a function of another input, and to determine the measure as a function of the output and the true output in the third iteration.

[0073] For a first design and a second design, the data structure 300 may include at least one data field 302 for determining the dimension for the first design of the computing hardware and for determining the dimension for the second design of the computing hardware. For example, the data structure 300 includes at least one data field 302 for determining the first design and the second design.

[0074] The first design and the second design differ, for example, in a number of memory cells for detecting or correcting the error or in a number of memory cells that are protected by the at least one memory cell for detecting or correcting the error.

[0075] The first design and the second design differ, for example, in the selection of memory cells protected by the at least one memory cell for detecting or correcting the error.

[0076] The data structure 300 includes, for example, at least one data field 302 for outputting the dimension determined for the first design and the dimension determined for the second design.

[0077] The data structure 300 includes, for example, at least one data field 302 for linking the first design to a first area occupied by the memory cells for detecting or correcting the error in the computing hardware according to the first design.

[0078] The data structure 300 includes, for example, at least one data field 302 for linking the second design to a second area occupied by the memory cells for detecting or correcting the error in the computing hardware according to the second design.

[0079] The data structure 300 includes, for example, at least one data field 302 to output the first area and the second area.

[0080] The data structure 300 includes, for example, at least one data field 302 for determining a first latency for the first design.

[0081] The data structure 300 includes, for example, at least one data field 302 for outputting the measure determined for the first design and the first area associated with the first latency.

[0082] The data structure 300 includes, for example, at least one data field 302 for determining a second latency for the second design.

[0083] The data structure 300 comprises, for example, at least one data field 302 for outputting the measure determined for the second design and the second area associated with the second latency.

Claims

[1] Apparatus (100) for determining a measure of accuracy of in-memory computing hardware for determining an output of a neural network, in particular for designing the computing hardware, wherein the computing hardware comprises memory cells representing weights of the neural network, wherein the computing hardware comprises at least one memory cell for detecting or correcting an error in at least one of the memory cells, wherein the neural network comprises at least one layer, wherein the apparatus (100) is configured to generate an error associated with at least one memory cell representing a weight of the at least one layer, wherein the apparatus (100) is configured to detect the output of the neural network comprising the error in response to an input to the neural network,configured to provide a true output for the input and to determine the measure depending on the output and the true output., [2] Device (100) according to claim 1, characterized by that the device (100) is configured to determine as a measure a divergence of pairs of an output and a true output or to determine a divergence of pairs of an output and a true output and to determine the measure as a function of the divergence. [3] Device (100) according to one of the preceding claims, characterized byin that the device (100) is configured to generate the error in the at least one memory cell of the at least one layer in a first iteration, to determine the measure as a function of the output and the true output in the first iteration, to generate a further error in the at least one memory cell in a second iteration or to generate the error in at least one other memory cell of the at least one layer, to determine the output and the true output in the second iteration as a function of the input or as a function of another input and to determine the measure as a function of the output and the true output in the second iteration. [4] Device (100) according to one of the preceding claims, characterized byin that the neural network comprises a further layer, wherein the device (100) is configured to generate the error in at least one memory cell of the further layer in a third iteration, to determine the output and the true output in dependence on the input or in dependence on another input in the third iteration, and to determine the measure in dependence on the output and the true output in the third iteration. [5] Device (100) according to one of the preceding claims, characterized byin that the device (100) is configured to determine the measure for a first design of the computing hardware and to determine the measure for a second design of the computing hardware, wherein the first design and the second design are distinguished by a number of memory cells for detecting or correcting the error or by a number of memory cells protected by the at least one memory cell for detecting or correcting the error, or by the selection of memory cells protected by the at least one memory cell for detecting or correcting the error, wherein the device (100) is configured to output the measure determined for the first design and the measure determined for the second design. [6] Device (100) according to claim 5, characterized by that the device (100) is configured to determine the first design and the second design. [7] Device (100) according to claim 6, characterized byin that the device (100) is configured to link the first design to a first area occupied by the memory cells for detecting or correcting the error in the computing hardware according to the first design, to link the second design to a second area occupied by the memory cells for detecting or correcting the error in the computing hardware according to the second design, and to output the first area and the second area. [8] Device (100) according to claim 7, characterized by in that the device (100) is configured to determine a first latency for the first design, output the measure determined for the first design and the first area associated with the first latency, determine a second latency for the second design, and output the measure determined for the second design and the second area associated with the second latency. [9] Non-volatile memory (104), characterized bythat the non-volatile memory (104) stores computer-readable instructions that, when executed by a computer, cause the computer to perform a method for determining a measure of accuracy of in-memory computing hardware for determining an output of a neural network, in particular for designing the computing hardware, wherein the computing hardware comprises memory cells representing weights of the neural network, wherein the computing hardware comprises at least one memory cell for detecting or correcting an error in at least one of the memory cells, wherein the neural network comprises at least one layer, the method comprising: generating an error associated with at least one memory cell representing a weight of the at least one layer, detecting the output of the neural network comprising the error in response to an input to the neural network,Providing a true output for the input and determining the measure as a function of the output and the true output., [10] The memory (104) according to claim 9, characterized by that the method comprises: determining a divergence of pairs of an output and a true output as the measure or determining a divergence of pairs of an output and a true output and determining the measure as a function of the divergence. [11] The memory (104) according to one of claims 9 or 10, characterized bythat the method comprises: generating the error in the at least one memory cell of the at least one layer in a first iteration, determining the measure as a function of the output and the true output in the first iteration, generating a further error in the at least one memory cell or generating the error in at least one other memory cell of the at least one layer in a second iteration, determining the output and the true output in the second iteration as a function of the input or as a function of another input and determining the measure as a function of the output and the true output in the second iteration. [12] The memory (104) according to one of claims 9 to 11, characterized bythat the neural network comprises a further layer, the method comprising generating the error in at least one memory cell of the further layer in a third iteration, determining the output and the true output in the third iteration as a function of the input or as a function of another input, and determining the measure as a function of the output and the true output in the third iteration. [13] The memory (104) according to one of claims 9 to 12, characterized byin that the method comprises determining the measure for a first design of the computing hardware and determining the measure for a second design of the computing hardware, wherein the first design and the second design are distinguished by a number of memory cells for detecting or correcting the error or by a number of memory cells protected by the at least one memory cell for detecting or correcting the error, or by the selection of memory cells protected by the at least one memory cell for detecting or correcting the error, and outputting the measure determined for the first design and the measure determined for the second design. [14] The memory (104) according to claim 13, characterized by that the method comprises determining the first design and the second design. [15] The memory (104) according to claim 14, characterized bythat the method comprises allocating the first design to a first area that the memory cells consume to detect or correct the error in the computing hardware according to the first design, allocating the second design to a second area that the memory cells consume to detect or correct the error in the computing hardware according to the second design, and outputting the first area and the second area. [16] The memory (104) according to claim 15, characterized by that the method comprises: determining a first latency for the first design, outputting the measure determined for the first design and the first area associated with the first latency, determining a second latency for the second design, and outputting the measure determined for the second design and the second area associated with the second latency. [17] Data structure (300) for determining a measure of accuracy of in-memory computing hardware for determining an output of a neural network, in particular for designing the computing hardware, wherein the computing hardware comprises memory cells representing weights of the neural network, wherein the computing hardware comprises at least one memory cell for detecting or correcting an error in at least one of the memory cells, wherein the neural network comprises at least one layer, wherein the data structure (300) comprises at least one data field (302) for generating an error associated with at least one memory cell representing a weight of the at least one layer, wherein the data structure (300) comprises at least one data field (302) for the output of the neural network comprising the error detected in response to an input to the neural network,for a true output for the input and for the measure determined depending on the output and the true output., [18] The data structure (300) according to claim 17, characterized by that the data structure (300) comprises at least one data field (302) for determining, as a measure, a divergence of pairs of an output and a true output or for determining a divergence of pairs of an output and a true output and determining the measure as a function of the divergence. [19] The data structure (300) according to one of claims 17 or 18, characterized bythat the data structure (300) comprises at least one data field (302) for generating the error in the at least one memory cell of the at least one layer in a first iteration, determining the measure as a function of the output and the true output in the first iteration, generating a further error in the at least one memory cell in a second iteration or generating the error in at least one other memory cell of the at least one layer, determining the output and the true output in the second iteration as a function of the input or as a function of another input, and determining the measure as a function of the output and the true output in the second iteration. [20] The data structure (300) according to any one of claims 17 to 19, characterized byin that the neural network comprises a further layer, wherein the data structure (300) comprises at least one data field (302) for generating the error in at least one memory cell of the further layer in a third iteration, determining the output and the true output in the third iteration as a function of the input or as a function of another input, and determining the measure as a function of the output and the true output in the third iteration. [21] The data structure (300) according to any one of claims 17 to 20, characterized byin that the data structure (300) comprises at least one data field (302) for determining the measure for a first design of the computing hardware and for determining the measure for a second design of the computing hardware, wherein the first design and the second design are distinguished by a number of memory cells for detecting or correcting the error or by a number of memory cells protected by the at least one memory cell for detecting or correcting the error or by the selection of memory cells protected by the at least one memory cell for detecting or correcting the error, wherein the data structure (300) comprises at least one data field (302) for outputting the measure determined for the first design and the measure determined for the second design. [22] Data structure (300) according to claim 21, characterized by that the data structure (300) comprises at least one data field (302) for determining the first design and the second design. [23] Data structure (300) according to claim 22, characterized by that the data structure (300) comprises at least one data field (302) for linking the first design to a first area occupied by the memory cells for detecting or correcting the error in the computing hardware according to the first design, for linking the second design to a second area occupied by the memory cells for detecting or correcting the error in the computing hardware according to the second design, for outputting the first area and the second area. [24] Data structure (300) according to claim 23, characterized by, that the data structure (300) has at least one data field (302) for determining a first latency for the first design, for outputting the measure associated with the first latency determined for the first design and the first area, for determining a second latency for the second design, and for outputting the measure associated with the second latency determined for the second design and the second area.

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