Logical data processing circuit integrated into a data storage circuit

Description

Scope of application

[0001] The invention generally relates to data storage circuits based on non-volatile memory cells. More particularly, the invention relates to the field of designing computational memory circuits or in-memory computing circuits (translated from the English term In-Memory Computing). The invention relates to a data storage circuit making it possible to carry out elementary Boolean logic operations within the storage circuit itself. Problem raised

[0002] Generally speaking, a system-on-chip comprises memory circuits for storing data and computation circuits for performing logical and arithmetic operations. Data exchange operations between memory circuits and computation circuits are very energy-intensive and reduce the system's computing performance. In this context, emerging non-volatile memory technologies make it possible to create memory circuits capable of performing both the storage function and the computing function. In this case, we speak of a "computation circuit in the memory". This makes it possible to avoid data transfers between storage means and computing means, and thus, makes it possible to reduce energy consumption and improve computing speed.

[0003] However, the development of “in-memory computing circuits” solutions presents several challenges and constraints such as: The use of large peripheral circuits around the memories to process the results. This significantly increases the circuit area and the complexity of physical implementation. Constraints on the accuracy of the calculations performed. More specifically, this problem occurs when executing algorithms requiring parallel calculations.

[0004] For example, in a conventional Von Neumann architecture, up to 90% of the energy consumption is lost in the transfer between the computing unit and the memory.

[0005] Thus, there is a need to design new architectures of computing circuits in memory, which are less complex and at the same time present a reduction in power consumption and an improvement in computing performance in terms of speed and precision. Prior Art / State of the Art Restrictions

[0006] The scientific publication entitled "Processing In-Memory Architecture with On-Chip Transfer Learning Function for Compensating Characteristic Variation," by M. Hayashikoshi et al presents a data storage circuit configured to perform logic processing in the memory matrix itself. The presented solution requires the addition of several additional transistors in each memory cell to connect the memory points together according to a predetermined connection. This has a disadvantage consisting of the considerable increase in the area occupied by the storage circuit. The increase in area generates additional manufacturing and integration costs. Document US 2022 / 027130 A1 describes a circuit configured to perform matrix multiplication and addition calculations, comprising a digital-to-time converter. Response to the problem and provision of a solution

[0007] To address the technical problems discussed above, the invention provides a data storage circuit comprising a non-volatile memory array and a data processing circuit configured to read operands from said array, and perform elementary logic operations from the read data without transferring the data outside the storage circuit. It is thus possible for the person skilled in the art to implement more complex algorithms from the elementary logic functions in the memory.

[0008] The operating principle of the data storage circuit according to the invention is compatible with a memory matrix of the ferroelectric type with variable electrical polarization or of the resistive type with variable conductive filament or a mixed resistive and capacitive memory matrix.

[0009] The device according to the invention can be produced with a considerably higher number of memory cells than known solutions. This offers the advantage of multiplying storage and computing capacities at the same time. This makes it possible to obtain a device compatible with the execution of complex computing algorithms within the storage circuit itself. In addition, the device is capable of parallelizing a considerable number of data processing operations to achieve better performance.

[0010] The invention further relates to a thin-film structure for producing the memory cells according to the invention. This elementary structure has the advantage of being compatible with the manufacturing techniques of the semiconductor industry. Thus, the device according to the invention has reduced production costs.

[0011] Furthermore, in the specific case of ferroelectric type memories, an additional problem arises: reading data corresponding to a high logic state (x=1) is destructive of said data. In this context, the data processing circuit according to the invention makes it possible to rewrite the read data (x=1) in the memory cell after each reading operation so as to carry out a non-destructive reading operation. The rereading operation is fully integrated by the data processing circuit according to the invention. There is no need to copy the data into buffer memories before reading, nor to transfer said data to external circuits. This makes it possible to reduce the implementation complexity of the storage circuit. This also makes it possible to reduce the energy consumption of the storage circuit by limiting the data exchanges at the input and / or output of the storage circuit. Summary / Claims

[0012] The subject of the invention is a data storage circuit comprising: a memory cell array such that each memory cell comprises: an elementary non-volatile storage component having a first electrode and a second electrode, a first input / output node connected to the second electrode, a second input / output node, a selection node; and a selection transistor having a gate connected to the selection node and connecting the first electrode to the second input / output node, a logic processing circuit configured to perform a logic operation having as operands N binary data stored in N input memory cells with N≥2; the second input / output nodes of said input memory cells being connected by a common bit line; the logic processing circuit comprising: a transimpedance amplifier stage configured to provide an analog read signal from the voltage of the common bit line;a comparator for comparing the analog read signal to a first adjustable reference voltage to generate a digital output signal corresponding to the result of the logic operation; a control unit configured to adjust the reference voltage to an amplitude chosen from among N distinct predetermined amplitudes, depending on the type of the logic operation.;

[0013] According to a particular aspect of the invention, the data storage circuit further comprises a sequencer configured to apply: a write and read control signal on the first input / output node of each of the input memory cells; a selection signal on the selection node of each of the input memory cells.

[0014] According to a particular aspect of the invention, the first input / output nodes of said input memory cells are connected by a common source line.

[0015] According to a particular aspect of the invention, the capacitive transimpedance amplifier stage comprises: an operational amplifier having: a first input connected to the second input / output node of the input memory cells, and a second input for receiving a second reference voltage; and an output for providing said analog read signal; a feedback impedance mounted between the output and the first input of the operational amplifier.

[0016] According to a particular aspect of the invention, the logic processing circuit further comprises a reset switch mounted between the output and the first input of the operational amplifier.

[0017] According to a particular aspect of the invention, the feedback impedance is a capacitive impedance and in which the elementary storage components of the input memory cells are of the ferroelectric type with variable electrical polarization. Each memory cell can have a first or a second logic state corresponding respectively to different levels of charges stored in the associated elementary storage component.

[0018] According to a particular aspect of the invention, each elementary storage component of the input memory cells has a first predetermined capacity, and in which the feedback impedance is a capacitive element having a second capacity greater than N times said first predetermined capacity.

[0019] According to a particular aspect of the invention, the N predetermined amplitudes are ordered in a decreasing order, and the logic processing circuit is configured to perform a logic operation by executing the following steps: i) a reset step for discharging the capacitive element, biasing the first input of the operational amplifier to the second reference voltage and adjusting the first reference voltage to the maximum amplitude among the N predetermined amplitudes;ii) a step of reading a first input memory cell by turning on its selection transistor and applying a read control signal to its first input / output node having an amplitude substantially equal to the second reference voltage so as to generate a transfer of charges from the elementary storage component of the selected memory cell to its associated capacitive element iii) a step of adjusting the first reference voltage by the control unit by adjusting the amplitude of the first reference voltage to the next order amplitude among the N predetermined amplitudes when the binary data read in the previous step is a high logic state; iv) repeating steps ii) and iii) for the N input memory cells;v) a step of adjusting the first reference voltage to a predetermined value, according to the type of the logic operation, among the N amplitudes by the control unit to generate a digital output signal corresponding to the result of the logic operation.;

[0020] According to a particular aspect of the invention, each elementary storage component of the input memory cells has a first predetermined capacity, and in which the feedback impedance is achieved by N capacitive elements mounted in parallel, each capacitive element being associated with an input memory cell and having a second capacity greater than or equal to said first predetermined capacity.

[0021] According to a particular aspect of the invention, the logic processing circuit is configured to perform a logic operation by executing the following steps: i') a reset step for discharging the capacitive elements, biasing the first input of the operational amplifier to the second reference voltage and adjusting the first reference voltage to the maximum amplitude among the N predetermined amplitudes; ii') a step for reading a first input memory cell by putting its selection transistor into the on state and applying a read control signal to its first input / output node having an amplitude substantially equal to the second reference voltage so as to generate a transfer of charges from the elementary storage component of the selected memory cell to its associated capacitive element.iii') repeating step ii') for the N input memory cells; iv') a step of adjusting the first reference voltage to a predetermined value, according to the type of the logic operation, among the N amplitudes to generate a digital output signal corresponding to the result of the logic operation.

[0022] According to a particular aspect of the invention, the sequencer circuit is configured to, following the reading of data corresponding to the second logic state in a selected memory cell, apply a control signal, to the first input / output node of said selected memory cell, having an amplitude lower than the second reference voltage and maintain the selection transistor of the selected memory cell in an on state so as to restore, in its elementary storage component, a charge level corresponding to the second logic state.

[0023] According to a particular aspect of the invention, said first logic state corresponds to an uncharged state of an elementary storage component. said sequencer circuit is such that, following the reading of data corresponding to a first logic state, said sequencer circuit is configured to make said transistor for selecting the selected memory cell non-conductive before modifying the control signal on the first input / output node to a new value, to maintain the memory cell just read in an uncharged state.

[0024] According to a particular aspect of the invention, the elementary storage component of an input memory cell is of the FeRAM type or of the ferroelectric tunnel junction FTJ type.

[0025] According to a particular aspect of the invention, the feedback impedance is a resistive impedance. The elementary storage components of the input memory cells are of the resistive type with variable conductive filament.

[0026] According to a particular aspect of the invention, the logic processing circuit is configured to perform a logic operation by executing the following steps: a) a reset step for biasing the first input of the operational amplifier to the second reference voltage and adjusting the first reference voltage to the maximum amplitude among the N predetermined amplitudes; b) a step for reading the input memory cells, by turning on their selection transistors in parallel or sequentially, and by applying a positive read control signal to their first input / output nodes; c) a step for adjusting the first reference voltage to a predetermined value, according to the type of the logic operation, among the N amplitudes, by the control unit, to generate a digital output signal corresponding to the result of the logic operation.

[0027] According to a particular aspect of the invention, during the step of adjusting the first reference voltage according to the type of the logic operation, the control unit is configured to adjust the first reference voltage to the minimum amplitude among the N predetermined amplitudes when the logic operation is of the AND type.

[0028] According to a particular aspect of the invention, during the step of adjusting the first reference voltage according to the type of the logic operation, the control unit is configured to adjust the first reference voltage to the maximum amplitude among the N predetermined amplitudes when the logic operation is of the OR type. Brief Description of the Drawings

[0029] Other features and advantages of the present invention will become more apparent upon reading the following description in relation to the following appended drawings. [ Fig. 1a] illustrates a sectional view of an example of an elementary component of a ferroelectric memory cell with variable electrical polarization compatible with the invention. [ Fig. 1b ] illustrates an electrical modeling of a ferroelectric memory cell with variable electrical polarization compatible with the invention. [ Fig. 2a ] illustrates an electrical diagram of a first embodiment of the processing circuit according to the invention connected to N=3 ferroelectric memory cells with variable electrical polarization. [ Fig. 2b ] illustrates the operating steps of the processing circuit according to the first embodiment of the invention to carry out an elementary logic operation. [ Fig. 2c ] illustrates the adjustment of the first reference voltage of the comparator of the processing circuit according to the first embodiment of the invention to carry out a three-operand AND type logic operation. [ Fig. 2d] illustrates the adjustment of the first reference voltage of the comparator of the processing circuit according to the first embodiment of the invention to carry out a three-operand OR type logic operation. [ Fig. 3a ] illustrates an electrical diagram of a second embodiment of the processing circuit according to the invention connected to N=3 ferroelectric memory cells with variable electrical polarization. [ Fig. 3b ] illustrates an electrical diagram of a third embodiment of the processing circuit according to the invention connected to N=3 ferroelectric memory cells with variable electrical polarization. [ Fig. 3c ] illustrates the operating steps of the processing circuit according to the third embodiment of the invention to carry out an elementary logic operation. [ Fig. 4a] illustrates an electrical diagram of a fourth embodiment of the processing circuit according to the invention connected to N=3 ferroelectric memory cells with variable electrical polarization. [ Fig. 4b ] illustrates the operating steps of the processing circuit according to the fourth embodiment of the invention to carry out an elementary logic operation. [ Fig. 4c ] illustrates a flowchart of the memory cell control signals following the reading of a low logic state (x=0) by the processing circuit according to the fourth embodiment of the invention. [ Fig. 4d ] illustrates a flowchart of the memory cell control signals following the reading of a high logic state (x=1) by the processing circuit according to the fourth embodiment of the invention. [ Fig. 5 ] illustrates a sectional view of an example of an elementary component of a resistive memory cell with variable conductive filament compatible with the invention. [ Fig. 6a] illustrates an electrical diagram of a fifth embodiment of the processing circuit according to the invention connected to N=3 resistive memory cells with variable conductive filament. [ Fig. 6b ] illustrates the operating steps of the processing circuit according to the fifth embodiment of the invention to carry out an elementary logic operation.

[0030] The invention is compatible with a variable electrical polarization ferroelectric type memory array or a variable conductive filament resistive type memory array or a mixed resistive and capacitive memory array. We will begin by describing the invention in the context of a variable electrical polarization ferroelectric type memory storage circuit. The Figure 1a presents a structural example of an elementary NVM component of a ferroelectric memory cell with variable electrical polarization, more precisely a FeRAM type component.

[0031] In the illustrated example, the elementary component NVM consists of the stack of thin layers in the following order: a first layer C1 made of an electrically conductive material forming a first electrode EL1; a second layer C2 made of a dielectric and ferroelectric material and a third layer C3 made of electrically conductive material forming a second electrode EL2. The second layer C2 is referred to in the remainder of the description as the “central layer”.

[0032] The stack of thin layers forms a MIM (acronym Metal-Insulator-Metal) type structure acting as a capacitive element with a capacitance C. The ferroelectric character of the central layer C2 induces the following behavior: when a positive electrical voltage is applied to the upper electrode EL2, the polarization of the electric dipoles of the central layer is directed in a so-called "negative" direction. Conversely, when a positive electrical voltage is applied to the lower electrode EL2, the polarization of the electric dipoles is directed in a so-called "positive" direction. The direction of the electrical polarization in the central layer C2 corresponds to a state of equilibrium maintained even in the absence of the electric field induced by the voltage applied to one of the electrodes EL1 or EL2, hence the operation in ferroelectric memory.

[0033] Thus, the following convention is chosen as an example: when an NVM memory component is configured to store binary data in the low logic state (x= 0), a write electrical voltage is temporarily applied to the upper electrode EL2 (illustrated by polarization +) so as to obtain a polarization directed in a “negative” direction in the central layer C2. Conversely, when an NVM memory component is configured to store binary data in the high logic state (x= 1), a write electrical voltage is temporarily applied to the lower electrode EL1 (illustrated by polarization -) so as to obtain a polarization directed in a “positive” direction in the central layer C2.

[0034] There Figure 1aillustrates an elementary NVM component of the FeRAM type compatible with the invention. We emphasize that it is also possible to implement the invention with elementary components of the ferroelectric tunnel junction (FTJ) type and any other type of ferroelectric non-volatile memory technology with variable electrical polarization.

[0035] There Figure 1billustrates an electrical diagram of a ferroelectric memory cell CM ij with variable electrical polarization compatible with the invention. The memory cell comprises CM ij an elementary memory component NVM, a selection transistor T1, a first input / output node SL, a second input / output node BL and a selection node WL. The memory cell CM ij is intended to be integrated in a matrix comprising a plurality of bit lines (bit line in English), a plurality of word lines (word line in English) and a plurality of source lines (source line in English). The first input / output node SL is intended to be connected to a source line associated with the memory cell CM ij . The second input / output node BL is intended to be connected to a bit line associated with the memory cell CM ij . The selection node WL is intended to be connected to a word line associated with the memory cell CM ij .

[0036] Within a memory cell CM ij , the first input / output node SL is connected to the second electrode EL2 of the elementary memory component NVM. The selection transistor T1 has a gate connected to the selection node WL. The selection transistor T1 connects the first electrode EL1 of the elementary memory component NVM to the second input / output node BL. The elementary component NVM behaves like a capacitive element having a variable capacitance depending on the direction of the electrical polarization of the central ferroelectric layer C2. The memory cell CM ij is thus modeled by a compact 1C1T architecture. This allows a direct action on the electrodes EL1 and EL2 of the capacitive element when the transistor T1 is in the on state.

[0037] There Figure 2aillustrates an electrical diagram of a first embodiment of the processing circuit according to the invention connected to N=3 ferroelectric memory cells with variable electrical polarization. The description of a logic operation with N=3 operands is given for illustrative purposes and is not limiting. The invention makes it possible to carry out elementary logic operations for N>=2 operands stored in as many memory cells.

[0038] The storage circuit according to the invention comprises a matrix 2 of memory cells CM ij as described in the Figures 1a and 1b and at least one data processing circuit 3. For the sake of simplification, the entire memory matrix 2 is not presented and is limited to the presentation of the input memory cells CM 1 , CM 2 and CM 3 containing respectively the input binary data x1, x2 and x3.

[0039] The input memory cells CM 1 , CM 2 and CM 3 share the same bit line forming a second input / output node BL common to said cells. The input memory cells CM 1 , CM 2 and CM 3 share the same source line forming a first input / output node SL common to said cells. The selection nodes WL1, WL2 and WL3 of each of the input memory cells CM 1 , CM 2 and CM 3 are distinct.

[0040] The logic processing circuit 3 is connected to the second common input / output node BL of the input memory cells CM 1 , CM 2 and CM 3 through an activation switch i3. The activation switch i3 makes it possible to isolate the node BL from the logic processing circuit 3 if necessary. The parasitic capacitance C BL seen by the second input / output node BL is shown here in order to facilitate the understanding of the invention.

[0041] The logic processing circuit 3 comprises a capacitive transimpedance amplifier stage 31 (translation of the term into English Capacitive TransImpedance Amplifier); a comparator 32, a control unit 34, a sequencer circuit 33 and a reset switch i1.

[0042] Generally, the transimpedance amplifier stage 31 is configured to provide an analog read signal Vs1_ao for each of the operands x1, x2, x3. The comparator 32 is configured to compare the analog read signal Vs1_ao with a first adjustable reference voltage VREF_cmp to generate a digital output signal Vs1_cmp. The control unit 34 is configured to adjust the first reference voltage VREF_cmp to an amplitude chosen from N=3 predetermined amplitudes VREF1, VREF2, VREF3 such that VREF1>VREF2>VREF3.

[0043] According to the first embodiment of the invention, the capacitive transimpedance amplifier stage 31 comprises an operational amplifier AO associated with a capacitive feedback impedance (CCR). The operational amplifier AO has a first input e1_ao connected to the second input / output node BL of the input memory cells; a second input e2_ao for receiving a second reference signal VREF0; and an output s1_ao for providing said analog read signal Vs1_ao. The capacitive feedback impedance CCR is mounted between the output s1_ao and the first input e1_ao of the operational amplifier. This type of assembly makes it possible to perform a direct reading of the quantity of charges contained in the elementary component NVM and not a reading of a voltage variation on the node BL. This assembly thus makes it possible to perform a reading operation whose precision is independent of the parasitic capacitance C BL .

[0044] In the illustrated embodiment, the capacitive feedback impedance CCR is achieved by a single capacitive element Cap1. The function of the capacitive feedback impedance CCR is to convert the quantity of charges supplied by the elementary component NVM (similar to a capacitive element) into an electrical voltage applied between the output s1_ao and the input e1_ao. Let Q be the quantity of charge supplied by an input memory cell that stores data in a high logic state. In the case where the logic processing circuit 3 is intended to perform logic operations with N operands, the capacitive element Cap1 is capable of receiving a quantity of charge greater than or equal to NxQ. In other words, if we assimilate the elementary component NVM of each input memory cell having a capacitance equal to C0, the capacitance C1 of the capacitive element Cap1 is greater than or equal to NxC0.

[0045] The operational amplifier AO has a dual function: maintain the BL node at a fixed potential equal to the potential of the second reference signal VREF0 when the read enable switch i3 is conducting. generate an analog read signal Vs1_ao having an amplitude dependent on the amount of charge transmitted from the elementary component NVM to the capacitive feedback impedance CCR during a cell read operation and during an elementary logic operation calculation step.

[0046] The comparator 32 has a first input e1_cmp connected to the output s1_ao of the operational amplifier; a second input e2_cmp for receiving said first adjustable reference signal VREF_cmp; and an output s1_cmp for providing a digital reading signal Vs1_cmp resulting from the comparison of the analog reading signal Vs1_ao with the first adjustable reference signal VREF_cmp.

[0047] The control unit 34 is configured to control the amplitude of the first reference voltage VREF_cmp when executing a predetermined elementary logic operation. It is a circuit configured according to a state machine implemented using logic gates. The action of the control unit 34 on the first reference voltage VREF_cmp will be detailed in a later section.

[0048] Optionally, the processing circuit 3 comprises a first feedback activation switch i2 between the capacitive feedback impedance CCR and the first input e1_ao of the operational amplifier.

[0049] The comparator 32 and the operational amplifier AO are each biased by a supply voltage VDD and the electrical ground GND.

[0050] The sequencer circuit 33 is configured to control the application: of a write and read control signal VSL on the first input / output node SL of the associated memory cell; and of a selection signal VWL1, VWL2, VWL3 on each selection node WL1, WL2 and WL3 of the input memory cells.

[0051] The reset switch i1 is connected between the output s1_ao and the first input e1_ao of the operational amplifier. When the reset switch i1 is in the on state, the capacitive feedback impedance CCR is discharged. This discharge also induces the reset of the analog output signal Vs1_ao to a potential equal to that of the second reference signal VREF0.

[0052] Advantageously, closing the reset switch i1 allows the cumulative charges on the second input / output node BL to be dissipated due to leakage currents. Indeed, for advanced technological nodes, there is an increase in leakage currents coming from the gates of the transistors of the operational amplifier AO connected to the second input / output node BL. These leakage currents cause an accumulation of charges at the level of the parasitic capacitance C BL . This induces potential fluctuations at the level of the second input / output node BL. Hence the specific interest of the reset switch i1 in this case.

[0053] All switches i1, i2 and i3 are controlled by control means not shown to simplify the illustration. Switches i1, i2 and i3 are implemented by CMOS transistors as an example.

[0054] In order to carry out an elementary logic operation having as operands the data x1, x2 and x3, the logic processing circuit 3 according to the first embodiment is configured to carry out the steps detailed in the flowchart of the Figure 2a . Switch i3 is closed to establish the connection between the input memory cells and the logic processing circuit 3.

[0055] The first step (i) is a reset step obtained by the following configuration: the reset switch i1, the feedback activation switch i2 are closed. The sequencer 33 generates a selection signal VWL so as to put the selection transistor T1 in a blocking state. The sequencer 33 generates a write and read control signal VSL on the first input / output node SL equal to the electrical ground. In addition, the control unit 34 is configured to adjust the first reference voltage VREF_cmp to the maximum amplitude VREF1. The maximum amplitude is used to detect a minimum amplitude variation of the analog output voltage Vs1_ao when a high logic state is read.

[0056] This step (i) allows to discharge the capacitive feedback impedance CCR and to bias the first input e1_ao of the operational amplifier to the second reference signal VREF0. Thus following the reset, the input / output node BL and the output s1_ao are biased to the second reference signal VREF0 (VBL= Vs1_ao= VREF0); the voltage across the capacitive feedback impedance CCR is zero; the reference voltage of comparator 32 is at VREF1; and the output of comparator s1_cmp is at a low logic state (Vs1_cmp=0).

[0057] The second step (ii) is a step of reading the first input memory cell CM 1 . The reset switch i1 is open, the switches i2 and i3 are closed (on state) and only the selection transistor T1 of the first input memory cell CM 1 is in the on state. The sequencer 33 is configured during this step to apply a selection signal VWL1 making it possible to put the selection transistor T1 in the on state (a rising edge in the case of an NMOS for example). The selection transistors of the second and third input memory cells are kept in the off state. This results in the creation of a connection path between the elementary component NVM and the capacitive feedback element CCR. In addition, the sequencer 33 is configured to apply a positive read control signal VSL to the first input / output node SL.This results in the application of a quasi-zero potential difference across the terminals of the NVM elementary component. Thus, the combination of the quasi-zero voltage across the NVM elementary component and its connection with the CCR feedback capacitive element induces a transfer of the charges previously stored in the NVM elementary component to the CCR feedback capacitive element. The amount of charge transferred depends on the logic state previously stored in the first input memory CM 1 . This induces a variation of the electrical voltage VCCR across the CCR feedback capacitive impedance. The value of the electrical voltage across the CCR feedback capacitive impedance depends on the amount of charges supplied by the NVM elementary component. This induces a variation of the analog output signal Vs1_ao which passes to VREFO-VCCR.

[0058] The amplitude VREF1 is chosen so as to obtain the behavior described below according to the content of a read input memory cell. In the case where x=1 is stored in the elementary component NVM, we obtain Vs1_ao= VREFO-VCCR < VREF1 with VCCR of the order of a few hundred millivolts. We thus obtain Vs1_cmp=VDD corresponding to a high logic level. Conversely, in the case where x=0 is stored in the elementary component NVM, we obtain Vs1_ao= VREFO-VCCR > VREF1 and therefore Vs1_cmp=GND corresponding to a low logic level. In the illustrated case, the comparator 32 is an inverting comparator circuit. Conversely, it is possible to implement a non-inverting comparator circuit according to the design choices of the person skilled in the art.

[0059] It should be emphasized that the charges are transferred entirely to the capacitive feedback impedance CCR during this step. The parasitic capacitance C BL does not receive these charges because it is maintained at a voltage equal to VREF0 thanks to the operational amplifier AO during the entire operation. The processing circuit 3 according to the invention thus makes it possible to carry out a reading operation in the charge domain independent of the value of the parasitic capacitance C BL .

[0060] This results in obtaining the following configuration at the end of step ii): in the case where x=0 is stored in the elementary component NVM, a quasi-zero quantity of charge Q 0 is accumulated in the capacitive feedback impedance CCR. In the case where x=1 is stored in the elementary component NVM, a quantity of charge Q 1 >> Q 0 is accumulated in the capacitive feedback impedance CCR.

[0061] The control unit 34 receives the digital output signal Vs1_cmp corresponding to the reading result of the first memory cell at the end of the previous step.

[0062] The third step (iii) consists of a step of adjusting the first reference voltage VREF_cmp by the control unit 33 by adjusting the amplitude of the first reference voltage according to the result of the previous reading step. If the data read is x1=0, the control unit 33 is configured to maintain the first reference voltage VREF_cmp at its current state, namely VREF1 in this case. If the data read is x1=1, the control unit 33 is configured to adjust the amplitude of the first reference voltage VREF_cmp to the next amplitude step among the sequence of N amplitudes VREF1 to VREF3.

[0063] Following this adjustment step, the reading step ii) is repeated for the second input memory cell CM 2 . We recall that the initial configuration of the processing circuit 3 before the reading step of the second input memory cell CM 2 depends on the logic value read in the first input memory cell CM 1 . Two scenarios are then possible: If x1=0, the first reference voltage VREF_cmp is maintained at VREF1 and the sequence of the reading step ii) of the second input memory cell CM 2 is identical to that described for the first input memory cell CM 1 . If x1=1, the first reference voltage VREF_cmp is biased to VREF2. This makes it possible to configure the comparator 32 to switch to a high logic state following the accumulation of a quantity of charges equal to 2xQ 1 (if x1=1 and x2=1) but also to generate a low digital output signal following the accumulation of a quantity of charges equal to 1xQ 1 (if x1=1 and x2=0).

[0064] Then the adjustment step (iii) of the first reference voltage VREF_cmp is repeated. Following the reading of the contents of the second input memory cell CM 2 , the control unit reacts as follows: if x1=1 and x2=1, the first reference voltage VREF_cmp is adjusted to the next amplitude step among the sequence of N amplitudes, namely, VREF_cmp = VREF3. if x1=1 and x2=0, the first reference voltage VREF_cmp is maintained at the current amplitude step among the sequence of N amplitudes, namely, VREF_cmp = VREF2. if x1=0 and x2=0, the first reference voltage VREF_cmp is maintained at the current amplitude step among the sequence of N amplitudes, namely, VREF_cmp = VREF1.

[0065] Similarly, following this second iteration of the adjustment step, the reading step ii) is repeated for the third input memory cell CM 3 .

[0066] From an analog point of view, each logical combination of data corresponds to a cumulative amount of charge in the capacitive feedback impedance CCR. At the end of the N iterations of steps ii) and iii), the capacitive element Cap1 stores an amount of charge equal to kxQ 1 , with k the number of input memory cells containing logic data at a high state “1”. The tables of Figures 2c and 2d illustrate the state of charge of the capacitive feedback impedance following three iterations of the read (ii) and adjust (iii) steps for the three input memory cells.

[0067] The next step consists of a step of adjusting the first reference voltage VREF_cmp according to the type of the logic operation to generate a digital output signal Vs1_cmp corresponding to the result of the logic operation.

[0068] For example, if the logic operation to be performed is of the AND type, this amounts to generating a digital output signal Vs1_cmp=1 only when x1=x2=x3=1. This corresponds to the detection of the accumulation of a charge quantity of 3xQ 1 in the capacitive feedback impedance CCR at the end of three successive reading operations. Thus, to perform an AND type logic operation, the control unit 34 is configured to bias the first reference voltage VREF_cmp to the amplitude corresponding to the minimum level VREF3. Thus, the output of the comparator 32 switches to a high logic state only when Vs1_ao= VREFO-VCCR < VREF3.

[0069] The amplitude of the reference voltage VREF3 is the minimum amplitude among VREF1 to VREF3. The minimum amplitude VREF3 is used to detect a maximum amplitude variation of the analog output voltage Vs1_ao. Indeed, the more cumulative charges there are in the capacitive feedback impedance CCR, the lower the voltage Vs1_ao = VREFO-VCCR. Therefore, the minimum amplitude VREF3 is the amplitude of the reference voltage for which the comparator 32 is able to detect the variation of the amplitude of the analog output voltage Vs1_ao.

[0070] Alternatively, if the logic operation to be performed is of the OR type, this amounts to generating a digital output signal Vs1_cmp=0 only when x1=x2=x3=0. This corresponds to the detection of the accumulation of a quasi-zero charge quantity of Q0 in the capacitive feedback impedance CCR at the end of three successive reading operations. Thus, to perform an OR type logic operation, the control unit 34 is configured to bias the first reference voltage VREF_cmp to the amplitude corresponding to the minimum level VREF1. Thus, the output of the comparator 32 switches to a low logic state only when Vs1_ao= VREFO-VCCR < VREF1.

[0071] We have thus carried out elementary logic operations with N operands stored in memory cells of the memory matrix in the storage circuit itself.

[0072] Advantageously, it is possible to carry out more complex logic operations (of the exclusive OR type for example) by using the same operating principle based on the accumulation of charges in combination with the control of the threshold voltage of comparator 32.

[0073] There Figure 3a illustrates an electrical diagram of a second embodiment of the processing circuit 3 according to the invention connected to N=3 ferroelectric memory cells with variable electrical polarization. Structurally, the second embodiment differs from the first embodiment by the realization of the capacitive feedback impedance CCR. Indeed, in the illustrated case, the capacitive feedback impedance CCR is produced by a plurality of capacitive elements Cap1, Cap2 and Cap3 connected in parallel between the output s1_ao and the first input e1_ao of the operational amplifier AO.

[0074] For each capacitive element among Cap1, Cap2 and Cap3, the processing circuit 3 further comprises a feedback activation switch (i2, i2' and i2" here implemented by transistors) between the associated capacitive feedback element and the first input e1_ao of the operational amplifier. Thus, during a read operation, each capacitive feedback element is dedicated to receiving the charges provided by an associated input memory cell. Let Q be the quantity of charge provided by an input memory cell that stores data in a high logic state. The first capacitive element Cap1 is able to receive a quantity of charge less than or equal to 1xQ; the second capacitive element Cap2 is able to receive a quantity of charge less than or equal to 2xQ; and the third capacitive element Cap3 is able to receive a quantity of charge less than or equal to 3xQ.

[0075] Thus, when the processing circuit 3 is configured to perform an elementary logic operation implementing 3 operands, the feedback activation switch i" associated with the third capacitive element Cap3 is closed and the other two feedback activation switches i and i' are open. The electrical connection is established between the third capacitive element Cap3 and the second input / output node BL common to the input memory cells.

[0076] Similarly, if the number of operands is equal to 2, the connection is established between the second capacitive element Cap2 and the second input / output node BL common to the input memory cells.

[0077] In the case where the processing circuit 3 is configured to perform only an operation of reading data from an input memory cell, the first capacitive element Cap1 is sufficient. Thus, the processing circuit 3 is configured to select the first capacitive element Cap1 to receive the charges provided by the input memory cell to be read.

[0078] Thus, this embodiment allows the adaptation of the value of the capacitance of the capacitive feedback impedance to the number of operands of the elementary logic operation to be carried out.

[0079] There Figure 3billustrates an electrical diagram of a third embodiment of the processing circuit 3 according to the invention connected to N=3 ferroelectric memory cells with variable electrical polarization. The third embodiment differs from the second embodiment by the sizing of the capacitive elements Cap1, Cap2 and Cap3. Indeed, each capacitive element among Cap1, Cap2 and Cap3 has a capacitance greater than or equal to that of the elementary component of an input memory cell. Each capacitive element among Cap1, Cap2 and Cap3 is capable of receiving a quantity of charge greater than or equal to 1xQ. The first capacitive element Cap1 is intended for receiving the charges supplied by the first input memory cell CM 1 when it is read. The second capacitive element Cap2 is intended for receiving the charges supplied by the second input memory cell CM 2 when it is read.The third capacitive element Cap3 is intended for receiving the charges supplied by the third input memory cell CM 3 when it is read.

[0080] There Figure 3c illustrates the operating steps of the processing circuit according to a third embodiment of the invention to carry out an elementary logic operation.

[0081] The first step (i') is a reset step identical to the reset step of the Figure 2a .

[0082] The next step (ii') consists of reading the first input memory cell CM 1 while selecting only the first capacitive element Cap1. The reading mechanism remains the same compared to what was detailed previously. This results in the accumulation of the charges provided by the first input memory cell CM1 in the first capacitive element Cap1.

[0083] The next step is to read the second input memory cell CM 2 while selecting only the second capacitive element Cap2. The reading mechanism remains the same as previously detailed. This results in the accumulation of the charges provided by the second input memory cell CM 2 in the second capacitive element Cap2.

[0084] The next step is to read the third input memory cell CM 3 while selecting only the third capacitive element Cap3. The reading mechanism remains the same as previously detailed. This results in the accumulation of charges provided by the third input memory cell CM 3 in the third capacitive element Cap3.

[0085] The advantage of this embodiment is that there is no need to adjust the amplitude of the first adjustable reference voltage VREF_cmp according to the reading result. This is possible thanks to the distribution of charges resulting from successive reading operations on separate capacitive elements.

[0086] The last step iv') consists of a step of adjusting the first reference voltage VREF_cmp according to the type of the logic operation in the same way described previously. During this step, all the switches i2, i2' and i2" are in the on state to evaluate all the quantities of charges distributed on the three capacitive elements.

[0087] In the following section, we will describe an embodiment of the invention for solving the problem of destructive reading of ferroelectric memories with variable electrical polarization. Indeed, during a read access, the elementary component NVM receives an electrical reading voltage on the upper electrode so as to rewrite it to a low logic state (x=0). We then observe the dynamics of the transition following the application of the reading voltage. If the electric dipoles of the central layer are previously polarized with an orientation in a “positive” direction (x=1), a relatively large quantity of electrical charges will be emitted by the device during the transition. Conversely, if the electric dipoles of the central layer are previously polarized with an orientation in a “negative” direction (x=0), the quantity of charges delivered during the transition is lower.As a result, the reading procedure consists of estimating the quantity of charges emitted during a polarization to a low logic state (x=0) and therefore erases the logic value of the stored data.

[0088] In this context, one problem to be solved is the destruction of the logical content of a ferroelectric memory cell with variable electrical polarization following a read operation.

[0089] There Figure 4a illustrates an electrical diagram of a fourth embodiment of the processing circuit 3 making it possible to solve the problem of destructive reading.

[0090] In this embodiment, the sequencer 33 receives the digital output signal Vs1_cmp so as to set up a feedback loop allowing a rewrite operation to be carried out by the reading circuit itself. This makes it possible to overcome the problems of destructive reading without complicating the circuit. In addition, the action of the sequencer makes it possible to carry out the rewrite without transferring the data to external buffer memories.

[0091] There Figure 4b illustrates the operating steps of the processing circuit 3 according to the fourth embodiment. The illustrated method differs from that described in Figure 2bby adding a rewrite step after each read operation according to the logical result of said operation. We recall that the rewrite operation is only required in the case where the data read corresponds to a high logical state. We will describe the progress of a rewrite step applied to an input memory cell.

[0092] There Figure 4cillustrates a flowchart of the control signals of the input memory cell following the reading of a low logic state (x=0) by the processing circuit 3. In this case, the sequencer 33 receives the digital output signal Vs1_cmp=0. In response to this result, the sequencer 33 is configured to emit a falling edge simultaneously on the SL and WL nodes of the memory cell being read. This makes it possible to isolate the elementary component NVM from the BL node and to maintain the logic state of said elementary component at x=0 obtained following the reading operation. (by pumping the charges during reading).

[0093] Alternatively, the figure 4dillustrates a flowchart of the control signals of the input memory cell following the reading of a high logic state (x=1) by the processing circuit 3. In this case, the sequencer 33 receives the digital read signal Vs1_cmp=VDD (x=1). In response to this result, the sequencer 33 is configured to apply a falling edge to the input / output node SL while maintaining the selection node WL in a high state. This results in the following combination: On the one hand, the first input / output node SL is at a low potential (preferably zero) under the action of the sequencer 33; On the other hand, the second input / output node BL is at a high electrical potential equal to VREF0 under the action of the operational amplifier AO; the transistor T1 being in the on state;

[0094] This corresponds to the application of a write voltage SET on the elementary NVM component as explained in the Figure 1a. Thus, a rewriting operation of the logical value x=1 was carried out via the action of the sequencer 33 allowing a rewriting operation to be carried out by the reading circuit itself. This makes it possible to overcome the problems of destructive reading without complicating the circuit.

[0095] We will describe the invention in the context of a variable conductive filament resistive type memory storage circuit. Figure 5 presents a structural example of an elementary NVM component of a resistive memory cell with variable conductive filament compatible with the invention.

[0096] Variable conductive filament resistive operation requires the formation of a conductive filament F through at least a portion of the electrically insulating central layer C2.

[0097] Initially, the NVM elementary component is a MIM (metal, insulator, metal) type structure having an infinite resistance between the two electrodes EL1 and EL2. In order to reconfigure the NVM elementary component according to a resistive memory operation, it is necessary to form the filament F starting from the upper electrode EL2 through at least a part of the volume of the central layer C2. The formation of the filament makes it possible to obtain a variable resistance by modulating the length I of the formed conductive filament. To form the filament, a forming electrical voltage is applied to the upper electrode EL2. The forming electrical voltage has a sufficiently high amplitude and / or duration to cause the generation of oxygen vacancies in the central layer C2.Indeed, the applied formation voltage must exceed a predetermined value so as to tear oxygen ions from the crystal lattice of the central metal oxide layer which will migrate towards the upper electrode EL2 and thus form a conductive filament F through the central layer made up of oxygen vacancies.

[0098] Once the conductive filament F is formed, the behavior of a resistive element with a variable resistance R is obtained depending on the length I of the conductive filament F. When a positive electrical voltage is applied to the lower electrode EL1, the reverse reaction occurs and oxygen ions will fill part of the oxygen vacancies forming the conductive filament. This results in a reduction in the length of the conductive filament. Thus, the resistance of the resistive element increases. This is referred to as a high resistive state and a RESET type write operation. Conversely, when a positive electrical voltage is applied to the upper electrode EL2, the length of the conductive filament F increases by the same mechanism described for the wire formation operation. Thus, the resistance of the resistive element decreases. This is referred to as a low resistive state and a SET type write operation.

[0099] The following convention is chosen as an example: when an NVM memory component is configured to store binary data in the high logic state (x = 1), a write electrical voltage is temporarily applied to the upper electrode EL2 (SET operation) so as to obtain a low resistive state. Conversely, when an NVM memory component is configured to store binary data in the low logic state (x = 0), a write electrical voltage is temporarily applied to the lower electrode EL1 (RESET operation) so as to obtain a high resistive state.

[0100] Reading a resistive NVM memory component involves estimating the resistance between the top electrode and the bottom electrode and comparing it to a threshold value to determine whether the resistive state is a high or low state.

[0101] There Figure 6aillustrates an electrical diagram of a fifth embodiment of the processing circuit 3 connected to N=3 resistive memory cells with variable conductive filament. In this case, the feedback impedance CCR is achieved by at least one feedback resistor R1 connected in parallel between the output s1_ao and the first input e1_ao of the operational amplifier AO. Advantageously, the reading circuit 3 comprises a second feedback activation switch i4 between the resistive feedback impedance RCR and the first input e1_ao of the operational amplifier A0.

[0102] There Figure 6b illustrates the operating steps of the processing circuit 3 according to the fifth embodiment of the invention to carry out an elementary logic operation.

[0103] The first reset step a) remains unchanged compared to the other embodiments. The second step b) consists of reading the input memory cells CM 1 , CM 2 , CM 3 . The selection transistors T1 of the input memory cells are turned on in parallel or sequentially. Then, the sequencer 33 is configured to apply a positive read control signal VSL to their first input / output nodes SL. The amplitude of the positive read control signal VSL is greater than that of the second reference signal VREF0 (potential of the second node BL). Each of the resistive elementary components NVM is then subjected to a non-zero potential difference. This results in the circulation of an electric current I1 to I3 through the resistor NVM. This induces an addition of the currents I tot =I1+I2+I3 in the feedback resistor R1.The intensity of the total current I tot depends on the number of input memory cells that store data in a high logic state (x=1). This induces a variation of the voltage VRCR across the resistive feedback impedance RCR which depends on the intensity of the current I tot . This results in a variation of the electrical potential at the output node s1_ao of the operational amplifier AO.

[0104] The last step c) consists of adjusting the amplitude of the first reference voltage VREF_cmp according to the type of the logic operation to generate a digital output signal Vs1_cmp corresponding to the result of the logic operation. This step remains unchanged compared to the other embodiments of the invention described previously.

Claims

1. A data storage circuit (1) comprising: - an array (2) of memory cells (CMij) such that each memory cell (CMij) comprises: • a non-volatile elementary storage component (NVM) having a first electrode (EL1) and a second electrode (EL2); • a first input / output node (SL) connected to the second electrode (EL2), a second input / output node (BL), a selection node (WL); • and a selection transistor (T1) having a gate connected to the selection node (WL) and linking the first electrode (EL1) to the second input / output node (BL); - a logic processing circuit (3) configured to carry out a logic operation having N binary data (x1, x2, x3) as operands stored in N input memory cells (CM1, CM2, CM3), with N ≥ 2; the second input / output nodes (BL) of said input memory cells (CM1, CM2, CM3) being linked by a common bit line; the logic processing circuit (3) comprising: • a transimpedance amplifier stage (31) configured to supply an analogue read signal (Vs1_ao) from the voltage of the common bit line (BL); the capacitive transimpedance amplifier stage (31) comprising: ∘ an operational amplifier (AO) having: a first input (e1_ao) connected to the second input / output node (BL) of the input memory cells, and a second input (e2_ao) for receiving a second reference voltage (VREF0); and an output (s1_ao) for supplying said analogue read signal (Vs1_ao); ∘ a feedback impedance (CCR) mounted between the output (s1_ao) and the first input (e1_ao) of the operational amplifier; • a comparator (32) intended to compare the analogue read signal (Vs1_ao) with a first adjustable reference voltage (VREF_cmp) to generate a digital output signal (Vs1_cmp) corresponding to the result of the logic operation; • a control unit (34) configured to adjust the reference voltage (VREF_cmp) to an amplitude selected from among N distinct predetermined amplitudes (VREF1, VREF2, VREF3), depending on the type of the logic operation; the feedback impedance (CCR) being a capacitive impedance and the elementary storage components (NVM) of the input memory cells (CM1, CM2, CM3) being of the variable electric biasing ferroelectric type; or the feedback impedance (CCR) being a resistive impedance and the elementary storage components (NVM) of the input memory cells (CM1, CM2, CM3) being of the variable conductive filament resistive type.

2. The data storage circuit (1) according to claim 1, further comprising a sequencer (33) configured to apply: - a write and read control signal (VSL) to the first input / output node (SL) of each of the input memory cells (CM1, CM2, CM3); - a selection signal (VWL1, VWL2, VWL3) to the selection node (WL) of each of the input memory cells (CM1, CM2, CM3).

3. The data storage circuit (1) according to any one of claim 1 or 2, wherein the first input / output nodes (SL) of said input memory cells (CM1, CM2, CM3) are linked by a common source line.

4. The data storage circuit (1) according to any one of claims 1 to 3, wherein the logic processing circuit (3) further comprises a reset switch (i1) mounted between the output (s1_ao) and the first input (e1_ao) of the operational amplifier.

5. The data storage circuit (1) according to any one of claims 1 to 4, wherein: when the feedback impedance (CCR) is a capacitive impedance and when the elementary storage components (NVM) of the input memory cells (CM1, CM2, CM3) are of the variable electric biasing ferroelectric type, each memory cell can have a first ("0") or a second ("1") logic state respectively corresponding to different levels of charges stored in the associated elementary storage component (NVM).

6. The data storage circuit (1) according to claim 5, wherein each elementary storage component (NVM) of the input memory cells (CM1, CM2, CM3) has a first predetermined capacitance, and wherein the feedback impedance (CCR) is a capacitive element (C1) having a second capacitance that is more than N times said first predetermined capacitance.

7. The data storage circuit (1) according to claim 6, wherein the N predetermined amplitudes (VREF1, VREF2, VREF3) are ordered in descending order, and wherein the logic processing circuit (3) is configured to carry out a logic operation by executing the following steps: i) a step of resetting for discharging the capacitive element (C1), biasing the first input (e1_ao) of the operational amplifier to the second reference voltage (VREFO) and adjusting the first reference voltage (VREF_cmp) to the maximum amplitude from among the N predetermined amplitudes (VREF1); ii) a step of reading a first input memory cell (CM1) by setting its selection transistor (T1) to the on-state and applying a read control signal (VSL) to its first input / output node (SL) having an amplitude substantially equal to the second reference voltage (VREFO) so as to cause a transfer of charges from the elementary storage component (NVM) of the selected memory cell to its associated capacitive element (C1). iii) a step of adjusting, by the control unit (33), the first reference voltage (VREF_cmp) by adjusting the amplitude of the first reference voltage to amplitude of the next order (VREF2) from among the N predetermined amplitudes when the binary piece of data read in the previous step is a high logic state; iv) repeating steps ii) and iii) for the N input memory cells (CM2, CM3); v) a step of adjusting, by the control unit (33), the first reference voltage (VREF_cmp) to a predetermined value, according to the type of the logic operation, from among the N amplitudes to generate a digital output signal (Vs1_cmp) corresponding to the result of the logic operation.

8. The data storage circuit (1) according to claim 5, wherein each elementary storage component (NVM) of the input memory cells (CM1, CM2, CM3) has a first predetermined capacitance, and wherein the feedback impedance (CCR) is produced by N capacitive elements (C1, C2, C3) mounted in parallel, with each capacitive element (C1, C2, C3) being associated with an input memory cell (CM1, CM2, CM3) and having a second capacitance greater than or equal to said first predetermined capacitance.

9. The data storage circuit (1) according to claim 8, wherein the logic processing circuit (3) is configured to carry out a logic operation by executing the following steps: i') a step of resetting for discharging the capacitive elements (C1, C2, C3), biasing the first input (e1_ao) of the operational amplifier to the second reference voltage (VREFO) and adjusting the first reference voltage (VREF1, VREF2, VREF3) to the maximum amplitude from among the N predetermined amplitudes; ii') a step of reading a first input memory cell (CM1) by setting its selection transistor (T1) to the on-state and applying a read control signal (VSL) to its first input / output node (SL) having an amplitude substantially equal to the second reference voltage (VREFO) so as to cause a transfer of charges from the elementary storage component (NVM) of the selected memory cell to its associated capacitive element (C1); iii') repeating step ii') for the N input memory cells (CM2, CM3); iv') a step of adjusting the first reference voltage (VREF_cmp) to a predetermined value, according to the type of the logic operation, from among the N amplitudes to generate a digital output signal (Vs1_cmp) corresponding to the result of the logic operation.

10. The data storage circuit (1) according to any one of claims 5 to 9, wherein the sequencer circuit (33) is configured to apply, after reading a piece of data corresponding to the second logic state ("1") in a selected memory cell, a control signal (VSL) to the first input / output node (SL) of said selected memory cell, having an amplitude below the second reference voltage (VREFO) and keeping the selection transistor (T1) of the selected memory cell in an on-state so as to restore, in its elementary storage component (NVM), a charge level corresponding to the second logic state ("1").

11. The data storage circuit (1) according to any one of claims 2 to 10, wherein said first logic state ("0") corresponds to an uncharged state of an elementary storage component (NVM), and wherein said sequencer circuit (33) is such that, after reading a piece of data corresponding to a first logic state ("0"), said sequencer circuit (33) is configured to make said selection transistor (T1) of the selected memory cell nonconductive before changing the control signal (VSL) on the first input / output node (SL) to a new value, to keep the memory cell that has just been read in an uncharged state.

12. The data storage circuit (1) according to any one of claims 5 to 11, wherein the elementary storage component (NVM) of an input memory cell (CM1, CM2, CM3) is of the FeRAM type or of the ferroelectric tunnel junction (FTJ) type.

13. The data storage circuit (1) according to any one of claims 1 to 4, wherein, when the feedback impedance (CCR) is a resistive impedance and wherein the elementary storage components (NVM) of the input memory cells (CM1, CM2, CM3) are of the variable conductive filament resistive type, the logic processing circuit (3) is configured to carry out a logic operation by executing the following steps: a) a step of resetting for biasing the first input (e1_ao) of the operational amplifier to the second reference voltage (VREFO) and adjusting the first reference voltage (VREF_cmp) to the maximum amplitude (VREF1) from among the N predetermined amplitudes; b) a step of reading the input memory cells (CM1, CM2, CM3), by setting their selection transistors (T1) to the on-state simultaneously or sequentially, and by applying a positive read control signal (VSL) to their first input / output nodes (SL); c) a step of adjusting, by the control unit (33), the first reference voltage (VREF_cmp) to a predetermined value, according to the type of the logic operation, from among the N amplitudes, to generate a digital output signal (Vs1_cmp) corresponding to the result of the logic operation.

14. The data storage circuit (1) according to any one of claims 7 or 9 or 13, wherein, during the step of adjusting the first reference voltage (VREF_cmp) according to the type of the logic operation, the control unit (33) is configured to adjust the first reference voltage (VREF_cmp) to the maximum amplitude (VREF3) from among the N predetermined amplitudes when the logic operation is of the AND type.

15. The data storage circuit (1) according to any one of claims 7 or 9 or 13, wherein, during the step of adjusting the first reference voltage (VREF_cmp) according to the type of the logic operation, the control unit (33) is configured to adjust the first reference voltage (VREF_cmp) to the maximum amplitude (VREF1) from among the N predetermined amplitudes when the logic operation is of the OR type.