Voltage ramp generator

Abstract

Voltage Ramp Generator This description relates to a circuit, or a process in a circuit, comprising: a first network of capacitors (3) comprising n nominally equal capacitive elements (Ci) each having a first electrode connected, via respective switches (Ki), either to a reference voltage (VREF) or to ground; a differential amplifier having a first input (-) connected to an output (21) of said first converter, a second input (+) connected to ground, and an output (28) providing a voltage ramp (VRAMP); a capacitive feedback circuit connecting the output of said differential amplifier to said first input;and a second network of capacitors (4) one output of which is connected to the first input (-) of the differential amplifier (25), the capacitive elements being arranged in sets and the method further comprising the controlled coupling, set by set, of second electrodes of the capacitive elements to said first input of the amplifier. Abstract figure: Fig. 3;

Description

Title of the invention: Voltage ramp generator Technical field

[0001] The present disclosure relates generally to voltage ramp generators and corresponding methods and, more particularly, to ramp generators used in analog-to-digital converters (ADCs). The present disclosure applies more particularly to image sensors. Prior art

[0002] Voltage ramp generators, particularly those that power ramp-type analog-to-digital converters in image sensors, are subject to strict specifications, particularly in terms of noise, in terms of supply voltage rejection ratio, or in terms of non-linearity with respect to an ideal ramp. For example, it is desirable to obtain a relatively high signal-to-noise ratio (SNR). Summary of the invention

[0003] There is a need for a ramp generator having better performance than existing solutions in terms of noise.

[0004] One embodiment overcomes all or part of the drawbacks of known ramp generators for digital-to-analog converters.

[0005] One embodiment provides a circuit comprising: a first capacitor network comprising n nominally equal capacitive elements each having a first electrode connected, via respective switches, either to a reference voltage or to ground; a differential amplifier having a first input connected to an output of said first capacitor network, a second input connected to ground, and an output providing a voltage ramp; and a capacitive feedback circuit connecting the output of said differential amplifier to said first input; and a capacitive feedback circuit connecting the output of the differential amplifier to said first input; and a second capacitor network, one output of which is connected to the first input of the differential amplifier, wherein the capacitive input elements are arranged in sets and second electrodes of the capacitive input elements are interconnected, set by set, and controllably connected to said amplifier input.

[0006] One embodiment provides a method comprising: in a circuit including: a first capacitor network comprising n nominally equal capacitive elements each having a first electrode connected, via respective switches, either to a reference voltage or to ground; a differential amplifier having a first input connected to an output of said first converter, a second input connected to ground and an output providing a voltage ramp;

[0007] a capacitive feedback circuit connecting the output of said differential amplifier to said first input; And a second network of capacitors, one output of which is connected to the first input of the differential amplifier (25), the capacitive elements being organized into sets and the method further comprising controllably coupling, set by set, second electrodes of the capacitive elements to said first input of the amplifier.

[0008] According to one embodiment, the capacitive elements are organized into m sets of n / (2Aj) capacitive elements, j ranging from 1 to m, plus a set of n / (2Am) capacitive elements, where 2Am represents a maximum conversion gain.

[0009] According to one embodiment, the switching of the capacitive elements is carried out at a given frequency to define voltage steps in the output signal of the differential amplifier, the duration of the steps of the first network of capacitors corresponding to the duration of the steps of the second network of capacitors multiplied by a conversion gain.

[0010] According to one embodiment, the gain conditions the number of sets connected to the first input of the amplifier.

[0011] According to one embodiment, the second capacitor network provides steps having an amplitude corresponding to the main DAC, divided by the conversion gain.

[0012] According to one embodiment, the sets of capacitive elements of the first network of capacitors are in parallel, m switches individually connecting each of the first m sets to the first input of the amplifier and said set of n / (2Am) capacitive elements is permanently connected to said first input.

[0013] According to one embodiment, each of the first m sets of capacitive elements of the first network of capacitances is connected to the set of capacitive elements of higher rank] by a switch and said set of n / (2Am) capacitive elements is permanently connected to said first input.

[0014] According to one embodiment, the frequency of the output steps remains the same for all conversion gains.

[0015] One embodiment provides a voltage ramp generator comprising a circuit as described.

[0016] One embodiment provides a digital-to-analog converter comprising a voltage ramp generator as described.

[0017] One embodiment provides an image sensor comprising at least one digital-to-analog converter as described. Brief description of the drawings

[0018] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0019] [Fig.l] schematically represents an electronic device, for example an image sensor;

[0020] [Fig.2] schematically represents an embodiment of a switched-capacitor ramp generator;

[0021] [Fig.3] represents, very schematically, an embodiment of a voltage ramp generator;

[0022] [Fig.4] represents the operation of the ramp generator of [Fig.3];

[0023] Figures 5A and 5B show two equivalent details of the ramp generator of [Fig.3];

[0024] [Fig.6] shows the operation of the ramp generator in the embodiment of Figures 5A and 5B;

[0025] Figures 7A and 7B represent two equivalent details of the ramp generator of [Fig.3], according to a binary approach and according to a thermometric approach, respectively;

[0026] [Fig.8] shows the operation of the ramp generator in the embodiment of Figures 7A and 7B; and

[0027] [Fig.9] schematically represents an alternative embodiment of a voltage ramp generator. Description of the embodiments

[0028] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0029] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0030] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") between them, this means that these two elements can be connected or linked through one or more other elements.

[0031] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0032] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0033] [Fig.l] schematically represents an electronic device, for example an image sensor 1.

[0034] The image sensor 1 comprises, among other things, a pixel matrix 12 and a digital-to-analog converter 14, the pixel matrix 12 being connected to an output of the converter 14 providing a voltage ramp VRAMP. The voltage ramp is, for example, used by single-slope analog-to-digital converters (not shown) of the pixel matrix 12, configured to convert the analog voltage levels of the pixels into digital values. In other embodiments, when the device 1 is not an image sensor, the element bearing the reference numeral 12 is a load to be supplied with a voltage ramp or a circuit using a voltage ramp, and comprising or not analog-to-digital converters of the ramp type.

[0035] The digital-to-analog converter 14 comprises a voltage ramp generator 2 (RAMP GEN) which provides the voltage ramp VRAMP, controlled by a controller 142 (CTRL). The ramp generator 2 is a switched capacitor ramp generator and the controller 142 is configured to provide control signals to the ramp generator 2 based on: a clock signal CK provided by a clock generator 144 (CK GEN); a CONFIG numeric value setting the amplitude, slope, timing, ramp offset, etc., of the VRAMP voltage ramp; and a VREF voltage which conditions, with other parameters, the slope of the ramp.

[0036] [Fig.2] schematically represents an embodiment of a generator of switched capacitor ramp 2.

[0037] The ramp generator 2 comprises a plurality of capacitive elements Ci, i.e. n capacitive elements Ci, with i ranging from 1 to n, having respective first electrodes 22i connected, via respective switches Ki, either to a node 23 or to a node 24, and a second common electrode, or their respective second electrodes, connected to a common node 21. The node 23 is configured to receive a DC voltage, for example a positive voltage VREF, from the control circuit 142. The node 24 is configured, in this example, to be grounded. According to a variant, the node 24 also receives a voltage supplied by the control circuit 142. The common node 21 is connected to an inverting input (-) of a differential amplifier 25. A non-inverting input (+) of the amplifier 25 is connected, preferably connected, to ground. The amplifier 25 is associated with a capacitive feedback circuit 26. The feedback circuit 26 comprises, in this example, a variable capacitive element CFB connecting an output node 28 of the amplifier 25 to its inverting input (-). The output node 28 of the amplifier 25 is preferably connected to ground via a filter capacitor CL.

[0038] A voltage ramp is generated by successively switching the switches Ki from ground to VREF to, at each step, transfer an additional charge to the feedback capacitor CFB in order to gradually decrease or increase the output voltage of the amplifier. The capacitive element CL filters the step ramp to obtain an approximate linear ramp VRAMP. Assuming that all the capacitive elements Ci have the same value Cin, the maximum variation (in absolute value) of the voltage ramp VRAMP corresponds to IVREF*n*Cin / CFBI. The controller 142 comprises, for example, a finite state machine which functions as a shift register to successively control the switches Ki, each switching operation transferring a charge of VREF*Cin to the capacitive element CFB. In the preceding and following description, when reference is made to the value of the amplitude of the steps, this means the absolute value of this amplitude.

[0039] A reset of the ramp can be carried out, for example, by short-circuiting, via a switch 27, the capacitive element CFB and by grounding all the capacitive elements Ci via their respective switches Ki.

[0040] A change of sign of the slope of the ramp can be obtained with the same circuit by permuting the switching order from ground to the reference voltage VREF or vice versa.

[0041] The above circuit is described in more detail in French patent application number FR2204819, filed on May 20, 2022 (B21465 - 21-GR2-0238).

[0042] In some applications and in particular in image sensors, it is desirable to modify the conversion gain of the ramp, i.e. its slope (the conversion gain is inversely proportional to the average slope), for example, taking into account the brightness level of the scene in order to adjust the full range of the sensor. The conversion gain of 1 corresponds to the maximum slope of the ramp necessary to convert the maximum amplitude of the read signal coming from the entire pixel matrix. If the maximum amplitude of the image signal is G times smaller than the maximum amplitude defined above, the amplitude of the ramp, and therefore its slope, can be divided by G, so that after analog-to-digital conversion, the distribution of digital codes always reaches the maximum value of the code. In this case, the conversion gain is G. The main values ​​of the conversion gains are powers of 2, but intermediate values ​​can also exist.

[0043] Such an adjustment can be made by modifying the value of the feedback capacitor CFB, as described in the application FR2204819 mentioned above, or by modifying the value of the reference voltage VREF supplied by the controller 142 to the node 23 and / or to the node 24.

[0044] Ramp noise contributes to noise known as "line noise" in image sensors, which is a critical parameter for image quality.

[0045] The described embodiments provide a novel approach to reducing noise, and thus reducing line noise in CIS (CMOS Image Sensors), while retaining the ability to adjust the conversion gain or ramp slope, for a conversion gain greater than 1.

[0046] The RMS noise of the ramp generator 2 corresponds to the square root of K*(l + Cin_total / CFB), where K is a factor which depends mainly on the characteristics of the amplifier 25 and the capacitance of the capacitive element CL.

[0047] According to the present description, when the conversion gain of the ramp is to be increased (the slope is to be inversely decreased), the number of input capacitive elements Ci used to generate the ramp is reduced. Thus, the total capacitance Cin_total, observed at the input of the amplifier 25, can be reduced by disconnecting the unused capacitance, which helps to reduce the noise.

[0048] For example, to increase the conversion gain from 1 to 2, only half of the capacitive elements Ci are needed to produce the expected output oscillation. The capacitive elements that are not used are disconnected, i.e., the other half of the capacitive elements Ci are disconnected from the input of amplifier 25. The amplitude of the ramp is therefore reduced from VREF*n*Cin / CFB to VREF*(n / 2)*Cin / CFB. The total capacitance observed at the input of amplifier 25 is divided by 2, which reduces the output noise.

[0049] However, the number of steps is also divided by 2, which has an impact on the ramp frequency, since the ramp duration must remain the same. If the conversion gain is modified, only the slope of the ramp should change, and the number of steps, therefore the frequency, should remain the same. However, by default, if for example only half of the capacitive elements are used, the number of steps is divided by two because one step corresponds to one capacitive element. In order to keep the same number of steps as for a nominal conversion gain using all the capacitive elements, an intermediate step is added. In other words, half VREF / 2*Cin / CFB amplitude step is added to each step of the ramp generated by the n / 2 capacitive elements. The frequency of the half-steps for a conversion gain of two corresponds to the frequency of the steps for a conversion gain of 1.

[0050] More generally, to increase the conversion gain by a factor G, n / G capacitive elements are used to generate a ramp. The amplitude of the ramp is therefore VREF*(n / G)*in / CFB and G intermediate steps (considering that the 1st of these intermediate steps is zero) are added to each step generated by the n / G capacitive elements. The frequency of the intermediate steps corresponds to the frequency of the steps for a conversion gain of 1.

[0051] This corresponds to the use of a "main" capacitive digital-to-analog converter (main DAC) to generate a first ramp of n / G steps and to add this first ramp to a second ramp of G steps generated by a "secondary" capacitive digital-to-analog converter (secondary DAC), the frequency of the first main converter being G times lower than the frequency of the secondary converter.

[0052] [Fig.3] represents, very schematically, an embodiment of a voltage ramp generator.

[0053] The embodiment of [Fig. 3] represents a switchable network 3 adapted to operate with four conversion gains, respectively a nominal or unit conversion gain 1, and conversion gains 2, 4 and 8 leading to reduced slopes compared to the unit conversion gain. The nominal conversion gain corresponds to the conversion gain of the ramp generator 2 based on the reference voltage VREF and on the n capacitive elements Ci.

[0054] As in the embodiment of [Fig.2], a first electrode 22i of each capacitive element Ci is connected by a switch Ki to the node 23 or to the node 24. The node 23 is configured to receive the voltage VREF. The node 24 is configured to be grounded.

[0055] Still as in the embodiment of [Fig.2], an output 21 of the capacitor network 3 is connected, preferably connected, to the inverting input (-) of the differential amplifier 25. The differential amplifier 25 has its output 28 which provides the voltage ramp VRAMP connected to its inverting input by the feedback capacitor CFB (preferably variable) and by the reset switch 27 in parallel, and its non-inverting input (+) grounded.

[0056] According to the embodiment of [Fig.3], the network 3 (or main network) of n capacitors is divided into 4 sets of respectively and approximately n / 2, n / 4, n / 8 and n / 8 capacitive elements Ci, the second electrodes of the capacitive elements Ci of each of the first three sets (n / 2, n / 4, n / 8 capacitive elements) being in interconnected to a respective switch SW1, SW2, SW3 to be connected to node 21 (or output of network 3), i.e. to the inverting input of amplifier 25, the n / 8 capacitive elements of the fourth set having their respective second electrodes interconnected preferably directly to node 21. Switches SW1, SW2 and SW3 are controlled by circuit 142 as a function of the desired conversion gain.

[0057] In addition to the network 3, another network 4 of capacitive elements is provided to generate a second secondary ramp at the node 21, to be added to the ramp generated by the network 3. This second network 4 can be considered as a secondary DAC intended to divide each step of the main DAC 3 into G secondary steps (the 1st secondary step being zero), where G represents the conversion gain. In the embodiment shown in [Fig. 3], the secondary DAC receives intermediate reference voltages VREF / 2, VREF / 4 and VREF / 8 from the circuit 142. According to another embodiment, these intermediate voltages are generated internally on the basis of the voltage reference VREF.

[0058] Exemplary embodiments of the secondary DAC 4 will be described later in relation to FIGS. 5 to 8.

[0059] To generate a ramp with a conversion gain of 1, all switches SW1, SW2 and SW3 are closed and all switches Ki, i.e. all capacitive elements Ci, are used and participate in the ramp. The secondary DAC does not operate, i.e. the amplitude and period of the respective steps generated by the main network 3 or the main DAC are not divided. This corresponds to the operation described in relation to [Fig.2].

[0060] To generate a ramp with a conversion gain of 2, switch SW 1 is, for example, open and switches SW2 and SW3 are closed. The number of capacitive elements involved in the generation of the main ramp is therefore n / 2. The secondary network 4 or secondary DAC generates a periodic signal alternating periods of amplitude 0 and periods of amplitude VREF / 2*Cin / CFB. This corresponds to the generation of a ramp (secondary ramp) of amplitude VREF / 2*Cin / CFB in steps of amplitudes 0 and VREF / 2*Cin / CFB. The frequency of the secondary ramp corresponds to the nominal frequency of the ramp generator, i.e. the frequency of the clock signal used for a conversion gain of 1. The frequency of the clock signal used for the main ramp, which conditions the duration of the steps of the main ramp, is divided by 2.

[0061] [Fig.4] represents the operation of the ramp generator of [Fig.3] for a conversion gain of 2.

[0062] [Fig.4] represents: - an example of an aspect 42 of the ramp generated by network 3, using half capacitive elements and a control frequency divided by two compared to the (nominal) frequency leading to the expected step duration (2*T) for the first ramp RAMP; - an example of an aspect 44 of the signal provided by the network 4, corresponding to a train of pulses of amplitude ICin*VREF / 2l and of frequency corresponding to the frequency leading to the expected step duration T; and - the resulting voltage ramp 46 obtained by adding the respective contributions of networks 3 and 4 to node 21.

[0063] The amplitude of each step of the ramp 42 corresponds to Cin*VREF. By adding the ramps 42 and 44, we obtain a ramp 46 of which each step has an amplitude of Cin*VREF / 2.

[0064] An advantage of the described embodiment is that the slope S of the ramp has been halved compared to operation with a conversion gain of 1, but the number of steps has been retained.

[0065] Furthermore, since only half of the capacitive elements have been used, the total capacitance seen by the amplifier is nominally halved, which contributes to the reduction of noise and output impedance.

[0066] To generate a ramp with a conversion gain of 4, i.e. with a slope divided by 4 compared to a ramp generated by the circuit of [Fig.2], switches SW1 and SW2 are open and switch SW3 is closed. Secondary network 4 generates a ramp of four steps each having an amplitude of VREF / 4 (the 1st step being zero). The frequency of the clock controlling the remaining n / 4 switches Ki of network 3 is divided by 4 compared to the nominal frequency and the frequency used to control secondary network DAC 4 corresponds to the nominal frequency.

[0067] To generate a ramp with a conversion gain of 8, all switches SW1, SW2 and SW3 are open and the secondary DAC 4 generates a ramp of eight steps each having an amplitude of VREF / 8.

[0068] More generally, the main network 3 of n capacitive elements Ci of the main DAC is divided into m+1 sets of capacitive elements Ci, where 2Am represents the maximum conversion gain of the ramp generator, namely m sets of n / (2Aj) capacitive elements, j ranging from 1 to m, connectable via the switches SWj to the node 21, plus an additional set m+1 of n / (2Am) capacitive elements preferably permanently connected to the node 21. The secondary DAC 4 can be configured to generate a secondary ramp of 2Aj steps and is therefore capable of generating m secondary ramps. The duration of the steps generated by the secondary DAC 4 is independent of the conversion gain and corresponds to the nominal frequency f, leading to a VRAMP ramp consisting of steps having a duration of T. The duration of the main DAC 3 steps corresponds to G*T, where G = 2Am.

[0069] Figures 5A and 5B represent two equivalent embodiments for generating a secondary ramp for a conversion gain of 2, i.e. to be associated with a main ramp using half of the capacitive elements Ci of the main network 3.

[0070] In the embodiment of [Fig.5A], the secondary DAC 4 receives, in addition to the ground, a voltage corresponding to half (1 / 2).VREF of the reference voltage VREF. A switch 51, controlled by a binary signal b0, connects a first electrode of a capacitive element 52 having a capacitance Cin either to a node at VREF / 2, or to the ground. The second electrode of the capacitive element 52 is connected, preferably connected, to the node 21.

[0071] In the embodiment of [Fig.5B], the secondary DAC receives, in addition to ground, the voltage VREF. A switch 53, controlled by a binary signal b0, connects a first electrode of a capacitive element 54 having a capacitance Cin / 2 either to a node at VREF, or to ground. The second electrode of the capacitive element 51 is connected, preferably connected, to the node 21.

[0072] When the desired conversion gain of the ramp generator is 1, the position of switch 51 or 53 has no impact, provided that it remains the same for the generation of the ramp provided by the main DAC.

[0073] [Fig.6] shows the operation of the secondary DAC of [Fig.5A] or 5B and the resulting ramp once added to the ramp generated by the main DAC 3.

[0074] This figure represents an example of the control signal bO (aspect 61), the corresponding signal provided by the secondary DAC 4 (aspect 65) with an amplitude of VREF / 2, the signal provided by the main DAC 3 with steps having an amplitude of VREF and a duration of 2T, and the resulting signal 67 with steps of amplitude VREF / 2 and duration T.

[0075] Figures 7A and 7B represent two equivalent embodiments for generating a secondary ramp for a conversion gain of 4, i.e. to be associated with a main ramp using a quarter of the capacitive elements Ci of the main network 3.

[0076] In the embodiment of [Fig.7A], the secondary DAC 4 receives, in addition to the ground, two voltages corresponding respectively to half (1 / 2).VREF of the reference voltage VREF and to a quarter (1 / 4).VREF of the reference voltage VREF. A switch 71, controlled by a binary signal bl (or the most significant bit of a 2-bit signal), connects a first electrode of a capacitive element 72 having a capacitance Cin either to the node at VREF / 2, or to ground. A switch 73, controlled by a binary signal b0 (or the least significant bit of a 2-bit signal), connects a first electrode of a capacitive element 74 having a capacitance Cin either to the node at VREF / 4, or to ground. The second electrodes of the capacitive elements 72 and 74 are interconnected at node 21.

[0077] In the embodiment of [Fig.7B], the secondary DAC 4 receives, in addition to the ground, three voltages having the amplitudes (1 / 4).VREF, (1 / 2).VREF and (3 / 4).VREF respectively. The four voltages (0, VREF / 4, VREF / 2, 3VREF / 4) are individually connected via a network 75 of four switches to a first electrode of a single capacitive element 76 having a capacitance Cin. The network 75 is controlled by a decoded 2-bit signal. The second electrode of the capacitive element 76 is connected, preferably connected, to the node 21.

[0078] The embodiment of [Fig.7A] corresponds to a so-called binary DAC and the embodiment of [Fig.7B] to a so-called thermometric DAC.

[0079] When the desired conversion gain of the ramp generator is 1, the position of switch 71 or 73, or of the switches of the network 75, has no impact provided that it remains the same during the generation of the ramp provided by the main DAC.

[0080] When the desired conversion gain of the ramp generator is 2, only switch 71, or positions VREF / 2 and ground of network 75, are used, and switch 73 (or positions 3VREF / 4 and VREF / 4 of network 75) remain in a fixed position.

[0081] [Fig.8] shows the operation of the secondary DAC of [Fig.7A] or 7B and the resulting ramp once added to the ramp generated by the main DAC 3.

[0082] This figure represents an example of decoded control signal 81, of the corresponding signal 83 supplied by the secondary DAC 4, of the signal 85 supplied by the main DAC 3 with steps of a duration of 4T, and the resulting signal 87 with steps of amplitude VREF / 4 and of a duration T.

[0083] The embodiments described in connection with Figures 7A and 7B can be extended to any number of bits depending on the desired conversion gain for the ramp generator.

[0084] [Fig.9] represents a variant of [Fig.3] in which the outputs of the capacitive elements Ci of the main network 3 are connected in series via the switches SW1, SW2 and SW3 instead of being connected in parallel as in [Fig.3],

[0085] The operation of the embodiment of [Fig.9] is identical to the operation of the embodiment of [Fig.3], with all switches SW1, SW2 and SW3 being closed for a conversion gain of 1, switch SW1 being open for a conversion gain of 2, switches SW1 and SW2 being open for a conversion gain of 4 and all switches SW1, SW2 and SW3 being open for a conversion gain of 8.

[0086] The principle described above can be applied to a different number of capacitive elements in order to adapt to different ratios and operating conditions.

[0087] Furthermore, the described solution can be combined with the solution of using multiple values ​​for the feedback capacity, as described in the already mentioned document FR2204819.

[0088] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0089] Finally, the practical implementation of the described embodiments and variants is within the reach of the person skilled in the art from the functional indications given above. In particular, the adaptation of the controller 142 to generate the appropriate control signals of the different switches is within the reach of the person skilled in the art, based on the above description.

Claims

Claims

1. Circuit comprising: a first capacitor network (3) comprising n nominally equal capacitive elements (Ci) each having a first electrode connected, via respective switches (Ki), either to a reference voltage (VREF) or to ground; a differential amplifier (25) having a first input (-) connected to an output (21) of said first capacitor network, a second input (+) connected to ground, and an output (28) providing a voltage ramp (VRAMP); and a capacitive feedback circuit (26) connecting the output of said differential amplifier to said first input;and a second capacitor network (4) one output of which is connected to the first input (-) of the differential amplifier (25), in which the input capacitive elements are organized in sets and the second electrodes of the input capacitive elements are interconnected, set by set, and controllably connected to said input of the amplifier.;

2. A circuit according to claim 1, wherein the capacitive elements are organized into m sets of n / (2Aj) capacitive elements, j ranging from 1 to m, plus one set of n / (2Am) capacitive elements, where 2Am represents a maximum conversion gain.

3. Circuit according to claim 1, in which the switching of the capacitive elements is carried out at a given frequency to define voltage steps in the output signal of the differential amplifier, the duration of the steps of the first network of capacitances (3) corresponds to the duration (T) of the steps of the second network of capacitances (4) multiplied by a conversion gain (G).

4. Circuit according to claim 2 or 3, in which the gain (G) conditions the number of sets connected to the first input of the amplifier (25).

5. A circuit according to any one of claims 1 to 4, wherein the second capacitor network (4) provides steps having an amplitude corresponding to the main DAC, divided by the conversion gain (G).

6. Circuit according to any one of claims 5 to 5, in which the sets of capacitive elements (Ci) of the first network of capacitances (3) are in parallel, m switches (SWj) individually connecting each of the first m sets to the first input (-) of the amplifier (25) and said set of n / (2Am) capacitive elements is permanently connected to said first input.

7. A circuit according to any one of claims 1 to 5, wherein each of the first m sets of capacitive elements (Ci) of the first capacitor network (3) is connected to the higher-ranking set of capacitive elements] by a switch (SWj) and said set of n / (2Am) capacitive elements is permanently connected to said first input.

8. A circuit according to any one of claims 1 to 7, wherein the frequency of the output steps remains the same for all conversion gains.

9. A method of controlling a circuit according to any one of claims 1 to 8.

10. Voltage ramp generator comprising a circuit according to one of claims 1 to 8.

11. A digital-to-analog converter comprising a voltage ramp generator according to claim 10.

12. Image sensor comprising at least one digital-to-analog converter according to claim 11.

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