Low inductance component

Abstract

To provide a low-inductance filter capacitance element (with an EMI / ESD protection function).SOLUTION: A low inductance component 100 includes a multilayer, monolithic device including a first active termination 104, a second active termination 106, a first ground termination 108, a second ground termination 110, and a pair of capacitors connected in series between the first and second active terminations. Active leads 112, 114, 116, 118 are coupled with the first active termination, second active termination, first ground termination and / or second ground termination, and have respective lengths 120 and maximum widths 124, where a ratio of the length to the maximum width of each lead is less than about 20.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is incorporated by reference in its entirety and has a filing date of 2019. This application claims the benefit of U.S. Provisional Patent Application No. 62 / 838,421, filed April 25, 2007. [Background technology]

[0002]

[0002] For some time now, the design of various electronic components has been driven by a trend toward miniaturization as well as increased functionality. This trend has been driven by a general industry trend towards multi-layer ceramic devices. Multi-layer ceramic devices, such as multi-layer ceramic capacitors and varistors, may consist of multiple dielectric electrode layers. During manufacturing, the layers may be pressed and formed into a vertically stacked structure. Multi-layer ceramic devices may contain a single capacitor or multiple capacitors. Such devices may be provided with lead wires for connection to other electrical components. However, the leads exhibit self-inductance that undesirably increases the overall inductance of the component. Summary of the Invention [Means for solving the problem]

[0003] According to one embodiment of the present invention, the low inductance component is a first active The multi-layer monolithic device may include a first active terminal, a second active terminal, at least one ground terminal, and a pair of capacitors connected in series between the first active terminal and the second active terminal. The leads may be coupled to the first active terminal, the second active terminal, and / or the at least one ground terminal. The leads may have respective lengths and maximum widths. A ratio of the length to the respective maximum widths of the leads may be less than about 20.

[0004] In accordance with another embodiment of the present invention, a method for forming a low inductance component is provided. The method may include providing a multilayer monolithic device body including electrodes forming a pair of capacitors; forming a first active terminal, a second active terminal, and at least one ground terminal external to the multilayer monolithic device body such that the pair of capacitors is connected in series between the first active terminal and the second active terminal; and connecting at least one lead to at least one of the first active terminal, the second active terminal, or the at least one ground terminal, wherein the at least one lead has a length and a maximum width, and a ratio of length to width of the at least one lead is less than about 20.

[0005]

[0005] Other features and aspects of the present invention are discussed in greater detail below.

[0006] A complete and effective disclosure of the subject matter of this disclosure, including the best mode thereof, directed to one of ordinary skill in the art. The disclosure is described herein with reference to the accompanying drawings in which: [Brief description of the drawings]

[0006] [Figure 1A]

[0007] 1 is an exterior perspective view of an exemplary embodiment of a low inductance component including leads in accordance with the subject matter of the present disclosure; FIG. [Figure 1B]

[0008] FIG. 1B illustrates another embodiment of a lead of the device of FIG. 1A according to an aspect of the present disclosure. [Diagram 2]

[0009] FIG. 2 is an exterior perspective view of another embodiment of a low inductance component including a discrete varistor in accordance with the subject matter of the present disclosure. [Figure 3A]

[0010] FIG. 1B illustrates a first electrode layer of the component of FIG. 1A, according to an embodiment of the presently disclosed subject matter. [Figure 3B] FIG. 1B illustrates a second electrode layer of the component of FIG. 1A, according to an embodiment of the presently disclosed subject matter. [Figure 3C]

[0011] 3B shows an electrode stack-up including a first electrode layer of FIG. 3A and a second electrode layer of FIG. 3B. [Figure 3D]

[0012] FIG. 1B is a schematic diagram of the device of FIG. 1A. [Figure 3E]

[0013] FIG. 3 is a schematic diagram of the device of FIG. 2. [Figure 4A]

[0014] FIG. 2 illustrates a first electrode layer of an electrode configuration of another embodiment of a low inductance component in accordance with aspects of the present disclosure. [Figure 4B] FIG. 13 illustrates a second electrode layer of an electrode configuration of another embodiment of a low inductance component in accordance with aspects of the present disclosure. [Figure 4C]

[0015] 4B shows an electrode stack including a first electrode layer of FIG. 4A and a second electrode layer of FIG. 4B. [Figure 5A]

[0016] FIG. 4B shows an additional electrode configuration including an additional capacitor compared to the electrode configurations described above with reference to FIGS. 3A to 4C. [Figure 5B]

[0017] FIG. 4B shows another additional electrode configuration including an additional capacitor compared to the electrode configuration described above with reference to FIGS. 3A to 4C. [Figure 6]

[0018] FIG. 6A is a schematic diagram of the device of FIG. 5A.

[0019] FIG. 6B is a schematic diagram of the device of FIG. 5B. [Figure 7]

[0020] 1 is a flow chart of a method for forming a low inductance component in accordance with the subject matter of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007]

[0021] Repeat use of reference characters throughout the present specification and the accompanying drawings is intended to represent the same or similar features, elements or steps thereof.

[0022] Reference will now be made in detail to various embodiments of the invention, one or more examples of which are set forth below. Each example is provided as an explanation of the invention, not a limitation of the invention. Indeed, it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope or spirit of the invention. For example, features illustrated or described as part of one embodiment can be used in another embodiment to yield yet a further embodiment. It is therefore intended that the present invention cover such modifications and variations as come within the scope of the appended claims and their equivalents.

[0008]

[0023] Generally speaking, the present invention relates to a low inductance component. The low inductance component may include one or more capacitors. Without intending to be limited by theory, a capacitor is an electrical component that stores electrical energy in an electric field. In some embodiments, the component may also include a discrete varistor connected with one or more capacitors. Without intending to be limited by theory, a varistor is an electrical component that has an electrical resistance that can change with applied voltage, thereby becoming a voltage-dependent resistor.

[0009]

[0024] The components may include one or more leads configured to exhibit low inductance. In certain applications, low inductance may be highly desirable. For example, aspects of the present disclosure may be particularly useful in automotive applications, such as motor start-stop applications.

[0010]

[0025] The low inductance leads may be coupled to the first active terminal, the second active terminal, and / or the ground terminal of the component. The leads may have a respective length and a maximum width. The ratio of the length to the respective maximum width of the leads is less than about 50, in some embodiments less than about 30, in some embodiments less than about 20, in some embodiments less than about 15, in some embodiments less than about 10, in some embodiments less than about 8, and in some embodiments less than about 10. In some embodiments, it may be less than about 5, in some embodiments, less than about 4, and in some embodiments, less than about 2.

[0011]

[0026] The leads may have a variety of suitable cross-sectional shapes. For example, one or more leads may have a generally rectangular cross-section. The generally rectangular cross-section may have a maximum width in a first direction and a minimum width in a second direction that is perpendicular to the first direction. The ratio of the maximum width to the minimum width may be greater than about 2, in some embodiments greater than about 3, in some embodiments greater than about 4, in some embodiments greater than about 5, in some embodiments greater than about 8, in some embodiments greater than about 10, in some embodiments greater than about 20, in some embodiments greater than 50, and in some embodiments greater than 100. However, in other embodiments, the leads may have a cross-sectional shape that is circular, oval, polygonal, or any other suitable shape.

[0012]

[0027] In some embodiments, one or more leads may comprise multiple elongated conductive members woven, braided, or otherwise configured together to form the lead.

[0013]

[0028] The above features may result in a low inductance component that may include one or more capacitors. For example, the first capacitor and the second capacitor may be connected to the first active terminal, the second active terminal, and at least one ground terminal in a split feedthrough type construction. The first and second capacitors may be formed by internal electrodes separated by a dielectric layer.

[0014]

[0029] In some embodiments, a discrete varistor is combined with the multi-layer monolithic device to form a low-inductance integrated component with both capacitor and varistor functions. The discrete varistor may include a first external varistor terminal connected with a first active terminal of the multi-layer capacitor and a second external varistor terminal connected with a second active terminal. For example, the discrete varistor and the multi-layer capacitor may be stacked to form a single monolithic component. The combination of the capacitor and the varistor may provide low-inductance filtering and EMI and / or EMI / ESD circuit protection in a single package, which may be particularly useful when space is limited. Furthermore, integrating the capacitor and varistor functions into one component reduces inductance compared to two separate components, each of which exhibits its own parasitic inductance (e.g., caused by their respective leads).

[0015]

[0030] In some embodiments, the leads can be connected to external terminals and / or the components can be overmolded. Thus, the overmolded layer can encapsulate the discrete varistor and multi-layer monolithic capacitor devices. The overmolded layer can protect the components from damage due to, for example, impact or moisture.

[0016]

[0031] As indicated above, the first and second capacitors may be configured in a split feed-through type configuration. For example, the first plurality of electrode layers may be disposed within the body and connected to a first active terminal. The second plurality of electrode layers may be disposed within the body and connected to a second active terminal. The third plurality of electrode layers may be connected to a ground terminal and may be capacitively coupled to each of the first and second plurality of electrode layers (e.g., in a split feed-through type configuration). The first capacitor may be formed in a first overlap region between the first and third plurality of electrode layers. The second capacitor may be formed in a second overlap region between the second and third plurality of electrode layers. It is possible.

[0017]

[0032] In one embodiment, the first capacitor may have a first capacitance and the second capacitor may have a second capacitance. In some embodiments, the first and second overlap areas may be approximately equal, such that the second capacitance may be approximately equal to the first capacitance. However, in other embodiments, the first and second overlap areas may be different, such that the first capacitance may be greater or less than the second capacitance.

[0018]

[0033] For example, at least one of the first capacitances of the second capacitances can be in the range of about 10 nF to about 3 μF, in some embodiments in the range of about 200 nF to about 2 μF, and in some embodiments in the range of about 400 nF to about 1.5 μF. The second capacitance can be in the range of about 5% to about 500%, in some embodiments in the range of about 10% to about 300%, in some embodiments in the range of about 25% to about 200%, and in some embodiments in the range of about 50% to about 150% of the first capacitance.

[0019]

[0034] In some embodiments, the third plurality of electrode layers can be generally cross-shaped and can connect with a pair of opposing ground terminals. For example, the third plurality of electrode layers can each include a pair of opposing edges. One of the opposing edges can connect with a first ground terminal and the other of the opposing edges can connect with a second ground terminal.

[0020]

[0035] The multilayer monolithic capacitor device may not include any additional capacitors formed within the monolithic body. For example, the first, second, and third plurality of electrodes may be comprised of electrode stacks that extend through a majority of the thickness of the monolithic body. For example, the ratio of the thickness of the electrode stacks to the thickness of the monolithic body may range from about 0.5 to about 0.97, in some embodiments, from about 0.6 to about 0.95, and in some embodiments, from about 0.7 to about 0.9.

[0021]

[0036] In general, the dielectric layer of the multi-layer monolithic device can be made of any material commonly applied in the art. For example, the dielectric layer can be made of a ceramic material containing titanate as a main component. The titanate can include, but is not limited to, barium titanate (BaTiO3). The ceramic material can also include oxides of rare earth metals and / or compounds of acceptor-type elements such as Mn, V, Cr, Mo, Fe, Ni, Cu, Co, etc. The titanate can also include MgO, CaO, Mn3O4, Y2O3, V2O5, ZnO, ZrO2, Nb2O5, Cr2O3, Fe2O3, P2O5, SrO, Na2O, K2O, Li2O, SiO2, WO3, etc. The ceramic material can also include other additives, organic solvents, plasticizers, binders, dispersants, etc. in addition to the ceramic powder.

[0022]

[0037] In general, the internal electrodes of the multilayer monolithic device can be made of any material commonly applied in the art. For example, the internal electrodes can be formed by sintering a conductive paste whose main component is a precious metal material. These materials can include, but are not limited to, palladium, palladium-silver alloy, nickel, and copper. For example, in one embodiment, the electrodes can be made of nickel or nickel alloy. The alloy can include one or more of Mn, Cr, Co, Al, W, etc., and the Ni content in the alloy is preferably 95% by weight or more. The Ni or Ni alloy can include various trace elements, such as P, C, Nb, Fe, Cl, B, Li, Na, K, F, S, etc., with 0.1% by weight or less.

[0023]

[0038] The ceramic body of the multilayer monolithic device can be formed using any method commonly known in the art, for example, by forming a stack of alternating ceramic sheets and patterned internal electrodes, removing the binder from the stack, sintering the debindered stack at high temperatures in the range of 1200° C. to 1300° C. in a non-oxidizing atmosphere, and reoxidizing the sintered stack in an oxidizing atmosphere.

[0024]

[0039] In general, the varistor may be configured to divert electrical surges to ground. For example, the varistor may have a clamping voltage in the range of about 3 volts to about 150 volts, in some embodiments about 5 volts to about 100 volts, in some embodiments about 10 volts to about 50 volts, and in some embodiments about 15 volts to about 30 volts.

[0025]

[0040] The varistor may include a ceramic body with an external electrode, the ceramic body being fabricated by sintering a laminate of alternating ceramic layers and internal electrodes, each pair of adjacent internal electrodes facing each other with a ceramic layer between them, each of which may be electrically coupled to a different external electrode.

[0026]

[0041] In general, the dielectric layer may include any suitable dielectric material, such as, for example, barium titanate, zinc oxide, or any other suitable dielectric material. For example, various additives may be included in the dielectric material to create or enhance the potential-dependent resistance of the dielectric material. For example, in some embodiments, the additive may include an oxide of cobalt, bismuth, manganese, or combinations thereof. In some embodiments, the additive may include an oxide of gallium, aluminum, antimony, chromium, boron, titanium, lead, barium, nickel, vanadium, tin, or combinations thereof. The dielectric material may be doped with an additive in a range of about 0.5 mole percent to about 3 mole percent, and in some embodiments, in a range of about 1 mole percent to about 2 mole percent. The average grain size of the dielectric material may contribute to the nonlinear properties of the dielectric material. In some embodiments, the average grain size may be in a range of about 10 microns to 100 microns, and in some embodiments, in a range of about 20 microns to 80 microns. The varistor may also include two terminals, and each electrode may be connected with a respective terminal. The electrodes may provide resistance along their length and / or at the connections between the electrodes and the terminals.

[0027]

[0042] In general, the internal electrodes can be made of any material commonly used in the art. For example, the internal electrodes can be formed by sintering a conductive paste whose main component is a precious metal material. These materials can include, but are not limited to, palladium, palladium-silver alloy, silver, nickel, and copper. For example, in one embodiment, the electrodes can be made of nickel or a nickel alloy. The alloy can include one or more of Mn, Cr, Co, Al, W, etc., and the Ni content in the alloy is preferably 95% by weight or more. The Ni or Ni alloy can include various trace elements, such as P, C, Nb, Fe, Cl, B, Li, Na, K, F, S, etc., at 0.1% by weight or less.

[0028]

[0043] The components may have a variety of sizes. For example, the components may have case sizes ranging from EIA 0504 or smaller to EIA 2920 or larger. Example case sizes include 0805, 1206, 1806, 2020, etc.

[0029]

[0044] Exemplary embodiments will now be described with reference to the drawings. FIG. 1A illustrates an exterior perspective view of an exemplary embodiment of a low inductance component 100 generally in accordance with the subject matter of this disclosure. As illustrated, the component 100 may include a body 102, such as a hexahedron. The component 100 includes a first active terminal 104, a second active terminal 106, a first terminal 108, a second terminal 109, a first terminal 200, a second terminal 210, a second terminal 220, a first terminal 230, a second terminal 240, a second terminal 250, a second terminal 260, a first terminal 270, a second terminal 280, a second terminal 290, a second terminal 300, a second terminal 310, a second terminal 320, a second terminal 330, a second terminal 340, a second terminal 350, a first terminal 360, a second terminal 370, a second terminal 380, a second terminal 39 ... It may include a ground terminal 108 and a second ground terminal 110 .

[0030]

[0045] The first and second active leads 112 and 114 may be connected to the first and second active terminals 104 and 106, respectively. The first and second ground leads 116 and 118 may be connected to the first and second ground terminals 108 and 110, respectively.

[0031]

[0046] One or more of the leads 112, 114, 116, 118 may have a length and a maximum width. The ratio of the length to the maximum width of at least one lead may be less than about 20. For example, the first active lead 112 may have a length 120 in the Z direction 122, a maximum width 124 in the X direction 126, and a minimum width 127 in the Y direction 128. The ratio of the maximum width 124 to the minimum width 127 may be greater than about 2. The first active lead 112 may have a generally rectangular cross-sectional shape, for example, the first active lead 112 may be generally flattened or ribbon-shaped. In some embodiments, the ratio of the length to the maximum width of one or more of the leads 112, 114, 116, 118 may be less than about 20. In some embodiments, each lead may have a respective length and width with a respective ratio that is less than about 20.

[0032]

[0047] 1B illustrates another embodiment of a lead 132 according to aspects of the present disclosure. The lead 132 may have a generally circular or oval cross-sectional shape. The lead 132 may have a maximum width 134 and a minimum width 136. In other embodiments, the lead may comprise a plurality of elongated braided conductive members.

[0033]

[0048] 2 illustrates an exterior perspective view of another embodiment of a component 200 in accordance with the subject matter of the present disclosure. Component 200 may include a multi-layer monolithic device 201, which may include a body 202, such as a hexahedron, a first active terminal 204, a second active terminal 206, a first ground terminal 208, and a second ground terminal 210, for example, as described above with reference to FIG. 1A.

[0034]

[0049] The component 200 may include a discrete varistor 240 having a first external varistor terminal 242 and a second external varistor terminal 244. The component 200 may include a first active lead 246 coupled to each of the first external varistor terminals 242 and the first active terminal 204 of the multilayer monolithic capacitor device 201. The component 200 may include a second active lead 248 coupled to each of the second external varistor terminals 244 and the second active terminals 206 of the multilayer monolithic capacitor device 201.

[0035]

[0050] One or more of the leads 246, 248, 250, 251 may have a length and a maximum width, for example, as described above with reference to FIG. 1A. The ratio of the length to the maximum width of one or more of the leads 246, 248, 250, 251 may be less than about 20. For example, as shown with reference to FIG. 2, the first active lead 248 may have a length 252 in the Z direction 122, a maximum width 254 in the X direction 126, and a minimum width 256 in the Y direction 128. The ratio of the maximum width 254 to the minimum width 256 may be greater than about 2. The first active lead 248 may have a generally rectangular cross-sectional shape. For example, the first active lead 248 may be generally flattened (e.g., like a ribbon shape). In some embodiments, each of the leads 246,248,250,251 can have a respective length that is at least 20 times greater than the respective maximum width of the leads 246,248,250,251.

[0036]

[0051] The low inductance component 100 of FIG. 1A and / or the multi-layer monolithic component 100 of FIG. The thick capacitor device 201 may include two capacitors formed in series between a first terminal and a second terminal, for example as described herein. As will be understood by those skilled in the art in connection with all of the embodiments described herein, the cooperating layers in the subject multi-layer structures comprise electrode layers, which then form an integrated capacitive structure.

[0037]

[0052] FIG. 3A shows a first electrode layer 320. The first electrode layer 320 is described with reference to the component 100 of FIG. 1A. However, it should be understood that the multilayer monolithic capacitor device 201 of FIG. 2 may be similarly configured. The first electrode layer 320 may include a cross-shaped electrode 322 having a pair of opposing edges 324, 326 connected to the first and second ground terminals 108, 110 of the component 100 of FIG. 1A, respectively. FIG. 3B shows a second electrode layer 328 including a first electrode 330 connected to the first active terminal 104 (FIG. 1A) and a second electrode 332 connected to the second active terminal 106 (FIG. 1A). FIG. 3C shows a stack of alternating first and second electrode layers 320, 328.

[0038]

[0053] FIG. 3D shows a schematic diagram 300 of the device 100 of FIG. 1A. The device 100 can provide a single device solution for accommodating series and parallel capacitors. The device 100 can include a first capacitor 338 and a second capacitor 340. As shown again with reference to FIGS. 3A and 3B, the first capacitor 338 can be formed in a first overlap region 334 between the cross-shaped electrode 322 and the first electrode 330. The second capacitor 356 can be formed in a second overlap region 336 between the cross-shaped electrode 322 and the second electrode 332. The first overlap region 334 can be approximately equal to the second overlap region 336 such that the first capacitor and the second capacitor exhibit approximately equal capacitances. However, in other embodiments, the first overlap area 334 may be larger or smaller than the second overlap area 336, such that the first capacitance may be larger or smaller than the second capacitance. One or both of the first capacitance and the second capacitance may range from about 10 nF to about 3 μF.

[0039]

[0054] The first active lead 112 may be connected to a first capacitor 338 (e.g., via the first active terminal 104 shown in FIG. 1). The second active lead 114 may be connected to a second capacitor 340 (e.g., via the second active terminal 106 shown in FIG. 1). The first and second ground leads 116, 118 may be connected at a location between the first and second capacitors 338, 340 in a split feedthrough configuration. For example, the first and second ground leads 116, 118 may be connected to the ground terminals 180, 110, respectively (FIG. 1A).

[0040]

[0055] Figure 3E shows a schematic diagram 350 of the device 200 of Figure 2. A varistor 352 may be electrically connected between the active leads 112, 114.

[0056] 4A and 4B show electrode configurations of another embodiment of a multilayer capacitor according to aspects of the present disclosure. As shown with reference to FIG. 4A, a first electrode layer 420 may include a cross-shaped electrode 222 having a pair of opposing edges 424, 426 that may be connected to the first and second ground terminals 108, 110 (FIG. 1A), respectively. FIG. 4B shows a second electrode layer 428 including a first electrode 430 connected to the first active terminal 104 and a second electrode 432 connected to the second active terminal 106. FIG. 4C shows a stack of alternating first and second electrode layers 420, 428. As shown again with reference to FIG. 4A , the cross-shaped electrode 422 may overlap the first electrode 430 along a first overlap region 434 to form a first capacitor 438 and may overlap the second electrode 432 along a second overlap region 436 to form a second capacitor 440.

[0041]

[0057] 5A and 5B show respective additional electrode configurations including additional capacitors with respect to the electrode configurations described above with reference to FIGS. 3A to 4C. The electrode configurations of FIGS. 5A and 5B are described with reference to the component 100 of FIG. 1A. However, it should be understood that the multilayer monolithic capacitor device 201 of FIG. 2 may be similarly configured. As shown with reference to FIG. 5A, the first electrode configuration 500 may include a first region 501 and a second region 508. The first region may include, for example, a cross-shaped electrode 502, a first electrode 504, and a second electrode 506, as described above with reference to FIGS. 3A to 3C.

[0042]

[0058] The second region 508 may include a third capacitor formed by a plurality of third electrodes 510 interleaved with a plurality of fourth electrodes 512. The third electrode 510 may be connected to the first active terminal 104 (FIG. 1A), and the fourth electrode 512 may be connected to the second active terminal 106 (FIG. 1A).

[0043]

[0059] 5B shows a second electrode configuration 550 including a first region 552, a second region 554, and a third region 556. The first region 552 may include an electrode stack including one or more cross-shaped electrodes 558, one or more first electrodes 560, and one or more second electrodes 562, for example, as described above with reference to FIGS.

[0044]

[0060] The second region 554 may include a plurality of third electrodes 564 interleaved with a plurality of fourth electrodes 566. The third electrodes 564 may be connected to the first active terminal 104 (FIG. 1A), and the fourth electrodes 556 may be connected to the second active terminal 106 (FIG. 1A).

[0045]

[0061] The third region 556 may include an electrode stack including a cross-shaped electrode 568, a first electrode 570, and a second electrode 572, for example, as described above with reference to Figures 3A-3C.

[0046]

[0062] FIG. 6A shows a schematic diagram 600 of the device 500 of FIG. 5A. More specifically, the device 500 may include active leads 602, 603. A first capacitor 604 and a second capacitor 606 may be formed in a first region 607, for example, as described above with respect to FIG. 5A. A ground lead 610 may be connected at a location between the first capacitor 604 and the second capacitor 606 (e.g., connected to the cross-shaped electrode 502 described above with reference to FIG. 5A). A third capacitor 608 may be electrically connected in parallel with the first and second capacitors 604, 606, between the active leads 602, 603, in a second region 609, for example, as described above with respect to FIG. 5A.

[0047]

[0063] Figure 6B shows a schematic diagram 650 of the device 550 of Figure 5B. The device 550 may be generally configured similarly to the device 500 of Figure 5A. In addition, a varistor 660 may be connected in parallel with the capacitors 654, 656, 658 between the active leads 648 and 652.

[0048]

[0064] FIG. 7 is a flow chart of a method 700 for forming a low inductance component. Generally, the method 700 is described herein with reference to the components 100, 200 of FIG. 1A and FIG. 2. However, it should be understood that the disclosed method 700 may be practiced with any suitable components. In addition, while FIG. 7 depicts steps performed in a particular order for purposes of illustration and explanation, the methods described herein are not limited to any particular order or arrangement. Those skilled in the art using the disclosure provided herein will be able to easily modify the various steps of the methods disclosed herein without departing from the scope of the disclosure. It will be understood that the groups may be omitted, rearranged, combined, and / or adapted in various ways.

[0049]

[0065] The method 700 may include, at 702, providing a multi-layer capacitor body including electrodes forming a pair of capacitors, for example as described above with reference to Figures 1A-6B.

[0050]

[0066] The method 700 may include, for example, forming (704) a first active terminal, a second active terminal, and at least one ground terminal external to the multilayer capacitor body such that a pair of capacitors are connected in series between the first active terminal and the second active terminal, as described above with reference to FIGS. 1A-6B.

[0051]

[0067] The method 700 may include, at 706, connecting at least one lead to at least one of the first active terminal, the second active terminal, or the at least one ground terminal. The leads may have respective lengths and maximum widths. A ratio of length to width of each of the at least one lead (if multiple leads are present) may be less than about 20.

[0052]

[0068] It should be understood that the individual steps in achieving the disclosed configurations are intended to be representative only and do not indicate the necessary use of other aspects beyond the general nature of the disclosure otherwise set forth For example, one skilled in the art will recognize that selected steps may be implemented to produce a particular design selected for a given application of the subject matter of the present disclosure.

[0053]

[0069] Although such subject matter of the present disclosure has been described in detail with respect to specific embodiments thereof, it will be understood that those skilled in the art, upon arriving at the foregoing understanding, can readily produce modifications, variations, and equivalents to such embodiments. Accordingly, the scope of the present disclosure is by way of example, not limitation, and the disclosure of the subject matter does not exclude the inclusion of such modifications, variations, and / or additions to the subject matter of the present disclosure, as would be readily apparent to one skilled in the art.

Claims

1. a multi-layer monolithic device comprising a first active terminal, a second active terminal, at least one ground terminal, and a pair of capacitors connected in series between the first active terminal and the second active terminal; at least one lead coupled to at least one of the first active terminal, the second active terminal, or the at least one ground terminal; the at least one lead has a length in a Z direction and a maximum width in a first direction perpendicular to the Z direction; a ratio of the length to the maximum width of the at least one lead is less than about 20; Low inductance components.

2. 2. The low inductance component of claim 1, wherein the at least one lead has a generally rectangular cross-section, the generally rectangular cross-section having a maximum width in a first direction and a minimum width in a second direction perpendicular to the first direction.

3. 3. The low inductance component of claim 2, wherein the at least one lead includes at least one ground lead connected with the at least one ground terminal, the at least one ground terminal having a ground terminal width in the first direction, the maximum width being approximately equal to the ground terminal width.

4. The low inductance component of claim 2 , wherein a ratio of said maximum width to said minimum width is greater than about 3.

5. 2. The low inductance component of claim 1, wherein the at least one lead comprises a first active lead, a second active lead, and at least one ground lead connected to the first active terminal, the second active terminal, and the at least one ground terminal, respectively.

6. 2. The low inductance component of claim 1, further comprising a discrete varistor comprising a first external varistor terminal and a second external varistor terminal, the at least one lead comprising a first lead coupled with each of the first active terminal and the first external varistor terminal.

7. The low inductance component of claim 1 , wherein at least one lead comprises a plurality of interwoven elongated conductive members.

8. the pair of capacitors comprises a first capacitor and a second capacitor, the multi-layer monolithic device further comprising: a body comprising a plurality of dielectric layers; a first plurality of electrode layers disposed within the body and connected to the first active terminal; a second plurality of electrode layers disposed within the body and connected to the second active terminal; 2. The low inductance component of claim 1, comprising: a third plurality of electrode layers connected to the at least one ground terminal, the third plurality of electrode layers capacitively coupled to each of the first plurality of electrode layers and the second plurality of electrode layers to form the first capacitor between the first plurality of electrode layers and the third plurality of electrode layers, and the second capacitor between the second plurality of electrode layers and the third plurality of electrode layers.

9. The low inductance component of claim 8 , wherein the third plurality of electrode layers are generally cross-shaped.

10. 9. The low inductance component of claim 8, wherein the at least one ground terminal comprises a first ground terminal and a second ground terminal, and each of the third plurality of electrode layers comprises the pair of opposing edges, one of the opposing edges being connected with the first ground terminal and the other of the opposing edges being connected with the second ground terminal.

11. The low inductance component of claim 10 , wherein the first ground terminal is located opposite the second ground terminal.

12. 9. The low inductance component of claim 8, wherein a ratio of a stack thickness of the first plurality of electrode layers, the second plurality of electrode layers, and the third plurality of electrode layers to a thickness of the body ranges from about 0.6 to about 0.

95.

13. 9. The low inductance component of claim 8, wherein the first capacitor has a first capacitance and the second capacitor has a second capacitance, and at least one of the first capacitance or the second capacitance is in a range from about 10 nF to about 3 μF.

14. the third plurality of electrode layers overlapping the first plurality of electrode layers along a first overlap region; The low inductance component of claim 8 , wherein the third plurality of electrode layers overlap the second plurality of electrode layers along a second overlap area that is equal to the first overlap area.

15. The low inductance component of claim 6 , wherein the discrete varistors are stacked relative to the multi-layer monolithic device.

16. The low inductance component of claim 6 further comprising an overmold layer encapsulating the discrete varistor and the multi-layer monolithic device.

17. The low inductance component of claim 8 , wherein a ratio of electrode stack thickness to body thickness is greater than about 0.

4.

18. 9. The low inductance component of claim 8, further comprising: a fourth plurality of electrodes connected to the first external terminal; and a fifth plurality of electrodes connected to the second external terminal and interleaved with the fourth plurality of electrodes to form a third capacitor.

19. 1. A method for forming a low inductance component, comprising: providing a multi-layer monolithic device body including electrodes forming a pair of capacitors; forming a first active terminal, a second active terminal, and at least one ground terminal external to the multilayer monolithic device body such that the pair of capacitors are connected in series between the first active terminal and the second active terminal; and connecting at least one lead to at least one of the first active terminal, the second active terminal, or the at least one ground terminal. the at least one lead has a length in a Z direction and a maximum width in a first direction perpendicular to the Z direction; The ratio of the length to the width of the at least one lead is less than about 20.

20. A low inductance component, a multi-layer monolithic device comprising a first active terminal, a second active terminal, at least one ground terminal, and a pair of capacitors connected in series between the first active terminal and the second active terminal; a discrete varistor having a first external varistor terminal and a second external varistor terminal; at least one lead coupled to at least one of the first active terminal, the second active terminal, the at least one ground terminal, the first external varistor terminal, or the second external varistor terminal; the at least one lead has a length and a maximum width, the ratio of the length to the maximum width of the at least one lead being less than 20; the at least one lead has a generally rectangular cross-section, the generally rectangular cross-section having the maximum width in a first direction and a minimum width in a second direction perpendicular to the first direction, the ratio of the maximum width to the minimum width being greater than 2; A low inductance component, wherein the at least one lead comprises at least one ground lead connected to at least one ground terminal, the at least one ground terminal having a ground terminal width in the first direction, the maximum width being approximately equal to the ground terminal width.

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