Reference Buffer

Abstract

The reference voltage generator (200) includes a comparator (225), a digital-to-analog converter (DAC) (255), and a switched capacitor accumulator (160). The comparator receives a reference voltage input (144), a feedback input (195), and a control signal (148). The DAC is coupled to the output of the comparator, and the switched capacitor accumulator is coupled to the output of the DAC. In some implementations, a digital filter is coupled between the output of the comparator and the input of the DAC. The switched capacitor accumulator may be coupled to a buffer (170) that outputs the feedback input and a reference voltage (130) for an analog-to-digital converter (ADC). In some implementations, the feedback loop includes N 1-bit DACs coupled to the output of the comparator, and N switched capacitor accumulators, each coupled to a unique 1-bit DAC.

Description

[Technical field]

[0001] Successive approximation register (SAR) analog-to-digital converters (ADCs) are common in multi-channel data acquisition systems, such as ultrasound and other medical imaging systems, manufacturing inspection and quality control systems, and temperature and stress sensing systems, among others. In a SAR ADC, a reference voltage output by a buffer is used to charge a capacitor during the HOLD or CONVERT phase, which allows the reference voltage to dip rather than remain constant. Some reference buffers include an error amplifier and a capacitor to help correct the dip in the reference voltage and maintain the level or DC reference voltage with a desired accuracy. However, the error amplifier and the capacitor occupy a large area of ​​the integrated circuit and consume a large amount of power. Also, the error amplifier adjusts the level or DC value of the reference voltage based on the time-averaged value of the reference voltage, including the transient dip. Because the transient dip contains signal and harmonic components, the error amplifier adjustment to the level or DC value of the reference voltage based on the time-averaged value of the reference voltage may introduce fundamental and harmonic errors into the ADC output. Summary of the Invention

[0002] The feedback loop includes a comparator, a digital-to-analog converter (DAC), and a switched-capacitor accumulator. The comparator has a first input for a reference voltage input, a second input for a feedback input, and a third input for a control signal. The DAC is coupled to an output of the comparator, and the switched-capacitor accumulator is coupled to an output of the DAC. In some implementations, a digital filter is coupled between an output of the comparator and an input of the DAC. In some examples, the feedback loop is coupled to a buffer configured to output the feedback input and a reference voltage for an analog-to-digital converter (ADC).

[0003] In some examples, the multiple feedback loops share a common comparator. A first feedback loop receives a second control signal and a second feedback loop receives a third control signal. A buffer is coupled to an output of the first feedback loop. A selector logic circuit receives a reference voltage input and an output of the buffer and outputs a feedback input. A control input of the selector logic circuit receives the second control signal. The second feedback loop outputs an offset correction signal for the comparator.

[0004] In some implementations where multiple feedback loops share a common comparator, a first feedback loop receives a first clock signal and a second feedback loop receives a second clock signal. A first buffer coupled to an output of the first feedback loop outputs a first reference voltage output and a second buffer coupled to an output of the second feedback loop outputs a second reference voltage output. A selector logic circuit receives the first and second reference voltage outputs and outputs a feedback input. A control input of the selector logic circuit receives the first clock signal. [Brief description of the drawings]

[0005] For a detailed description of various examples, reference will now be made to the accompanying drawings.

[0006] [Figure 1A] 1 illustrates a graph of the SAMPLE and CONVERT control signals for an analog-to-digital converter (ADC) and a reference voltage provided to the ADC.

[0007] [Figure 1B] 1B illustrates an example reference voltage generator configured to provide the reference voltages shown in FIG. 1A.

[0008] [Figure 2A] 1 illustrates a reference voltage generator having a 1-bit digital feedback loop.

[0009] [Figure 2B] 2B is a graph of a control signal in the reference voltage generator shown in FIG. 2A.

[0010] [Diagram 3] 1 illustrates a reference voltage generator having a 1-bit digital feedback loop and a bias voltage.

[0011] [Figure 4] 1 illustrates a reference voltage generator having a 1-bit digital feedback loop, a bias voltage, and a digital filter.

[0012] [Figure 5A] 1 illustrates a reference voltage generator having a shared comparator for multiple reference voltage outputs.

[0013] [Figure 5B] 5B is a graph of the control signal and the reference voltage in the reference voltage generator shown in FIG. 5A.

[0014] [Figure 6A] 1 illustrates a reference voltage generator with auto-zeroing.

[0015] [Figure 6B] 6B illustrates a graph of a control signal in the reference voltage generator shown in FIG. 6A.

[0016] In the drawings, the same reference numbers are used to denote the same or similar (by function and / or structure) features. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] The described digital feedback loop includes a comparator, a 1-bit digital-to-analog converter (DAC), and a switched-capacitor accumulator. Some example circuit elements occupy less area and consume less power than a conventional analog error amplifier and capacitor. Also, because the feedback loop is digital instead of analog, the feedback loop adjusts the reference voltage output based on a setpoint of the reference voltage instead of the time-averaged value of the reference voltage. In some examples, the digital feedback loop further includes a digital filter to reduce noise from the comparator and a bias voltage to improve direct current (DC) gain.

[0018] 1A illustrates graphs of the SAMPLE and CONVERT control signals in an analog-to-digital converter (ADC) and the reference voltages provided to the ADC. The control signals SAMPLE 105 and CONVERT 110 are inverted relative to each other. In a successive approximation register (SAR) ADC, the reference buffer output REF_OUT 130 charges a capacitor during the CONVERT phase, which allows REF_OUT 130 to dip rather than remain constant.

[0019] Some conventional reference buffers maintain a time average VREF_AVERAGE 115 of REF_OUT 130 approximately equal to the input reference voltage. The settling value VREF_SETTLED 120 of REF_OUT 130 is not equal to the input reference voltage and contains signal and harmonic components that cause signal gain and harmonic errors in the SAR ADC. To reduce the effect of transient dips in REF_OUT 130, an additional SAR comparison cycle, called a dynamic error correction cycle, can be inserted during the CONVERT phase. Dynamic Error Correction Cycle allows the reference voltage generator for the ADC to set a settling value VREF_SETTLED 120 equal to the input reference voltage, rather than the time average VREF_AVERAGE 115.

[0020] FIG. 1B illustrates a reference voltage generator 100 with a digital feedback loop 140 that corrects errors in VREF_SETTLED 120 but not VREF_AVERAGE 115. For ease of explanation, reference voltage generator 100 is described herein with reference to FIG. 1A and includes a low bandwidth, high gain digital feedback loop 140 and a buffer stage 170. Digital feedback loop 140 has a smaller area (e.g., area on a semiconductor substrate) than an analog feedback loop with high gain amplifiers and capacitors. In some examples, feedback loop 140 is implemented with ADC 150, DAC 155, and switched capacitor accumulator 160. Buffer stage 170 is a high bandwidth buffer stage for fast settling and is implemented with a flipped voltage follower in this example, although any suitable buffer stage may be used.

[0021] The ADC 150 in the digital feedback loop 140, which may be any suitable type of ADC or multi-bit digitizer, receives a reference voltage input VREF_IN 144, a clock input LATP 148, and a reference feedback signal REF_FB 195. The output of the ADC 150 is provided to a DAC 155, which also receives the SAMPLE 105. The analog output of the DAC 155 is provided to a switched capacitor accumulator 160, which includes a switch 164 and a storage capacitor CD 168. One terminal of the switch 164 is coupled to an input of the switched capacitor accumulator 160, which switch 164 is controlled by the CONVERT 110. The capacitor CD 168 is coupled between the other terminal of the switch 164 and a common potential (e.g., ground) 194. The voltage VSTG1 is the output of the digital feedback loop 140 integrated into CD 168 and is provided to the input of the buffer stage 170.

[0022] The buffer stage 170 is a flipped voltage follower in this example and includes transistors M1-M2, a current source 175, two resistors 180 and 185 with R1 and R2, respectively, and a capacitor 190 with capacitance C. The transistors M1-M2 are metal oxide semiconductor field effect transistors (MOSFETs). The M1-M2 are p-type MOSFETs (PMOS) in this example. In other examples, one or more of the M1-M2 are n-type MOSFETs (NMOS) or bipolar junction transistors (BJTs). The BJT includes a base corresponding to the gate terminal, and a collector and an emitter corresponding to the drain and source terminals of the MOSFETs. The base of the BJT and the gate terminal of the MOSFET are also referred to as the control input. The collector and emitter of the BJT and the drain and source terminals of the MOSFET are also referred to as the current terminals.

[0023] A source terminal of M1 is coupled to a supply voltage rail VDD 198 (e.g., 5 volts) and a drain terminal of M1 is coupled to a source terminal of M2. The drain terminal of M2 and the gate terminal of M1 are coupled to an input of a current source 175, which is further coupled to ground 194. The gate terminal of M2 is coupled to an output of a digital feedback loop 140. A resistor 180 has a first terminal coupled to the drain terminal of M1 and the source terminal of M2 and a second terminal coupled to an output of a buffer stage 170 configured to provide a reference voltage REF_OUT 130.

[0024] A resistor 185 has a first terminal coupled to the output of buffer stage 170 and the second terminal of resistor 180, and a second terminal coupled to a first terminal of a capacitor 190. A second terminal of capacitor 190 is coupled to ground 194. A reference feedback signal REF_FB 195 is output from between the drain terminal of M1 and the source terminal of M2 to the ADC 150, and a reference voltage output REF_OUT 130 is output from buffer stage 170 to the ADC.

[0025] M1 and M2 act as an analog amplifier, causing the voltage at the first terminal of resistor 180 to be approximately equal to voltage VSTG1 plus the threshold voltage of M2. The voltage across current source 175 causes M1 to operate as a closed switch, and current flows through M1 through resistors 180 and 185 and capacitor 190 to generate the output reference voltage REF_OUT 130 from buffer stage 170. In response to voltage VSTG1 being greater than the threshold voltage Vth of M2, M2 acts as a closed switch. While M2 acts as a closed switch, the current through M1 flows through M2 and current source 175, as well as through resistors 180 and 185 and capacitor 190, changing the value of output reference voltage REF_OUT 130 to be equal to input reference voltage VREF_IN 144.

[0026] FIG. 2A illustrates a reference voltage generator 200 with a 1-bit digital feedback loop. For ease of explanation, the reference voltage generator 200 is described herein with reference to FIGS. 1A and 1B and includes a comparator 225, a 1-bit DAC 255, and a switched capacitor accumulator 160. The DAC 255 is a 1-bit DAC in this illustrative embodiment, but any suitable number N of N-bit DACs can be used. The 1-bit DAC reduces power consumption and area used by the DAC 255 compared to larger values ​​of N-bit DACs. The 1-bit DAC also allows the ADC 150 shown in FIG. 1B to be implemented with the comparator 225. The comparator 225 receives a reference voltage input VREF_IN 144, a clock input LATP 148, and a reference feedback signal REF_FB 195. The comparator 225 outputs a first output BIT and an inverted output BITZ to the DAC 255.

[0027] The 1-bit DAC 255 includes four switches 232, 234, 236, and 238 and a sampling capacitor Cs 240. The switch 232 is coupled to a supply voltage rail configured to receive a supply voltage VDD (e.g., 5 volts) and is controlled by the SAMPLE 105. The switch 234 is coupled to the switch 232 and is controlled by a first output BIT of the comparator 225. The switch 236 is coupled to the switch 234 and is controlled by an inverted output BITZ of the comparator 225. The switch 238 is coupled to the switch 236 and to a supply voltage rail configured to receive a supply voltage VSS 210 (e.g., −5 volts). The switch 238 is controlled by the SAMPLE 105. The Cs 240 is coupled between the switches 234 and 236 and to a common potential (e.g., ground) 194. The switched-capacitor accumulator 160 is coupled to the output of the 1-bit DAC 255 and to the input of a buffer stage 170. The buffer stage 170 outputs a reference feedback signal REF_FB 195 and an output reference voltage REF_OUT 130.

[0028] 2B illustrates graphs of the control signals SAMPLE 105, CONVERT 110, and LATP 148 in the reference voltage generator 200 shown in FIG. 2A. The comparator 225 outputs the difference between the reference voltage input VREF_IN 144 and the reference feedback signal REF_FB 195 at the time indicated by the clock input LATP 148. The reference feedback signal REF_FB 195 from the buffer stage 170 represents the output reference voltage REF_OUT 130. The clock input LATP 148 causes the comparator 225 to sample the output reference voltage REF_OUT 130 once during the SAMPLE phase where it settles to the set value VREF_SETTLED 120. Thus, the comparator 225 outputs the difference BIT between the reference voltage input VREF_IN 144 and the set value VREF_SETTLED 120, rather than the time average value VREF_AVERAGE 115.

[0029] The comparator 225 outputs the difference BIT and the inverse BITZ of the difference BIT. For example, the comparator 225 outputs the difference BIT of a logic 1 and the inverse BITZ of a logic 0 while the settling value VREF_SETTLED 120 is less than the reference voltage input VREF_IN 144. Conversely, the comparator 225 outputs the difference BIT of a logic 0 and the inverse BITZ of a logic 1 while the settling value VREF_SETTLED 120 is greater than the reference voltage input VREF_IN 144.

[0030] Within the 1-bit DAC 255, switches 232 and 238 are closed during the SAMPLE phase of operation. The LATP 148 is configured to cause the comparator 225 to output BIT and BITZ during the SAMPLE phase of operation, and switches 234 and 236 open and close based on the values ​​of BIT and BITZ, respectively, to couple one of the supply voltages VDD 198 or VSS 210 to the sampling capacitor Cs 240. The sampling capacitor Cs 240 is charged by VDD 198 or discharged by VSS 210 during the SAMPLE phase of operation.

[0031] During the CONVERT phase of operation, switches 232 and 238 are open, disconnecting supply voltages VDD 198 and VSS 210 from sampling capacitor Cs 240. Switch 164 in switched capacitor accumulator 160 is closed, coupling sampling capacitor Cs 240 to storage capacitor CD 168. Charge from sampling capacitor Cs 240 is transferred to storage capacitor CD 168 to regulate the voltage VSTG1 on the output of digital feedback loop 140.

[0032] The comparator 225 and the 1-bit DAC 255 act as a transconductor with an output current I 260 that can be expressed as: TIFF2024516674000002.tif776 where σ represents the standard deviation of the comparator noise, k represents a constant related to the type of noise distribution of the comparator noise, VSTEP represents the voltage step generated by the 1-bit DAC 255, Fs represents the sampling frequency of the ADC, and VSTEP is the difference between the supply voltage VDD 198 on the output of the digital feedback loop 140 and VSTG1.

[0033] If VSTEP were independent of VSTG1, the direct current (DC) gain of comparator 225 with DAC 255 would be very high, resulting in a low DC offset. However, because VSTEP is dependent on VSTG1, the DC gain is reduced (e.g., about 60 dB), thereby reducing the DC reference voltage accuracy. The voltage VSTG1 on the output of digital feedback loop 140 is provided to buffer stage 170, which outputs reference voltage REF_OUT 130 and reference feedback signal REF_FB 195.

[0034] 3 illustrates a reference voltage generator 300 having a digital feedback loop 140 and a bias voltage. The reference voltage generator 300 is similar to the reference voltage generator 200 described herein with respect to FIG. 2A. The reference voltage generator 300 includes a 1-bit DAC 355, which in some examples is a low bandwidth high gain stage, and includes switches 332, 334, 336, 338, and 360, in addition to switches 232, 234, 236, and 238, and a buffer 340 and a sampling capacitor Cs 240 included in the 1-bit DAC 255 in the reference voltage generator 200.

[0035] The switch 332 is coupled to a supply voltage rail configured to receive VDD 198 and is controlled by the CONVERT 110. The switch 334 is coupled to the switch 332 and is controlled by a first output BIT of the comparator 225. The switch 336 is coupled to the switch 334 and is controlled by an inverted output BITZ of the comparator 225. The switch 338 is coupled to the switch 336 and to a supply voltage rail configured to receive VSS 210. The switch 338 is controlled by the CONVERT 110. A first terminal of the capacitor Cs 240 is coupled between the switches 234 and 236 and between the switches 334 and 336, and a second terminal of the capacitor Cs 240 is coupled to the switched capacitor accumulator 160.

[0036] One terminal of switch 360 is coupled between Cs 240 and switch 255, and the other terminal of switch 360 is coupled to the output of buffer 340. Switch 360 is controlled by SAMPLE 105. Buffer 340 is configured to receive a bias voltage VBIAS 350 approximately equal to the value of VSTG1 set by digital feedback loop 140. During the SAMPLE phase of operation, switches 232, 234, 236, and 238 operate as described herein with reference to Figures 2A and 2B. Switch 360 is also closed, coupling bias voltage VBIAS 350 from buffer 340 to the second terminal of Cs 240.

[0037] During the CONVERT phase of operation, switch 360 is open, decoupling buffer 340 from the second terminal of Cs 240. Switches 332 and 338 are closed. Switches 334 and 336 open and close based on the values ​​of BIT and BITZ, respectively, to couple one of the supply voltages VDD 198 or VSS 210 to sampling capacitor Cs 240. Sampling capacitor Cs 240 is charged by VDD 198 through switch 332 or discharged by VSS 210 through switch 338 during the SAMPLE phase of operation.

[0038] The modification of 1-bit DAC 355 to 1-bit DAC 255 shown in FIG. 2A biases Cs 240 and makes VSTEP independent from VSTEG1. Reference voltage generator 300 improves DC accuracy compared to reference voltage generator 200. The stability of reference voltage generator 300 is improved by keeping the delay of buffer 170 smaller than the digital delay. Therefore, the bandwidth of buffer 170 is selected such that the inversion of the bandwidth is much smaller than the clock period.

[0039] 4 illustrates a reference voltage generator 400 having a digital feedback loop 140, a bias voltage, and a digital filter. The reference voltage generator 400 is similar to the reference voltage generator 300 described herein with respect to FIG. 3, but also includes a digital filter 410 coupled between the comparator 225 and the 1-bit DAC with voltage bias 355. The digital filter 410 can band-limit or low-pass filter the 1-bit comparator output signal to filter out noise frequencies introduced by the comparator 225. The digital filter 410 can be any suitable digital filter that takes into account the comparator noise and noise requirements of a particular implementation.

[0040] For example, the digital filter 410 can be a 1-bit accumulator that averages the comparator output signal over M clock cycles, and the filter output toggles the 1-bit DAC 355 once every M clock cycles. In another example, the digital filter 410 can be a finite impulse response filter with N taps. The digital filter 410 takes up less area and uses less power than the capacitors used to band-limit noise in traditional reference buffers with high gain amplifiers and capacitors. The digital filter 410 also provides fine control over the noise transfer function, resulting in better filtering.

[0041] FIG. 5A illustrates a reference voltage generator 500 having a shared comparator 225 for multiple reference voltage outputs REF_OUT1 130A and REF_OUT2 130B. The output of the comparator 225 is coupled to a first signal chain 540A and a second signal chain 540B. Each of the signal chains 540A and 540B includes a D flip-flop 505 and a 1-bit DAC and switched-capacitor accumulator 510 as shown in FIG. 5A. In some implementations, the DAC and accumulator 510 also includes a voltage bias as described herein with respect to FIG. 3, and / or a digital filter as described herein with respect to FIG. 4. In this example, the signal chains 540A and 540B include a D flip-flop, although any suitable circuitry, such as an SR latch, may be used.

[0042] In signal chain 540A, D flip-flop 505A receives the differential BIT output from comparator 225 and is controlled by SAMPLE1 105A. D flip-flop 505A outputs BIT1 and BIT1Z to DAC and accumulator 510A, which is controlled by SAMPLE1 105A and CONVERT1 110A. The output of DAC and accumulator 510A is provided to buffer 170A, which outputs REF_OUT1 130A. In signal chain 540B, D flip-flop 505B receives the differential BIT output from comparator 225 and is controlled by SAMPLE2 105B. D flip-flop 505B outputs BIT2 and BIT2Z to DAC and accumulator 510B, which is controlled by SAMPLE2 105B and CONVERT2 110B. The output of the DAC and accumulator 510B is provided to a buffer 170B which outputs REF_OUT2 130B.

[0043] REF_OUT1 130A and REF_OUT2 130B are provided to an ADC (not shown) and a multiplexer 570, which selectively outputs REF_OUT1 130A or REF_OUT2 130B based on SAMPLE1 105A. Although a multiplexer is used in this example, any suitable selector logic circuit may be used. The output of the multiplexer 570 is REF_FB 195, which is provided to the comparator 225.

[0044] In some ADCs, multiple voltage references may be used (e.g., a reference voltage for initial decisions and a fine reference voltage for final decisions). If multiple references are used, they should be matched, and therefore the comparator 225 may be shared between the two reference generators. For example, the signal chain 540B and buffer 170B may be a buffer of the coarse reference voltage used for the initial CONVERT stage, where the largest capacitors are charged and where most of the signal-dependent load current is provided.

[0045] Signal chain 540A and buffer 170A may be a buffer of the fine reference voltage used for the final SAR determination after the dynamic error correction cycle to provide a current that is primarily signal independent. Any error introduced by the shared comparator 225 is present in both REF_OUT1 130A and REF_OUT2 130B so that the DACs and accumulators 510A and 510B are consistent. Although only two reference voltage output chains are shown in this example, any suitable number may be used.

[0046] FIG. 5B shows a graph of the control signals of the reference voltage generator 500 shown in FIG. 5A. Here, for ease of explanation, SAMPLE1 105A and SAMPLE2 105B are shown as two unique control signals. In other implementations, a single control signal SAMPLE is used and the signal chains 540A and 540B operate on alternate SAMPLE phases. Similarly, CONVERT1 110A and CONVERT2 110B are shown here as two unique control signals for ease of explanation. In other implementations, a single control signal CONVERT1 10 is used and the signal chains 540A and 540B operate on alternate CONVERT phases. The LATP 148 is configured such that a logic high on the LATP 148 occurs between the logic highs on SAMPLE1 105A and SAMPLE2 105B, and the comparator 225 samples the settling values ​​of the REF_OUT1 130A and REF_OUT2 130B outputs from the multiplexer 570.

[0047] The multiplexer 570 and the comparator 225 can be used to sample REF_OUT1 130A and REF_OUT2 130B on alternate SAMPLE phases and adjust the two reference output chains 540A and 540B independently. For example, in the first CONVERT phase of operation while CONVERT1 110A is logic high and SAMPLE1 105A is logic low, the multiplexer 570 outputs REF_OUT1 130A as the feedback signal REF_FB 195. The comparator 225 samples REF_OUT1 130A based on the trigger signal LATP 148 and adjusts the value of VSTG1 at the output of the DAC and accumulator 510A. REF_OUT2 130B is output as a coarse reference voltage. In the second CONVERT operation phase while CONVERT2 110B is logic high, SAMPLE2 105B is logic low, SAMPLE1 105A is logic low, and multiplexer 570 outputs REF_OUT2 130B as feedback signal REF_FB 195. Comparator 225 samples REF_OUT2 130B based on trigger signal LATP 148 and adjusts the value of VSTG2 at the output of DAC and accumulator 510B. REF_OUT1 130A is output as a fine reference voltage.

[0048] FIG. 6A illustrates a reference voltage generator 600 with auto-zeroing capability. Thus, the reference voltage generator 600 can compensate for comparator drift, such as due to temperature changes, by shorting the inputs of the comparator 225 and generating a voltage offset VCTRL_OFFSET 630 for the comparator 225. The output of the shared comparator 225 is coupled to a first signal chain 640A and a second signal chain 640B. Each of the signal chains 640A and 640B includes a D flip-flop 605 and a DAC and switched-capacitor accumulator 610, as shown in FIG. 2A. In some implementations, the DAC and accumulator 610 also includes a voltage bias as described herein with respect to FIG. 3 and / or a digital filter as described herein with respect to FIG. 4.

[0049] Signal chain 640A outputs a control signal VCTRL_OFFSET 630 to comparator 225 to compensate for comparator drift. The output of signal chain 640B is provided to a buffer 170 which outputs a reference voltage REF_OUT 130 to an ADC (not shown) and a multiplexer 650. Multiplexer 650 selectively outputs REF_OUT 130 or VREF_IN 144 based on SAMPLE1 105A. Although a multiplexer is used in this example, any suitable selector logic circuit may be used. The output of multiplexer 650 is REF_FB 195 which is provided to comparator 225. Reference voltage generator 600 operates similarly to the operation of reference voltage generator 500 described herein with reference to FIG. 5B, except that instead of signal chain 540A and buffer 170A outputting REF output 130A, the output of signal chain 640A is provided to comparator 225 as a control signal to compensate for comparator drift.

[0050] The comparator 225 may be auto-zeroed during the SAMPLE phase when both comparator inputs receive VREF_IN 144 and the signal chain 640A generates the offset correction voltage VCTRL_OFFSET 630. The comparator 225 may be auto-zeroed in approximately 1 nanosecond compared to the microseconds used to auto-zero an analog error amplifier. Auto-zeroing the comparator reduces phase noise. Also, the bandwidth of the comparator 225 may be dynamically changed or multiple comparator decisions may be made during the auto-zero phase to reduce thermal noise contributions.

[0051] In this description, the term "coupled" may encompass direct and indirect connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, (A) in a first example, device A is coupled to device B by a direct connection, where device A generates a signal to control device B to perform an action, or (b) in a second example, device A is coupled to device B via an intervening component C, where intervening component C does not change the functional relationship between device A and device B, and device B is controlled by device A via a control signal generated by device A.

[0052] Use of the phrase "ground voltage potential" in this description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of this description. Unless otherwise specified, "about," "approximately," or "substantially" means + / - 10% of the stated value.

[0053] As used in this description, the terms "terminal," "node," "interconnect," and "pin" are used interchangeably. Unless otherwise noted, these terms are used generally to mean an interconnection between, or a termination of, a device element, a circuit element, an integrated circuit, a device, or other electronic or semiconductor component.

[0054] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the invention.

Claims

1. A reference voltage generator, comprising: a comparator having a reference voltage input, a feedback input, a first control signal input, and an output; a 1-bit digital-to-analog converter (DAC) having an input coupled to the output of the comparator and an output; a switched-capacitor accumulator having an input coupled to the output of the 1-bit DAC and an output coupled to a feedback input of the comparator; a reference voltage generator including:

2. 2. The reference voltage generator of claim 1, The first control signal input is a clock input.

3. 2. The reference voltage generator of claim 1, The switched capacitor accumulator comprises: a switch coupled to an output of the 1-bit DAC and an output of the reference voltage generator; a capacitor coupled to the output of the reference voltage generator and to ground; a reference voltage generator including:

4. 2. The reference voltage generator of claim 1, The reference voltage generator further includes a digital filter coupled between the output of the comparator and the input of the 1-bit DAC.

5. 2. The reference voltage generator of claim 1, The 1-bit DAC is a first switch coupled to a first supply voltage rail, the first switch having a control input coupled to receive a second control signal; a second switch coupled to the first switch, the second switch having an input coupled to the output of the comparator; a third switch coupled to the second switch, the third switch having an input coupled to an inverting output of the comparator; a fourth switch coupled to the third switch and to a second supply voltage rail, the fourth switch having a control input coupled to receive the second control signal; a sampling capacitor coupled between the second switch and the third switch, the sampling capacitor further coupled to ground; a reference voltage generator including:

6. 2. The reference voltage generator of claim 1, The 1-bit DAC is a first switch and a second switch coupled to a first supply voltage rail, the first switch having a control input coupled to receive a second control signal, and the second switch having a control input coupled to receive a third control signal; a third switch and a fourth switch having an input coupled to an output of the comparator, the third switch being further coupled to the first switch and the fourth switch being further coupled to the second switch; a fifth switch and a sixth switch having an input coupled to an inverting output of the comparator, the fifth switch being coupled to the third switch and the sixth switch being coupled to the fourth switch; a seventh switch and an eighth switch coupled to a second supply voltage rail, the seventh switch being further coupled to the fifth switch, the seventh switch having a control input coupled to receive the second control signal, the eighth switch being further coupled to the sixth switch, the eighth switch having a control input coupled to receive the third control signal; and a sampling capacitor coupled between the third and fifth switches and the fourth and sixth switches, the sampling capacitor further coupled to an output of the 1-bit DAC; a ninth switch coupled to the output of the 1-bit DAC, the ninth switch having a control input coupled to receive the second control signal; a buffer coupled to the ninth switch, the buffer having a bias voltage input; a reference voltage generator including:

7. 2. The reference voltage generator of claim 1, The reference voltage generator is coupled to a buffer, the buffer having a reference voltage for an analog to digital converter and the feedback input.

8. An apparatus comprising: a comparator having a reference voltage input, a feedback input, a first control signal input, and an output; a first feedback loop coupled to an output of the comparator, the first feedback loop having an input coupled to receive a second control signal and an output; a buffer coupled to an output of the first feedback loop, the buffer having an output; a selector logic circuit having a first input coupled to said reference voltage input, a second input coupled to an output of said buffer, a third input coupled to receive a third control signal, and an output coupled to said feedback input; a second feedback loop coupled to an output of the comparator, the second feedback loop having an input coupled to receive the third control signal and an output for an offset correction signal for the comparator; 13. An apparatus comprising:

9. 9. The apparatus of claim 8, the selector logic circuit is configured to output a reference voltage; The second feedback loop is configured to output the offset correction signal while the second control signal is a logic high and the third control signal is a logic low.

10. 9. The apparatus of claim 8, Each of the first and second feedback loops comprises: a 1-bit digital-to-analog converter (DAC) coupled to an output of the comparator, the 1-bit DAC having an output; a switched-capacitor accumulator coupled to an output of the 1-bit DAC; 13. An apparatus comprising:

11. 11. The apparatus of claim 10, At least one of the first and second feedback loops further includes a digital filter coupled between the output of the comparator and the input of the 1-bit DAC.

12. 11. The apparatus of claim 10, The 1-bit DAC is a first switch coupled to a first supply voltage rail, the first switch having an input coupled to receive the second control signal; a second switch coupled to the first switch, the second switch having an input coupled to the output of the comparator; a third switch coupled to the second switch, the third switch having an input coupled to an inverting output of the comparator; a fourth switch coupled to the third switch and to a second supply voltage rail, the fourth switch having an input coupled to receive the second control signal; a sampling capacitor coupled between the second switch and the third switch, the sampling capacitor further coupled to ground; 13. An apparatus comprising:

13. 11. The apparatus of claim 10, The 1-bit DAC is a first switch and a second switch coupled to a first supply voltage rail, the first switch having a control input coupled to receive the second control signal, and the second switch having a control input coupled to receive the third control signal; a third switch and a fourth switch having inputs coupled to an output of the comparator, the third switch being coupled to the first switch and the fourth switch being coupled to the second switch; a fifth switch and a sixth switch having inputs coupled to an inverting output of the comparator, the fifth switch being coupled to the third switch and the sixth switch being coupled to the fourth switch; a seventh switch and an eighth switch coupled to a second supply voltage rail, the seventh switch being further coupled to the fifth switch, the seventh switch having a control input coupled to receive the second control signal, the eighth switch being further coupled to the sixth switch, the eighth switch having a control input coupled to receive the third control signal; and a sampling capacitor coupled between the third and fifth switches and the fourth and sixth switches, the sampling capacitor further coupled to an output of the 1-bit DAC; a ninth switch coupled to an output of the 1-bit DAC, the ninth switch having a control input coupled to receive the second control signal; a buffer coupled to the ninth switch, the buffer having a bias voltage input; 13. An apparatus comprising:

14. 11. The apparatus of claim 10, The switched capacitor accumulator comprises: a switch coupled to an output of the 1-bit DAC and to an output of each feedback loop, the switch having a control input coupled to receive the third control signal; a capacitor coupled to the output of each of the feedback loops and to ground; 13. An apparatus comprising:

15. 9. The apparatus of claim 8, The apparatus is included in an analog-to-digital converter (ADC), The apparatus further includes an output configured to provide a reference potential to the ADC.

16. 16. The apparatus of claim 15, the ADC is a successive approximation register ADC, An apparatus, wherein an output of the apparatus is configured to charge at least one capacitor within the ADC.

17. A reference voltage generator, comprising: a comparator having a reference voltage input, a feedback input, a clock input for receiving the first clock signal, and an output; a first feedback loop coupled to an output of the comparator, the first feedback loop having a clock input for receiving a second clock signal and an output; a first buffer coupled to an output of the first feedback loop, the first buffer having a first reference voltage output; a second feedback loop coupled to the output of the comparator, the second feedback loop having a clock input receiving a third clock signal, and an output; a second buffer coupled to an output of the second feedback loop, the second buffer having a second reference voltage output; a selector logic circuit having a first input coupled to the first reference voltage output, a second input coupled to the second reference voltage output, a control input configured to receive the first clock signal, and an output coupled to the feedback input; a reference voltage generator including:

18. 18. A reference voltage generator as claimed in claim 17, comprising: The first feedback loop and the first buffer constitute a coarse reference voltage generator, and the second feedback loop and the second buffer constitute a fine reference voltage generator.

19. 18. The reference voltage generator of claim 17, further comprising: N feedback loops coupled to the output of the comparator, each feedback loop having a unique clock input and output; N feedback loops, each buffer coupled to a unique feedback loop output from the N feedback loops, each buffer having a unique reference voltage output; a reference voltage generator including:

20. 20. The reference voltage generator of claim 19, A reference voltage generator, wherein the frequency of the N unique clock signals is divided by N.

21. 18. A reference voltage generator as claimed in claim 17, comprising: The second and third clock signals are inverted relative to each other.

22. 18. A reference voltage generator as claimed in claim 17, comprising: A reference voltage generator, wherein the frequency of the second and third clock signals is equal to approximately half the frequency of the first clock signal.

23. 18. A reference voltage generator as claimed in claim 17, comprising: Each of the first and second feedback loops comprises: a 1-bit digital-to-analog converter (DAC) coupled to an output of the comparator, the 1-bit DAC having an output; a switched-capacitor accumulator coupled to an output of the 1-bit DAC; a reference voltage generator including:

24. 24. A reference voltage generator as claimed in claim 23, comprising: At least one of the first and second feedback loops further includes a digital filter coupled between the output of the comparator and the input of the 1-bit DAC.

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