Linear power supply circuit

Abstract

To provide a linear power supply circuit having excellent linearity in input-output characteristic and a small gain error.SOLUTION: A linear power supply circuit 100 includes: an input part 1 to which an input signal Vin is inputted, for outputting first current signals I11, I12; a current-voltage conversion part 2 for converting the first current signals I11, I12 to a first voltage signal V1; a voltage-current conversion part 3 for converting the first voltage signal V1 to second current signals I31, I32; and an output part 4 for generating an output voltage signal Vo from the second current signals I31, I32 by a first current mirror part 41, a second current mirror part 42, and a third current mirror part 43, and outputting the output voltage signal Vo to an output terminal OUT, where the input part 1 and the current-voltage conversion part 2 configure a current feedback type operational amplifier 5.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a linear power supply circuit. [Background technology]

[0002] Patent Document 1 describes a voice coil motor (VCM) driver for driving a VCM. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-004128 A

[0004] [overview] It is desirable for the power amplifier used in the VCM driver to have good linearity of the input / output characteristics and small gain error. The power amplifiers that have been commonly used up until now have been configured using voltage feedback operational amplifiers. However, there are limitations to improving the linearity of the input / output characteristics and reducing the gain error in power amplifiers that use voltage feedback operational amplifiers.

[0005] An object of the present disclosure is to provide a linear power supply circuit applicable to a power amplifier, which has good linearity in the input / output characteristics and small gain error.

[0006] In order to solve the above-mentioned problems, a linear power supply circuit according to one embodiment of the present disclosure includes an input section that receives an input signal and outputs a first current signal, a current-voltage conversion section that converts the first current signal into a first voltage signal, a voltage-current conversion section that converts the first voltage signal into a second current signal, and an output section that generates an output voltage signal from the second current signal using a first current mirror section, a second current mirror section, and a third current mirror section, and outputs the output voltage signal to an output terminal, and the input section and the current-voltage conversion section form a current feedback operational amplifier. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram of a linear power supply circuit according to an embodiment. [Figure 2A] FIG. 2A is a diagram showing an example of the configuration of a first current mirror circuit used in the embodiment. [Figure 2B] FIG. 2B is a diagram illustrating an example of the configuration of a second current mirror circuit used in the embodiment. [Diagram 3] FIG. 3 is a circuit diagram of a VCM driver using a linear power supply circuit according to the embodiment. [Figure 4] FIG. 4 is a diagram showing the relationship between the input voltage Vi and the output voltages VA and VB of a VCM driver using a linear power supply circuit according to the embodiment. [Diagram 5] FIG. 5 is an enlarged view of region V in FIG. [Figure 6] FIG. 6 is a diagram showing the amplification factor G(VA) of the first output voltage VA of the VCM driver using the linear power supply circuit according to the embodiment. [Figure 7] FIG. 7 shows operational waveforms of each part of a VCM driver using a linear power supply circuit according to the embodiment in relation to an input voltage Vi. [Figure 8] FIG. 8 is a circuit diagram of a VCM driver using a linear power supply circuit of a comparative example. [Figure 9] FIG. 9 is a diagram showing the relationship between the input voltage Vi and the output voltages VA and VB of a VCM driver using a linear power supply circuit of the comparative example. [Figure 10] FIG. 10 is an enlarged view of region X in FIG. [Figure 11] FIG. 11 is a diagram showing the amplification factor G(VA) of the first output voltage VA of a VCM driver using a linear power supply circuit of the comparative example. [Figure 12] FIG. 12 shows operational waveforms of each part of a VCM driver using a linear power supply circuit of the comparative example relative to an input voltage Vi. [Figure 13] FIG. 13 shows operational waveforms of each part of a VCM driver using a linear power supply circuit of a comparative example provided with a shoot-through current prevention circuit in response to an input voltage Vi.

[0008] [Detailed Description] Hereinafter, the embodiments will be described with reference to the drawings. Note that the embodiments described below are comprehensive or specific examples. The numerical values, shapes, materials, components, installation positions and connection forms of the components shown in the following embodiments are merely examples and are not intended to limit the present disclosure. In addition, among the components in the following embodiments, components that are not described in the independent claims showing the highest concept are described as optional components. Furthermore, the dimensional ratios in the drawings are exaggerated for the convenience of explanation and may differ from the actual ratios.

[0009] 1 is a block diagram of a linear power supply circuit 100 according to an embodiment. The linear power supply circuit 100 is configured to be applicable to a power amplifier of a VCM driver. The linear power supply circuit 100 includes a positive input terminal INP and a negative input terminal INN as input terminals, an input section 1, a current-voltage conversion section 2, a voltage-current conversion section 3, an output section 4, and an output terminal OUT.

[0010] The input unit 1 receives, for example, an input voltage Vin input between the positive input terminal INP and the negative input terminal INN and a feedback current Ierr input to the negative input terminal INN as input signals, and generates first current signals I11 and I12 according to the input signals. The current-voltage conversion unit 2 converts mirror currents I21 and I22 generated by the first current mirror circuit 11 and the second current mirror circuit 12 as mirror currents of the first current signals I11 and I12 into a first voltage signal V1. The value of the first voltage signal V1 varies depending on the balance between the mirror current I21 and the mirror current I22. The voltage-current conversion unit 3 converts the first voltage signal V1 into second current signals I31 and I32 and outputs them. The output unit 4 generates an output voltage signal Vo from the second current signals I31 and I32 using the first current mirror unit 41, the second current mirror unit 42, and the third current mirror unit 43, and outputs the output voltage signal Vo to the output terminal OUT. A first DC power supply VCC1 and a second DC power supply VCC2 are connected to the output unit 4. A third DC power supply VCC3 is connected to the input unit 1, the current-voltage conversion unit 2, and the voltage-current conversion unit 3.

[0011] The input section 1 includes a buffer circuit 10. The buffer circuit 10 is, for example, configured as a SEPP (Single Ended Push-Pull) circuit. The buffer circuit 10 has a high input impedance at its positive input terminal +, whereas its negative input terminal - has a low input impedance. That is, as a feature of a current feedback operational amplifier, the negative input terminal - corresponds to the output terminal of the buffer circuit 10, and therefore the input impedance of the negative input terminal - is low. The positive input terminal INP is connected to the positive input terminal + of the buffer circuit 10, and the negative input terminal INN is connected to the negative input terminal - of the buffer circuit 10.

[0012] The current-voltage conversion unit 2 includes a bias circuit 20. The bias circuit 20 is connected to the buffer circuit 10 via a first current mirror circuit 11 and a second current mirror circuit 12.

[0013] The first current mirror circuit 11 includes a first front-stage transistor Q1 and a second front-stage transistor Q2, for example, as shown in FIG. 2A. The first front-stage transistor Q1 and the second front-stage transistor Q2 are each configured, for example, by a P-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The control electrode (for example, a gate) of the first front-stage transistor Q1 is connected to a first main electrode (for example, a drain) of the first front-stage transistor Q1 and a control electrode (for example, a gate) of the second front-stage transistor Q2. The second main electrodes (for example, sources) of the first front-stage transistor Q1 and the second front-stage transistor Q2 are connected to each other and serve as a power supply terminal connected to a third DC power supply VCC3. The first main electrode (for example, a drain) of the first front-stage transistor Q1 serves as a reference current terminal through which a reference current (first current signal I11) flows. The first main electrode (for example, a drain) of the second front-stage transistor Q2 serves as a mirror current terminal through which a mirror current I21 flows. By changing the size of the second front-stage transistor Q2 relative to the first front-stage transistor Q1, it is possible to adjust the ratio (mirror ratio) of the first current signal I11, which is a reference current, to the mirror current I21. For example, if the first front-stage transistor Q1 and the second front-stage transistor Q2 are made the same size, the mirror ratio is 1, that is, the first current signal I11 = the mirror current I21.

[0014] The second current mirror circuit 12 includes a third front-stage transistor Q3 and a fourth front-stage transistor Q4, for example, as shown in FIG. 2B. The third front-stage transistor Q3 and the fourth front-stage transistor Q4 are each formed of, for example, an N-channel MOSFET. The control electrode (for example, a gate) of the third front-stage transistor Q3 is connected to a first main electrode (for example, a drain) of the third front-stage transistor Q3 and a control electrode (for example, a gate) of the fourth front-stage transistor Q4. The second main electrodes (for example, sources) of the third front-stage transistor Q3 and the fourth front-stage transistor Q4 are connected to each other and form a power supply terminal connected to the ground. The first main electrode (for example, a drain) of the third front-stage transistor Q3 is a reference current terminal through which a reference current (first current signal I12) flows. The first main electrode (for example, a drain) of the fourth front-stage transistor Q4 is a mirror current terminal through which a mirror current I22 flows. By changing the size of the fourth front-stage transistor Q4 relative to the third front-stage transistor Q3, the ratio (mirror ratio) of the first current signal I12, which is a reference current, to the mirror current I22 can be adjusted. For example, if the third front-stage transistor Q3 and the fourth front-stage transistor Q4 are made the same size, the mirror ratio is 1, that is, the first current signal I12=mirror current I22. Also, when the feedback current Ierr flowing into the negative input terminal INN is zero, the first current signal I11=I12. When the feedback current Ierr flowing into the negative input terminal INN is not zero, the first current signal I11+Ierr=I12.

[0015] The configurations of the first current mirror circuit 11 and the second current mirror circuit 12 are not limited to the above configurations. Since the current mirror circuit is a well-known existing technology, a designer can select an appropriate configuration as appropriate.

[0016] The first current mirror circuit 11 has a power supply terminal supplied with a DC voltage from a third DC power supply VCC3, a reference current terminal connected to the first terminal a of the buffer circuit 10, and a mirror current terminal connected to the first terminal c of the bias circuit 20. The second current mirror circuit 12 has a power supply terminal connected to ground, a reference current terminal connected to the second terminal b of the buffer circuit 10, and a mirror current terminal connected to the second terminal d of the bias circuit 20. The first front-stage transistor Q1 of the first current mirror circuit 11 and the third front-stage transistor Q3 of the second current mirror circuit 12 are included in the input section 1. The second front-stage transistor Q2 of the first current mirror circuit 11 and the fourth front-stage transistor Q4 of the second current mirror circuit 12 are included in the current-voltage conversion section 2.

[0017] The input section 1 and the current-voltage conversion section 2 constitute a current feedback operational amplifier 5 .

[0018] The buffer circuit 10 generates a first current signal I11 at a first terminal a and a first current signal I12 at a second terminal b in response to an input signal input to a positive input terminal + and a negative input terminal -, for example, an input voltage Vin and a feedback current Ierr. The first current mirror circuit 11 generates a mirror current I21 with a predetermined mirror ratio for the first current signal I11, and inputs it to a first terminal c of the bias circuit 20. The second current mirror circuit 12 generates a mirror current I22 with a predetermined mirror ratio for the first current signal I12, and outputs it from a second terminal d of the bias circuit 20. The bias circuit 20 outputs a first voltage signal V1 according to the mirror currents I21 and I22 between a third terminal e and a fourth terminal f. The first voltage signal V1 is input between a first terminal g and a second terminal h of the voltage-current conversion unit 3.

[0019] The voltage-current converter 3 converts the first voltage signal V1 input between the first terminal g and the second terminal h into second current signals I31, I32 and outputs them from the third terminal i and the fourth terminal j to the output unit 4. The second current signals I31, I32 include a positive-side second current signal I31 flowing from the output unit 4 to the third terminal i of the voltage-current converter 3, and a negative-side second current signal I32 flowing from the fourth terminal j of the voltage-current converter 3 to the output unit 4. The voltage-current converter 3 is supplied with a DC voltage of the third DC power supply VCC3, which is the same as that of the input unit 1 and the current-voltage converter 2, at a power supply terminal k. In addition, the ground terminal l of the voltage-current converter 3 is connected to the ground. The voltage-current converter 3 may be provided with a phase compensation circuit for compensating the phase of the second current signals I31, I32 relative to the phase of the first voltage signal V1 in order to suppress oscillation.

[0020] The voltage-to-current converter 3 and the output unit 4 configure a class AB amplifier 6. The bias circuit 20 supplies the voltage-to-current converter 3 with a first voltage signal V1 obtained by superimposing a voltage obtained by current-to-voltage conversion of mirror currents I21, I22 of the first current signals I11, I12 corresponding to the input signals Vin, Ierr and a bias voltage of the class AB amplifier 6.

[0021] The current feedback operational amplifier 5 is configured to increase the transimpedance by the bias circuit 20. The transimpedance of a current feedback operational amplifier corresponds to the open loop gain in a voltage feedback operational amplifier. By increasing the transimpedance of the current feedback operational amplifier 5, it is possible to improve the responsiveness and reduce the gain error to improve the linearity of the input / output characteristics. Note that the means for increasing the transimpedance of the current feedback operational amplifier 5 is not limited to the bias circuit 20.

[0022] The output section 4 includes a first current mirror section 41, a second current mirror section 42, and a third current mirror section 43.

[0023] The first current mirror section 41 includes a first transistor Q11 and a second transistor Q12. The first transistor Q11 and the second transistor Q12 are each configured by a P-channel MOSFET, which is a P-channel MOS transistor. The control electrode (gate) of the first transistor Q11 is connected to a first main electrode (drain) of the first transistor Q11 and a control electrode (gate) of the second transistor Q12. The second main electrodes (sources) of the first transistor Q11 and the second transistor Q12 are connected to a second DC power supply VCC2. The first main electrode (drain) of the first transistor Q11 is connected to a third terminal i of the voltage-current conversion section 3, and a positive-side second current signal I31 flows therethrough as a reference current. A third current signal I4, which is a mirror current of the positive-side second current signal I31, flows through the first main electrode (drain) of the second transistor Q12.

[0024] By changing the size of the second transistor Q12 relative to the first transistor Q11, it is possible to adjust the ratio (mirror ratio) between the second positive current signal I31, which is a reference current, and the third current signal I4, which is a mirror current. For example, if the first transistor Q11 and the second transistor Q12 are set to the same size, the mirror ratio of the first current mirror unit 41 becomes 1, that is, the second positive current signal I31 and the third current signal I4 become equal. In this embodiment, the mirror ratio of the first current mirror unit 41 is set to 1.

[0025] The second current mirror section 42 includes a third transistor Q21 and a fourth transistor Q22. The third transistor Q21 and the fourth transistor Q22 are each configured by an N-channel power MOSFET, which is an N-channel MOS transistor. A first main electrode (drain) of the third transistor Q21 is connected to a first main electrode (drain) of the second transistor Q12 through which the third current signal I4 flows. A control electrode (gate) of the third transistor Q21 is connected to a first main electrode (drain) of the third transistor Q21 and a control electrode (gate) of the fourth transistor Q22. A first main electrode (drain) of the fourth transistor Q22 is connected to a first DC power supply VCC1, and a positive-side fourth current signal I51, which is a mirror current of the third current signal I4, flows through the first main electrode (drain) of the fourth transistor Q22. A second main electrode (source) of the fourth transistor Q22 is connected to a second main electrode (source) of the third transistor Q21.

[0026] The third current mirror section 43 includes a fifth transistor Q31 and a sixth transistor Q32. The fifth transistor Q31 and the sixth transistor Q32 are each configured by an N-channel power MOSFET, which is an N-channel MOS transistor. A first main electrode (drain) of the fifth transistor Q31 is connected to the fourth terminal j of the voltage-current conversion section 3, and a second negative current signal I32 flows through the fifth transistor Q31. A control electrode (gate) of the fifth transistor Q31 is connected to a first main electrode (drain) of the fifth transistor Q31 and a control electrode (gate) of the sixth transistor Q32. A first main electrode (drain) of the sixth transistor Q32 is connected to a second main electrode (source) of the fourth transistor Q22. The second main electrode (source) of the fifth transistor Q31 and the second main electrode (source) of the sixth transistor Q32 are connected to ground. A fourth negative current signal I52 flows through the first main electrode (drain) of the sixth transistor Q32 as a mirror current of the second negative current signal I32.

[0027] The series circuit of the fourth transistor Q22 and the sixth transistor Q32, which are both N-channel power MOSFETs, forms the output stage, and the output terminal OUT is connected to the connection point between the fourth transistor Q22 and the sixth transistor Q32. The fourth transistor Q22 forms the high-side transistor of the output stage, and the sixth transistor Q32 forms the low-side transistor of the output stage. The third transistor Q21 and the fifth transistor Q31 form a class AB bias circuit of the output stage of the series circuit of the fourth transistor Q22 and the sixth transistor Q32.

[0028] In the case of a linear power supply circuit using a voltage feedback op-amp, if both the high-side and low-side transistors in the output stage are configured with N-channel power MOSFETs, it is not possible to realize proper class AB amplifier operation in the circuit. In addition, in order to prevent the output from oscillating, it is necessary to keep the open loop gain of the voltage feedback op-amp low, which results in poor linearity and responsiveness of the input / output characteristics.

[0029] In contrast, in the linear power supply circuit 100 according to the embodiment, the input section 1 and the current-voltage conversion section 2 are configured as a current feedback operational amplifier 5 to increase the transimpedance, thereby improving responsiveness and oscillation stability. Also, by configuring the voltage-current conversion section 3 and the output section 4 as a class AB amplifier 6, the fourth transistor Q22 and the sixth transistor Q32 of the output stage, which are made up of N-channel power MOSFETs, can be driven simultaneously, and the idling current can be set appropriately, preventing a through current from flowing through the output stage.

[0030] A first resistor R1 for reducing an idling current may be connected in parallel to the third transistor Q21 of the second current mirror section 42. A second resistor R2 for reducing an idling current may be connected in parallel to the fifth transistor Q31 of the third current mirror section 43.

[0031] In the embodiment, the first current mirror unit 41 has a mirror ratio set to 1 and outputs a third current signal I4 having the same magnitude as the second positive current signal I31. The second current mirror unit 42 receives the third current signal I4 having the same magnitude as the second positive current signal I31 as a reference current. The third current mirror unit 43 receives the second negative current signal I32 as a reference current. If the mirror ratios of the second current mirror unit 42 and the third current mirror unit 43 are set to any equal value greater than 1, the amplification factor can be I51 / I31=I52 / I32>1. For example, if the mirror ratio of the second current mirror unit 42 and the third current mirror unit 43 is set to 1000, then I51 / I31=I52 / I32=1000. Since the output current Io is approximately 3 [A] at maximum, when the mirror ratio is 1000, the maximum current value of I31, I32, and I4 is approximately 3 [mA], which is 1 / 1000 of the output current Io. Note that the method of setting the mirror ratios of the first current mirror section 41, the second current mirror section 42, and the third current mirror section 43 is not limited to this, and may be set appropriately depending on the purpose. The output current signal Io is Io=I4+I51-I52.

[0032] With this configuration, in the output section 4, the second positive side current signal I31 is converted into the gate-source voltage of the fourth transistor Q22, and the second negative side current signal I32 is converted into the gate-source voltage of the sixth transistor Q32, and the output voltage signal Vo is output to the output terminal OUT. In other words, the output section 4 performs current-voltage conversion on the second positive side current signal I31 and the second negative side current signal I32 into the output voltage signal Vo.

[0033] The first DC power supply VCC1 is set to, for example, a DC voltage of +12 V. The second DC power supply VCC2 is set to a voltage value greater than that of the first DC power supply VCC1, for example, a DC voltage of +12 V+5.25 V=+17.25 V. The third DC power supply VCC3 is set to a voltage value less than that of the first DC power supply VCC1 and the second DC power supply VCC2, for example, a DC voltage of 5.25 V. The input unit 1, the current-voltage conversion unit 2, and the voltage-current conversion unit 3 connected to the third DC power supply VCC3 can be configured by electronic circuit elements of the 5 V system.

[0034] In the linear power supply circuit 100, the input section 1, the current-voltage conversion section 2, and the voltage-current conversion section 3 can be configured with 5V electronic circuit elements, so that the linear power supply circuit 100 can be configured with one IC (Integrated Circuit) chip to achieve area saving. In addition, in the linear power supply circuit 100 according to the embodiment, the circuit configuration is simple, so that low current consumption can be achieved. In addition, in the linear power supply circuit 100 according to the embodiment, the idling current can be reduced by adding a first resistor R1 in parallel to the second current mirror section 42 of the output section 4 and adding a second resistor R2 in parallel to the third current mirror section 43.

[0035] In the linear power supply circuit 100, the response can be improved by configuring the fourth transistor Q22 as a high-side transistor and the sixth transistor Q32 as a low-side transistor from the same element, an N-channel power MOSFET in this embodiment.

[0036] Next, with reference to FIGS. 3 to 7, the operation of the linear power supply circuit 100 according to the embodiment will be described using an example in which the linear power supply circuit 100 is used as a power amplifier for a VCM (Voice Coil Motor) driver 200 for driving a voice coil motor.

[0037] 3, the VCM driver 200 is configured with a first linear power supply circuit 100-1 and a second linear power supply circuit 100-2, which have the same configuration as the linear power supply circuit 100. The fourth transistor Q22 as a high-side transistor and the sixth transistor Q32 as a low-side transistor are configured by N-channel power transistors.

[0038] An input voltage Vi from a digital-to-analog converter (DAC) 150 as a signal source is input to a positive input terminal of a first linear power supply circuit 100-1 via a resistor Rc, and is also input to a negative input terminal of a second linear power supply circuit 100-2 via a resistor Rc. In the first linear power supply circuit 100-1, a first reference voltage Vr1 is input to a negative input terminal via a resistor Rb, a second reference voltage Vr2 is input to a positive input terminal via a resistor Rd, an output terminal and a negative input terminal are connected via a resistor Ra, and an output terminal is connected to a first output terminal AOUT. In the second linear power supply circuit 100-2, a first reference voltage Vr1 is input to a positive input terminal via a resistor Rb, a second reference voltage Vr2 is input to a positive input terminal via a resistor Rd, an output terminal and a negative input terminal are connected via a resistor Ra, and an output terminal is connected to a second output terminal BOUT. The first reference voltage Vr1 is a voltage for biasing the midpoint of the input voltage Vi. The second reference voltage Vr2 is a voltage for biasing the midpoint between the first output voltage VA at the first output terminal AOUT and the second output voltage VB at the second output terminal BOUT.

[0039] Between the first output terminal AOUT and the second output terminal BOUT, a voice coil motor M is connected. Here, L is an inductance component of the voice coil motor M, and RL is a resistance component of the voice coil motor M.

[0040] The ideal values ​​of the first output voltage VA and the second output voltage VB of the VCM driver 200 configured in this manner are expressed by the following equations (1) and (2). VA = Vr2 + G (Vi - Vr1) (1) VB = Vr2 - G (Vi - Vr1) (2) Here, G is the amplification factor, which is set by the resistance values ​​of resistors Ra, Rb, Rc, and Rd. In general, if Rb=Rc=Rx and Ra=Rd=Ry, then the amplification factor is set as G=Ry / Rx.

[0041] Next, the simulation results of the relationship between the input voltage Vi and the output voltages VA and VB of the VCM driver 200 configured as above will be described with reference to FIGS. 4 to 7. Here, the first linear power supply circuit 100-1 and the second linear power supply circuit 100-2 are both set to an amplification factor G=12. The first DC power supply VCC1 is set to +12V, the first reference voltage Vr1 is set to +0.75V which is the midpoint voltage value of the input voltage Vi, and the second reference voltage Vr2 is set to +6V which is the midpoint voltage value of the first DC power supply VCC1. The inductance L of the voice coil motor M is set to 1mH and the resistance RL is set to 8Ω. The amplification factor G is set to 192 / 16=12 with Rb=Rc=16kΩ and Ra=Rd=192kΩ.

[0042] Under these conditions, the ideal values ​​of the first output voltage VA and the second output voltage VB are expressed by the following equations (3) and (4). VA=6+12×(Vi-0.75)=-3+12Vi...(3) VB=6-12×(Vi-0.75)=15-12Vi...(4)

[0043] FIG. 4 plots the relationship between the input voltage Vi from DAC150 and the first output voltage VA and the second output voltage VB when the input voltage Vi is scanned from 0V to 1.5V under these conditions, and FIG. 5 shows an enlarged view of the region V near the center of FIG. 4. In addition, in order to clarify the linearity between the input voltage Vi and the first output voltage VA, FIG. 6 plots the relationship between the input voltage Vi from DAC150 and the amplification factor G(VA) of the first output voltage VA when the input voltage Vi is scanned from 0V to 1.5V. The amplification factor G(VA) of the first output voltage VA is expressed by the following equation (5) from equation (1). G(VA)=dVA / dVi=(VA-Vr2) / (Vi-Vr1) ···(5) Further, the amplification factor G(VB) of the second output voltage VB is expressed as the following equation (6) from equation (2). G(VB)=dVB / dVi=(Vr2-VB) / (Vi-Vr1) ···(6)

[0044] As can be seen from Figures 4 and 5, the linearity of the first output voltage VA and the second output voltage VB with respect to the input voltage Vi is good when the input voltage Vi is in the range of 0.3 to 1.2 V. Also, as can be seen from Figure 6, when the input voltage Vi is in the range of 0.3 to 1.2 V, the gain factor G(VA) almost matches the set gain factor G=12 and the gain error is small, except that it deteriorates slightly when the input voltage Vi is in the vicinity of the first reference voltage Vr1=0.75 V. The small gain error also confirms that the linearity of the input voltage Vi and the first output voltage VA is good.

[0045] 7 shows the voltage or current waveforms of each part when the input voltage Vi is changed in a stepwise manner from 75 mV to 810 mV at a time of 0.2 ms, where Ivcm is the current flowing through the voice coil motor M, Ic1 is the current flowing through the high-side transistor Q22 of the first linear power supply circuit 100-1, and Ic2 is the current flowing through the high-side transistor Q22 of the second linear power supply circuit 100-2.

[0046] When the input voltage Vi changes from 75 mV to 810 mV, the first output voltage VA changes from the initial value 0.32 V to 6.75 V, and the second output voltage VB changes from the initial value 11.55 V to 5.30 V, and Ic1, Ic2, and Ivcm change accordingly. When the input voltage Vi is 810 mV, the amplification factor G(VA)=12.5 is calculated from the first output voltage VA=6.75 V and equation (5), and the amplification factor G(VB)=11.6 is calculated from the second output voltage VB=5.30 V and equation (6). Thus, in the embodiment, it can be seen that the gain error of the amplification factor G(VA) and the amplification factor G(VB) is small with respect to the set amplification factor G=12.

[0047] Furthermore, when a linear power supply circuit using a voltage feedback operational amplifier is used as the power amplifier of the VCM driver, a shoot-through current, as described below, occurs in the high-side transistor Q22 and low-side transistor Q32 of the output stage when the input voltage Vi changes stepwise. In contrast, when a linear power supply circuit 100 using a current feedback operational amplifier 5 is used as the power amplifier of the VCM driver 200 as in the embodiment, as can be seen from the graphs of Ic1 and Ic2 in FIG. 7, the shoot-through current occurring in the high-side transistor Q22 and low-side transistor Q32 of the output stage can be prevented.

[0048] Next, for comparison with the embodiment, the operation will be described with reference to Figures 8 to 13, taking as an example a case where a linear power supply circuit 110 of a comparative example is used as a VCM driver 210. The linear power supply circuit 100 of the embodiment is configured using a current feedback operational amplifier 5, whereas the linear power supply circuit 110 of the comparative example is different in that the input section is configured using a differential pair of voltage feedback operational amplifiers.

[0049] As shown in Fig. 8, in the comparative example, a VCM driver 210 is configured to include a first linear power supply circuit 110-1 and a second linear power supply circuit 110-2, which are linear power supply circuits 110 using a voltage feedback operational amplifier. Other configurations of the VCM driver 210 are similar to those of the VCM driver 200 according to the embodiment shown in Fig. 3. Also, similar to the embodiment, Rb=Rc=16 kΩ, Ra=Rd=192 kΩ, and the amplification factor G=12 are set.

[0050] In the VCM driver 210 of the comparative example, the relationship between the input voltage Vi from the DAC 150 and the first output voltage VA and the second output voltage VB when the input voltage Vi is scanned from 0 to 1.5 V is plotted in Fig. 9, and an enlarged view of an area X near the center of Fig. 9 is shown in Fig. 10. Also, Fig. 11 plots the relationship between the input voltage Vi from the DAC 150 and the amplification factor G(VA) of the first output voltage VA when the input voltage Vi is scanned from 0 to 1.5 V.

[0051] As can be seen from Figures 9 and 10, when the input voltage Vi is in the range of 0.3 to 1.2 V, the linearity of the first output voltage VA and the second output voltage VB relative to the input voltage Vi deteriorates near the first reference voltage Vr1=0.75 V, which is the bias voltage of the input voltage Vi. Also, as can be seen from Figure 11, when the input voltage Vi is in the range of 0.3 to 1.2 V, not only does the amplification factor G(VA) deteriorate significantly near the input voltage Vi where the first reference voltage Vr1=0.75 V, but the accuracy for the set amplification factor G=12 is poor overall, and the gain error is large. The large gain error also confirms that the linearity of the input voltage Vi and the first output voltage VA is not good.

[0052] FIG. 12 shows the voltage or current waveforms of each part when the input voltage Vi is changed stepwise from 75 mV to 810 mV at time 0.2 ms in the VCM driver 210 of the comparative example.

[0053] When the input voltage Vi changes from 75 mV to 810 mV, the first output voltage VA changes from the initial value 0.22 V to 6.66 V, and the second output voltage VB changes from the initial value 11.78 V to 5.35 V, and Ic1, Ic2, and Ivcm change accordingly. When the input voltage Vi is 810 mV, the amplification factor G(VA)=11.0 is calculated from the first output voltage VA=6.66 V and equation (5), and the amplification factor G(VB)=10.8 is calculated from the second output voltage VB=5.35 V and equation (6). Thus, in the comparative example, it can be seen that the gain error of the amplification factor G(VA) and the amplification factor G(VB) with respect to the set amplification factor G=12 is large compared to the embodiment.

[0054] Furthermore, the VCM driver 210 of the comparative example employs a linear power supply circuit 110 that uses a voltage feedback operational amplifier as a power amplifier. For this reason, as shown by the graphs of Ic1 and Ic2 in Fig. 12, when the input voltage Vi changes stepwise, the high-side transistor Q22 and the low-side transistor Q32 turn on simultaneously, generating a shoot-through current.

[0055] In order to prevent shoot-through current in a linear power supply circuit 110 using a voltage feedback operational amplifier, it is necessary to provide a shoot-through current prevention circuit inside the linear power supply circuit 110. Figure 13 shows the voltage or current waveforms of each part when the input voltage Vi is changed in a step shape from 75 mV to 810 mV at time 0.2 ms in a VCM driver 210 of a comparative example using a linear power supply circuit 110 provided with an internal shoot-through current prevention circuit.

[0056] In this way, by providing a shoot-through current prevention circuit inside linear power supply circuit 110, it is possible to prevent shoot-through current as shown in the graphs of Ic1 and Ic2 in Fig. 13, and other operations are equivalent to those in Fig. 12. However, if linear power supply circuit 110 with a shoot-through current prevention circuit inside is configured on a single IC (Integrated Circuit) chip, the internal circuit configuration becomes complex, resulting in a large area and high current consumption.

[0057] Compared with a VCM driver 210 of a comparative example configured with a linear power supply circuit 110 using a voltage feedback operational amplifier, the VCM driver 200 configured with a linear power supply circuit 100 using a current feedback operational amplifier 5 according to the embodiment has the following improvements. That is, it can be seen that the VCM driver 200 configured with the linear power supply circuit 100 has good linearity of the input / output characteristics and small gain error. In addition, since the VCM driver 200 configured with the linear power supply circuit 100 does not generate a shoot-through current, there is no need to provide a shoot-through current prevention circuit in the linear power supply circuit 100, and therefore the area of ​​the linear power supply circuit 100 can be reduced.

[0058] (Appendix 1) The linear power supply circuit 100 includes an input unit 1 that receives an input signal Vin and outputs first current signals I11, I12, a current-voltage conversion unit 2 that converts the first current signals I11, I12 into a first voltage signal V1, a voltage-current conversion unit 3 that converts the first voltage signal V1 into second current signals I31, I32, and an output unit 4 that generates an output voltage signal Vo from the second current signals I31, I32 using a first current mirror unit 41, a second current mirror unit 42, and a third current mirror unit 43, and outputs the output voltage signal Vo to an output terminal OUT. The input unit 1 and the current-voltage conversion unit 2 configure a current feedback operational amplifier 5.

[0059] The configuration as described in Supplementary Note 1 makes it possible to realize a linear power supply circuit with good linearity in the input / output characteristics and small gain error.

[0060] (Appendix 2) In the linear power supply circuit 100 described in Supplementary Note 1, the second current signals I31, I32 include a second positive current signal I31 flowing into the voltage-current converter 3 and a second negative current signal I32 flowing out of the voltage-current converter 3. The output section 4 also includes a first current mirror section 41 having a first transistor Q11 through which the second positive side current signal I31 flows and a second transistor Q12 through which a third current signal I4 that is a mirror current of the second positive side current signal I31 flows, a second current mirror section 42 having a third transistor Q21 through which the third current signal I4 flows and a fourth transistor Q22 through which a mirror current I51 of the third current signal I4 flows, a third current mirror section 43 having a fifth transistor Q31 through which the second negative side current signal I32 flows and a sixth transistor Q32 through which a mirror current I52 of the second negative side current signal I32 flows, and a series circuit in which the fourth transistor Q22 and the sixth transistor Q32 are connected in series.

[0061] (Appendix 3) In the linear power supply circuit 100 described in Appendix 2, a first end of the series circuit is connected to a first DC power supply VCC1, and a second end of the series circuit is connected to a ground potential GND. The third transistor Q21, the fourth transistor Q22, the fifth transistor Q31, and the sixth transistor Q32 are N-channel MOS transistors. An output voltage signal Vo is output to an output terminal OUT connected to a connection point between the fourth transistor Q22 and the sixth transistor Q32.

[0062] (Appendix 4) In the linear power supply circuit 100 described in Supplementary Note 3, the first transistor Q11 and the second transistor Q12 are P-channel MOS transistors.

[0063] (Appendix 5) In the linear power supply circuit 100 described in Supplementary Note 3 or 4, the second DC power supply VCC2 that drives the first current mirror section 41 has a voltage value greater than that of the first DC power supply VCC1.

[0064] (Appendix 6) In the linear power supply circuit 100 described in Supplementary Note 5, the third DC power supply VCC3 that drives the input section 1, the current-voltage conversion section 2, and the voltage-current conversion section 3 has a smaller voltage value than the first DC power supply VCC1 and the second DC power supply VCC2.

[0065] (Appendix 7) In the linear power supply circuit 100 described in any one of Supplementary Notes 2 to 6, the output section 4 further includes a first resistor R1 connected in parallel to the second current mirror section 42, and a second resistor R2 connected in parallel to the third current mirror section 43.

[0066] (Appendix 8) In the linear power supply circuit 100 described in any of Appendices 1 to 7, the input section 1 includes input terminals INP, INN to which an input signal Vin is input, and a buffer circuit 10 connected to the input terminals INP, INN, and outputs first current signals I11, I12 from the buffer circuit 10 to the current-voltage conversion section 2.

[0067] (Appendix 9) In the linear power supply circuit 100 described in Supplementary Note 8, the buffer circuit 10 is configured as a SEPP (Single Ended Push-Pull) circuit.

[0068] (Appendix 10) In the linear power supply circuit 100 described in any one of Supplementary Notes 1 to 9, the voltage-current conversion section 3 and the output section 4 form a class AB amplifier 6.

[0069] (Appendix 11) In the linear power supply circuit 100 described in Supplementary Note 10, the current-voltage conversion unit 2 includes a bias circuit 20 for the class AB amplifier 6.

[0070] Although the present disclosure has been described in detail above, it is clear to those skilled in the art that the present disclosure is not limited to the embodiments described in the present disclosure. One or more elements of one embodiment can be combined with one or more elements of another embodiment. The present disclosure can be implemented in modified and altered forms without departing from the spirit and scope of the present disclosure as defined by the claims. Therefore, the description of the present disclosure is intended to be illustrative and does not have any limiting meaning on the present disclosure. [Explanation of symbols]

[0071] 1 Input section 2 Current-to-voltage conversion section 3. Voltage-to-current converter 4 Output section 5 Current feedback operational amplifier 6. Class AB Amplifier 10 Buffer Circuit 11 First current mirror circuit 12 Second current mirror circuit 20 Bias Circuit 41 First current mirror section 42 Second current mirror section 43 Third current mirror section 100 Linear power supply circuit 150 Digital to Analog Converter (DAC) 200 VCM driver AOUT 1st output terminal BOUT Second output terminal I11,I12 1st current signal I21, I22 Mirror current of the first current signal I31,I32 2nd current signal I4 3rd current signal I51,I52 4th current signal Ierr Feedback current INN Negative input terminal INP Positive input terminal M Voice coil motor (VCM) OUT Output terminal Q1 First pre-stage transistor Q2 Second front-stage transistor Q3 3rd front-stage transistor Q4 4th front-stage transistor Q11 First transistor Q12 Second transistor Q21 3rd transistor Q22 4th transistor (high side transistor) Q31 5th transistor Q32 6th transistor (low side transistor) R1 First resistor R2 2nd resistor VA 1st Output Voltage VB Second output voltage VCC1 1st DC power supply VCC2 2nd DC power supply VCC3 3rd DC power supply Vo output voltage signal Vr1 First reference voltage Vr2 Second reference voltage

Claims

1. an input section that receives an input signal and outputs a first current signal; a current-voltage converter that converts the first current signal into a first voltage signal; a voltage-to-current converter that converts the first voltage signal into a second current signal; an output section that generates an output voltage signal from the second current signal by a first current mirror section, a second current mirror section, and a third current mirror section, and outputs the output voltage signal to an output terminal; Equipped with The input section and the current-voltage conversion section form a current feedback operational amplifier. Linear power supply circuit.

2. the second current signal includes a second positive current signal flowing into the voltage-to-current converter and a second negative current signal flowing out from the voltage-to-current converter, The output unit is the first current mirror section including a first transistor through which the second positive current signal flows and a second transistor through which a third current signal that is a mirror current of the second positive current signal flows; the second current mirror section including a third transistor through which the third current signal flows and a fourth transistor through which a mirror current of the third current signal flows; the third current mirror unit including a fifth transistor through which the second negative current signal flows and a sixth transistor through which a mirror current of the second negative current signal flows; a series circuit in which the fourth transistor and the sixth transistor are connected in series; Equipped with 2. The linear power supply circuit of claim 1.

3. a first end of the series circuit is connected to a first DC power source, and a second end of the series circuit is connected to a ground potential; the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are N-channel MOS transistors, the output voltage signal is output to the output terminal connected to a connection point between the fourth transistor and the sixth transistor; 3. The linear power supply circuit of claim 2.

4. 4. The linear power supply circuit of claim 3, wherein the first transistor and the second transistor are P-channel MOS transistors.

5. 4. The linear power supply circuit according to claim 3, wherein a second DC power supply that drives said first current mirror section has a voltage value greater than that of said first DC power supply.

6. 6. The linear power supply circuit according to claim 5, wherein a third DC power supply that drives the input section, the current-to-voltage converter, and the voltage-to-current converter has a voltage value smaller than that of the first DC power supply and the second DC power supply.

7. 3. The linear power supply circuit according to claim 2, wherein the output section further comprises a first resistor connected in parallel to the second current mirror section, and a second resistor connected in parallel to the third current mirror section.

8. 2. The linear power supply circuit according to claim 1, wherein the input section includes an input terminal to which the input signal is input, and a buffer circuit connected to the input terminal, and the first current signal is output from the buffer circuit to the current-voltage conversion section.

9. 9. The linear power supply circuit according to claim 8, wherein the buffer circuit is configured as a SEPP (Single Ended Push-Pull) circuit.

10. 2. The linear power supply circuit according to claim 1, wherein the voltage-to-current conversion section and the output section form a class AB amplifier.

11. The linear power supply circuit according to claim 10 , wherein the current-voltage conversion section includes a bias circuit for the class AB amplifier.

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