Multilayer ceramic electronic component

Abstract

To provide a multilayer ceramic electronic component capable of suppressing structural defects in a capacitance portion.SOLUTION: A multilayer ceramic electronic component includes a laminated structure in which a plurality of internal electrode layers and a plurality of dielectric layers are laminated, and a pair of cover layers provided outside an outermost internal electrode layer among the plurality of internal electrode layers, and the pair of cover layers has ceramic as a main component, and at least one of the pair of cover layers has an average grain number in the stacking direction in the laminated structure that is smaller than the average grain number in at least one dielectric layer among the plurality of dielectric layers.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a multilayer ceramic electronic component. [Background technology]

[0002] 2. Description of the Related Art Multilayer ceramic electronic components such as multilayer ceramic capacitors (MLCCs) are used in high-frequency communication systems, typified by mobile phones (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-137298 A Summary of the Invention [Problem to be solved by the invention]

[0004] When some kind of external impact is applied, the impact is transmitted to the dielectric layers, which may cause a structural defect in the capacitance portion of the multilayer ceramic electronic component.

[0005] The present invention has been made in consideration of the above-mentioned problems, and has an object to provide a multilayer ceramic electronic component capable of suppressing structural defects in a capacitive section. [Means for solving the problem]

[0006] The multilayer ceramic electronic component according to the present invention comprises a laminated structure in which a plurality of internal electrode layers and a plurality of dielectric layers are laminated, and a pair of cover layers provided outside an outermost internal electrode layer among the plurality of internal electrode layers, the pair of cover layers having a ceramic as a main component, and at least one of the pair of cover layers having an average grain number in a stacking direction in the laminated structure that is smaller than the average grain number in at least one dielectric layer among the plurality of dielectric layers.

[0007] In the above-mentioned monolithic ceramic electronic component, the average number of grains in the lamination direction in the at least one cover layer may be 100 or less.

[0008] The average number of grains in the at least one dielectric layer in the lamination direction of the multilayer ceramic electronic component may be one or more.

[0009] In the above-described monolithic ceramic electronic component, the average number of grains in the lamination direction in the at least one cover layer may be less than one time the average number of grains in the lamination direction in the at least one dielectric layer.

[0010] In the above-described monolithic ceramic electronic component, an average grain diameter in the at least one cover layer may be larger than an average grain diameter in the at least one dielectric layer.

[0011] In the above-mentioned monolithic ceramic electronic component, the at least one cover layer may have an average grain diameter of 0.01 μm or more.

[0012] In the above-described monolithic ceramic electronic component, the at least one cover layer may be thinner than the at least one dielectric layer.

[0013] In the above-mentioned monolithic ceramic electronic component, the at least one cover layer may have a thickness of 100 μm or less. Effect of the Invention

[0014] According to the present invention, it is possible to provide a multilayer ceramic electronic component capable of suppressing structural defects in a capacitive section. [Brief description of the drawings]

[0015] [Figure 1] FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. [Diagram 2] 2 is a cross-sectional view taken along line AA in FIG. 1. [Diagram 3] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 4] (a) and (b) are enlarged views of the area near the external electrodes. [Diagram 5] FIG. 2 is an enlarged cross-sectional view of the vicinity of the cover layer. [Figure 6] 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. [Figure 7] 1(a) and (b) are diagrams illustrating a printing process. [Figure 8] 11A to 11C are diagrams illustrating a pressure bonding process. [Figure 9] 11A to 11C are diagrams illustrating a step of attaching a side margin. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, an embodiment will be described with reference to the drawings.

[0017] (First embodiment) FIG. 1 is a partial cross-sectional perspective view of the multilayer ceramic capacitor 100 according to the first embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. FIG. 3 is a cross-sectional view taken along line BB in FIG. 1. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes an element body 10 having a substantially rectangular parallelepiped shape, and external electrodes 20a, 20b provided on any two opposing end faces of the element body 10. Of the four faces of the element body 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces. The external electrodes 20a, 20b extend on the top, bottom and two side faces in the stacking direction of the element body 10. However, the external electrodes 20a, 20b are spaced apart from each other.

[0018] 1 to 3, the Z-axis direction (first direction) is the stacking direction, and is the direction in which the internal electrode layers face each other. The X-axis direction (second direction) is the direction in which the two end faces of the element body 10 face each other, and is the direction in which the external electrodes 20a and 20b face each other. The Y-axis direction (third direction) is the width direction of the internal electrode layers, and is the direction in which the two side faces other than the two end faces of the element body 10 face each other of the four side faces. The X-axis direction, Y-axis direction, and Z-axis direction are mutually perpendicular.

[0019] The element body 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 are alternately laminated. One end of each internal electrode layer 12 is alternately drawn out to the end face of the element body 10 on which the external electrode 20a is provided and the end face on which the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately conductive to the external electrode 20a and the external electrode 20b. As a result, the multilayer ceramic capacitor 100 has a configuration in which a plurality of dielectric layers 11 are laminated via the internal electrode layers 12. In addition, in the laminated structure of the dielectric layers 11 and the internal electrode layers 12, the internal electrode layers 12 are arranged on the outermost layers in the lamination direction, and the upper and lower surfaces of the laminate are covered by the cover layers 13. The cover layers 13 are mainly composed of a ceramic material. For example, the cover layers 13 may have the same composition as the dielectric layers 11 or may have a different composition.

[0020] The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes.

[0021] The internal electrode layers 12 are mainly composed of base metals such as nickel (Ni), copper (Cu), and tin (Sn). Noble metals such as platinum (Pt), palladium (Pd), silver (Ag), and gold (Au), or alloys containing these metals, may be used as the internal electrode layers 12. The average thickness of each of the internal electrode layers 12 in the Z-axis direction is, for example, 4.0 μm or less, 2.0 μm or less, or 0.7 μm or less. The thickness of each of the internal electrode layers 12 can be measured by observing the cross section of the multilayer ceramic capacitor 100 with a SEM (scanning electron microscope), measuring the thickness at 10 different points, and deriving the average value of each measurement point.

[0022] The dielectric layer 11 is, for example, a compound represented by the general formula ABO 3 The main phase of the ceramic material is a perovskite structure represented by the formula: 3-α For example, the ceramic material includes barium titanate (BaTiO 3 ), calcium zirconate (CaZrO 3 ), calcium titanate (CaTiO 3 ), strontium titanate (SrTiO 3 ), magnesium titanate (MgTiO 3 ), Ba that forms a perovskite structure 1-x-y Ca x Sr y Ti 1-z Zr z O 3 (0≦x≦1, 0≦y≦1, 0≦z≦1) and the like. 1-x-y Ca x Sr y Ti 1-z Zr z O 3are barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate, and barium calcium titanate zirconate. For example, the dielectric layer 11 contains 90 at % or more of the main component ceramic. The thickness of the dielectric layer 11 is, for example, 20.0 μm or less, 5.0 μm or less, or 1.0 μm or less. The thickness of the dielectric layer 11 can be measured by observing the cross section of the multilayer ceramic capacitor 100 with a SEM (scanning electron microscope), measuring the thickness at 10 points on each dielectric layer 11, and deriving the average value of the measurement points.

[0023] An additive may be added to the dielectric layer 11. Examples of the additive to the dielectric layer 11 include oxides of zirconium (Zr), hafnium (Hf), magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), and rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), or oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0024] 2, a region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region that generates capacitance in the multilayer ceramic capacitor 100. Therefore, the region that generates capacitance is referred to as a capacitive portion 14. In other words, the capacitive portion 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

[0025] The region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b being interposed therebetween is referred to as the end margin 15. The region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a being interposed therebetween is also the end margin 15. In other words, the end margin 15 is a region where the internal electrode layers 12 connected to the same external electrode face each other without an internal electrode layer 12 connected to a different external electrode being interposed therebetween. The end margin 15 is a region that does not generate capacitance.

[0026] 3, in the element body 10, a pair of side margins 16 are regions provided so as to cover the ends (ends in the Y-axis direction) on two side surfaces of the dielectric layer 11 and the internal electrode layer 12. In other words, the side margins 16 are regions provided outside the capacitive portion 14 in the Y-axis direction. The side margins 16 are also regions that do not generate capacitance.

[0027] FIG. 4(a) is an enlarged cross-sectional view of the vicinity of the external electrode 20a. FIG. 4(b) is an enlarged cross-sectional view of the vicinity of the external electrode 20b. Hatching is omitted in FIG. 4(a) and FIG. 4(b). As illustrated in FIG. 4(a) and FIG. 4(b), the external electrodes 20a, 20b have a structure in which a plating layer 22 is provided on an underlayer 21. The underlayer 21 is mainly composed of nickel, copper, etc. The underlayer 21 may contain ceramic particles as a co-material, or may contain a glass component. The plating layer 22 is mainly composed of a metal such as nickel, copper, aluminum, zinc, tin, etc., or an alloy of two or more of these metals. The plating layer 22 may be a plating layer of a single metal component, or may be a plurality of plating layers of different metal components. For example, the plating layer 22 has a structure in which a first plating layer 23, a second plating layer 24, and a third plating layer 25 are formed in this order from the underlayer 21 side. The first plating layer 23 is, for example, a copper plating layer. The second plating layer 24 is, for example, a nickel plating layer, and the third plating layer 25 is, for example, a tin plating layer.

[0028] A multilayer ceramic capacitor may be subjected to an external impact. In this case, if the impact is transmitted to the inside, structural defects may occur in the capacitive section 14. In response to this, the multilayer ceramic capacitor 100 according to this embodiment has a configuration that can suppress structural defects in the capacitive section 14.

[0029] FIG. 5 is an enlarged cross-sectional view of the vicinity of the cover layer 13. In FIG. 5, a YZ cross section is depicted as an example. In FIG. 5, hatching representing a cross section is omitted. As illustrated in FIG. 5, the cover layer 13 has a structure in which a plurality of ceramic grains 31 are sintered. The dielectric layer 11 has a structure in which a plurality of ceramic grains 32 are sintered. In this embodiment, the average number of grains in the cover layer 13 is smaller than the average number of grains in the dielectric layer 11 in the Z-axis direction. According to this configuration, the number of grain boundaries in the cover layer 13 is reduced. As a result, when an impact is applied to the multilayer ceramic capacitor 100 from the outside, the cover layer 13 is destroyed preferentially, and the impact is less likely to be transmitted to the capacitance section 14. As a result, structural defects in the capacitance section 14 can be suppressed.

[0030] The average number of grains in the Z-axis direction of the cover layer 13 can be measured by polishing to expose the YZ cross section of the cover layer 13 on the capacitance portion 14, photographing it with an SEM, measuring the number of grains in the Z-axis direction at 10 equally spaced points in the Y-axis direction, and calculating the average value. The average number of grains in the Z-axis direction of the dielectric layer 11 can be measured by applying a similar measurement method to the dielectric layer 11 in the capacitance portion 14.

[0031] If the average number of grains in the Z-axis direction in the cover layer 13 is not sufficiently small, there is a risk that the number of grain boundaries in the cover layer 13 cannot be sufficiently reduced. Therefore, it is preferable to set an upper limit on the average number of grains in the Z-axis direction in the cover layer 13. In this embodiment, the average number of grains in the Z-axis direction in the cover layer 13 is preferably 1000 or less, more preferably 100 or less, and even more preferably 50 or less.

[0032] In addition, in the Z-axis direction, the average number of grains in the cover layer 13 is preferably less than 1 time, more preferably less than 0.8 times, and even more preferably less than 0.5 times the average number of grains in the dielectric layer 11.

[0033] It is preferable to set a lower limit on the average number of grains in the Z-axis direction in the dielectric layer 11. In this embodiment, the average number of grains in the Z-axis direction in the dielectric layer 11 is preferably 1 or more, more preferably 3 or more, and further preferably 5 or more.

[0034] Also, the average grain diameter in the cover layer 13 is preferably larger than the average grain diameter in the dielectric layer 11. This is because if the average grain diameter in the cover layer 13 is small, the difference in grain diameter between the cover layer 13 and the dielectric layer 11 during firing will be small. The average grain diameters in the cover layer 13 and the dielectric layer 11 can be measured by exposing the cross section by polishing, photographing the cross section with a fixed field of view using an SEM, measuring the diameter of each grain using imaging software or the like, and dividing the diameter by the number of grains.

[0035] For example, the average grain size in the cover layer 13 is preferably 0.01 μm or more, more preferably 0.1 μm or more, and even more preferably 0.5 μm or more.

[0036] The thinner the cover layer 13 is formed, the larger the capacitance portion 14 can be made within a limited size. Therefore, it is preferable that the cover layer 13 is formed thinner than the dielectric layer 11. For example, the thickness of the cover layer 13 is preferably 100 μm or less, more preferably 50 μm or less, and even more preferably 10 μm or less.

[0037] In the above, the average grain number, average grain diameter, thickness, etc. of the cover layer 13 are described, but attention may be paid to only one of the two cover layers 13. In the above, the average grain number, average grain diameter, thickness, etc. of the dielectric layer 11 are described, but attention may be paid to at least one of the dielectric layers 11.

[0038] Next, a description will be given of a method for manufacturing the multilayer ceramic capacitor 100. FIG 6 is a diagram illustrating a flow of the method for manufacturing the multilayer ceramic capacitor 100.

[0039] (Raw powder production process) First, a dielectric material for forming the dielectric layer 11 and a cover material for forming the cover layer 13 are prepared. The dielectric material and the cover material include ceramic raw material powder having a perovskite structure. For example, barium titanate is a tetragonal compound having a perovskite structure and exhibits a high relative dielectric constant. This barium titanate can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. As a method for synthesizing the above-mentioned ceramic raw material powder, various methods have been known in the past, such as a solid phase method, a sol-gel method, a hydrothermal method, etc. In this embodiment, any of these can be adopted.

[0040] A predetermined additive compound is added to the obtained ceramic raw material powder according to the purpose. Examples of the additive compound include oxides of zirconium, hafnium, magnesium, manganese, molybdenum, vanadium, chromium, rare earth elements (yttrium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, and ytterbium), oxides containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon, or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0041] The particle size of the resulting ceramic raw material powder can be adjusted to form the dielectric material and the cover material, for example by making the particle size of the cover material larger than that of the dielectric material.

[0042] (Coating process) A binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the dielectric material and wet mixed. The obtained slurry is used to coat a ceramic green sheet 51 on a substrate by, for example, a die coater method or a doctor blade method, and then dried. The substrate is, for example, a polyethylene terephthalate (PET) film.

[0043] (Printing process) Next, as shown in Fig. 7(a), a metal conductive paste for forming internal electrodes containing an organic binder is printed on the surface of a ceramic green sheet 51 by screen printing, gravure printing, or the like to arrange an internal electrode pattern 52 that is alternately drawn to a pair of external electrodes with different polarities. Ceramic particles are added to the metal conductive paste as a co-material. The main component of the ceramic particles is not particularly limited, but is preferably the same as the main component ceramic of the dielectric layer 11. For example, barium titanate with an average particle size of 50 nm or less may be uniformly dispersed.

[0044] Next, a binder such as an ethyl cellulose-based binder and an organic solvent such as a terpineol-based binder are added to the dielectric material, and the mixture is kneaded in a roll mill to obtain a reverse pattern paste. As shown in Fig. 7(a), the reverse pattern paste is printed in the peripheral area of ​​a ceramic green sheet 51 where an internal electrode pattern 52 is not printed, thereby arranging a reverse pattern 53 and filling in the step with the internal electrode pattern 52. The ceramic green sheet 51 on which the internal electrode pattern 52 and the reverse pattern 53 are printed is called a lamination unit.

[0045] 7(b), the lamination units are laminated so that the internal electrode layers 12 and the dielectric layers 11 are alternately arranged, and the edges of the internal electrode layers 12 are alternately exposed on both end faces in the length direction of the dielectric layers 11 and alternately led out to a pair of external electrodes 20a, 20b having different polarities. For example, the number of layers of the internal electrode pattern 52 is set to 100 to 1000.

[0046] (Crimping process) Next, a binder such as an ethyl cellulose-based binder and an organic solvent such as a terpineol-based binder are added to the cover material and kneaded in a roll mill to obtain a cover sheet 54. As shown in Fig. 8, a predetermined number of cover sheets 54 are laminated on the top and bottom of a laminate in which the lamination units are laminated, and are thermocompression bonded. Then, the laminate is cut to a predetermined chip size (for example, 1.0 mm x 0.5 mm).

[0047] (coating process) The ceramic laminate thus obtained was subjected to 2 After binder removal processing in a deaerated atmosphere, air atmosphere, or the like, a metal paste that will become the base layer of the external electrodes 20a, 20b is applied by a dipping method.

[0048] (Firing process) Then, oxygen partial pressure 10 -10 ~10 -7 The ceramic laminate is fired at 1100°C to 1300°C for 10 minutes to 2 hours in a reducing atmosphere of 1 atm.

[0049] (Reoxidation treatment process) Then, N2 A reoxidation treatment may be carried out in a gas atmosphere at 600°C to 1000°C.

[0050] (Plating process) Thereafter, the underlayers of the external electrodes 20a, 20b are coated with a metal such as Cu, Ni, Sn, etc. by plating. Through the above steps, the multilayer ceramic capacitor 100 is completed.

[0051] The side margin portion may be attached or applied to the side surface of the laminated portion. Specifically, as illustrated in Fig. 9, ceramic green sheets 51 and internal electrode patterns 52 having the same width as the ceramic green sheets 51 are alternately laminated to obtain the laminated portion. Next, a sheet formed from a reverse pattern paste may be attached as a side margin portion 55 to the side surface of the laminated portion.

[0052] In the manufacturing method according to this embodiment, by adjusting firing conditions such as the firing temperature and the firing atmosphere, the average number of grains in the cover layer 13 in the Z-axis direction can be made smaller than the average number of grains in the dielectric layer 11. Alternatively, by using a cover material instead of a dielectric material for the lowermost ceramic green sheet 51, the average number of grains in the cover layer 13 in the Z-axis direction can be made smaller than the average number of grains in the dielectric layer 11. Alternatively, by making the cover material contain more material that promotes grain growth than the dielectric material, the average number of grains in the cover layer 13 can be made smaller than the average number of grains in the dielectric layer 11.

[0053] In the above embodiments, a multilayer ceramic capacitor has been described as an example of a multilayer ceramic electronic component, but the present invention is not limited to this. For example, other multilayer ceramic electronic components such as a varistor or a thermistor may be used.

[0054] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention described in the claims. [Explanation of symbols]

[0055] 10 Base 11 Dielectric layer 12 Internal electrode layer 13 Cover Layer 14 Capacity part 15 End Margin 16 Side Margin 20a,20b external electrode 51 Ceramic green sheet 52 Internal electrode pattern 53 Reverse pattern 54 Cover Sheet 55 Side margin 100 Multilayer ceramic capacitors

Claims

1. a laminated structure in which a plurality of internal electrode layers and a plurality of dielectric layers are laminated; a pair of cover layers provided outside an outermost internal electrode layer among the plurality of internal electrode layers; The pair of cover layers are mainly composed of ceramic, a multilayer ceramic electronic component, wherein at least one of the pair of cover layers has an average number of grains in a stacking direction of the stacked structure that is smaller than an average number of grains in at least one of the plurality of dielectric layers.

2. 2. The multilayer ceramic electronic component according to claim 1, wherein an average number of grains in the lamination direction in said at least one cover layer is 100 or less.

3. 2. The multilayer ceramic electronic component according to claim 1, wherein the average number of grains in the at least one dielectric layer in the stacking direction is one or more.

4. 2. The multilayer ceramic electronic component according to claim 1, wherein an average number of grains in the lamination direction in the at least one cover layer is less than one time an average number of grains in the lamination direction in the at least one dielectric layer.

5. 2. The multilayer ceramic electronic component according to claim 1, wherein an average grain diameter in said at least one cover layer is larger than an average grain diameter in said at least one dielectric layer.

6. 2. The multilayer ceramic electronic component according to claim 1, wherein the at least one cover layer has an average grain diameter of 0.01 [mu]m or more.

7. The multilayer ceramic electronic component according to claim 1 , wherein the at least one cover layer is thinner than the at least one dielectric layer.

8. 2. The multilayer ceramic electronic component according to claim 1, wherein the at least one cover layer has a thickness of 100 μm or less.

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